System, apparatus, and method for controlling the duty cycle of a clock signal for a multi-point interconnect

Abstract

In an embodiment, a host controller is coupled to an interconnect to which multiple devices may be coupled. The host controller may include: a first driver for driving first information onto the interconnect according to a bus clock signal; a first receiver for receiving second information from at least one of the multiple devices via the interconnect according to the bus clock signal; and a clock generation circuit for generating a bus clock signal having an asymmetric duty cycle. Other embodiments are described and claimed.

Description

Technical Field

[0001] Embodiments relate to communication via a multi-drop bus structure. Background Art

[0002] Many different types of buses and other interfaces are known for connecting different components using various interconnect topologies. For example, on-chip buses are used to couple different on-chip components of a given integrated circuit (IC), such as a processor, a system-on-chip, etc. External buses can be used to couple different components of a given computing system via interconnect traces on a circuit board, such as a motherboard, wires, etc.

[0003] The latest multi-point interface technology is the improved bus based on the Integrated Circuit (I3C) specification, which is expected to be available from the Mobile Industry Processor Interface (MIPI) Alliance. TM (www.mipi.org) This interface is intended to be used to connect devices (such as internal or external sensors, etc.) to a host processor, application processor, or standalone device via a host controller or input / output controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of a system according to an embodiment of the present invention.

[0005] Figure 2 is a block diagram of a system according to another embodiment of the present invention.

[0006] Figure 3A is a flowchart of a method according to an embodiment of the present invention.

[0007] Figure 3B is a flowchart of a method according to another embodiment of the present invention.

[0008] Figure 4 is a block diagram of a clock generation circuit according to an embodiment of the present invention.

[0009] Figure 5 is a timing diagram illustrating clock signal generation according to an embodiment.

[0010] Figure 6 An embodiment of a structure consisting of point-to-point links interconnecting a set of components.

[0011] Figure 7 is an embodiment of a system-on-chip design according to an embodiment.

[0012] Figure 8 is a block diagram of a system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] In various embodiments, a bus clock signal with an asymmetric duty cycle can be used to perform read and write operations (or at least one of the read and write operations) along a multi-point bus. That is, since the data changes of the read and / or write operations can be carried out during the low part time period of the periodic bus clock signal, the bus clock signal can be controlled to have a low part time period longer than the high part time period. This asymmetric duty cycle is implemented to relax the timing constraints for being able to transmit the data read from the device, and to provide loose timing constraints in the host controller.

[0014] As will be further described herein, in an exemplary embodiment, a plurality of devices may be coupled to a multi-point bus, including at least one master device and one or more slave devices. During a read operation of the master device (i.e., when the slave device is transmitting data / command information to the master device), the master device may provide a bus clock signal to the slave device. Therefore, there may be strict timing constraints. This is particularly true because, in certain communication modes, the slave device is allowed to change data during the low portion of the bus clock signal so that the master device can reliably sample data on the positive edge of the bus clock signal. Thus, this communication mode, referred to herein as single data rate (SDR) mode, is implemented with a half-cycle path timing that may result in approximately 40 nanoseconds (ns), with bus operation occurring at a rate of 12.5 megahertz (MHz).

[0015] In an embodiment, bus speed can be optimized by providing such an asymmetric duty cycle, wherein the low portion of the bus clock signal is increased and the high portion of the bus clock signal is decreased, while maintaining a given operating frequency of the bus clock signal. In this way, a larger timing budget can be achieved for read / write operations. As a result, system manufacturers such as original equipment manufacturers (OVMs) can have greater flexibility, for example, allowing the use of longer board trace lengths.

[0016] Thus, embodiments use this asymmetric clocking technique for read and (possibly) write operations to implement a long reach solution. As a result, devices are provided with more system timing margin for read and write operations while maintaining a given bus operating frequency. Thus, the bus implementation described herein can be implemented in client and server segments with longer board trace topologies. In this way, bus performance can be improved at a given bus speed (e.g., 12.5 megabits per second (Mbps)) without compromising bus operating speed, while providing flexibility through the configurability of controllable duty cycles as described herein.

[0017] Now refer to Figure 1 , which is a block diagram of a system according to an embodiment of the present invention. More specifically, Figure 1The system 10 shown in the figure represents at least a portion of any one of various different types of computing devices. In different embodiments, the scope of such computing devices can range from relatively small low-power devices (such as smart phones, tablet computers, wearable devices, etc.) to larger devices (such as laptop or desktop computers, server computers, automotive infotainment devices, etc.). In any case, system 10 includes bus 15. In the embodiments herein, bus 15 can be implemented as an I3C bus that meets the upcoming I3C specification. However, it should be understood that the scope of the present invention is not limited thereto, and in other embodiments, bus 15 can be implemented as any type of multi-point interconnection.

[0018] As shown, a primary or main master device 20 is coupled to bus 15. In various embodiments, master device 20 may be implemented as a host controller that includes hardware logic to act as a bus master for bus 15. Master device 20 may include a controller (not shown). Figure 1 ) to control data (SDA) and clock (SCL), and to use, for example, internal current sources or passive pull-ups to maintain bus 15 when all coupled devices are powered off. In some cases, master device 20 may be a relatively simple host controller for a low-complexity bus or other multi-drop bus, such as one compliant with I 2 C or I 3 C specification. Other multi-drop interfaces such as Serial Peripheral Interface and / or Microwire may also be present in certain embodiments.

[0019] In different implementations, the master device 20 can be an interface circuit of a multi-core processor or other system on chip (SoC), an application processor, etc. In other cases, the master device 20 can be an independent host controller (such as a given integrated circuit (IC)) or a main master device for the bus 15. Of course, other implementations are also possible. In other cases, the master device 20 can be implemented as hardware, software and / or firmware or a combination thereof, such as dedicated hardware logic, for example, programmable logic, to perform bus master activities for the bus 15.

[0020] Note that bus 15 is implemented as a two-wire bus, with a single serial line forming the data interconnect and another single serial line forming the clock interconnect. In this way, data communication can occur, for example, in a bidirectional manner, and clock communication can occur in a single direction. Master device 20 can be a relatively computationally complex device (compared to other devices on bus 15) that consumes more power than other devices coupled to bus 15.

[0021] like Figure 1 As shown, there are multiple auxiliary master devices 301-30 NIn various embodiments, the auxiliary master devices 30 (generally) can be implemented as dedicated master devices or bridge devices, such as separate ICs coupled to the bus 15. In other cases, these devices can be independent logic functions of a SoC or other processor (and in some cases can be implemented in the same IC as the master device 20, which is referred to as an auxiliary master). As will be described herein, one or more such auxiliary master devices 30 can be controlled to act as bus masters for the bus 15 when the primary master device 20 is in a low-power state, so that bus operations can continue while in that low-power state.

[0022] like Figure 1 As further shown in FIG, multiple slave devices 401-40 N Also coupled to bus 15. In different embodiments, slave device 40 (generally) can take many different forms. For the purposes of this discussion, it can be assumed that slave device 40 can be an always-on (AON) device, such as a sensor such as a micro-electromechanical system (MEMS), an imaging sensor, a peer device, a debugging device, etc. It should be understood that although Figure 1 The embodiments are shown at this high level, but many variations and alternatives are possible.

[0023] During a read / write operation on bus 15, the timing window available to complete the read / write is approximately 50% of the bus for that period of time. For write mode, this available bus window is as follows: busavail＝ t master +t Skew +t setup <=40ns. For read mode, the available bus window is: t busavail＝ t master +t m-s-m +t Slave +t setup <=40ns, where t master is the host propagation delay (e.g., 5-6ns), t slave is the slave device response time (e.g., 12ns-20ns), t m-s-m is the return path signal from the master-slave-master, t setup is the setup time (e.g., 3ns), and t skew is the total system skew. Note that t can be considered when determining the bus operating frequency. m-s-m and t skew , especially when signal timing is lost more due to reflections and larger signal rise times (non-monotonic rise / fall times), which may limit the platform bus topology to shorter traces and matched routing. Embodiments can relax these timing constraints.

[0024] use Figure 1In this arrangement, a slave device (e.g., slave device 40 or auxiliary master device 30) can change the data to be communicated while the bus clock signal is low. When the master device 20 drives the clock signal, the clock signal can be generated from a system clock signal at a certain frequency (e.g., 10-20 times greater than the bus clock signal), and the asymmetric duty cycle control provides more margin to the slave device.

[0025] In this way, master device 20 can dynamically adjust the low partial time period of bus clock signal with the unit or granularity of system clock signal.In a specific example, the granularity of about 4 nanoseconds can be provided for adjusting the duty cycle of the bus clock signal output from master device 20.In a specific embodiment, this low partial time period can be increased for a larger form factor platform and this low partial time period can be reduced for a smaller form factor platform.And similarly, for a larger form factor platform, the high partial time period can be reduced, and for a smaller form factor platform, the high partial time period can be increased.Utilize this asymmetric duty cycle, allow more time for the falling edge to propagate to slave device 40, thereby provide more time for these devices to drive data line before the next rising edge of bus clock signal.

[0026] Due to the limited time that the read window bus is available in the absence of an embodiment, many system platform topologies provide specification limitations on long distance platform solutions. For example, circuit board traces (FR4) may be limited to 15-20 inches, while standard cable lengths are limited to 0.3 meters (m)-0.5 meters, depending on the type of cable for a given system specification. Many types of computing systems such as client, Internet of Things (IoT), and automotive applications may have longer board traces than 20 inches and cable lengths longer than, for example, 1 meter to 5 meters or more. In addition, certain proprietary slave devices may have longer delays than specified in a given specification, which may also limit the options for slave device selection. Using an embodiment, system designers can provide the flexibility to use long distance solutions for circuit board traces or cables (e.g., for automotive and IoT segments) without limiting the bus operating frequency.

[0027] Embodiments provide techniques for controlling the duty cycle of a bus clock signal transmitted on bus 15. To this end, bus master 20 may receive configuration information including an adjustment value, for example, during boot or otherwise. Based at least in part on the adjustment value, bus master 20 may control the bus clock signal transmitted on bus 15 to have an asymmetric duty cycle. It is understood that the controllable adjustment value may provide bus master 20 with the capability of programmable asymmetric duty cycles, for example, based on a given platform on which the bus master is implemented.

[0028] Now refer to Figure 2, which is a block diagram of a system according to an embodiment of the present invention. Figure 2 As shown, a portion of the system 100 includes a primary host device 105 that is coupled to a plurality of devices 140 via a multi-drop bus 130. A -140 B 1. As further shown, the main master device 105 includes an input / output (I / O) portion 111. Devices 140 (also referred to herein as "slaves") can have different operating characteristics and can also have different capabilities for being added / removed from the bus 130. As will be described herein, the host controller 110 can be configured as a bus master, at least during certain operating phases. The bus 130 is implemented as a two-wire bus, with a single serial line forming a data interconnect and another single serial line forming a clock interconnect. In this way, data communication can occur in a bidirectional manner, and clock communication can occur in a unidirectional manner.

[0029] exist Figure 2 At a high level as shown in FIG, it is assumed that there are different types of devices 140. Device 140 A-B In particular, the device 140 has different physical locations and electrical properties. A may always be powered on and present as coupled to bus 130. As an example, device 140 A It may be a given type of sensor, such as an accelerometer or other sensor that may be incorporated into a given system (e.g., a smartphone or other mobile platform). For the purposes of this discussion, it is assumed that device 140 A Operates as a slave device to the host controller 110 (but can also be configured as an auxiliary bus master). A Corresponding clock receiver 142, receiver 146, and transmitter 144 may be included, all coupled to slave control circuit 145. Of interest here is that slave control circuit 145 may place new write data for communication on bus 130 during the low portion of the received bus clock signal.

[0030] Device 140 B As an example, assume that device 140 B is another type of sensor, such as a camera device. In such an example, the device 140 may be turned on only when the camera function of the system is active. B In other cases, the device 140 B It may be a slave device that can be physically added / removed via hot-plug or hot-replace operations, such as a cable, card, or external peripheral device coupled to the bus 130, for example, via a cable, external connection, etc. In other cases, the device 140 BThe coupling may be via an in-box cable. In this case, the device 140 B There may be a long distance between the device 140 and the host controller 110. B Can be compared with equipment 140 A It is relatively farther away from the host controller 110 .

[0031] like Figure 2 As shown in , host controller 110 includes processing circuitry 112. It is understood that many different types of host controllers may be provided. As an example, host controller 110 may be interface circuitry for a multi-core processor or other SoC, application processor, etc. In other cases, host controller 110 may be a stand-alone host controller for bus 130. Of course, other implementations are possible. In different implementations, processing circuitry 112 may represent one or more cores or other hardware processing logic of a particular device, or it may simply be part of the interface circuitry to act as a transmitter and receiver for host controller 110. Processing circuitry 112 is then coupled to corresponding write control circuitry 124 and read control circuitry 122 via read / write control circuitry 118, coupled to driver 113 that drives data onto bus 130. And read control circuitry 122 is coupled to receiver 114, which receives incoming data via the data lines of bus 130.

[0032] As further shown, read / write control circuitry 118 can provide control signals and data / command information to write control circuitry 124 and read control circuitry 122. Such control signals include write and read enable signals to write control circuitry 124 and read control circuitry 122, respectively. Furthermore, actual data and / or command information to be transmitted via bus 130 (forward or reverse) can also be communicated via read / write control circuitry 118, such that incoming data / command information can be provided from read control circuitry 122 to read / write control circuitry 118 (which can, in turn, provide such information to processing circuitry 112). Additionally, output data / command information, such as originating from processing circuitry 112, can be communicated to write control circuitry 124 via read / write control circuitry 118 for communication from host controller 110.

[0033] Host controller 110 also includes a clock generator 115 for providing a bus clock signal to a clock line of bus 130 (and / or receiving a bus clock signal in some implementations) via a corresponding driver 116. In various embodiments, clock generator 115 may be configured to provide additional clock signals for use in host controller 110 (for ease of illustration, Figure 2 not shown).

[0034] To perform programmable asymmetric duty cycle control of the bus clock signal, clock generator 115 receives an adjustment value (Adjust_dutyclk[3:0]) from read / write control circuit 118, which can store this value in a configuration register. Note that read / write control circuit 118 can receive this value to store in the configuration register at boot time of a system including primary master device 105. In addition, read / write control circuit 118 can also provide a system clock signal to clock generator 115. In various embodiments, the system clock signal can be generated internally within primary master device 105, or can be provided from an off-chip source such as another clock generator, a crystal oscillator, etc.

[0035] In any case, when enabled by the clock enable signal from the read / write control circuit 118, the clock generation circuit 115 can control the generation of the bus clock signal (SCL) to have an asymmetric duty cycle based at least in part on an adjustment value. Although in the embodiments herein, the adjustment value may cause the low portion of the total time period of the clock signal to be greater than the high portion of the total time period, in other cases, the asymmetric duty cycle may be implemented to have a higher portion of the time period that is greater than the lower portion of the time period.

[0036] Note that the system clock signal can run at a much faster rate than the SCL clock. Although the scope of the present invention is not limited in this respect, by way of example, the system clock signal can be between approximately 200-400 MHz, while the bus clock signal can run at a rate of approximately 12.5 MHz.

[0037] Now refer to Figure 3A , shows a flow chart of a method according to an embodiment of the present invention. Figure 3A As shown, method 200 can be performed by hardware, software, firmware, and / or a combination thereof. In a particular embodiment, method 200 can be performed by a clock generation circuit of a bus master device, such as a host controller as described herein. As shown, method 200 is a method for providing control information from a first portion of a clock generation circuit to a second portion of the clock generation circuit. Method 200 begins by receiving a system clock signal and a clock enable (block 210). Note that the system clock signal can be received from an on-chip source or an off-chip source, and the clock enable can indicate that normal operation is to occur.

[0038] At block 220, a counter may be operated based on the system clock signal. In an example embodiment, the counter may be implemented as a 4-bit counter to maintain a counter value between 0 and 15. In an embodiment, the counter may be an up-counter, but in other cases, a down-counter may be used. Still referring to Figure 3A, during normal operation, the counter value may be output to a control circuit (block 230). Note that the control circuit is another (e.g., second) portion of the clock generation circuit as described herein. Thus, during normal operation, the counter value updated according to the system clock signal may be provided to the control circuit in an incremental manner (e.g., starting from a value of 0 and advancing to a value of N-1). It is understood that, although Figure 3A The embodiments are shown at this high level, but many variations and alternatives are possible.

[0039] Now refer to Figure 3B , shows a flow chart of a method according to another embodiment of the present invention. Figure 3B As shown, method 250 can be performed by hardware, software, firmware, and / or a combination thereof, such as a control circuit of a clock generation circuit. As shown, method 250 can begin by receiving an adjustment value from a configuration storage device (block 260). Note that in one embodiment, the adjustment value can be provided at a system reset or other boot operation. In one embodiment, the adjustment value can be a four-bit value. Figure 3B , control then passes to block 270, where the counter value is received. As an example, the frequency of the system clock signal can be obtained from the first part of the clock generation circuit (according to Figure 3A Method 200) receives the counter value.

[0040] Next, at diamond 280, a determination is made as to whether the counter value is at least equal to a threshold value (i.e., the value of N / 2 minus the adjustment value). If not, control passes to block 285 where the bus clock signal may be output at a high value. Thus, in response to the determination that the counter value is less than the threshold value, a high or logic 1 value of the bus clock signal is output via the clock line as part of the high portion of the asymmetric duty cycle. Conversely, if it is determined at diamond 280 that the counter value is at least equal to the threshold value, control passes to block 290 where the bus clock signal may be output at a low value. Thus, in response to the determination that the counter value is at least equal to the threshold value, a low or logic 0 value of the bus clock signal is output via the clock line as part of the low portion of the asymmetric duty cycle. It is understood that although Figure 3B While the embodiments are shown at this high level, many variations and alternatives are possible.

[0041] Although the scope of the present invention is not limited in this respect, embodiments can provide system designers with flexibility for multi-drop buses to cover long-distance solutions for the Internet of Things (IoT), automotive, and client segments. As a result, embodiments do not need to reduce the bus operating frequency for such systems and can extend the maximum operating frequency.

[0042] Now refer to Figure 4 , shows a block diagram of a clock generating circuit according to an embodiment of the present invention. Figure 4 As shown, the clock generation circuit 400 can be implemented as a hardware circuit, but other implementations are also possible. Figure 4 In the particular embodiment shown, clock generation circuit 400 includes counter 410, which can be implemented as an up-counter that counts from 0 to N-1. As shown, when enabled by a clock enable signal, counter 410 is clocked by the system clock signal. In turn, counter 410 provides a counter value output (counter[N:0]) to control circuit 420. In the embodiment herein, control circuit 420 is further coupled to receive the system clock signal and an adjustment value (adjust_dutyclk[3:0]).

[0043] In an embodiment, the control circuit 420 is configured to perform e.g. Figure 3B , to receive the system clock signal and output a bus clock signal (SCL) having an asymmetric duty cycle based on the counter value and the adjustment value. In an embodiment, the control circuit 420 may further include a clock divider circuit for generating a bus clock signal at a given bus clock frequency, such as a fractional integer of the system clock signal. Although Figure 4 While the embodiments are shown at this high level, many variations and alternatives are possible.

[0044] Now refer to Figure 5 , shows a timing diagram of clock signal generation according to an embodiment. Figure 5 As shown, a bus clock signal SCL having a given frequency is generated. Note that the bus clock signal has an asymmetric duty cycle, such that the duration of its high portion of the time period is shorter than the duration of its low portion of the time period. More specifically, as shown in the figure, the high portion of the time period may have (0.5*T period -N*T sysclk ) width, where T period is the time period of the bus clock signal, N is the adjustment value, and T sysclk is the time period of the system clock signal. In turn, the low part time period can have (0.5*T period +N*T sysclk ) width. Note that the value of N can be programmable, for example, depending on the specific devices coupled within the platform via the bus (which can be controllably changed at each system reset). For example, the value of N can be configured by the Basic Input / Output System (BIOS) or other system software. In other cases, the adjustment value can be configured via register programming.

[0045] Note that for a given platform there may be a minimum allowed high fraction period (T high ), so the lower part (T low) is constrained to a certain configurable value (e.g., a relatively small number). However, this configurable value may be sufficient to allow increasing the trace length for various form factors, thereby increasing read and write margins.

[0046] Although for ease of implementation, the bus clock signal can be maintained with a fixed asymmetric duty cycle for all operating phases, embodiments are not limited thereto. That is, in other cases, the asymmetric duty cycle of the bus clock signal can be dynamically controlled only during the bus master read operation from one or more specific slave devices to make it effective. On the contrary, for write operations from the bus master and / or read operations from other slave devices, the bus clock signal can be communicated with a symmetric duty cycle. In addition, although the examples here are about the control of the bus clock signal by the bus master, in some cases, one or more other devices may generate a bus clock signal (with a programmable asymmetric duty cycle), such as in the case of one or more auxiliary bus masters and / or one or more slave devices with advanced computing and internal clock generation capabilities.

[0047] Embodiments may be implemented in various interconnect structures. Figure 6 , shows an embodiment of a structure consisting of point-to-point links interconnecting a set of components. System 600 includes a processor 605 and system memory 610 coupled to a controller hub 615. Processor 605 includes any processing element, such as a microprocessor, a main processor, an embedded processor, a coprocessor, or other processor. Processor 605 is coupled to controller hub 615 via a front-side bus (FSB) 606. In one embodiment, FSB 606 is a serial point-to-point interconnect. In another embodiment, link 606 includes a parallel serial differential interconnect architecture that conforms to different interconnect standards and can be coupled to one or more host controllers to perform asymmetric clock control as described herein.

[0048] System memory 610 includes any memory device, such as random access memory (RAM), nonvolatile (NV) memory, or other memory accessible to devices in system 600. System memory 610 is coupled to controller hub 615 through memory interface 616. Examples of memory interfaces include a double data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

[0049] In one embodiment, controller hub 615 is a root hub, root complex, or root controller in the PCIe interconnect hierarchy. Examples of controller hub 615 include a chipset, a memory controller hub (MCH), a north bridge, an input / output controller hub (ICH), a south bridge, and a root controller / hub. Typically, the term chipset refers to two physically separate controller hubs, a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems typically include an MCH integrated with processor 605, while controller 615 communicates with I / O devices in a similar manner to that described below. In some embodiments, peer-to-peer routing is optionally supported through root complex 615.

[0050] Here, controller hub 615 is coupled to switch / bridge 620 via serial link 619. Input / output modules 617 and 621 (also referred to as interfaces / ports 617 and 621) include / implement a layered protocol stack to provide communication between controller hub 615 and switch 620. In one embodiment, multiple devices can be coupled to switch 620.

[0051] Switch / bridge 620 routes packets / messages from device 625 from upstream (i.e., upward levels) toward the root complex to controller hub 615 and from downstream, i.e., from levels away from the root controller downward from processor 605 or system memory 610 to device 625. In one embodiment, switch 620 is referred to as a logical component of multiple virtual PCI to PCI bridge devices. Device 625 includes any internal or external device or component to be coupled to an electronic system, such as an I / O device, a network interface controller (NIC), an add-on card, an audio processor, a network processor, a hard drive, a storage device, a CD / DVDROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a FireWire device, a Universal Serial Bus (USB) device, a scanner, and other input / output devices, for example, which can be coupled via an I3C bus. Typically in PCIe terminology, such devices are referred to as endpoints. Although not specifically shown, device 625 can include a PCIe to PCI / PCI-X bridge to support traditional or other versions of PCI devices. Endpoint devices in PCIe are typically categorized as legacy, PCIe, or root complex endpoints.

[0052] Graphics accelerator 630 is also coupled to controller hub 615 via serial link 632. In one embodiment, graphics accelerator 630 is coupled to the MCH, which is coupled to the ICH. Switch 620 and corresponding I / O devices 625 are then coupled to the ICH. I / O modules 631 and 618 are also used to implement a layered protocol stack for communication between graphics accelerator 630 and controller hub 615. The graphics controller or graphics accelerator 630 itself can be integrated into processor 605.

[0053] Next turn Figure 7 , depicts an embodiment of a SoC design according to an embodiment. As a specific illustrative example, SoC 700 can be configured to be inserted into any type of computing device from a portable device to a server system. Here, SoC 700 includes two cores 706 and 707. Cores 706 and 707 can conform to an instruction set architecture, such as an ISA based on Architecture Core TM , Advanced Micro Devices (AMD) processors, MIPS-based processors, ARM-based processor designs, or their customers, and their licensees or adopters. Cores 706 and 707 are coupled to a cache control 708, which is associated with a bus interface unit 709 and an L2 cache 710 for communicating with the rest of system 700 via an interconnect 712.

[0054] The interconnect 712 provides a communication channel to other components, such as a subscriber identity module (SIM) 730 that interfaces with a SIM card, a boot ROM 735 that holds boot code for execution by cores 706 and 707 to initialize and boot the SoC 700, an SDRAM controller 740 for interfacing with external memory (e.g., DRAM 760), a flash controller 745 for interfacing with non-volatile memory (e.g., flash memory 765), a peripheral controller 750 (e.g., an eSPI interface) for interfacing with peripherals, a video codec 720, and a video interface 725 for displaying and receiving input (e.g., touch-enabled input), a GPU 715 for performing graphics-related calculations, and the like. Any of these interconnects / interfaces can incorporate aspects described herein, including the asymmetric duty cycle clock control described herein. In addition, the system shows peripherals for communication, such as a Bluetooth module 770, a 3G modem 775, a GPS 780, and a WiFi 785. A power controller 755 is also included in the system.

[0055] Now refer to Figure 8 , which is a block diagram of a system according to an embodiment of the present invention. Figure 8As shown, the multiprocessor system 800 includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850. Figure 8 As shown, each of processors 870 and 880 may be a many-core processor, including representative first and second processor cores (ie, processor cores 874a and 874b and processor cores 884a and 884b).

[0056] Still refer to Figure 8 , the first processor 870 further includes a memory controller hub (MCH) 872 and point-to-point (PP) interfaces 876 and 878. Similarly, the second processor 880 includes an MCH 882 and PP interfaces 886 and 888. Figure 8 As shown, MCHs 872 and 882 couple the processors to respective memories, namely, memory 832 and memory 834, which may be portions of system memory (e.g., DRAM) locally connected to the respective processors. First processor 870 and second processor 880 may be coupled to chipset 890 via PP interconnects 862 and 864, respectively. Figure 8 As shown, chipset 890 includes PP interfaces 894 and 898 .

[0057] In addition, the chipset 890 includes an interface 892 that couples the chipset 890 to the high-performance graphics engine 838 via the PP interconnect 839. Figure 8 As shown, various input / output (I / O) devices 814 may be coupled to first bus 816 along a bus bridge 818 which couples first bus 816 to a second bus 820. Various devices may be coupled to second bus 820 including, for example, a keyboard / mouse 822, communication devices 826, and a data storage unit 828, such as a disk drive or other mass storage device, which may include code 830, in one embodiment. Additionally, an audio I / O 824 may be coupled to second bus 820. Figure 8 Any of the devices shown in can be configured to perform bus master activities (including asymmetric duty cycle clocking) for one or more of the interconnect structures, as described.

[0058] The following embodiments refer to other embodiments.

[0059] In one example, an apparatus includes a host controller coupled to an interconnect that can couple multiple devices. The host controller may include: a first driver configured to drive first information onto the interconnect according to a bus clock signal; a first receiver configured to receive second information from at least one of the multiple devices via the interconnect according to the bus clock signal; and a clock generation circuit configured to generate a bus clock signal having an asymmetric duty cycle.

[0060] In an example, the host controller includes a configuration register for storing an adjustment value, a clock generation circuit for generating a bus clock signal having an asymmetric duty cycle using the adjustment value.

[0061] In an example, the adjustment value is determined based at least in part on a topology of a platform including a plurality of devices and a host controller.

[0062] In an example, the clock generation circuit is configured to generate a bus clock signal having an asymmetric duty cycle formed by a plurality of time periods, each of the plurality of time periods having a low portion time period and a high portion time period, the low portion time period being longer than the high portion time period.

[0063] In an example, the host controller further includes a read controller coupled to the first receiver to read the second information during a high portion of the bus clock signal.

[0064] In an example, the read controller is configured to sample the second information at a positive edge transition of the bus clock signal from the low portion of the time period to the high portion of the time period.

[0065] In an example, the clock generation circuit is configured to receive a system clock signal with a symmetrical duty cycle and generate a bus clock signal with an asymmetrical duty cycle based thereon.

[0066] In an example, the clock generation circuit includes a counter for receiving a system clock signal and maintaining a counter value based on the system clock signal.

[0067] In an example, the clock generation circuit further includes a control circuit for receiving the adjustment value and the counter value, and outputting the bus clock signal having an asymmetric duty cycle in response to the counter value and the adjustment value.

[0068] In an example, the counter counts between 0 and N-1, and the adjustment value comprises a configurable value between 0 and N-1.

[0069] In the example, the adjustment value will be set by the firmware when the device is reset.

[0070] In an example, a host controller includes a master device for sending a bus clock signal to a plurality of devices including a plurality of slave devices.

[0071] In an example, the first receiver is configured to receive second information from a first slave device that transmits the second information during a low portion of a bus clock signal received from the host controller.

[0072] In another example, a method includes receiving an adjustment value in a control circuit of a clock generation circuit of a host controller coupled to one or more slave devices via a bus; receiving a counter value according to a system clock signal in the control circuit; comparing the counter value with a threshold value in the control circuit, the threshold value being based at least in part on a width of the counter and the adjustment value; and outputting a bus clock signal on the bus having an asymmetric duty cycle based on a result of the comparison of the counter value with the threshold value.

[0073] In an example, the method further includes outputting the bus clock signal with an asymmetric duty cycle, wherein a low portion time period is greater than a high portion time period.

[0074] In an example, the method further includes receiving first information in the host controller from a first slave device coupled to the bus and sampling the first information at a rising edge of a bus clock signal, the first slave device changing data of the first information during a low portion of a time period of the bus clock signal.

[0075] In another example, a computer readable medium comprising instructions is used to perform the method of any of the above examples.

[0076] In another example, a computer-readable medium including data is to be used by at least one machine to fabricate at least one integrated circuit to perform the method of any of the above examples.

[0077] In another example, an apparatus includes means for performing the method of any of the above examples.

[0078] In another example, a system includes: a host controller for generating a bus clock signal having an asymmetric duty cycle for communicating on a bus, the host controller having a read controller for reading data transmitted from a first device coupled to the host controller via the bus on a rising edge of the bus clock signal; a first device coupled to the host controller via the bus, wherein the first device provides data to the bus during a low portion of the bus clock signal; and a second device coupled to the host controller via the bus.

[0079] In an example, the host controller includes a configuration register for storing an adjustment value, the adjustment value used by the host controller to generate a bus clock signal having an asymmetric duty cycle.

[0080] In an example, the host controller is configured to receive a system clock signal having a symmetrical duty cycle and generate a bus clock signal based thereon.

[0081] In an example, the host controller includes a counter for receiving a system clock signal and maintaining a counter value based on the system clock signal, the host controller outputting a bus clock signal having a high value when the counter value is small, and outputting a bus clock signal having a low value when the counter value is at least equal to a threshold value, the threshold value being based at least in part on the adjustment value.

[0082] In yet another example, an apparatus includes: a clock generation unit for generating a bus clock signal having an asymmetric duty cycle; a clock driver unit for driving the bus clock signal having an asymmetric duty cycle on a bus coupling the apparatus to a plurality of devices; a data driver unit for driving first information onto the bus according to the bus clock signal having an asymmetric duty cycle; and a receiver unit for receiving second information from at least one device of the plurality of devices via the bus according to the bus clock signal having an asymmetric duty cycle.

[0083] In an example, the apparatus further includes a configuration storage unit for storing an adjustment value, and the clock generation unit is configured to generate a bus clock signal having an asymmetric duty cycle using the adjustment value.

[0084] In an example, the clock generation unit is configured to receive a system clock signal with a symmetrical duty cycle and generate a bus clock signal with an asymmetrical duty cycle based thereon.

[0085] In an example, the clock generation unit includes a counter unit for receiving a system clock signal and maintaining a counter value based on the system clock signal.

[0086] In an example, the clock generation unit further includes a control unit for receiving the adjustment value and the counter value, and outputting the bus clock signal having an asymmetric duty cycle in response to the counter value and the adjustment value.

[0087] In an example, the clock generation unit is configured to generate a bus clock signal having an asymmetric duty cycle formed by a plurality of time periods, each of the plurality of time periods having a low portion time period and a high portion time period, the low portion time period being longer than the high portion time period. In an example, the apparatus further includes a read control unit configured to read second information during the high portion time period of the bus clock signal having the asymmetric duty cycle.

[0088] It will be appreciated that various combinations of the above examples are possible.

[0089] Note that the terms "circuit" and "circuitry" are used interchangeably herein. As used herein, these terms and the term "logic" are used alone or in any combination to refer to analog circuits, digital circuits, hard-wired circuits, programmable circuits, processor circuits, microcontroller circuits, hardware logic circuits, state machine circuits, and / or any other type of physical hardware component. Embodiments may be used in many different types of systems. For example, in one embodiment, a communication device may be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to communication devices, and rather, other embodiments may relate to other types of apparatus for processing instructions, or include one or more machine-readable media that, in response to execution on a computing device, cause the device to perform one or more of the methods and techniques described herein.

[0090] The embodiments may be implemented in code and may be stored on a non-transitory storage medium having instructions stored thereon, which instructions may be used to program a system to execute the instructions. The embodiments may also be implemented in data and may be stored on a non-transitory storage medium, which, if used by at least one machine, causes at least one machine to manufacture at least one integrated circuit to perform one or more operations. Further embodiments may be implemented in a computer-readable storage medium comprising information that, when manufactured as a SoC or other processor, will configure the SoC or other processor to perform one or more operations. The storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a solid-state drive (SSD), a compact disk read-only memory (CD-ROM), a compact disk rewritable disk (CD-RW) and a magneto-optical disk, a semiconductor device such as a read-only memory (ROM), a random access memory (RAM) such as a dynamic random access memory (DRAM), a static random access memory (SRAM), an erasable programmable read-only memory (EPROM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a magnetic card or an optical card, or any other type of medium suitable for storing electronic instructions.

[0091] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations that fall within the true spirit and scope of the present invention.

Claims

1. A device for generating a bus clock signal, comprising: A host controller coupled to the interconnect to which a plurality of devices are capable of being coupled, the host controller comprising: a first driver for driving first information onto the interconnect according to the bus clock signal; a first receiver for receiving second information from at least one device of the plurality of devices via the interconnect in accordance with the bus clock signal; a clock generating circuit for generating the bus clock signal having an asymmetric duty cycle; and Configuration registers, which are used to store adjustment values, The clock generation circuit is configured to use the adjustment value to generate the bus clock signal having the asymmetric duty cycle.

2. The device according to claim 1, wherein The adjustment value is determined based at least in part on a topology of a platform including the plurality of devices and the host controller.

3. The device according to claim 1, wherein The clock generation circuit is configured to generate the bus clock signal having an asymmetric duty cycle formed by a plurality of time periods, each of the plurality of time periods having a low portion time period and a high portion time period, the low portion time period being longer than the high portion time period.

4. The device according to claim 3, wherein The host controller further includes a read controller coupled to the first receiver to read the second information during the high portion of the bus clock signal.

5. The device according to claim 4, wherein The read controller is configured to sample the second information at a positive edge transition of the bus clock signal from the low portion of the time period to the high portion of the time period.

6. The device according to claim 1, wherein The clock generation circuit is configured to receive a system clock signal with a symmetrical duty cycle and generate the bus clock signal with the asymmetrical duty cycle based on the system clock signal.

7. The device according to claim 6, wherein The clock generation circuit includes a counter for receiving the system clock signal and maintaining a counter value based on the system clock signal.

8. The device according to claim 7, wherein The clock generation circuit further includes a control circuit configured to receive the adjustment value and the counter value, and output the bus clock signal having the asymmetric duty cycle in response to the counter value and the adjustment value.

9. The device according to claim 7, wherein The counter counts between 0 and N-1, and the adjustment value comprises a configurable value between 0 and N-1.

10. The device of claim 1, wherein: The adjustment value is set by firmware upon reset of the device.

11. The device according to claim 1, wherein The host controller includes a master device for sending the bus clock signal to the plurality of devices, including a plurality of slave devices.

12. The device according to claim 11, wherein The first receiver is configured to receive the second information from a first slave device, and the first slave device is configured to transmit the second information during a low portion of a bus clock signal received from the host controller.

13. A method for controlling a bus clock signal, comprising: receiving the adjustment value in a control circuit of a clock generation circuit of a host controller coupled to one or more slave devices via a bus; receiving a counter value in the control circuit according to a system clock signal; In the control circuit, comparing the counter value to a threshold value, the threshold value being determined based at least in part on a width of the counter and the adjustment value; as well as The bus clock signal is output on the bus with an asymmetric duty cycle according to a comparison result of the counter value and the threshold value.

14. The method of claim 13, further comprising outputting the bus clock signal having the asymmetric duty cycle, wherein The low part of the time period is greater than the high part of the time period.

15. The method of claim 14, further comprising: First information is received in the host controller from a first slave device coupled to the bus and is sampled on a rising edge of the bus clock signal, the first slave device being configured to change data of the first information during the low portion of the bus clock signal.

16. A computer-readable storage medium comprising computer-readable instructions for implementing the method of any one of claims 13 to 15 when executed.

17. A system for generating a bus clock signal, comprising: a host controller for generating the bus clock signal having an asymmetric duty cycle for communicating on a bus, the host controller having a read controller for reading data transmitted from a first device coupled to the host controller via the bus at a rising edge of the bus clock signal, wherein the host controller includes a configuration register for storing an adjustment value, and wherein the host controller is configured to use the adjustment value to generate the bus clock signal having the asymmetric duty cycle; the first device coupled to the host controller via the bus, wherein the first device is configured to provide the data to the bus during a low portion of the bus clock signal; and A second device is coupled to the host controller via the bus.

18. The system of claim 17, wherein: The host controller is configured to receive a system clock signal with a symmetrical duty cycle and generate the bus clock signal based thereon.

19. The system of claim 18, wherein: The host controller includes a counter for receiving the system clock signal and maintaining a counter value based on the system clock signal, the host controller for outputting the bus clock signal having a high value when the counter value is less than a threshold and outputting the bus clock signal having a low value when the counter value is at least equal to the threshold, the threshold being based at least in part on the adjustment value.

20. An apparatus for generating a bus clock signal, comprising: a clock generating unit for generating the bus clock signal having an asymmetric duty cycle; a clock driver unit for driving said bus clock signal having said asymmetric duty cycle on a bus coupling said apparatus to a plurality of devices; a data driver unit for driving first information onto the bus according to the bus clock signal having the asymmetric duty cycle; a receiver unit for receiving second information from at least one device of the plurality of devices via the bus according to the bus clock signal having the asymmetric duty cycle; as well as A configuration memory cell for storing adjustment values, The clock generation unit is configured to use the adjustment value to generate the bus clock signal having the asymmetric duty cycle.

21. The apparatus of claim 20, wherein: The clock generation unit is configured to receive a system clock signal with a symmetrical duty cycle and generate the bus clock signal with the asymmetrical duty cycle based on the system clock signal.

22. The apparatus of claim 21, wherein: The clock generation unit includes a counter unit for receiving the system clock signal and maintaining a counter value based on the system clock signal.

23. The apparatus of claim 22, wherein: The clock generation unit further includes a control unit for receiving the adjustment value and the counter value, and outputting the bus clock signal having the asymmetric duty cycle in response to the counter value and the adjustment value.

24. The apparatus of claim 20, wherein: The clock generation unit is configured to generate the bus clock signal having the asymmetric duty cycle formed by a plurality of time periods, each of the plurality of time periods having a low portion time period and a high portion time period, the low portion time period being longer than the high portion time period.

25. The apparatus of claim 24, further comprising a read control unit for reading the second information during the high portion of the bus clock signal having the asymmetric duty cycle.

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