A charging pile detection system

Abstract

The present invention provides a charging pile detection system; the charging pile detection system comprises a data acquisition component, a data processing component, a data display component and a mechanical control component; the data acquisition component is composed of various sensors and is used to collect voltage and current data of the charging pile; the data processing component comprises an A / D sampling board, a differential transmission board and an FPGA processing mainboard, which are used for data processing, and send a display signal to the data display component, and send a control signal to the mechanical control component; the data display component comprises a host computer display software and a liquid crystal display, which are used to display detection data, and send a user's command signal to the data processing component; the mechanical control component comprises a driving component and a circuit machine, which are used to receive a control signal and perform related mechanical actions at the same time; this power supply system can meet customers' needs for charging pile detection, and greatly facilitates the staff who perform charging pile detection.

Description

Technical Field

[0001] The present invention relates to the field of electrical design, and in particular to a charging pile detection system. Background Art

[0002] At present, the electronic industry and digital circuits are developing continuously, and various electronic products with different functions are entering people's lives. The biggest highlight of the electronics industry is the continuous development and improvement of integrated circuit technology, such as the circuits used are becoming smaller and smaller, the speed is constantly increasing, and the energy consumption and cost are constantly falling. In the next few years, new electronic devices based on digital logic will continue to enter people's lives, their costs will continue to decrease, and their performance will continue to improve.

[0003] With the increasing popularity of electric vehicles, people's demand for electric vehicle charging piles is constantly increasing. The power supply stability of charging piles in daily use has become one of the current research hotspots. In the development of electric vehicles, the charging pile detection system is indispensable. It is one of the key systems to ensure the power supply stability of electric vehicle charging piles. A complete charging pile detection system is a reliable guarantee for the stability of the charging pile power supply. Only by timely detecting the fault signals and unqualified signals of the charging piles and eliminating the faults can the power supply stability of the charging piles be improved. Due to the influence of various factors, traditional charging piles often have high design costs, long development cycles, complex use steps, and cannot achieve good human-computer interaction. These have greatly increased the complexity of the work of relevant staff and affected the timely elimination of charging pile faults, which has greatly restricted the popularity of electric vehicles. Summary of the invention

[0004] In order to solve the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a charging pile detection system and a working method to meet the development trend of electronic circuits.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a charging pile detection system; the charging pile detection system includes a data acquisition component, a data processing component, a data display component and a mechanical control component; the data acquisition component is in direct contact with the charging pile to be detected, and is used to collect the voltage and current data of the charging pile; the data processing component receives the data of the data acquisition component, processes the data, and sends the display signal to the data display component, and sends the control signal to the mechanical control component; the data display component is used to display the detection data, and send the user's command signal to the data processing component; the mechanical control component is used to receive the control signal of the data processing component and perform related mechanical actions.

[0006] The data acquisition component includes a voltage sensor, a current sensor and a harmonic measurement device; the voltage sensor is used to detect the voltage signal in the charging pile; the current sensor is used to detect the current signal in the charging pile; the harmonic measurement device is used to detect the harmonics in the charging pile.

[0007] The data processing component includes an A / D sampling board, a differential transmission board and an FPGA processing main board; the A / D sampling board is used to convert the analog signal of the sensor into a digital signal; the differential transmission board is used to send the sampled data to the FPGA processing main board, and send the AD control timing signal of the FPGA processing main board to the A / D sampling board; the FPGA processing main board is used to perform circuit calculations on the sampled data, provide control signals for the mechanical control component, and send the calculated data to the data display component for display.

[0008] The data display component includes a host computer display software and a liquid crystal display; the host computer display software is used to receive system display data and send user control data to the FPGA processing mainboard; the liquid crystal display is used to display and receive user control data; the host computer display software is set on the liquid crystal display display interface.

[0009] The mechanical control component includes a driving component and a circuit machine; the driving component is used to receive the control signal of the FPGA processing mainboard and send the control signal to the circuit machine; the circuit machine performs relevant mechanical actions according to the control signal.

[0010] The present invention also provides a working method using the charging pile detection system, the method comprising the following steps:

[0011] 1) Start AD conversion and perform A / D sampling. The A / D conversion chip is a 4-channel 12-bit ADS7841E chip, which is controlled by a clock for serial input. The A2, A1, and A0 bits in the chip DIN are channel selection bits, and the MODE bit is the 12b-it / 8bit conversion selection bit; select high-precision 12bit conversion and single-ended conversion of the SGL / DIF bit;

[0012] 2) The AD converted data is sent to the FPGA processing mainboard for data processing;

[0013] 3) The FPGA processing motherboard uses a mean elimination algorithm; the so-called mean elimination algorithm is to subtract the current value of a sample from a reference value and then take the absolute value. If the result exceeds a certain threshold, it means that it does not meet the requirements and the data is discarded; assuming that the random variable X has a mathematical expectation μ and variance σ 2, then, for any positive number ε, the inequality holds, which is the Chebyshev inequality, μ is the expectation of the normal distribution, σ is the mean square error of the normal distribution; if ε=3σ, then P{|X-μ|<3σ}≥0.8889; when the random variable X obeys the normal distribution of (μ, σ), P{|X-μ|<3σ}≥0.9974; for a normal random variable X, it is almost inevitable that its value falls within the interval [μ-3σ, μ+3σ], that is, the 3σ rule;

[0014] 4) If the data processed by the FPGA meets the conditions in step 2, i.e., the 3σ rule, the system starts the mechanical control component and performs the relevant mechanical rejection operation;

[0015] 5) If the data processed by the FPGA does not meet the conditions in step 2, return to step 1 and perform AD conversion and A / D sampling again;

[0016] 6) The FPGA program sends the generated rejection signal to the data display component, and the data is displayed on the host computer.

[0017] Preferably, the system synchronization of the working method is controlled by a shaft encoder to ensure the consistency of the system during operation.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0019] (1) The present invention utilizes FPGA program to perform charging pile detection, which has the advantages of high reusability, convenient programming, low design cost, short development cycle, flexible control, and high rejection rate.

[0020] (2) The present invention combines data processing components with mechanical control components. When a fault signal appears on the charging pile, automatic troubleshooting can be achieved. The degree of automation is high, which reduces the workload of relevant staff.

[0021] (3) The present invention combines the data processing component with the data display component to realize human-computer interaction, making it convenient for relevant staff to monitor the status of the charging pile. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural schematic diagram of a charging pile detection system of the present invention;

[0023] Figure 2 A working flow chart of a charging pile detection system of the present invention;

[0024] Figure 3 It is a schematic diagram of the structure of the FPGA mainboard chip of the present invention. DETAILED DESCRIPTION

[0025] In order to further understand the structure, features and other purposes of the present invention, the preferred embodiments are described in detail with reference to the accompanying drawings as follows. The embodiments described in the drawings are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention.

[0026] First, if Figure 1 As shown, Figure 1 It is a structural schematic diagram of a charging pile detection system of the present invention; the charging pile detection system includes a data acquisition component, a data processing component, a data display component and a mechanical control component; the data acquisition component is in direct contact with the detected charging pile, and is used to collect the voltage and current data of the charging pile; the data processing component receives the data of the data acquisition component, processes the data, and sends the display signal to the data display component, and sends the control signal to the mechanical control component; the data display component is used to display the detection data, and send the user's command signal to the data processing component; the mechanical control component is used to receive the control signal of the data processing component and perform related mechanical actions.

[0027] The data acquisition component includes a voltage sensor, a current sensor and a harmonic measurement device; the voltage sensor is used to detect the voltage signal in the charging pile; the current sensor is used to detect the current signal in the charging pile; the harmonic measurement device is used to detect the harmonics in the charging pile.

[0028] The data processing component includes an A / D sampling board, a differential transmission board and an FPGA processing main board; the A / D sampling board is used to convert the analog signal of the sensor into a digital signal; the differential transmission board is used to send the sampled data to the FPGA processing main board, and send the AD control timing signal of the FPGA processing main board to the A / D sampling board; the FPGA processing main board is used to perform circuit calculations on the sampled data, provide control signals for the mechanical control component, and send the calculated data to the data display component for display.

[0029] The data display component includes a host computer display software and a liquid crystal display; the host computer display software is used to receive system display data and send user control data to the FPGA processing mainboard; the liquid crystal display is used to display and receive user control data; the host computer display software is set on the liquid crystal display display interface.

[0030] The mechanical control component includes a driving component and a circuit machine; the driving component is used to receive the control signal of the FPGA processing mainboard and send the control signal to the circuit machine; the circuit machine performs relevant mechanical actions according to the control signal.

[0031] For further information, see Figure 2 , Figure 2The following is a working flow chart of a charging pile detection system of the present invention; the method mainly comprises the following steps:

[0032] 1) Start AD conversion and perform A / D sampling. The A / D conversion chip is a 4-channel 12-bit ADS7841E chip, which is controlled by a clock for serial input. The A2, A1, and A0 bits in the chip DIN are channel selection bits, and the MODE bit is the 12b-it / 8bit conversion selection bit; select high-precision 12bit conversion and single-ended conversion of the SGL / DIF bit;

[0033] 2) The AD converted data is sent to the FPGA processing mainboard for data processing;

[0034] 3) The FPGA processing motherboard uses a mean elimination algorithm; the so-called mean elimination algorithm is to subtract the current value of a sample from a reference value and then take the absolute value. If the result exceeds a certain threshold, it means that it does not meet the requirements and the data is discarded. Assume that the random variable X has a mathematical expectation μ and a variance σ 2 , then, for any positive number ε, the inequality holds, which is the Chebyshev inequality, μ is the expectation of the normal distribution, σ is the mean square error of the normal distribution; if ε=3σ, then P{|X-μ|<3σ}≥0.8889; when the random variable X obeys the normal distribution of (μ, σ), P{|X-μ|<3σ}≥0.9974; for a normal random variable X, it is almost inevitable that its value falls within the interval [μ-3σ, μ+3σ], that is, the 3σ rule;

[0035] 4) If the data processed by the FPGA meets the conditions in step 2, i.e., the 3σ rule, the system starts the mechanical control component and performs the relevant mechanical rejection operation;

[0036] 5) If the data processed by the FPGA does not meet the conditions in step 2, return to step 1 and perform AD conversion and A / D sampling again;

[0037] 6) The FPGA program sends the generated rejection signal to the data display component, and the data is displayed on the host computer.

[0038] Also, see Figure 3 , Figure 3The schematic diagram of the structure of the FPGA motherboard chip of the present invention; the system adopts EP3C16Q FPGA for control logic programming. The device is a CycloneII series high-performance field programmable gate array produced by ALXERA, and has rich logic resources. EP3C16Q has 15408 logic units, 56 embedded multipliers and 4 phase-locked loops (PLLs), its internal RAM capacity is 504Kbits, the system frequency is as high as 260MHz, and the stability is very high. Using a single-chip FPGA to realize logic control and data processing functions can simplify circuit design, improve system reliability and save costs. Not only can it be repeatedly programmed, but it is also very convenient to debug the circuit.

[0039] Finally, the specific technical features of a charging pile detection system and working method of the present invention are as follows:

[0040] (1) The present invention utilizes FPGA program to perform charging pile detection, which has the advantages of high reusability, convenient programming, low design cost, short development cycle, flexible control, and high rejection rate.

[0041] (2) The present invention combines data processing components with mechanical control components. When a fault signal appears on the charging pile, automatic troubleshooting can be achieved. The degree of automation is high, which reduces the workload of relevant staff.

[0042] (3) The present invention combines the data processing component with the data display component to realize human-computer interaction, making it convenient for relevant staff to monitor the status of the charging pile.

[0043] It should be noted that the above invention content and specific implementation methods are intended to demonstrate the practical application of the technical solution provided by the present invention and should not be interpreted as limiting the scope of protection of the present invention. Those skilled in the art can make various modifications, equivalent substitutions or improvements within the spirit and principles of the present invention. The scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A charging pile detection system, characterized in that: The charging pile detection system includes a data acquisition component, a data processing component, a data display component and a mechanical control component; wherein the data acquisition component is in direct contact with the detected charging pile and is used to collect voltage and current data of the charging pile; the data processing component receives data from the data acquisition component, processes the data, and sends a display signal to the data display component and a control signal to the mechanical control component; the data display component is used to display the detection data and send the user's command signal to the data processing component; the mechanical control component is used to receive the control signal of the data processing component and perform related mechanical actions; The data acquisition component includes a voltage sensor, a current sensor and a harmonic measurement device; wherein the voltage sensor is used to detect the voltage signal in the charging pile; the current sensor is used to detect the current signal in the charging pile; the harmonic measurement device is used to detect the harmonics in the charging pile; The data processing component includes an A / D sampling board, a differential transmission board and an FPGA processing main board; wherein the A / D sampling board is used to convert the analog signal of the sensor into a digital signal; the differential transmission board is used to send the sampled data to the FPGA processing main board, and send the AD control timing signal of the FPGA processing main board to the A / D sampling board; the FPGA processing main board is used to perform circuit calculations on the sampled data, provide control signals for the mechanical control component, and send the calculated data to the data display component for display; The data display component includes a host computer display software and a liquid crystal display; wherein the host computer display software is used to receive system display data and send user control data to the FPGA processing mainboard; the liquid crystal display is used to display and receive user control data; the host computer display software is set on the liquid crystal display display interface; The mechanical control component includes a driving component and a circuit mechanism; wherein the driving component is used to receive the control signal of the FPGA processing mainboard and send the control signal to the circuit mechanism; the circuit mechanism performs relevant mechanical actions according to the control signal.

2. A working method using the charging pile detection system according to claim 1, the method comprising the following steps: 1) Start AD conversion and perform A / D sampling. The A / D conversion chip is a 4-channel 12-bit ADS7841E chip, which is controlled by a clock for serial input. The A2, A1, and A0 bits in the chip DIN are channel selection bits, and the MODE bit is the 12b-it / 8bit conversion selection bit; select high-precision 12bit conversion and single-ended conversion of the SGL / DIF bit; 2) The AD converted data is sent to the FPGA processing mainboard for data processing; 3) The FPGA processing motherboard uses a mean elimination algorithm; the so-called mean elimination algorithm is to subtract the current value of a sample from a reference value and then take the absolute value. If the result exceeds a certain threshold, it means that it does not meet the requirements and the data is discarded; assuming that the random variable X has a mathematical expectation μ and variance σ 2 , then, for any positive number ε, the inequality If it holds, then it is Chebyshev's inequality, μ is the expectation of the normal distribution, and σ is the mean square error of the normal distribution; if ε=3σ, then P{|X-μ|<3σ}≥0.8889; when the random variable X obeys the normal distribution of (μ, σ), P{|X-μ|<3σ}≥0.9974; for a normal random variable X, it is almost inevitable that its value falls within the interval [μ-3σ, μ+3σ], which is the 3σ rule; 4) If the data processed by the FPGA meets the conditions in step 2, i.e., the 3σ rule, the system starts the mechanical control component and performs the relevant mechanical rejection operation; 5) If the data processed by the FPGA does not meet the conditions in step 2, return to step 1 and perform AD conversion and A / D sampling again; 6) The FPGA program sends the generated rejection signal to the data display component, and the data is displayed on the host computer.

3. The working method according to claim 2, characterized in that: The system synchronization of the working method is controlled by a shaft encoder to ensure the consistency of the system during operation.

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