A storage device that stores data in order based on barrier commands

Abstract

A method of programming data into a storage device including a non-volatile storage device, comprising: receiving, from a host, a first barrier command to a third barrier command; receiving, from the host, first data to third data corresponding to the first barrier command to the third barrier command; combining the first barrier command and the second barrier command and sequentially programming the first data and the second data into the non-volatile storage device based on the order of the first barrier command and the second barrier command; verifying completion of programming of both the first data and the second data, and mapping mapping information of the first data and the second data when the programming of the first data and the second data is completed; and mapping out information of both the first data and the second data when programming of at least one of the first data and the second data is not completed; and programming the third data into the non-volatile storage device after mapping in or mapping out.

Description

[0001] Cross - Reference to Related Applications

[0002] Claims priority to U.S. Provisional Patent Application No. 62 / 616,718, filed on January 12, 2018, and Korean Patent Application No. 10 - 2018 - 0068127, filed on June 14, 2018, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The disclosure herein relates to a storage device, and more particularly, to a storage device that stores data in order based on a barrier command. Background Art

[0004] Data stored in a storage device as a non - volatile storage medium can be retained permanently or semi - permanently regardless of whether the storage device is powered on. Generally, such a storage device can first store data provided from a host to a buffer memory, and then can store the data from the buffer memory to non - volatile memory. However, due to the above - mentioned programming operation, before storing data in non - volatile memory, the data is first stored in the buffer memory, so the order of write requests from the host may not be guaranteed.

[0005] To ensure the write order, the host can transfer data to the storage device, wait until the transferred data is stored (or flushed) to the non - volatile memory of the storage device, and then transfer the next data to the storage device. However, this operation may degrade the performance of the host. Therefore, there is a need for a storage device that can guarantee the order of write requests without degrading the performance of the host. Summary of the Invention

[0006] Embodiments of the inventive concept provide a storage device that stores data in order based on a barrier command.

[0007] Embodiments of the inventive concept provide a method for programming data into a storage device including a non-volatile storage device, the method including: receiving, by the storage device, a first barrier command, a second barrier command, and a third barrier command from a host; receiving, by the storage device, first data corresponding to the first barrier command, second data corresponding to the second barrier command, and third data corresponding to the third barrier command from the host; merging, by the storage device, the first barrier command and the second barrier command, and sequentially programming the first data and the second data into the non-volatile storage device based on the order of the first barrier command and the second barrier command; verifying, by the storage device, completion of programming of both the first data and the second data; when programming of the first data and the second data is completed, mapping, by the storage device, mapping information of the first data and the second data into a mapping table of the storage device, and when programming of at least one of the first data and the second data is not completed, mapping out mapping information of both the first data and the second data; and after mapping in and mapping out, programming, by the storage device, the third data into the non-volatile storage device.

[0008] Embodiments of the inventive concept also provide an operating method of a memory controller controlling a non-volatile storage device, including receiving, by the memory controller, a first barrier command and a first programming command, a second barrier command and a second programming command, and a third barrier command and a third programming command from a host; receiving, by the memory controller, first data corresponding to the first barrier command, second data corresponding to the second barrier command, and third data corresponding to the third barrier command from the host; merging, by the memory controller, the first to third barrier commands, and sequentially programming the first to third data into the non-volatile storage device; and verifying, by the memory controller, whether the first to third data are programmed, and when all of the first to third data are programmed, classifying the first to third data as valid data, and when at least one of the first to third data is not programmed, classifying the first to third data as invalid data.

[0009] Embodiments of the inventive concept also provide a computer system, which includes: a host; and a storage device configured to receive a first barrier command, a second barrier command, and a third barrier command from the host, and first data, second data, and third data corresponding to the first barrier command, the second barrier command, and the third barrier command, respectively. The storage device includes: a plurality of non-volatile storage devices configured to store the first data, the second data, and the third data; and a memory controller configured to control the plurality of non-volatile storage devices, merge the first barrier command, the second barrier command, and the third barrier command, sequentially program the first data, the second data, and the third data into the non-volatile storage devices, determine whether the programming of the first data, the second data, and the third data is completed, map the first data, the second data, and the third data into a mapping table of the storage device as valid data when the programming of all of the first data, the second data, and the third data is completed, and map the first data, the second data, and the third data out to the mapping table as invalid data when the programming of at least one of the first data, the second data, and the third data is not completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 FIG. 1 is a block diagram of a computer system according to an embodiment of the inventive concept.

[0012] Figure 2 FIG. 2 shows Figure 1 a timing diagram of operations in which a host performs logging.

[0013] Figure 3 FIG. 3 shows Figure 1 a block diagram of a controller.

[0014] Figure 4 FIG. 4 is a diagram showing operations in which a storage device does not support barrier commands according to an embodiment of the inventive concept.

[0015] Figure 5 FIG. 5 is a diagram showing operations in which a storage device processes barrier commands according to an embodiment of the inventive concept.

[0016] Figure 6 FIG. 6 is a diagram showing operations in which a storage device processes barrier commands according to another embodiment of the inventive concept.

[0017] Figure 7 FIG. 7 is a diagram showing operations in which a storage device processes barrier commands according to another embodiment of the inventive concept.

[0018] Figure 8A diagram showing an operation in which a storage device processes received barrier commands in order and all data is programmed normally according to an embodiment of the inventive concept.

[0019] Figure 9 A diagram showing an embodiment of the inventive concept Figure 8 in which a storage device processes received barrier commands in order and all data is not programmed.

[0020] Figure 10 A diagram showing an operation in which a storage device processes received barrier commands in order and data is programmed normally according to another embodiment of the inventive concept.

[0021] Figure 11 A diagram showing another embodiment of the inventive concept Figure 10 in which a storage device processes received barrier commands in order and another diagram of an operation in which all data is not programmed normally.

[0022] Figure 12 A diagram showing an operation in which a storage device processes received barrier commands in order according to another embodiment of the inventive concept.

[0023] Figure 13 A diagram showing an operation in which a storage device processes received barrier commands in order according to another embodiment of the inventive concept.

[0024] Figure 14 A diagram showing Figure 1 a block diagram of a non-volatile memory in a non-volatile storage device.

[0025] Figure 15 A diagram showing Figure 14 a circuit diagram of a first block of a three-dimensional memory block included in a memory cell array of.

[0026] Figure 16 A diagram showing Figure 1 a flowchart of an operation method of a storage device.

[0027] Figure 17 A diagram showing a software stack of a host that supports a system call for a write order according to an embodiment of the inventive concept.

[0028] Figure 18 A diagram showing Figure 17 a timing diagram of an operation in which a host performs logging on a storage device.

[0029] Figure 19A graph showing the IOPS (Input / Output Operations Per Second) and command queue depth of a storage device according to an embodiment of the inventive concept. Detailed Description of the Invention

[0030] Embodiments of the inventive concept will be described in detail and clearly below to the extent that a person of ordinary skill in the art can easily implement the inventive concept.

[0031] As is traditional in the field of the inventive concept, embodiments may be described and illustrated in terms of blocks that perform one or more of the described functions. These blocks may be referred to herein as units or modules, etc., and are physically implemented by analog and / or digital circuitry, such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, etc., and may optionally be driven by firmware and / or software. The circuitry may be embodied, for example, in one or more semiconductor chips or on a substrate support such as a printed circuit board. The circuitry constituting the blocks may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware implementing some functions of the blocks and a processor implementing other functions of the blocks. Without departing from the scope of the inventive concept, each block of an embodiment may be physically separated into two or more interacting and discrete blocks. Similarly, without departing from the scope of the inventive concept, the blocks of an embodiment may be physically combined into more complex blocks.

[0032] Figure 1 A block diagram of a computer system according to an embodiment of the inventive concept is shown. The computer system 10 includes a host 100 and a storage device 200. The computer system 10 may be applied to or implemented within an electronic device, such as, for example, a personal computer, a server, a workstation, a notebook, a tablet, a mobile device, a smart phone, etc. The host 100 may transfer barrier commands and data to the storage device 200 (e.g., a solid state drive (SSD)). The storage device 200 may store data based on the barrier commands. The host 100 may issue barrier commands to notify the write order of data to the storage device 200, and the storage device 200 may follow or maintain the write order of data requested by the host 100 based on the barrier commands. The host 100 includes a processing unit 110, a host memory 120, and an interface (I / F) circuit 130.

[0033] The processing unit 110 may run software loaded onto the main memory 120. For example, the processing unit 110 may run application programs, file systems, block input / output schedulers, and device drivers. The processing unit 110 may include a homogeneous multi-core processor or a heterogeneous multi-core processor. For example, the processing unit 110 may include at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), and a neural processing unit (NPU).

[0034] The operating system OS (operating system) that manages all the hardware and software in the computer system 10 may be loaded onto the host memory 120. Specifically, the application program 121 included in the user space, the file system 122 included in the kernel space, the block input / output (I / O) scheduler 123, and the device driver 125 may be loaded onto the host memory 120. The software layers 121 to 123 and 125 loaded onto the host memory 120 may be included in a software stack for accessing the storage device 200. The host memory 120 may include a storage medium such as, for example, a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device.

[0035] The application program 121 may run as a basic (or default) service or may be run at the request of the user (or in response to the request of the user). The user space storing the application program 121 and the kernel space storing the kernel including the file system 122, the block I / O scheduler 123, the device driver 125, etc. may be separated from each other. The application program 121 cannot directly access resources such as the storage device 200. Instead, the application program 121 may call a function defined in a library (not shown) containing system call functions and may request necessary tasks from the kernel. In the case of calling the system call function, the mode may be switched from user mode to kernel mode.

[0036] The file system 122 may manage files or data stored in the storage device 200. For example, the file system 122 may include FAT (file allocation table), NTFS TM (new technology file system), HFS (hierarchical file system), HPFS (high-performance file system), UFS (unix file system), ext2 (secondary extended file system), ext3, ext4, JFS (journaling file system), ISO 9660, File-11, VxFS (veritas file system), ZFS TM , ReiserFS, UDF (universal disk format), etc. In particular, the file system 122 may perform logging to prevent the consistency of databases, files, or data from being unable to be maintained due to sudden power off (SPO) or system crashes.

[0037] The block I / O scheduler 123 may exist in the block layer. The block I / O scheduler 123 may receive an IO request from the file system 122 and may store the received IO request in the scheduler queue 124. The block I / O scheduler 123 may manage the scheduler queue 124. The block I / O scheduler 123 may merge IO requests or may adjust the order (reorder) of the IO requests. For example, the scheduler queue 124 may include a Noop scheduler, a Deadline scheduler, an Anticipatory scheduler, a completely fair queuing (CFQ) scheduler, etc.

[0038] The device driver 125 is a program that operates as part of the kernel to control hardware devices such as the storage device 200. The device driver 125 may remove an IO request from the scheduler queue 124 and may generate a command for controlling the storage device 200. The device driver 125 may process the IO requests of the scheduler queue 124. For example, the device driver 125 may be a block device that performs data input / output on the storage device 200 in blocks. In other embodiments, the programs and software layers loaded onto the host memory 120 are not limited toFigure 1 Example of

[0039] Interface circuit 130 may provide a physical connection between host 100 and storage device 200. For example, interface circuit 130 may convert (or translate) commands, addresses, and data corresponding to various IO requests generated from host 100 according to a scheme for communicating with storage device 200.

[0040] Host 100 may transfer barrier commands and data to storage device 200. Host 100 may request storage device 200 to write data in order by issuing a barrier command. Storage device 200 may receive a barrier command and data corresponding to the barrier command from host 100. Storage device 200 includes a controller 210, a buffer memory 220, and a non-volatile memory device 230.

[0041] Controller 210 (or memory controller) may process commands received from host 100. Controller 210 may control the operations of buffer memory 220 and non-volatile memory device 230. Controller 210 may store or buffer data received from host 100 in buffer memory 220, whose data I / O speed is faster than that of non-volatile memory device 230, and then may write or program the data stored in buffer memory 220 into non-volatile memory device 230.

[0042] In one embodiment, controller 210 and interface circuit 130 may communicate with each other based on one or more of various interface protocols, such as, for example, universal serial bus (USB), small computer system interface (SCSI), peripheral component interconnect express (PCIe), non-volatile memory express (NVME), mobile PCIe (M-PCIe), advanced technology attachment (ATA), parallel ATA (PATA), serial ATA (SATA), serial attached SCSI (SAS), integrated drive electronics (IDE), universal flash storage (UFS), and FirewireTM 。

[0043] The buffer memory 220 may temporarily store data received from the host 100 or data received from the non-volatile memory device 230. The buffer memory 220 may store a mapping table that indicates the relationship between the logical address LA (logical address, LA) (or logical block address LBA (logical block address, LBA)) of the host 100 and the physical address PA (physical address) (or physical block address PBA (physical block address, PBA)) of the non-volatile memory device 230. The buffer memory 220 may be implemented by using a DRAM device or an SRAM device.

[0044] The non-volatile memory device 230 may include a non-volatile memory that communicates with the controller 210 through a first channel CH1, a non-volatile memory that communicates with the controller 210 through a second channel CH2, and a non-volatile memory that communicates with the controller 210 through a third channel CH3. The number of channels between the non-volatile memory device 230 and the controller 210 is not limited to Figure 1 the example shown. Each non-volatile memory may include, for example, non-volatile memory cells such as NAND flash memory cells, NOR flash memory cells, resistive random access memory (RERAM) cells, ferroelectric random access memory (FRAM) cells, phase change random access memory (PRAM) cells, or magnetic random access memory (MRAM) cells. Hereinafter, a description will be given on the assumption that each of the first to third non-volatile memories includes NAND flash memory cells.

[0045] In one embodiment, the controller 210 may use the buffer memory 220 as a cache memory. The controller 210 may store and merge data corresponding to the programming units of the non-volatile memory device 230 into the buffer memory 220, and may simultaneously program the merged data into the non-volatile memory device 230. The lifespan and performance of the non-volatile memory device 230 may be improved by the above operations, but the data sets may not be programmed into the non-volatile memory device 230 in the order of the write commands received from the host 100. Here, the term "data set" may be used to indicate various forms of data respectively corresponding to the write commands, and the data set may be referred to as "multi-data" or "multiple data". The host 100 may issue a barrier command so that the data sets are programmed into the non-volatile memory device 230 in order based on the type of data to be stored in the storage device 200 or the application 121.

[0046] Figure 2 shows Figure 1 a timing diagram of the operation of the host performing logging. Reference will be made to Figure 1 describe Figure 2 . For example, an operating system (e.g., Android TM OS) loaded on the host memory 120 may frequently generate cache flush commands. The operating system may generate cache flush commands to ensure that the data is actually programmed into the non-volatile memory device 230, but may generate cache flush commands to ensure the order in which the data sets are written into the non-volatile memory device 230. As described above, the file system 122 may perform logging. In the case where the host 100 modifies a part of the database file, the host 100 may back up the original data to be modified to the log, may modify the database file, and may delete the log. The file system 122 may transmit a cache flush command to the storage device 200 for committing the log transaction or maintaining the consistency of the database. The cache flush command may be used to maintain the write order.

[0047] Reference Figure 2, when backing up the log or after modifying the database file, system calls such as fsync() can be invoked. In the case where fsync() starts, the file system 122 can insert (or queue) the write request into the scheduler queue 124 of the block layer for transferring the file data "D" to the storage device 200. The write request can be dispatched to the storage device 200. The file system 122 waits until the direct memory access (DMA) transfer of the file data "D" is completed. The DMA transfer can mean that a DMA controller (not shown) in the host 100 independent of the processing unit 110 directly exchanges data with the storage device 200. In the case where the DMA transfer of the file data "D" is completed, the file system 122 can trigger the journal block device (hereinafter referred to as "JBD (journal block device)") to commit the journal transaction. The JBD can be a thread running in a part of the host memory 120, and the file system 122 protects it for logging.

[0048] The JBD can insert the write request into the scheduler queue 124 for transferring the log data JD to the storage device 200. The write request can be dispatched by the device driver 125 to the storage device 200. The JBD waits until the DMA transfer of the log data JD is completed. In the case where the DMA transfer of the log data JD is completed, the file system 122 can insert the flush request into the scheduler queue 124 so that the log data JD is flushed from the buffer memory 220 to the non-volatile memory device 230. The flush request can be dispatched by the device driver 125 to the storage device 200 (i.e., the transfer of the cache flush command). In the case where the flush of the log data JD is completed, the write request inserted into the scheduler queue 124 can be dispatched to the storage device 200. In the case where the DMA transfer of the log commit JC is completed according to the write request and the log commit JC is fully flushed, fsync() can return. Only after the log commit JC is written to the non-volatile memory device 230 can the file system 122 commit the journal record transaction. After committing the journal record transaction, the file system 122 can perform another operation.

[0049] Reference Figure 2 , in order to maintain the write order during the operation of logging, the file system 122 must wait until the DMA transfer of the file data "D", the DMA transfer and flush of the log data JD, and the DMA transfer and flush of the log commit JC are all completed. Reference Figure 2The described logging may neutralize parallel processing in the storage device 200, or may reduce the depth of the command queue of the controller 210. Specifically, the operation of the host 100 may be delayed by the time required for unit programming in the storage device 200. Thus, the host 100 may generate a barrier command instead of a cache flush command to maintain the write order and reduce the latency caused by the cache flush command. The host 100 may issue a barrier command instead of a cache flush command and may perform another operation without waiting for the operation of the storage device 200 corresponding to the barrier command to complete.

[0050] In one embodiment, the barrier command may be defined in the interface protocol between the host 100 and the storage device 200. The barrier command may occupy one entry of the scheduler queue 124 described above. In another embodiment, the host 100 may set a write command as a barrier command by setting a flag (e.g., REQ_BARGE) of the write command. The storage device 200 may decode the flag of the write command and may determine whether the write command is a barrier command. The storage device 200 may store the data corresponding to the barrier command in order. The barrier command may include a programming command, i.e., a write command.

[0051] An example of calling fsync() is shown in Figure 2 , but fdatasync() may be called. fdatasync() is similar to fsync(). fsync() may modify file metadata. However, when fdatasync() is called, the file metadata may not be modified without additionally modifying the file metadata for reading the newly written data.

[0052] Figure 3 is a block diagram of the controller shown Figure 1 . Reference will be made to Figure 1 for a description Figure 3 . The controller 210 includes a processing unit 211, a working memory 212, a host interface (I / F) circuit 214, a buffer memory interface (I / F) circuit 215, and a flash memory interface circuit 216. The controller 210 may be implemented, for example, by using a system on chip (SoC), an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). The buffer memory 220 may be provided independently of the controller 210, as Figure 1 shown, or may be included in the controller 210, as Figure 2 shown.

[0053] The processing unit 211 may decode the commands provided from the host 100. The processing unit 211 may control the operations of the other components 212 to 216 of the controller 210 based on the commands. The processing unit 211 may run a flash translation layer (FTL) for performing garbage collection for managing the non-volatile memory device 230, a mapping table indicating the relationship between logical addresses and physical addresses, wear leveling, etc. The processing unit 211 may include at least one of the above-described processing units.

[0054] The working memory 212 may operate as a cache memory. The working memory 212 may store the decoding results of the processing unit 211. For example, a command queue 213 storing commands CMD1 to CMD3 in the order of the commands CMD1 to CMD3 transmitted from the host 100 may be allocated to an area of the working memory 212. Here, the number of commands to be stored in the command queue 213 is not limited to Figure 3 the example shown. Different from Figure 3 the illustration of, the command queue 213 may be placed in the processing unit 211 or in a partial area of the buffer memory 220.

[0055] The host interface circuit 214 may communicate with the host 100 according to the above communication protocol. For example, the host interface circuit 214 may operate according to the NVMe protocol. The processing unit 211 may receive commands through the host interface circuit 214 and may insert the received commands into the command queue 213 in order.

[0056] The buffer memory interface circuit 215 may control the read operation and the write operation of the buffer memory 220 under the control of the processing unit 211. The buffer memory interface circuit 215 may provide a mapping table indicating the relationship between logical addresses and physical addresses to the buffer memory 220. The buffer memory interface circuit 215 may provide the data stored in the buffer memory 220 to the host interface circuit 214 or the flash memory interface circuit 216. The buffer memory interface circuit 215 may provide the data provided from the host interface circuit 214 or the flash memory interface circuit 216 to the buffer memory 220.

[0057] The buffer memory 220 may include an area to which the write-back cache 221 is allocated and an area to which the write buffer 222 is allocated. For example, in the case where the size of the data provided from the host 100 and corresponding to the command is smaller than the programming unit of the non-volatile memory device 230, the data may be stored in the write-back cache 221. In the case where the size of the data provided from the host 100 and corresponding to the command is not smaller than the programming unit of the non-volatile memory device 230, the data may be stored in the write buffer 222.

[0058] The flash interface circuit 216 can exchange data with the non-volatile memory device 230. The flash interface circuit 216 can write the data provided from the buffer memory 220 into the non-volatile memory device 230 through Figure 1 channels CH1 to CH3. The flash interface circuit 216 can receive data from the non-volatile memory device 230 through channels CH1 to CH3, and can provide the received data to the buffer memory 220. Hereinafter, various examples in which the controller 210 processes the barrier command will be described.

[0059] Figure 4 and Figure 5 FIG. shows an operation of a storage device processing a barrier command according to an embodiment of the inventive concept. Reference will be made to Figure 1 together with Figure 4 and Figure 5 . The command queue 213, write-back cache 221, write buffer 222, and non-volatile memory device 230 of the storage device 200 (reference Figure 1 ) are shown only for convenience of description. The non-volatile memory device 230 may include a plurality of blocks. However, in Figure 4 and Figure 5 only one block is shown. The block may include at least one or more physical pages. The physical page may include storage units corresponding to a read unit or a write (or program) unit. The storage units of the block may correspond to an erase unit.

[0060] The controller 210 of the storage device 200 may sequentially receive a first write command WCMD1, a second barrier command BCMD2, and a third write command WCMD3, and the first write command WCMD1, the second barrier command BCMD2, and the third write command WCMD3 may be sequentially inserted into the command queue 213. Assume that Figure 4 the storage device 200 does not support the second barrier command BCMD2, and Figure 5 the storage device 200 supports the second barrier command BCMD2 and maintains the write order. Also, assume that each of the size of the first data DATA1 corresponding to the first write command WCMD1 and the size of the second data DATA2 corresponding to the second barrier command BCMD2 is 4KB, which is less than the programming unit (e.g., 16KB) of the non-volatile memory device 230, and the size of the third data DATA3 corresponding to the third write command WCMD3 is 16KB, which is the same as the programming unit of the non-volatile memory device 230. In Figure 4 and Figure 5An example is shown in which the programming units of the non-volatile memory device 230 match the size of the physical pages. In other embodiments, the programming units may be different from the size of the physical pages.

[0061] For example, the controller 210 may simultaneously program multiple physical pages through multi-channel, multi-way, and multi-plane in an interleaving scheme to reduce the programming time of the non-volatile memory device 230. That is, the programming units of the non-volatile memory device 230 may be determined according to the number of channels connecting the non-volatile memory device 230 and the controller 210, the number of channels connected to each channel, the number of planes of the non-volatile memory, the size of the physical pages, and the number of bits stored in the memory cells.

[0062] The controller 210 may store the first data DATA1 and the second data DATA2, the sizes of which are smaller than the programming units, into the write-back cache 221. For example, the controller 210 may merge data sets smaller than the programming units into the write-back cache 221, and may program the merged data corresponding to the programming units into the non-volatile memory device 230. The write-back cache 221 may be used to merge data sets, the sizes of which are smaller than the programming units. The controller 210 may store the third data DATA3 corresponding to the programming units into the write buffer 222. The write buffer 222 may be used to store data, the size of which is the same as or larger than the programming units.

[0063] Reference Figure 4 , before another data is merged into the first data DATA1 and the second data DATA2, each of the first data DATA1 and the second data DATA2 does not correspond to the programming units, and the third data DATA3 corresponding to the programming units may be programmed into the non-volatile memory device 230 before the second data DATA2. In the case where the third data DATA3 is programmed and then SPO (i.e., sudden power-off) or system crash occurs, the first data DATA1 and the second data DATA2 already stored in the write-back cache 221 may be lost. Figure 4 The controller 210 of cannot program the first data DATA1, the second data DATA2, and the third data DATA3 in order according to the second barrier command BCMD2.

[0064] On the contrary, Figure 5The controller 210 can decode the second barrier command BCMD2 and can program the first data DATA1, the second data DATA2, and the third data DATA3 in order. The controller 210 can merge a part (e.g., 8KB) of the first data DATA1, the second data DATA2, and the third data DATA3 and can program the merged data into the non-volatile memory device 230. Here, the size of the merged data can correspond to a programming unit. Even if the size of the second data DATA2 corresponding to the second barrier command BCMD2 is smaller than the programming unit, the controller 210 can borrow any other data from the write-back cache 221 or the write buffer 222, can merge the borrowed data and the second data DATA2, and can program the merged data corresponding to the programming unit into the non-volatile memory device 230. That is, the controller 210 can maintain the write order of the second data DATA2 based on the second barrier command BCMD2.

[0065] Figure 6 FIG. shows an operation of a storage device processing a barrier command according to another embodiment of the inventive concept. Reference will be made to Figure 1 and Figure 5 together. Figure 6 . Reference Figure 4 and Figure 5 described assumptions can also be applied to Figure 6 , and it is assumed that Figure 6 the storage device 200 supports the second barrier command BCMD2 and maintains the write order.

[0066] Returning again Figure 5 , in a case where the controller 210 merges a part of the third data DATA3 with the second data DATA2, the remaining part of the third data DATA3 can be programmed into another physical page. Even if the size of the third data DATA3 corresponds to the programming unit, the third data DATA3 can be divided into different pages and can be programmed into different pages. In this case, in order to read all of the third data DATA3, the non-volatile memory device 230 must activate at least two physical pages in which the third data DATA3 is stored.

[0067] Reference Figure 6, the controller 210 may merge the first data DATA1 and the second data DATA2 with dummy data instead of the third data DATA3. The controller 210 may adjust the size of the second data DATA2 corresponding to the second barrier command BCMD2 to a programming unit by using the dummy data. The controller 210 may merge the first data DATA1, the second data DATA2, and the dummy data, program the merged data corresponding to the programming unit into a physical page of the non-volatile memory device 230, and then program the third data DATA3 into another physical page of the non-volatile memory device 230. Here, the position of the physical page in which the second data DATA2 is programmed and the position of the physical page in which the third data DATA3 is programmed may be adjacent to each other or may be away from each other. The controller 210 may maintain the write order of the second data DATA2 based on the second barrier command BCMD2.

[0068] Figure 7 FIG. illustrates an operation in which a storage device processes a barrier command according to another embodiment of the inventive concept. Reference will be made together Figure 1 and Figure 5 described Figure 7 . The assumptions described with reference to Figure 4 and Figure 5 may also be applied to Figure 7 , and it is assumed that Figure 7 the storage device 200 supports the second barrier command BCMD2 and maintains the write order.

[0069] The controller 210 may store the first data DATA1 and the second data DATA2 stored in the write-back cache 221 into the first block BLK1, and then may store the third data DATA3 stored in the write buffer 222 into the second block BLK2. Although not shown in Figure 7 , the controller 210 may merge Figure 6 the first data DATA1, the second data DATA2, and the dummy data, and may store the merged data into the first block BLK1.

[0070] In Figure 7Among them, the first data DATA1 and the second data DATA2 smaller than the programming unit may be hot data that is updated relatively frequently, and the third data DATA3 corresponding to the programming unit may be cold data that is not updated relatively frequently. The controller 210 may separate the first block BLK1 storing the hot data and the second block BLK2 storing the cold data, while maintaining the write order of the second data DATA2 based on the second barrier command BCMD2. For example, each of the memory cells in the first block BLK1 may be a single level cell (SLC) storing one bit, and each of the memory cells in the second block BLK2 may be a multi-level cell (MLC) storing at least two bits.

[0071] Reference Figures 5 to 7 , the controller 210 may perform a programming operation in the following order: 1) program the first data DATA1 received before the second data DATA2 corresponding to the second barrier command BCMD2 into the non-volatile memory device 230, 2) program the second data DATA2 into the non-volatile memory device 230, and 3) program the third data DATA3 received after the second data DATA2 into the non-volatile memory device 230. Although not shown in Figures 5 to 7 , the first data DATA1 may be programmed, another data may be programmed, and the second data DATA2 may be programmed. In addition, the second data DATA2 may be programmed, another data may be programmed, and the third data DATA3 may be programmed. In all cases, the controller 210 may maintain the write order of the second data DATA2 regardless of whether another data is programmed.

[0072] Figure 8 And Figure 9 show diagrams of operations in which a storage device processes received barrier commands in order according to an embodiment of the inventive concept. Figure 8 And Figure 9 will be described together and will be described with reference to Figure 1 In Figure 8 And Figure 9Among them, it is assumed that the size of each of the first data DATA1 to the fourth data DATA4 corresponds to a programming unit. In the computer system 10, the host 100 can sequentially transmit the first barrier command BCMD1 to the third barrier command BCMD3 to the storage device 200, and can transmit the first data DATA1 to the third data DATA3 to the storage device 200 in the DMA scheme. The host 100 can sequentially transmit the first barrier command BCMD1, the first data DATA1, the second barrier command BCMD2, the second data DATA2, the third barrier command BCMD3, and the third data DATA3. The first data DATA1 can be sequentially provided after receiving the first barrier command BCMD1. The second data DATA2 can be sequentially provided after receiving the second barrier command BCMD2. However, the host 100 can transmit the second barrier command BCMD2 while transmitting the first data DATA1.

[0073] The controller 210 of the storage device 200 can sequentially receive the first barrier command BCMD1 to the third barrier command BCMD3 from the host 100, and can sequentially insert the first barrier command BCMD1 to the third barrier command BCMD3 into the command queue 213. The controller 210 can receive the first data DATA1 to the third data DATA3 corresponding to the first barrier command BCMD1 to the third barrier command BCMD3 respectively, and can store the first data DATA1 to the third data DATA3 in the buffer memory 220 (①).

[0074] The controller 210 can decode the first barrier command BCMD1 to the third barrier command BCMD3, and can sequentially program the first data DATA1 to the third data DATA3 into the non-volatile memory device 230 (②) in the order of receiving the first barrier command BCMD1 to the third barrier command BCMD3. The controller 210 can atomically execute the programming operations of the first data DATA1 to the third data DATA3. In the case where the controller 210 executes the atomic programming operation, all of the first data DATA1 to the third data DATA3 can be normally programmed into the non-volatile memory device 230 (refer to Figure 8 ), or all of the first data DATA1 to the third data DATA3 may not be programmed into the non-volatile memory device 230 (refer to Figure 9)。According to the atomic programming operation, a situation where only a part of the first data DATA1 to the third data DATA3 is not programmed into the non-volatile memory device 230 does not occur. The controller 210 may program the first data DATA1 to the third data DATA3 into the non-volatile memory device 230 and may commit the programming operations of the first data DATA1 to the third data DATA3. Alternatively, the controller 210 may roll back without programming the first data DATA1 to the third data DATA3. After completing the atomic programming operation on the first data DATA1 to the third data DATA3, the controller 210 may program the fourth data DATA4 into the non-volatile memory device 230. Figure 8 and Figure 9 a command for the fourth data DATA4 is not shown in

[0075] Referring to Figure 8 , the first data DATA1 may be programmed into the first physical page <p1>, the second data DATA2 can be programmed into the second physical page <p2>, and the third data DATA3 can be programmed into the third physical page <p3>(Atomic programming is successful). In this case, the controller 210 may map or update the mapping information of the first to third physical pages <P1:P3> in the mapping table L2P (③). Here, the term "map in" may represent the operation of the controller 210 updating the mapping information of the first to third physical pages <P1:P3> in the mapping table L2P. The controller 210 may classify all the first data DATA1 to the third data DATA3 as valid data through the map-in operation. The controller 210 may map in the first data DATA1 to the third data DATA3.

[0076] Reference Figure 9 , the first data DATA1 may be programmed into the first physical page <p1>; The third data DATA3 can be programmed into the third physical page <p3>, but due to SPO or system crash (atomic programming failure), the second data DATA2 may not be programmed into the second physical page <p2>. In this case, the controller 210 can map out the first physical page in the mapping table L2P <p1>and the third physical page <p3>mapping information and the second physical page <p2>The mapping information (③). Here, the term "mapping out" may indicate an operation in which the controller 210 does not update the mapping information of the first to third physical pages <P1:P3> in the mapping table L2P. The controller 210 may classify all the first data DATA1 to the third data DATA3 as invalid data through the mapping out operation. The controller 210 may perform garbage collection on the first data DATA1 to the third data DATA3, and may erase the first data DATA1 to the third data DATA3 (④).

[0077] Figure 10 and Figure 11 FIG. shows an operation of a storage device sequentially processing received barrier commands according to another embodiment of the inventive concept. Figure 10 and Figure 11 will be described together and will be described with reference to Figure 1 description. Similar to Figure 8 and Figure 9 the case of, the controller 210 may sequentially receive the first barrier command BCMD1 to the third barrier command BCMD3, and may sequentially insert the first barrier command BCMD1 to the third barrier command BCMD3 into the command queue 213. The controller 210 may merge and process multiple barrier commands. For example, the controller 210 may merge the first barrier command BCMD1 and the second barrier command BCMD2. The controller 210 may first process the merged first barrier command BCMD1 and the second barrier command BCMD2, and then may process the third barrier command BCMD3.

[0078] The controller 210 may receive the first data DATA1 to the third data DATA3 respectively corresponding to the first barrier command BCMD1 to the third barrier command BCMD3, and may store the first data DATA1 to the third data DATA3 in the buffer memory 220 (①). The controller 210 may sequentially program the first data DATA1 and the second data DATA2 into the second page of the non-volatile memory device 230 based on the order of the first barrier command BCMD1 and the second barrier command BCMD2 <p2>and the third page <p3>Next, the controller 210 may program the commit page to the fourth page of the non-volatile memory device 230 <p4>, a programming operation (②) for determining whether to submit the first data DATA1 and the second data DATA2.

[0079] The controller 210 can determine whether to submit the first data DATA1 and the second data DATA2 by reading the submission page. The controller 210 can read or scan the first physical page <p1>and the fourth physical page <p4>The submission page, and can determine whether to submit the programming operations of the first data DATA1 and the second data DATA2 between the submission pages. Refer to Figure 10 , the controller 210 can classify the first data DATA1 and the second data DATA2 as valid data, and can map them into the first physical page in the mapping table L2P <p1>and the second physical page <p2>mapping information (③).

[0080] On the contrary, referring to Figure 11 , due to SPO or system crash, the second data DATA2 may not be programmed into the third physical page <p3>, the submission page may not be programmed to the fourth physical page <p4>。The controller 210 may classify the first data DATA1 and the second data DATA2 as invalid data, and may map out the first physical page in the mapping table L2P <p1>and the second physical page <p2>mapping information (③). Here, even when the second data DATA2 is programmed into the third physical page <p3>and only the submission page is not programmed to the fourth physical page <p4>In this case, the controller 210 can also map out the first physical page in the mapping table L2P <p1>and a second physical page <p2>The mapping information (③). After that, the controller 210 can perform garbage collection on the first data DATA1 and the second data DATA2 (④).

[0081] Map in or map out the first physical page in the mapping table L2P <p1>and the second physical page <p2>After the mapping information of, the controller 210 can program the third data DATA3 into the fifth physical page <p5>Next, the controller 210 can program the commit page to the sixth physical page <p6>, a programming operation (④) for determining whether to submit the third data DATA3. The controller 210 can read or scan the submission page and can determine whether to submit the programming operation of the third data DATA3 between the submission pages.

[0082] Reference Figure 10 , the controller 210 can program to the fourth physical page <p4>and the sixth physical page <p6>The fifth physical page between <p5>The third data DATA3 is classified as valid data and can be mapped into the fifth physical page in the mapping table L2P <p5>mapping information (⑤). Refer to Figure 11 , the controller 210 can program to the first physical page <p1>and the sixth physical page <p6>The fifth physical page between <p5>The third data DATA3 is classified as valid data and can be mapped into the fifth physical page in the mapping table L2P <p5>mapping information (⑤). For example, referring to Figure 11 , the time to perform garbage collection on the first data DATA1 and the second data DATA2 can be after the time (⑤) when the third data DATA3 is programmed.

[0083] Figure 12 FIG. shows an operation in which a storage device sequentially processes received barrier commands according to another embodiment of the inventive concept. Reference will be made to Figure 1 for description Figure 12 . In Figure 12 , it is assumed that all atomic programming operations of data are successful.

[0084] Similar to the case of Figures 8 to 11 , the controller 210 can sequentially receive the first barrier command BCMD1 to the third barrier command BCMD3, and can sequentially insert the first barrier command BCMD1 to the third barrier command BCMD3 into the command queue 213. For example, the controller 210 can merge the second barrier command BCMD2 and the third barrier command BCMD3. The controller 210 can first process the first barrier command BCMD1, and then can process the merged second barrier command BCMD2 and third barrier command BCMD3. The controller 210 can receive the first data DATA1 to the third data DATA3 corresponding to the first barrier command BCMD1 to the third barrier command BCMD3 respectively, and can store the first data DATA1 to the third data DATA3 in the buffer memory 220 (①).

[0085] Different from the case of Figures 8 to 11 , the controller 210 can program data together with flag information into the non-volatile memory device 230, rather than only programming data into the non-volatile memory device 230. The flag information can mark the barrier command indicating the write order of the data.

[0086] The epoch of the data can be determined according to the barrier command of the host 100. The epoch number represents the epoch of the data and is used to distinguish the first programmed data from the subsequently programmed data with respect to the barrier command. The controller 210 can include the epoch number of the data in the flag information of the data. The controller 210 can assign the same epoch number to the data set corresponding to the merged barrier command. Referring to Figure 12 , the controller 210 can assign the first epoch number EP<1> to the first data DATA1, and can assign the second epoch number EP<2> to the second data DATA2 and the third data DATA3. The commit record bit "C" can be included in the flag information of the data by the controller 210. Similar to in the commit page, the commit record bit "C" can be used to determine whether to commit the programming operation of the data.

[0087] The controller 210 may program the first data DATA1, the first period number EP<1>, and the commit record bit "C" into the first physical page of the non-volatile memory device 230 <p1>(②). The controller 210 can handle the first physical page <p1>The first data DATA1 and the first physical page in the data area <p1>Program the first epoch number EP<1> and the submission record bit "C" in the spare area of. However, different from Figure 12 As shown, in other embodiments, the first epoch number EP<1> and the submission record bit "C" can be stored in different pages or different blocks of the non-volatile memory device 230.

[0088] The controller 210 can read the first physical page <p1>The submission record bit is "C", and it is possible to determine whether to submit the programming operation of the first data DATA1. The controller 210 can classify the first data DATA1 as valid data and map it into the first physical page in the mapping table L2P <p1>mapping information (③).

[0089] Similar to in the first data DATA1, the controller 210 can program the second data DATA2 and the second epoch number EP2 into the second physical page P2, and program the third data DATA3, the second epoch number EP2, and the commit record bit "C" into the third physical page P3 (④). The controller 210 can read the third physical page <p3>The submission record bit is "C", and the programming operation of whether to submit the second data DATA2 and the third data DATA3 can be determined. The controller 210 can classify the second data DATA2 and the third data DATA3 as valid data, and can map them into the second physical page in the mapping table L2P <p2>and the third physical page <p3>Mapping information (⑤).

[0090] In an embodiment of the inventive concept, the controller 210 may program the commit record bit "C" together with the final programming data of the data set corresponding to the merged command and having the same sequence number (refer to Figure 12 , the third data DATA3). The controller 210 may not include the commit record bit "C" in the flag information of the remaining data of the data set having the same sequence number other than the final programming data. In other embodiments, the controller 210 may rearrange the write order in the data set corresponding to the merged command and having the same sequence number. For example, the controller 210 may program the third data DATA3 into the second physical page <p2>, and program the second data DATA2 and the submission record bit "C" into the third physical page <p3>。

[0091] Figure 13 A diagram illustrating the operation in which a storage device processes received barrier commands in sequence according to another embodiment of the inventive concept will be described with reference to Figure 1 description Figure 13 In Figure 13 , it is assumed that all atomic programming operations of data are successful, and the size of each of the first data DATA1 to the third data DATA3 is smaller than the programming unit.

[0092] As in the case of Figures 8 to 12 , the controller 210 may receive the first barrier command BCMD1 to the third barrier command BCMD3 in sequence and may insert the first barrier command BCMD1 to the third barrier command BCMD3 into the command queue 213 in sequence. For example, the controller 210 may merge the first barrier command BCMD1 to the third barrier command BCMD3. For example, the controller 210 may merge the barrier commands based on the size of the barrier data. The size of the data set corresponding to the merged barrier commands may be the programming unit.

[0093] The controller 210 may receive the first data DATA1 to the third data DATA3 corresponding to the first barrier command BCMD1 to the third barrier command BCMD3, respectively, and may store the first data DATA1 to the third data DATA3 in the buffer memory 220(①). For example, the first data DATA1 may be 8KB, the second data DATA2 may be 4KB, the third data DATA3 may be 4KB, and the size of the merged data set may be 16KB and may be the programming unit.

[0094] The controller 210 may program the first data DATA1 to the third data DATA3 into the first physical page of the non-volatile memory device 230 <p1>(②). Although not shown in Figure 13 , the controller 210 may be in the first physical page <p1>The flag information of the first data DATA1 to the third data DATA3 (i.e., Figure 12 the period number and the submission record bit) is programmed in the spare area. In other embodiments of the inventive concept, the positions of the first data DATA1 to the third data DATA3 may be rearranged by the controller 210 without limitation and may be different from Figure 13 as shown. The controller 210 may classify the first data DATA1 to the third data DATA3 as valid data and may map them into the first physical page in the mapping table L2P <p1>Mapping information (③).

[0095] Figure 14 shows Figure 1 A block diagram of a non-volatile memory in a non-volatile storage device. The non-volatile memory 231 includes a memory cell array 231_1, an address decoder 231_2, a page buffer 231_3, an input / output (I / O) circuit 231_4, and a control logic and voltage generation circuit 231_5. The non-volatile memory 231 may also be referred to as a "non-volatile memory chip".

[0096] The memory cell array 231_1 may include a plurality of memory blocks. Each of the memory blocks may include a plurality of cell strings. Each of the cell strings may include memory cells. The memory cells may be connected to word lines WL. Each memory cell may include a single-level cell (SLC) storing one bit or a multi-level cell (MLC) storing at least two bits.

[0097] In one embodiment, the memory cell array 231_1 may include a three-dimensional memory array. The three-dimensional (3D) memory array may be monolithically formed in one or more physical levels of the memory cell array, which has an active area on a circuit disposed on a silicon substrate, the circuit being related to the operation of the memory cells. The circuit associated with the operation of the memory cells may be located in or on the substrate. The term "monolithic" means that each layer of each level of the 3D memory array is directly deposited on the layer of each underlying level of the array. The 3D memory array includes vertically oriented vertical NAND strings such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trapping layer. Each vertical NAND string may include at least one select transistor located above the memory cell. The at least one select transistor may have the same structure as the memory cell and be monolithically formed with the memory cell. The following patent documents (incorporated herein by reference) describe suitable configurations of three-dimensional memory arrays, where the three-dimensional memory arrays are configured as multiple levels, and word lines and / or bit lines are shared between levels: U.S. Patent No. 7,679,133; No. 8,553,466; No. 8,654,587; No. 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0098] The address decoder 231_2 is connected to the memory cell array 231_1 via word lines WL, string select lines SSL, and ground select lines GSL. The address decoder 231_2 can receive and decode a physical address ADD from the controller 210, and can drive the word lines WL based on the decoding result. For example, the address decoder 231_2 can select at least one of the word lines WL.

[0099] The page buffer 231_3 is connected to the memory cell array 231_1 via bit lines BL. Under the control of the control logic and voltage generation circuit 231_5, the page buffer 231_3 can drive the bit lines BL such that the data "DATA" received from the input / output circuit 231_4 by page is stored in the memory cell array 231_1. Alternatively, under the control of the control logic and voltage generation circuit 231_5, the page buffer 231_3 can read the data stored in the memory cell array 231_1 by page, and can provide the read data to the input / output circuit 231_4.

[0100] The input / output circuit 231_4 can receive the data "DATA" from the controller 210, and can provide the data "DATA" to the page buffer 231_3. Alternatively, the input / output circuit 231_4 can receive the data "DATA" from the page buffer 231_3, and can provide the data "DATA" to the controller 210. The input / output circuit 231_4 can exchange data with an external device based on a control signal CTRL.

[0101] The control logic and voltage generation circuit 231_5 can control the address decoder 231_2, the page buffer 231_3, and the input / output circuit 231_4 in response to a storage command CMD and a control signal CTRL received from the controller 210. For example, the control logic and voltage generation circuit 231_5 can control other components in response to signals CMD and CTRL such that the data "DATA" is stored in the memory cell array 231_1. Alternatively, the control logic and voltage generation circuit 231_5 can control other components in response to signals CMD and CTRL such that the data "DATA" stored in the memory cell array 231_1 is transferred to an external device. The control logic and voltage generation circuit 231_5 can generate various voltages required for the operation of the non-volatile memory 231. The control logic and voltage generation circuit 231_5 can generate, for example, a programming voltage, pass voltages, a select read voltage, a non-select read voltage, an erase voltage, and a verify voltage. The control logic and voltage generation circuit 231_5 can provide the generated voltages to the address decoder 231_2 or the substrate of the memory cell array 231_1.

[0102] Figure 15 shows a circuit diagram of a first block of three-dimensional memory blocks included in a Figure 14 memory cell array. In the first block BLK1, the number of cell strings, the number of rows and columns composed of cell strings, the number of cell transistors GST, MC, DMC, SST, etc., the number of lines GSL, WL, DML, SSL, etc. connected to the cell transistors, and the height of the first block BLK1 are not limited, as Figure 15 shown. The remaining memory blocks included in the non-volatile memory device 230 may also have a structure similar to that of the first block BLK1.

[0103] The first block BLK1 may include cell strings CS11 to CS22. The cell strings CS11 to CS22 may be arranged along the row direction and the column direction. The cell strings CS11 and CS12 may be connected to string select lines SSL1a and SSL1b (first row). The cell strings CS21 and CS22 may be connected to string select lines SSL2a and SSL2b (second row). The cell strings CS11 and CS21 may be connected to a first bit line BL1 (first column). The cell strings CS12 and CS22 may be connected to a second bit line BL2 (second column).

[0104] Each of the cell strings CS11 to CS22 may include cell transistors. Each of the cell strings CS11 to CS22 may include string select transistors SSTa and SSTb, memory cells MC1 to MC8, ground select transistors GSTa and GSTb, and dummy memory cells DMC1 and DMC2. Each of the memory cells MC1 to MC8 may be a charge trap flash (CTF) memory cell.

[0105] The memory cells MC1 to MC8 may be connected in series and may be stacked in a height direction perpendicular to the plane defined by the row direction and the column direction. In each cell string, the string select transistors SSTa and SSTb may be connected in series with each other and may be arranged between the memory cells MC1 to MC8 and the bit line BL. In each cell string, the ground select transistors GSTa and GSTb may be connected in series with each other and may be arranged between the memory cells MC1 to MC8 and the common source line CSL. In each cell string, the first dummy memory cell DMC1 may be disposed between the memory cells MC1 to MC8 and the ground select transistors GSTa and GSTb. In each cell string, the second dummy memory cell DMC2 may be disposed between the memory cells MC1 to MC8 and the string select transistors SSTa and SSTb. The ground select transistors GSTa and GSTb of the cell strings CS11 to CS22 may be commonly connected to a ground select line GSL.

[0106] The first ground selection transistors GSTa of the cell strings CS11 and CS12 in the first row can be connected to the first ground selection line, and the first ground selection transistors GSTa of the cell strings CS21 and CS22 in the second row can be connected to the second ground selection line. The ground selection transistors provided at the same height from the substrate (not shown) can be connected to the same ground selection line, and the ground selection transistors provided at different heights can be connected to different ground selection lines. For example, the first ground selection transistors GSTa of the cell strings CS11 to CS22 can be connected to the first ground selection line, and their second ground selection transistors GSTb can be connected to the second ground selection line.

[0107] Memory cells (or ground selection transistors GSTa and GSTb) at the same height from the substrate are commonly connected to the same word line, and memory cells at different heights from it are connected to different word lines. The first memory cells MC1 to the eighth memory cells MC8 in the cell strings CS11 to CS22 can be commonly connected to the first word line WL1 to the eighth word line WL8, respectively. String selection transistors belonging to the same row among the first string selection transistors SSTa at the same height can be connected to the same string selection line, and string selection transistors belonging to different rows among the first string selection transistors SSTa at the same height can be connected to different string selection lines. For example, the first string selection transistors SSTa of the cell strings CS11 and CS12 in the first row can be commonly connected to the string selection line SSL1a, and the first string selection transistors SSTa of the cell strings CS21 and CS22 in the second row can be commonly connected to the string selection line SSL2a. Also, the second string selection transistors SSTb of the cell strings CS11 and CS12 in the first row can be commonly connected to the string selection line SSL1b, and the second string selection transistors SSTb of the cell strings CS21 and CS22 in the second row can be commonly connected to the string selection line SSL2b.

[0108] String selection transistors of cell strings in the same row can be commonly connected to the string selection line. For example, the first string selection transistors SSTa and the second string selection transistors SSTb of the cell strings CS11 and CS12 in the first row can be commonly connected to the same string selection line. The first string selection transistors SSTa and the second string selection transistors SSTb of the cell strings CS21 and CS22 in the second row can be commonly connected to the same string selection line. Virtual memory cells at the same height can be connected to the same virtual word line, and virtual memory cells at different heights can be connected to different virtual word lines. For example, the first virtual memory cell DMC1 can be connected to the first virtual word line DWL1, and the second virtual memory cell DMC2 can be connected to the second virtual word line DWL2.

[0109] In the first block BLK1, read and write operations can be performed by the row. For example, a row in the first block BLK1 can be selected by string select lines SSL1a, SSL1b, SSL2a, and SSL2b. When a conduction voltage is supplied to the string select lines SSL1a and SSL1b and a cutoff voltage is supplied to the string select lines SSL2a and SSL2b, the cell strings CS11 and CS12 in the first row can be connected to the bit lines BL1 and BL2. In the opposite case, the cell strings CS21 and CS22 in the second row can be connected to the bit lines BL1 and BL2. When driving the word line, memory cells belonging to the same height are selected from among the memory cells of the cell string in the selected row. The selected memory cells can correspond to physical page units. Read or write operations can be performed on the selected memory cells.

[0110] Figure 16 shows Figure 1 A flowchart of an operation method of a storage device is shown. In operation S110, the controller 210 of the storage device 200 receives a barrier command and data (or a data set) corresponding to the barrier command respectively. As described above, the data can be transferred from the host 100 in a DMA scheme.

[0111] In operation S120, the controller 210 merges the barrier commands and programs the data sequentially into the non-volatile memory device 230 based on the order of the barrier commands or according to the order of the barrier commands. The controller 210 can merge the barrier commands based on the programming units of the non-volatile memory device 230, the number of physical pages to be accessed simultaneously, the number of bits to be stored in the memory cells, the size of one physical page, multi-channels, multi-way, and multi-planes. In Figures 8 to 13 An embodiment is shown in which the data is stored in any one physical page. However, the data can be distributed and stored in multiple chips, multiple planes, multiple blocks, or multiple pages in the non-volatile memory device 230. The programming of operation S120 can be performed atomically.

[0112] In operation S130, the controller 210 verifies the completion of the programming in operation S120. The controller 210 can read Figure 10 and Figure 11 of the commit page, or can read Figure 12 of the commit record bit. The controller 210 determines the data assigned to the commit page or the commit record bit as valid data and determines the data not assigned to the commit page or the commit record bit as invalid data.

[0113] In the case of successful programming (successful programming in S130), in operation S140, the controller 210 maps the mapping information of the physical page in which valid data is programmed in the mapping table L2P. In the case of failed programming (failed programming in S130), in operation S150, the controller 210 unmaps the mapping information of the physical page in which invalid data is programmed in the mapping table L2P. In the case where a part of the data targeted for the atomic programming operation is distributed and stored in multiple chips, multiple planes, multiple blocks, or multiple pages of the non-volatile memory device 230, and the remaining data is not stored, the controller 210 unmaps the mapping information of the physical page storing the part of the data. In an embodiment of the inventive concept, after unmapping or mapping the data corresponding to the barrier command, or after completely programming the data, the controller 210 may program different data corresponding to different barrier commands into the non-volatile memory device 230.

[0114] Figure 17 FIG. illustrates a software stack of a host supporting a system call for a write order according to an embodiment of the inventive concept. Figure 18 illustrates Figure 17 The timing diagram of the operation of the host performing logging on the storage device. Reference will be made to Figure 1 and Figure 2 to describe together Figure 17 and Figure 18 . The storage device (i.e., the barrier-compatible storage device) 400 may be the storage device 200 that supports the barrier command. Figure 1 The host 300 of

[0115] Figure 17 may include the components of the host 100 of Figure 1 . In terms of hardware, the host 300 may be implemented substantially the same as the host 100 of Figure 1 . A plurality of software loaded onto the host memory 120 of Figure 1 may also run in the host 300 of Figure 17 . However, different from the host 100, the host 300 may support system calls such as fbarrier() or fdatababarrier(). The barrier file system (dual-mode logging) 322, the dispatcher (i.e., order-preserving dispatching) 323, and the input / output (I / O) scheduler (i.e., epoch-based scheduler) 324 may be loaded onto the host memory (refer to the host memory 120 of Figure 1 ) of the host 300.

[0116] The operation of the barrier file system 322 can be similar to that of the file system 122. In an embodiment of the inventive concept, in the case of calling fsync() or fdatasync(), the barrier file system 322 can determine whether to call fsync() or fdatasync() to write data in order by using hint information. The barrier file system 322 can determine whether the extension of a file is a predetermined word, whether the file name is a predetermined word, or whether the name of the process that calls fsync() or fdatasync() is a predetermined word. The hint information can include the extension of a predetermined file, the predetermined file name, or the name of the process that calls fsync() or fdatasync().

[0117] In another embodiment of the inventive concept, in the case of calling fbarrier() or fdatababarrier(), the barrier file system 322 can determine to call fbarrier() or fdatababarrier() to write data in order. fbarrier() is similar to fdatababarrier(). File metadata can be modified by fbarrier(). However, when fbarrier() is called, the file metadata may not be modified without additionally modifying the file metadata for reading the newly written data. The barrier file system 322 can allocate a commit thread to the host memory to dispatch a write request to the storage device 400, and allocate a flush thread to the host memory to flush the data corresponding to the write request. The barrier file system 322 can generate a commit thread and a flush thread to perform dual-mode logging.

[0118] Reference Figure 18 , the barrier file system 322 can perform logging. When backing up a log or after modifying a database file, fbarrier() or fdatababarrier() can be called. In the case where fbarrier() starts, the barrier file system 322 can insert (or enqueue) a write request into a scheduler queue (not shown) of the block layer (refer to Figure 1 the scheduler queue 124) for transferring file data "D" to the storage device 400. The write request can be dispatched to the storage device 400. Different from the file system 122, the barrier file system 322 can trigger a commit thread without waiting for the DMA transfer of the file data "D" to complete.

[0119] The submission thread can insert write requests into the scheduler queue for transferring log data JD and log submission JC to the storage device 400. The write requests can be dispatched to the storage device 400. The submission thread can wait until the DMA transfer of log data JD and the DMA transfer of log submission JC are completed. The submission thread can trigger the flush thread when the DMA transfer of log data JD and the DMA transfer of log submission JC are completed. The flush thread can insert flush requests into the scheduler queue to flush the log data JD and log submission JC. The flush requests can be dispatched to the storage device 400. When the log data JD and log submission JC are fully flushed, fbarrier() can be returned.

[0120] Reference Figure 18 , in the case of calling fsync(), Figure 1 the file system 122 has to wait until the DMA transfer of file data "D", the DMA transfer and flush of log data JD, and the DMA transfer and flush of log submission JC are all completed. In contrast, in the case of calling fbarrier() as in Figure 18 , the barrier file system 322 can insert IO requests into the scheduler queue without waiting for the DMA transfer and flush of file data "D", log data JD, and log submission JC to be completed.

[0121] Returning again Figure 17 , the dispatcher 323 of the block layer can dispatch the IO requests input to the scheduler queue to the command queue of the storage device 400 (refer to the command queue 213 in Figures 3 to 13 ). For example, the dispatcher 323 can dispatch barrier commands to the command queue. The dispatcher 323 can ensure the following order: 1) process the existing commands in the command queue, 2) process the barrier commands, and 3) process the commands after the barrier commands. The dispatcher 323 can allow the order of dispatching commands from the host 300 to the storage device 400 to be consistent with the order of processing commands at the command queue of the storage device 400. The dispatcher 323 can be referred to as an "order-preserving dispatcher".

[0122] In an embodiment, the barrier command dispatched from the dispatcher 323 can be a write command with a barrier flag. In another embodiment, the barrier command dispatched from the dispatcher 323 can be generated from an input request independent of the write request and occupy an entry in the scheduler queue.

[0123] Based on epochs, the input / output scheduler 324 may allow the order in which IO requests are inserted into the scheduler queue to be consistent with the order in which commands are dispatched from the host 300 to the storage device 400. The input / output scheduler 324 may maintain the order between epochs. The input / output scheduler 324 may determine whether the IO request inserted into the scheduler queue is a barrier write request. In the case where the inserted IO request is a barrier write request, the input / output scheduler 324 may no longer receive IO requests. Thus, all IO requests that are input into the scheduler queue before the barrier write request and appear in the scheduler queue after the barrier write request may belong to one epoch. The input / output scheduler 324 may rearrange or merge the IO requests belonging to that epoch. The input / output scheduler 324 may send the IO requests present in the scheduler queue to the device driver (refer to the device driver 125 of Figure 1 ). The input / output scheduler 324 may designate the final output IO request as a new barrier write request. When all the IO requests present in the scheduler queue are dequeued or sent, the input / output scheduler 324 may receive new IO requests.

[0124] Figure 19 A graph showing the IOPS and command queue depth of a storage device according to an embodiment of the inventive concept. A storage device according to an embodiment of the inventive concept may include the storage device 200 or 400 described with reference to Figures 1 to 18 . In Figure 19 , "XnF" represents a transfer and refresh scheme (refer to Figure 2 ), "X" represents a wait-for-transfer scheme, and "OP" represents an order-preserving scheme according to an embodiment of the inventive concept (refer to Figure 18 ). In the case where each of UFS 2.0 (GS6) corresponding to the implementation of Universal Flash Storage 2.0 in Samsung Galaxy 6, SSD (850 PRO) corresponding to Samsung SSD 850 Pro, and SSD (843TN) corresponding to Samsung SSD 843TN, which can each be obtained from Samsung Electronics Co., Ltd., processes IO requests with the XnF scheme, "X" scheme, and OP scheme, the input / output operations per second (IOPS) and command queue depth are as shown in Figure 19 . In the case of the OP scheme according to an embodiment of the inventive concept, the host 100 / 300 may transfer commands to the storage device 100 / 200 according to the IO requests without waiting for the DMA transfer of data and the refresh of data to be completed. Thus, compared to the XnF scheme or "X" scheme, the IOPS and queue depth of the storage device 100 / 200 may be increased by the OP scheme.

[0125] According to an embodiment of the inventive concept, a storage device may support a barrier command for maintaining a write order. A host communicating with the storage device may provide write requests to the storage device in order without waiting for the storage device to complete each of the write requests generated in order.

[0126] Although the inventive concept has been described with reference to exemplary embodiments of the present invention, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A method of programming data into a storage device including a non-volatile memory device, the method comprising: Receiving a first barrier command, a second barrier command, and a third barrier command from a host in sequence into a command queue; Receiving from the host in sequence first data corresponding to the first barrier command, second data corresponding to the second barrier command, and third data corresponding to the third barrier command, wherein the amounts of the first data and the second data are less than a programming unit of the non-volatile memory device, and the amount of the third data is greater than the programming unit of the non-volatile memory device, wherein the first barrier command to the third barrier command notify the write order of the first data to the third data such that the write order is maintained based on the barrier commands; Storing each of the first data to the third data into a buffer memory including a write-back cache and a write buffer, wherein when the amount of each of the first data to the third data is less than the programming unit of the non-volatile memory device, each of the first data to the third data is stored into the write-back cache, and when the amount of each of the first data to the third data is not less than the programming unit of the non-volatile memory device, each of the first data to the third data is stored into the write buffer; Merging the first barrier command and the second barrier command; Borrowing fourth data from the write-back cache or the write buffer when the amounts of the first data and the second data are less than the programming unit of the non-volatile memory device; Processing the merged first barrier command and second barrier command by sequentially programming the first data and the second data together with the fourth data into the non-volatile memory device based on the order of the first barrier command and the second barrier command; Verifying the completion of programming of both the first data and the second data; Mapping in the first data and the second data when the programming of the first data and the second data is completed, or mapping out both the first data and the second data when the programming of at least one of the first data and the second data is not completed; and After the mapping in or the mapping out, programming the third data into the non-volatile memory device, wherein each of the first barrier command to the third barrier command includes a programming command, wherein each of the first barrier command to the third barrier command is marked as flag information in a spare area of the non-volatile memory device, and wherein the flag information includes an epoch number, and the data set corresponding to the merged first barrier command and second barrier command has the same epoch number.

2. The method according to claim 1, wherein A commit record bit is additionally written into the epoch number of the second barrier command.

3. The method according to claim 1, wherein, Determining whether the programming of both the first data and the second data is completed with reference to the commit record bit.

4. The method according to claim 1, wherein Providing the first data from the host sequentially after receiving the first barrier command.

5. The method according to claim 1, wherein, After receiving the second barrier command, provide the second data following the second barrier command from the host.

6. The method according to claim 1, wherein After determining that programming of both the first data and the second data is complete, program the third data.

7. The method according to claim 6, wherein The first data and the second data are programmed into a first block of the non-volatile memory device, and the third data is programmed into a second block of the non-volatile memory device.

8. The method according to claim 1, wherein The mapping in includes classifying the first data and the second data as valid data.

9. The method according to claim 1, wherein The mapping out includes classifying the first data and the second data as invalid data.

10. The method according to claim 9, further comprising: Performing garbage collection on the first data and the second data classified as the invalid data.

11. The method according to claim 1, wherein, Based on the programming units of the non-volatile memory device, the number of physical pages to be accessed simultaneously, the number of bits to be stored in the memory cells, the size of one physical page, multi-channel, multi-way, and multi-plane, merge the first barrier command and the second barrier command.

12. An operating method of a memory controller for controlling a non-volatile memory device, the operating method comprising: Receiving, by the memory controller, a first barrier command and a first programming command, a second barrier command and a second programming command, and a third barrier command and a third programming command from a host in sequence; Receiving, by the memory controller, in sequence from the host, first data corresponding to the first barrier command, second data corresponding to the second barrier command, and third data corresponding to the third barrier command, wherein the amounts of the first data and the second data are less than the programming units of the non-volatile memory device, and the amount of the third data is greater than the programming units of the non-volatile memory device, wherein the first barrier command to the third barrier command notify the write order of the first data to the third data such that the write order is maintained based on the barrier commands; Storing, by the memory controller, each of the first data to the third data into a buffer memory including a write-back cache and a write buffer, wherein when the amount of each of the first data to the third data is less than the programming units of the non-volatile memory device, each of the first data to the third data is stored in the write-back cache, and when the amount of each of the first data to the third data is not less than the programming units of the non-volatile memory device, each of the first data to the third data is stored in the write buffer; Merging, by the memory controller, the first barrier command to the third barrier command; Borrowing fourth data from the write-back cache or the write buffer when the amounts of the first data to the third data are less than the programming unit of the non-volatile memory device; and Programming, based on the order of the first barrier command to the third barrier command, the first data to the third data together with the fourth data into the non-volatile memory device sequentially; and The memory controller verifies whether the first data to the third data are programmed. When all of the first data to the third data are programmed, the first data to the third data are classified as valid data, or when at least one of the first data to the third data is not programmed, the first data to the third data are classified as invalid data. Wherein, it is determined whether the first data to the third data are programmed with reference to the commit record bit.

13. The operating method according to claim 12, wherein, The sum of the sizes of the first data to the third data is equal to or less than the programming unit of the non-volatile memory device.

14. A computer system for programming data, comprising: A host; And A storage device configured to sequentially receive a first barrier command, a second barrier command, and a third barrier command from the host, and first data, second data, and third data to be programmed corresponding to the first barrier command, the second barrier command, and the third barrier command, respectively. Wherein, the storage device includes: A buffer memory including a write-back cache and a write buffer; A plurality of non-volatile memory devices configured to store the first data, the second data, and the third data, and A memory controller configured to: Control the plurality of non-volatile memory devices, When the amount of each of the first data to the third data is less than the programming unit of the non-volatile memory device, store each of the first data to the third data in the write-back cache and the write buffer, and when the amount of each of the first data to the third data is not less than the programming unit of the non-volatile memory device, store each of the first data to the third data in the write buffer, Merge the first barrier command, the second barrier command, and the third barrier command, When the amount of the first data to the third data is less than the programming unit of the non-volatile memory device, borrow fourth data from the write-back cache or the write buffer, Program the first data, the second data, and the third data sequentially together with the fourth data, Determine whether the programming of the first data, the second data, and the third data is completed, When the programming of all of the first data, the second data, and the third data is completed, map in the first data, the second data, and the third data as valid data, and When the programming of at least one of the first data, the second data, and the third data is not completed, map out the first data, the second data, and the third data as invalid data, Wherein, the first data, the second data, and the third data are sequentially programmed into the plurality of non-volatile memory devices according to the epoch number and the commit record bit.

15. The computer system according to claim 14, wherein, The host is configured not to flush the first data, the second data, and the third data corresponding to the first barrier command, the second barrier command, and the third barrier command, respectively, when providing the first barrier command, the second barrier command, and the third barrier command to the storage device.

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