Network equipment and operation methods

Abstract

A network device includes a transmit buffer having a plurality of memory groups, and a transmit buffer controller, the transmit buffer controller being configured to: perform a first number of write operations to write processed packets to the memory groups of the transmit buffer; monitor the occupancy of the transmit buffer; and when the occupancy of the transmit buffer is at least equal to a threshold, perform a predetermined number of read operations during each memory cycle, and when the occupancy of the transmit buffer is less than the threshold, perform a second number of read operations greater than the predetermined number during each memory cycle. The device uses multiple ports to concurrently perform multiple read operations and multiple write operations in a single cycle. The buffer controller distributes data between the memory groups by assigning write addresses to keep the memory occupancy substantially uniform between the memory groups, thereby freeing up ports to allow the execution of read operations.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of co-pending, commonly assigned U.S. Provisional Patent Application No. 62 / 617,972, filed on January 16, 2018, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to a memory module suitable for use as a transmit buffer or transmit FIFO in a data exchange device. More particularly, the present disclosure relates to a transmit buffer or transmit FIFO that can operate at least at a predetermined or guaranteed rate under worst case conditions, but can operate at a higher rate when possible. Background Art

[0004] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. The work of the inventors is neither explicitly nor implicitly admitted to be prior art against the present disclosure to the extent that the work is described in this background section, and to the extent that the description may not otherwise qualify as prior art at the time of filing.

[0005] Network switching equipment operates at high data rates and high bandwidths. In order to maintain stable communications between devices, it is important to avoid "underrun" conditions, that is, situations where there is insufficient data to be transmitted, because underrun conditions may cause remote devices to assume that a session transmission is complete when it is not, or to assume that the connection has been broken. During and after processing, data units usually need to be written to and read from memory in network devices (such as switches). Some systems are designed to ensure that data units can be written to a transmission buffer at a guaranteed rate after processing, which is sufficient to ensure that underruns are avoided. However, providing a physical resource with a guaranteed write rate to the transmission buffer can only guarantee a lower rate for reading data units from the transmission buffer. If the rate for reading data units from memory is to be increased to above a guaranteed read rate, it may no longer be possible to guarantee a guaranteed write rate without increasing system resources beyond the system resources required to guarantee the write rate. However, it is still desirable to utilize the existing capacity of device resources that allow a guaranteed write rate to the greatest extent possible in an effort to approach the "full line speed" for both read and write operations. Summary of the invention

[0006] According to an embodiment of the subject matter of the present disclosure, a method of operating a network device includes: performing a first number of write operations during each memory cycle to write processed packet data to a transmit buffer; monitoring an occupancy of the transmit buffer; and performing a predetermined number of read operations during each memory cycle to read the packet data stored in the transmit buffer when the occupancy of the transmit buffer is at least equal to a threshold, and performing a second number of read operations during each memory cycle to read the packet data stored in the transmit buffer when the occupancy of the transmit buffer is less than the threshold, the second number being greater than a predetermined number.

[0007] In an embodiment of such a method, performing a second number of read operations greater than the predetermined number includes concurrently performing the plurality of read operations and the plurality of write operations in a single cycle using the plurality of ports.

[0008] In such an embodiment, concurrently performing multiple read operations and multiple write operations in a single cycle at multiple ports includes performing two or more concurrent read operations through a single port and using error correction techniques to reconstruct the data to be read.

[0009] In another embodiment of such a method, the transmit buffer has a certain number of write ports, and the first number is twice the certain number. The method also includes doubly clocking the transmit buffer.

[0010] In a third embodiment of such a method, the transmit buffer includes a plurality of memory banks. The method further includes distributing data among the memory banks by assigning write addresses by a memory controller of the transmit buffer to keep memory occupancy substantially uniform among the memory banks, thereby freeing up ports to allow the second number of read operations to be performed.

[0011] In a variation of the third embodiment, when the occupancy of the transmit buffer is less than a threshold value, performing a second number of read operations greater than a predetermined number during each memory cycle is performed only when the occupancy of all memory groups of the transmit buffer is less than the threshold value. The method further includes: performing a predetermined number of read operations during each memory cycle when the occupancy of the transmit buffer is less than the threshold value and the occupancy of at least one of the memory groups of the transmit buffer is at least equal to the threshold value.

[0012] In a second variation of the third embodiment, write addresses are assigned by a memory controller of the transmit buffer to control the distribution of data between memory groups to keep memory occupancy substantially uniform between memory groups, thereby freeing up ports to allow a second number of read operations to be performed, which occurs when the location of the grouped write is determined.

[0013] A fourth embodiment of such a method further includes assigning, by a memory controller of the transmit buffer, a write address based on an address from which data is read, thereby freeing up the port to allow the second number of read operations to be performed.

[0014] In a fifth implementation of such a method, the predetermined number of read operations is half the first number of write operations.

[0015] According to other embodiments of the subject matter of the present disclosure, a network device configured to process network packets received from a network includes a transmit buffer having multiple memory groups, and a transmit buffer controller, the transmit buffer controller being configured to: during a memory cycle in a series of memory cycles, perform a first number of write operations to write processed packets to the memory groups of the transmit buffer, monitor the occupancy of the transmit buffer, and when the occupancy of the transmit buffer is at least equal to a threshold, perform a predetermined number of read operations during each memory cycle to read the packet data stored in the transmit buffer, and when the occupancy of the transmit buffer is less than the threshold, perform a second number of read operations during each memory cycle to read the packet data stored in the transmit buffer, the second number being greater than the predetermined number.

[0016] In such an embodiment, the network device is configured to perform a second number of read operations greater than the predetermined number by concurrently performing the plurality of read operations and the plurality of write operations in a single cycle using the plurality of ports.

[0017] In this embodiment, the network device is configured to concurrently perform multiple read operations and multiple write operations in a single cycle at multiple ports by performing two or more concurrent read operations via a single port and reconstructing the data to be read using error correction techniques.

[0018] In a second embodiment, the network device further comprises a certain number of write ports, the first number is twice the certain number, and the transmit buffer controller is further configured to double-clock each memory bank.

[0019] In a third embodiment, the transmit buffer controller is further configured to distribute data among the memory banks by assigning write addresses to keep memory occupancy substantially uniform among the memory banks, thereby freeing up ports to allow the second number of read operations to be performed.

[0020] In a first variant of the third embodiment, the transmit buffer controller is configured to perform a second number of read operations greater than a predetermined number during each memory cycle only when the occupancy of the transmit buffer is less than a threshold and the occupancy of each memory group in the memory group is less than the threshold, and the transmit buffer controller is further configured to perform a predetermined number of read operations during each memory cycle when the occupancy of the transmit buffer is less than a threshold and the occupancy of at least one memory group in the memory group is at least equal to the threshold.

[0021] In a second variation of this third embodiment, the transmit buffer controller is further configured to assign a write address when the location of the packet write is determined to control data distribution between memory groups to keep memory occupancy substantially uniform between memory groups, thereby freeing up ports to allow a second number of read operations to be performed.

[0022] In a third variation of the third embodiment, the transmit buffer has a nominal transmit buffer size plus a spare capacity equal to 50% of the nominal transmit buffer size. In the third variation, each memory bank may have a nominal bank size plus a spare capacity equal to 50% of the nominal bank size.

[0023] In a fourth embodiment, the transmit buffer controller is further configured to assign write addresses based on addresses from which data is read, thereby freeing up ports to allow a second number of read operations to be performed.

[0024] In a fifth embodiment, the predetermined number of read operations is half of the first number of write operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Further features of the present disclosure, its nature and various advantages will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

[0026] Figure 1 is a representation of a network switching device including a transmit buffer according to an embodiment of the disclosed subject matter;

[0027] Figure 2 is a representation of the internal structure of an embodiment of a transmit buffer according to the present disclosure; and

[0028] Figure 3 is a flow chart of a method for determining whether to perform a read operation in a deterministic mode or in a probabilistic mode, according to an embodiment of the disclosed subject matter. DETAILED DESCRIPTION

[0029] To probabilistically ensure that underruns can be avoided at near full line rate, embodiments of the disclosed subject matter provide a transmit buffer, also referred to as a "transmit FIFO (TXFIFO)", that provides a guaranteed number of write operations that can be performed per memory cycle, as well as a deterministic floor on the number of read operations (to maintain output of data for transmission to avoid underruns), while providing a "best effort" possibility or probabilistic "speed-up" to enable more read operations to be performed per memory cycle (at near full line rate).

[0030] A transmit buffer according to an embodiment of the disclosed subject matter receives packet data from a packet buffer of a switching device for subsequent transmission outside the switching device to some other device on a network. Data received from the packet buffer is written to the transmit buffer for temporary storage until it can be transmitted outside the switching device based on its header information. Typically, the physical resources of the switching device are configured to ensure that newly processed packet data can be written to the transmit buffer as quickly as the packet processor of the switching device can supply processed packet data ready for transmission.

[0031] In order to prevent under-run, there should also be a minimum or predetermined read rate for transmission outside the switching device. In some embodiments, the same physical resource (such as a port) is used to read and write packet data from a transmit buffer. However, although some physical resources may be able to guarantee a specific write rate, i.e., the maximum rate at which packets can be processed by a packet processor and supplied to the transmit buffer on the input side, these same resources can only guarantee a lower read rate on the output side from the transmit buffer. If the read rate of those same resources that provide a guaranteed write rate is increased to more than the guaranteed read rate, the write rate will inevitably be reduced to less than the previously guaranteed write rate. In order to approach the full line speed at which both write operations and read operations are executed at the maximum rate enabled by system resources, the read rate should exceed the predetermined guaranteed read rate whenever possible.

[0032] The ability to exceed a predetermined guaranteed read rate depends on having an available port on the memory bank of the transfer buffer. This in turn depends on the occupancy of the memory bank, that is, the fraction of the storage capacity of each memory bank used. For example, commonly assigned U.S. Patent 8,514,651 and commonly assigned U.S. Patent Publication 2016 / 0328158 (each of which is hereby incorporated by reference in its entirety) describe corresponding techniques for performing multiple read operations and write operations in a single cycle at a single port using XOR error correction techniques. Regardless of whether XOR error correction is used, in some multi-bank memory systems, each bank is able to perform a number of simultaneous memory operations in a memory bank; the number is limited by the number of physical ports leading to the memory bank. When a read operation needs to read data from a predetermined address located in a particular memory bank, the memory access port leading to the memory bank is occupied by the read operation. Write operations cannot be performed concurrently using the memory access port being used to perform read operations. Therefore, write operations use ports that are not occupied by simultaneous read operations or write operations to write to memory banks in a multi-bank memory system, and then return the address of the location where the data is written. Therefore, as the occupancy of a memory bank increases, there is a statistically increasing probability that some of the ports of the memory bank will be unavailable to perform simultaneous write operations, for example, because the ports are already being used for read operations.

[0033] Deterministically guaranteeing a minimum data rate imposes a cost in terms of device area and power consumption. Some deterministic write rate should be provided (since it must be possible to store in the transmit buffer any data that the system has designated for transmission, e.g., processed packet data), while some minimum read rate for data to be transmitted out of the transmit buffer should also be provided in order to prevent underruns. Thus, in accordance with embodiments of the disclosed subject matter, a guaranteed minimum deterministic read rate is provided, and higher read rates are achieved when possible.

[0034] In order to minimize the above-mentioned costs in terms of area and power consumption, a transmit buffer according to an embodiment of the subject matter of the present disclosure is constructed to allow a certain predetermined, guaranteed, deterministic write rate, and a certain minimum or predetermined, guaranteed, deterministic read rate. The predetermined guaranteed read rate is less than the predetermined write rate, but by probabilistically controlling the distribution of data between memory banks within the transmit buffer, the transmit buffer will be able to operate at a read rate that is higher than the predetermined guaranteed read rate and close to the write rate during a large portion of the time.

[0035] In an embodiment of the subject matter of the present disclosure, the guaranteed minimum deterministic read rate corresponds to the number of read operations that can be provided in a single memory cycle while still deterministically guaranteeing a minimum number of write operations in the memory cycle based on statistical analysis. In one embodiment example, when the fullness or occupancy level of the multi-group memory is relatively low and data is distributed between the memory groups of the multi-group system, an increased number of simultaneous read operations greater than the guaranteed minimum number of read operations can generally be serviced without reducing the number of guaranteed simultaneous write operations. The increased number of simultaneous read operations is constrained by the maximum number of possible simultaneous read operations that can be performed in the memory cycle based on the number of physical ports of any particular memory group in the multi-group memory system. Although the memory cycle can be the same as the clock cycle, the subject matter of the present disclosure is not limited to such an embodiment, and the memory cycle of the transmit buffer can be asynchronous with the clock of the network switching device.

[0036] Figure 1 A transmission part or egress part of a network switching device 100 comprising at least one transmit buffer (TXFIFO) 101 according to an embodiment of the disclosed subject matter is shown. Figure 1 The embodiment of the network switching device 100 shown in FIG. 1 includes a port group 102. The port group 102 may be bidirectional, but only the transmission function or egress function of the port group 102 is relevant to the present disclosure. Figure 1 One transmit buffer 101 and one port group 102 are shown, but other implementations within the scope of the disclosed subject matter may have other numbers of port groups 102 and other numbers of transmit buffers 101. Additionally, the ratio of port groups 102 to transmit buffers 101 may be other than one-to-one.

[0037] The transmission request generator 103 issues a request (REQ) to the transmission queue 104 to initiate a transmission or outgoing process for a packet. The transmission queue 104 returns a packet descriptor (DESC) to the transmission request generator 103, which in turn issues a cell request (Cell REQ) to the packet buffer 105. The transmission request generator 103 also forwards the packet descriptor (DESC) with the cell tag to the descriptor memory 111 of the transmission buffer 101. The packet buffer 105 returns a payload response to the transmission buffer 101, the payload response including the payload data stored in the word buffer 121 of the transmission buffer 101 until the transmission logic 131 of the transmission buffer 101 issues a read request (RD REQ) to the word buffer 121. At 141, the transmission logic 131 also matches the payload data read out from the word buffer 121 with the header data using the descriptor information. The assembled network packet (including the header data and the payload data) is then transmitted via the port group 102.

[0038] Figure 2 2 shows an internal structure of an embodiment 200 of the word buffer 121 of the transmission buffer 101 according to an embodiment of the present disclosure.

[0039] The word buffer 200 includes six memory groups - Group 0 (210), Group 1 (220), Group 2 (230), Group 3 (240), Group 4 (250), and Group 5 (260) - in one embodiment, each group having a capacity of 150×32=4800 bytes. Each memory group 210-260 is shown as a quad-port memory, but in an alternative embodiment, can be a double-clocked dual-port memory. Although each memory group 210-260 has a capacity of 4800 bytes, according to an embodiment of the present disclosure, each memory group 210-260 has a nominal capacity of only 3200 bytes, with a spare capacity of more than 50% of the nominal capacity in order to implement a probabilistic speedup that allows the word buffer 200 to approach full line speed.

[0040] Typically, each memory bank 210-260 operates at a nominal occupancy of approximately two-thirds of its actual capacity. However, it is possible that, in an extreme case, although the occupancy of word buffer 200 as a whole is at or near the nominal capacity (which is two-thirds of the actual capacity), four of the memory banks 210-260 are at or near the actual capacity, while two of the memory banks are empty or nearly empty. Note that there may also be situations in between. Regardless of the distribution of occupancy, word buffer 200 operates to allow a guaranteed deterministic number of write operations, and a minimum guaranteed number of read operations that are expected to be exceeded.

[0041] Word buffer 200 also includes a controller 201 that implements a distribution function that determines which of memory banks 210-260 receives each packet payload or payload portion ("chunk") sent from packet buffer 105 for transmission out of network switch device 100. Word buffer 200 also returns a packet ID (PID) that informs transmit logic 131 where in word buffer 200 a particular packet or chunk has been written.

[0042] As explained above, in each memory cycle, the transmit buffer 101 needs to be able to support a guaranteed deterministic number of writes 202 and a guaranteed minimum deterministic number of reads 203. As an example, the deterministic number of writes 202 per memory cycle is eight writes per memory cycle, and the minimum deterministic number of reads 203 per memory cycle is four reads per memory cycle. However, these numbers are only examples and the actual number can be larger or smaller. In addition, the 2:1 ratio of the deterministic number of writes 202 per memory cycle to the minimum deterministic number of reads 203 per memory cycle is also only an example. The deterministic number of writes 202 per memory cycle will usually exceed the guaranteed minimum deterministic number of reads 203 per memory cycle. The guaranteed number of writes 202 is a function of the number of memory groups, the size of each memory group, and the occupancy level of each memory group, and the number of ports that cannot be used for writing (when the packet needs to be read, the reading is given priority) due to being used to read packets from the transmit buffer 101.

[0043] According to an embodiment of the subject matter of the present disclosure, when a read request is sent to a packet buffer 105, the response-write technique in the transmit buffer 101 does not pre-assign addresses in the memory groups 210-260. Instead, the write addresses are assigned or determined only when the packets are to be actually written to the memory groups 210-260, for example using techniques such as described in the aforementioned commonly assigned U.S. Patent Publication 2016 / 0328158, according to which the controller 201 rather than an external host or client determines the memory addresses. In this way, it is possible to optimally distribute writes among the memory groups 210-260 while maintaining a guaranteed minimum number of reads 203, regardless of where the data is located among the memory groups 210-260.

[0044] Write distribution is in this embodiment handled by the controller 201 inside the word buffer 200. According to an embodiment of the disclosed subject matter, the write distribution function of the controller 201 monitors the number of free ports at each of the memory groups 210-260, and their occupancy level 221, determined, for example, by the fill monitor 211. Based on the number of free ports and the occupancy level at each of the memory groups 210-260, write addresses are allocated in a manner that balances the occupancy levels among the memory groups 210-260 to the greatest extent possible, and write operations are probabilistically distributed among the memory groups 210-260.

[0045] If any one of the memory groups 210-260 becomes too full, write operations will be disproportionately directed to other memory groups in the memory groups 210-260, which may conflict with read operations at these other memory groups in the memory groups 210-260. Because read operations have priority, if read operations occur at these other memory groups in the memory groups 210-260, the guaranteed minimum number of write operations may not be performed, resulting in data errors. Probabilistically balancing the occupancy levels between the memory groups 210-260 prevents any one of the memory groups 210-260 from becoming too full, and avoids such a situation. In addition, for a total read rate higher than the guaranteed minimum deterministic read rate, more ports will be released at each of the memory groups 210-260 for reading, thereby allowing additional best-effort reading 204 in addition to the guaranteed minimum number of read operations 203 per memory cycle.

[0046] Although controller 201 attempts to balance write operations among memory banks 210-260 by assigning write addresses to free ports for read operations above a minimum deterministic rate, situations may arise where write operations become unbalanced and the occupancy of at least one of memory banks 210-260 exceeds a desired level. In such a situation, word buffer 200 may have to revert to deterministic operation, performing a predetermined minimum number of read operations 203 per memory cycle, because there may not be enough free ports for additional read operations.

[0047] As an example of such a situation where word buffer 200 may have to revert to deterministic operation, if there is heavy read activity from a particular one or more of memory banks 210-260, it will reduce the port availability for write operations at the one or more of memory banks 210-260, particularly in a system as described above where the same port may be used for both reading and writing. In this case, write operations will have to be directed by disproportionately allocating write addresses to other memory banks 210-260, such that the occupancy of these other memory banks 210-260 may exceed a desired level.

[0048] As noted above, each of the memory banks 210-260 may have a spare capacity that is higher than its nominal capacity—for example, a nominal capacity that is 50% above the nominal capacity (i.e., a total capacity that is 150% of the nominal capacity). As another example of a situation in which the word buffer 200 may have to revert to deterministic operation, in an extreme case of occupancy imbalance, four of the memory banks 210-260 may be at maximum capacity (including the spare capacity), while two of the memory banks 210-260 may be empty. The word buffer 200 would be at nominal capacity in this case, but because of the occupancy imbalance (not just one but four of the memory banks 210-260 are above nominal occupancy), the word buffer 200 would revert to deterministic operation in which only a predetermined minimum number of read operations 203 occur per memory cycle.

[0049] Although in the foregoing discussion, the focus is on whether the data distribution between the memory groups 210-260 is balanced, in practice, in some embodiments, the controller 201 checks a more objective criterion, such as whether the occupancy of the word buffer 200 exceeds or is less than a threshold value, which may be a predetermined fraction of the capacity, such as 85%. When the occupancy of the word buffer 200 is at least equal to the threshold value, the word buffer 200 operates in a deterministic mode, performing a guaranteed minimum number of read operations per memory cycle. When the occupancy of the word buffer 200 is less than the threshold value, the word buffer 200 operates in the probabilistic mode described above to provide additional reads on a best-effort basis.

[0050] As noted above, when write operations are distributed by probabilistically assigning write addresses, the number of write ports used is minimized to allow more than the guaranteed minimum number of read operations per memory cycle to be performed. In some embodiments, the total number of read operations per memory cycle in the probabilistic pattern is always the same number that is greater than the guaranteed minimum number of read operations per memory cycle, e.g., equal to the number of write operations per memory cycle. In other embodiments, the number of read operations per memory cycle in the probabilistic pattern will be greater than the guaranteed minimum number of read operations per memory cycle, but will vary from just above the guaranteed minimum number of read operations per memory cycle to some maximum number of read operations per memory cycle, depending on the extent to which the occupancy of word buffer 200 is less than a threshold.

[0051] In another embodiment, the controller 201 determines whether to operate in the deterministic mode or the probabilistic mode based not on the overall occupancy of the word buffer 200, but rather on the occupancy of any one of the memory groups 210-260 being at least equal to or below a threshold, for example, 85% of the actual capacity (including spare capacity, if any).

[0052] Figure 3 Flowchart of a portion 300 of the operation of controller 201 as described above for determining whether to perform a read operation in a deterministic mode or a probabilistic mode. At 301, data is received at word buffer 200 to be written to memory banks 210-260 for eventual transmission out of or from a network device (such as a network switch). At 302, subject to port availability based on current read activity levels (which may cause data to be distributed unequally, in some cases, at least for a temporary period of time), the data is distributed equally among memory banks 210-260.

[0053] In parallel with 301 and 302, at 311, a request to read data from the memory bank 210-260 for transmission out is received. At 312, the occupancy of one or more of the memory banks 210-260 is compared to a threshold (as noted above, the comparison can be the total occupancy of the memory banks 210-260 relative to the threshold, or the occupancy of any one of the memory banks 210-260 relative to the threshold). If at 312, the occupancy of the (multiple) memory banks 210-260 is at least equal to the threshold, then at 313, a guaranteed minimum number of read operations is performed during each memory cycle, and the method 300 ends. If at 312, the occupancy of the (multiple) memory banks 210-260 is less than the threshold, then at 314, in one embodiment, a best-effort number of read operations (in addition to the guaranteed minimum number) based on the error correction techniques described above is performed during each memory cycle, and the method 300 ends.

[0054] In an implementation of the disclosed subject matter, the error correction techniques described above are used to increase the number of concurrent read operations that can be performed through a given port.

[0055] Note that in an embodiment of the disclosed subject matter, during a memory cycle, read operations at 313, 314 are given priority to access ports needed to read data stored in one or more of the memory banks. Write operations at 301, 302 performed in a concurrent memory cycle with a read operation at either of 313, 314 are performed using ports not used for read operations in the concurrent cycle, and the memory controller provides an indication of the bank and memory address to which the data (such as a network packet) is written (once determined).

[0056] Thus, it can be seen that a transmit buffer or "transmit FIFO (TXFIFO)" is provided which provides a guaranteed deterministic floor on the number of read operations that can be performed per memory cycle (to maintain the output of data for transmission to avoid underruns), while providing the possibility of "best effort" "speed-up" based on the above-mentioned error correction techniques and the probability distribution of write operations so that more read operations can be performed per memory cycle (at close to full line speed).

[0057] As used herein and in the following claims, the structure "one of A and B" shall mean "A or B."

[0058] Note that the foregoing merely illustrates the principles of the present invention and that the present invention may be practiced by other embodiments than those described, which are presented for purposes of illustration and not limitation, and that the present invention is limited only by the claims that follow.

Claims

1. A method for operating a network device, the method comprising: During each memory cycle, performing a first number of write operations to write processed packet data to a transmit buffer; monitoring the occupancy of the transmit buffer; as well as When the occupancy rate of the transmit buffer is at least equal to a non-zero predetermined threshold, during each memory cycle, performing a non-zero predetermined number of read operations to read the packet data stored in the transmit buffer, and When the occupancy rate of the transmit buffer is less than the predetermined threshold, during each memory cycle, a second number of read operations is performed to read the packet data stored in the transmit buffer, the second number being greater than the predetermined number.

2. The method of claim 1 , wherein performing the second number of read operations greater than the predetermined number comprises: Use multiple ports to perform multiple read operations and multiple write operations concurrently in a single cycle.

3. The method of claim 2, wherein concurrently performing a plurality of read operations and a plurality of write operations in the single cycle at the plurality of ports comprises: Two or more concurrent read operations are performed through a single port, and error correction techniques are used to reconstruct the data to be read.

4. The method according to claim 1, wherein the transmit buffer has a certain number of write ports, wherein: The first number is twice the certain number; and the method further comprises: The transmit buffer is double clocked.

5. The method of claim 1 , wherein the transmit buffer comprises a plurality of memory banks, the method further comprising: Data is distributed among the memory banks through assignment of write addresses by the memory controller of the transfer buffer to keep memory occupancy substantially even among the memory banks, thereby freeing up ports to allow the second number of read operations to be performed.

6. The method according to claim 5, wherein: When the occupancy rate of the transmit buffer is less than the predetermined threshold, performing a second number of read operations greater than the predetermined number during each memory cycle is performed only when the occupancy rates of all the memory groups of the transmit buffer are less than the predetermined threshold; the method further comprises: When the occupancy of the transmit buffer is less than the predetermined threshold and the occupancy of at least one of the memory banks of the transmit buffer is at least equal to the predetermined threshold, the predetermined number of read operations is performed during each memory cycle.

7. The method of claim 5 , wherein the write address is assigned by the memory controller of the transmit buffer to control the distribution of data between the memory groups to keep the memory occupancy substantially uniform between the memory groups, thereby freeing up ports to allow the second number of read operations to be performed, occurs when the location of the packet write is determined.

8. The method according to claim 1, further comprising: A write address is assigned by a memory controller of the transfer buffer based on an address from which data is read, thereby freeing up a port to allow the second number of read operations to be performed.

9. The method of claim 1, wherein the predetermined number of read operations is half of the first number of write operations.

10. A network device configured to process a network packet received from a network, the network device comprising: a transmit buffer including a plurality of memory banks; as well as Transmit buffer controller, configured as: performing a first number of write operations to write processed packets to a memory bank of the transmit buffer during a memory cycle in a series of memory cycles; monitoring the occupancy of the transmit buffer; as well as When the occupancy rate of the transmit buffer is at least equal to a non-zero predetermined threshold, during each memory cycle, performing a non-zero predetermined number of read operations to read the packet data stored in the transmit buffer, and When the occupancy rate of the transmit buffer is less than the predetermined threshold, a second number of read operations is performed during each memory cycle to read the packet data stored in the transmit buffer, the second number being greater than the predetermined number.

11. The network device of claim 10, wherein the network device is configured to perform the second number of read operations greater than the predetermined number by concurrently performing multiple read operations and multiple write operations in a single cycle using multiple ports.

12. The network device of claim 11, wherein the network device is configured to concurrently perform the multiple read operations and the multiple write operations in the single cycle at the multiple ports by performing two or more concurrent read operations via a single port and reconstructing the data to be read using error correction techniques.

13. The network device according to claim 10, further comprising a certain number of write ports; wherein: The first number is twice the certain number; and The transmit buffer controller is also configured to double clock each memory bank.

14. The network device of claim 10, wherein the transmit buffer controller is further configured to: Data is distributed among the memory banks by assigning write addresses to keep memory occupancy substantially even among the memory banks, thereby freeing up ports to allow the second number of read operations to be performed.

15. The network device according to claim 14, wherein: The transmit buffer controller is configured to: perform the second number of read operations greater than the predetermined number during each memory cycle only when the occupancy rate of the transmit buffer is less than the predetermined threshold and the occupancy rate of each of the memory banks is less than the predetermined threshold; and The transmit buffer controller is further configured to perform the predetermined number of read operations during each memory cycle when an occupancy rate of the transmit buffer is less than the predetermined threshold and an occupancy rate of at least one of the memory banks is at least equal to the predetermined threshold.

16. A network device according to claim 14, wherein the transmit buffer controller is further configured to: assign a write address when the location of the packet write is determined to control the data distribution between the memory groups to keep the memory occupancy rate substantially uniform between the memory groups, thereby freeing up ports to allow the second number of read operations to be performed.

17. The network device of claim 14, wherein the transmit buffer has a nominal transmit buffer size plus a spare capacity, the spare capacity being equal to 50% of the nominal transmit buffer size.

18. The network device of claim 17, wherein each memory group has a nominal group size plus a spare capacity, the spare capacity being equal to 50% of the nominal group size.

19. The network device of claim 10, wherein the transmit buffer controller is further configured to assign write addresses based on addresses from which data is read, thereby freeing up ports to allow the second number of read operations to be performed.

20. The network device of claim 10, wherein the predetermined number of read operations is half of the first number of write operations.

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