Semiconductor device with body contact and dielectric spacer and corresponding manufacturing method

Abstract

The present invention discloses a semiconductor device with a body contact and a dielectric spacer and a corresponding manufacturing method. A semiconductor device includes a groove extending into a first main surface of a semiconductor substrate, and a gate electrode and a gate dielectric in the groove. The gate dielectric separates the gate electrode from the semiconductor substrate. A first region with a first conductivity type is formed in the semiconductor substrate and is located at the first surface and adjacent to the groove. A second region with a second conductivity type is formed in the semiconductor substrate and is located below the first region and adjacent to the groove. A third region with a first conductivity type is formed in the semiconductor substrate and is located below the second region and adjacent to the groove. A contact opening in the semiconductor substrate extends into the second region. An electrically insulating spacer is arranged on a sidewall of the semiconductor substrate formed by the contact opening, and the conductive material in the contact opening is adjacent to the electrically insulating spacer on the sidewall.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a body contact and a dielectric spacer and a corresponding manufacturing method. Background Art

[0002] The channel size of power MOSFETs is routinely reduced to increase performance. The distance between the channel of the device and the recessed contact of the body region of the device also becomes smaller, resulting in several key tradeoffs, including: the interaction of the p+ contact implant into the recess with the channel dopant; and the reduction in the slope of the threshold voltage characteristic as depletion capacitance degrades gate control and parasitic source capacitance increases.

[0003] The distance between the channel and the recessed contact can be kept large enough, but this results in a higher Rdson (on-state resistance). The reduction in the slope of the threshold voltage characteristic can be addressed by using a thinner oxide which produces a smaller gate capacitance. However, the smaller gate capacitance increases the gate total charge figure of merit (FOMg).

[0004] Therefore, a new power MOSFET with smaller channel size and acceptable FOMg is needed. Summary of the invention

[0005] According to an embodiment of a semiconductor device, the semiconductor device comprises: a trench extending into a first main surface of a semiconductor substrate; a gate electrode and a gate dielectric in the trench, the gate dielectric separating the gate electrode from the semiconductor substrate; a first region of a first conductivity type, the first region being formed in the semiconductor substrate at the first surface and adjacent to the trench; a second region of a second conductivity type, the second region being formed in the semiconductor substrate below the first region and adjacent to the trench; a third region of the first conductivity type, the third region being formed in the semiconductor substrate below the second region and adjacent to the trench; a contact opening in the semiconductor substrate, the contact opening extending into the second region; an electrically insulating spacer, the electrically insulating spacer being located on a sidewall of the semiconductor substrate formed by the contact opening; and a conductive material, the conductive material being located in the contact opening and adjacent to the electrically insulating spacer on the sidewall of the semiconductor substrate formed by the contact opening. A corresponding manufacturing method is also provided.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The elements of the drawings are not necessarily to scale with respect to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they are mutually exclusive. The embodiments are depicted in the drawings and are detailed in the following description.

[0008] Figures 1 to 4 Respective partial cross-sectional views of embodiments of a semiconductor device having a body contact and a dielectric spacer are illustrated.

[0009] Figures 5A to 5D Diagram for manufacturing Figures 1 to 4 An embodiment of some processing steps of a semiconductor device is shown in FIG.

[0010] Figure 6 The picture is Figures 1 to 4 A partial top view of an embodiment of a semiconductor device is shown in FIG.

[0011] Figures 7 to 10 Respective partial cross-sectional views of additional embodiments of semiconductor devices having body contacts and dielectric spacers are illustrated.

[0012] Figures 11A to 11Q Picture made in Fig.10 An embodiment of a method for a semiconductor device is shown in FIG.

[0013] Fig.12 A partial cross-sectional view of an embodiment of a semiconductor device having a body contact and dielectric spacers and an integrated Schottky barrier diode is illustrated. DETAILED DESCRIPTION

[0014] The embodiments described herein provide a power MOSFET with reduced channel size and good FOMg, and a corresponding manufacturing method. By introducing a spacer dielectric along the sidewall of the contact to the high-doped body contact region of the power device, the lateral size of the channel region can be further reduced, while also reducing the source capacitance and increasing the distance between the high-doped body contact region and the channel region. A small fin-shaped portion of the device body region between the contact opening / groove and the gate trench in the semiconductor substrate is connected in parallel with the contact opening / groove, thereby reducing the IV curve and DIBL (drain induced barrier drop) swing. The high-doped body contact region is decoupled from the channel region by the spacer dielectric along the contact opening / groove, thereby improving the threshold voltage stability. The dielectric spacer also introduces stress along the side of the channel, which should reduce Rdson and leakage.

[0015] Figure 1A partial cross-sectional view of a semiconductor device 100 having a body contact and a dielectric spacer is shown. The semiconductor device 100 includes a semiconductor substrate 102 having a gate trench 104 extending into a front surface 106 of the semiconductor substrate 102. The semiconductor substrate 102 may include any type of semiconductor material, such as a single element semiconductor (e.g., Si, Ge, etc.), silicon on insulator, a binary semiconductor (e.g., SiC, GaN, GaAs, etc.), a ternary semiconductor, etc., with or without (one or more) epitaxial layers. A gate electrode 108 and a gate dielectric 110 are disposed in each gate trench 104, the gate dielectric 110 separating the corresponding gate electrode 108 from the semiconductor substrate 102. Field plates 112 may be disposed in the gate trenches 104 below the gate electrodes 108, each field plate 112 being separated from the semiconductor substrate 102 and the corresponding gate electrode 108 by a field dielectric 114 that is thicker than the gate dielectric 110. Alternatively or additionally, the field plate may be disposed in a dedicated field plate trench. Figure 1 Not shown.

[0016] A first (source / emitter) region 116 of a first conductivity type (e.g., n-type in the case of an n-channel device, or p-type in the case of a p-channel device) is formed in the semiconductor substrate 102 at the front surface 106 and adjacent to each gate trench 104. A second (body) region 118 of a second conductivity type (e.g., p-type in the case of an n-channel device, or n-type in the case of a p-channel device) is formed in the semiconductor substrate 102 below the source / emitter region 116 and adjacent to each gate trench 104. A third (drift) region 120 of the first conductivity type is formed in the semiconductor substrate 102, e.g., as part of an epitaxial layer, below the body region 118 and adjacent to each gate trench 104. A drain / collector region 122 of the first conductivity type is formed at a back surface 124 of the semiconductor substrate 102 opposite the front surface 106, and is more heavily doped than the drift region 120.

[0017] exist Figure 1 The semiconductor device 100 shown in FIG. 1 is a vertical power MOSFET having a channel region 126 extending in a vertical direction along a gate dielectric 110 in a body region 118. By applying a sufficient gate voltage to the gate electrode 108, minority carriers (electrons in the case of a p-type body region 118, or holes in the case of an n-type body region 118) gather in the channel region 126 along the gate dielectric 110, and a conductive path is completed between the source / emitter region 116 and the drain / collector region 122 via the drift and channel regions 120, 126.

[0018] An interlayer dielectric 128 such as silicon dioxide, silicon nitride, tetraethyl orthosilicate (TEOS), etc. is formed on the front surface 106 of the semiconductor substrate 102 to separate one or more overlying metal layers (not shown) from the underlying semiconductor substrate 102. A contact opening 130 extends through the interlayer dielectric 128 and into the semiconductor substrate 102. In one embodiment, the minimum width (w1) of the contact opening 130 in the interlayer dielectric 128 is greater than the minimum width (w2) of the contact opening 130 in the semiconductor substrate 102. The width of the drift region 120 between adjacent gate trenches 104 is about 1 / 8 of the width of the drift region 120. Figure 1 The portion of the contact opening 130 formed in the semiconductor substrate 102 is also referred to herein as a recess. The conductive material 132 fills the contact opening 130 to form a body contact plug 134, which has a stepped profile in the contact opening 130 due to the width difference (w1>w2) described above.

[0019] The contact opening 130 extends at least into the body region 118. Figure 1 In the embodiment illustrated in FIG, the contact opening 130 terminates within the body region 118 such that the body contact plug 134 is separated from the drift region 120 by a segment of the body region 118. A highly doped (e.g., p+) body contact region 136 of the second conductivity type and more heavily doped than the body region 118 is formed in the body region 118 adjacent to the bottom of the contact opening 130. The highly doped body contact region 136 abuts the body contact plug 134 at the bottom of the contact opening 130 and is in ohmic contact therewith.

[0020] Electrically insulating spacers 138 are disposed on sidewalls 140 of the semiconductor substrate 102 formed by the contact openings 130. The conductive material 132 in the contact openings 130 abuts the electrically insulating spacers 138 on the sidewalls 140 of the semiconductor substrate 102 formed by the contact openings 130. By providing the electrically insulating spacers 138 along the sidewalls 140 of the semiconductor substrate 102 formed by the contact openings 130, the lateral size of the channel region 126 can be reduced while also reducing the source capacitance and increasing the distance between the body contact plug 134 and the channel region 126. As a result, the body contact plug 134 is better decoupled from the channel region 126 by the electrically insulating spacers 138 disposed on the sidewalls 140 of the semiconductor substrate 102 formed by the contact openings 130. Any suitable electrically insulating material such as oxide, nitride, carbon, TEOS, etc. can be used for the electrically insulating spacers 138.

[0021] According to Figure 1, the electrically insulating spacer 138 extends onto the front surface 106 of the semiconductor substrate 102, extends along the sidewalls 142 of the interlayer dielectric 128 formed by the contact opening 130, and extends onto the surface 144 of the interlayer dielectric 128 facing away from the semiconductor substrate 102. With such a contact recess spacer configuration, the ohmic contact between the highly doped body contact region 136 and the body contact plug 134 formed in the semiconductor substrate 102 only occurs at the bottom of the contact opening 130. As previously described herein, the semiconductor substrate 102 may include one or more epitaxial layers, such as Si epitaxial layers. For example, the heavily doped drain / collector region 122 may have been fabricated from a semiconductor wafer, and the body region 118 and the drift region 120 may be formed in one or more epitaxial layers grown on the heavily doped drain / collector region 122.

[0022] Figure 2 A partial cross-sectional view of another embodiment of a semiconductor device 200 having a buried dielectric plug is illustrated. Figure 2 The embodiments shown in Figure 1 130. However, the difference is that a portion of the electrically insulating spacer 138 disposed in the contact opening 130 is recessed below the front surface 106 of the semiconductor substrate 102 along the sidewall 140 of the semiconductor substrate 102 formed by the contact opening 130. According to this embodiment, the electrically insulating spacer 138 is recessed before the formation of the highly doped body contact region 136. As a result, a portion of the source / collector region 116 exposed as a result of the removal of the electrically insulating spacer 138 in the selected area is implanted during the body contact formation process. After a corresponding annealing process, a first highly doped body contact region 136 of a second conductivity type that is more heavily doped than the body region 118 is formed in the body region 118 adjacent to the bottom of the contact opening 130. A second highly doped body contact region 202 of a second conductivity type may be formed in a portion of the source / collector region 116 exposed as a result of the selective removal of the electrically insulating spacer 138. The first highly doped body contact region 136 is adjacent to and in ohmic contact with the body contact plug 134 at the bottom of the contact opening 130, while the second highly doped body contact region 202 is adjacent to and in ohmic contact with the body contact plug 134 along the portion of the contact opening 130 without the electrically insulating spacer 138. Figure 2A variation of the embodiment shown in can omit the second highly doped body contact region 202, so that the source / collector region 116 along the sidewalls of the contact opening 130 and possibly along portions of the front surface 106 of the semiconductor body 102 are at least partially uncovered by the electrically insulating spacers 138. For example, the first highly doped body contact region 136 can be formed by an implant (e.g., p+) at the bottom of the contact opening 130. Some of the implanted dopant species may also reach the uncovered portions of the sidewalls of the contact opening 130. In a first option, the uncovered portions of the source / collector region 116 are implanted and include the highly doped contact region 202 in the final product. In a second option, the implantation does not substantially affect the doping of the source / collector 116, so that the final product does not include the highly doped contact region 202, but has a total (net) doping concentration that is sufficient to act as a source / collector of the device and ensure that a good ohmic contact (e.g., n+) is maintained.

[0023] Figure 3 A partial cross-sectional view of yet another embodiment of a semiconductor device 300 having a body contact and a dielectric spacer is shown. Figure 3 The embodiments shown in Figure 2 106. However, the difference is that the segment 302 of the body region 118 extends to the front surface 106 of the semiconductor substrate 102, and each source / collector region 116 is laterally arranged between adjacent gate trenches 104 and the segment 302 of the body region 118 extending to the front surface 106 of the semiconductor substrate 102. The contact opening 130 is formed in the segment 302 of the body region 118 extending to the front surface 106 of the semiconductor substrate 102. The electrically insulating spacer 138 is recessed below the front surface 106 of the semiconductor substrate 102 along the sidewall 140 of the segment 302 of the body region 118 extending to the front surface 106 of the semiconductor substrate 102, so that the upper portion of the sidewall 140 is free of the electrically insulating spacer 138.

[0024] Figure 4 A partial cross-sectional view of yet another embodiment of a semiconductor device 400 having a body contact and a dielectric spacer is shown. Figure 4 The embodiments shown in Figure 3. However, the difference is that the contact opening 130 extends to a deeper depth (d_co) measured from the front surface 106 in the semiconductor substrate 102 than the body region 118 and extends into the underlying drift region 120, so that the body contact plug 134 extends into the drift region 120. According to this embodiment, a highly doped body contact region 136 is formed in the drift region 120 adjacent to the body contact plug 134 at the bottom of the contact opening 130 and provides a blocking capability of the resulting pn junction with the drift region 120. The upper highly doped body contact region 202 provides a low ohmic connection to the body contact plug 134 at the front surface 106 of the semiconductor substrate 102.

[0025] In some embodiments, the source / collector region 116 has a depth in a range between 10 nm and 50 nm, the body region 118 has a depth in a range between 100 nm and 200 nm, the interlayer dielectric 128 has a thickness in a range between 50 nm and 300 nm, the contact opening 130 in the interlayer dielectric 128 has a minimum width w1 in a range between 200 nm and 220 nm, the contact (recess) opening 130 in the semiconductor body 100 has a minimum width w2 in a range between 100 nm and 140 nm, the length of the channel region 126 in the vertical direction is in a range between 50 nm and 200 nm, and / or the lateral channel length is less than 250 nm. Other depth, thickness, width, and length ranges are contemplated.

[0026] Figures 5A to 5D Diagram for manufacturing Figures 1 to 4 An embodiment of some processing steps of a semiconductor device is shown in FIG.

[0027] Figure 5A An interlayer dielectric 128 is shown formed on the front surface 106 of the semiconductor substrate 102 after the gate trench 104 , the source / collector region 116 , the body region 118 , the drift region 120 , and the drain / collector region 122 are formed.

[0028] Figure 5B An opening 500 is shown formed in the interlayer dielectric 128. The opening 500 may be formed using a self-aligned process, using a photolithography alignment process, etc. The critical dimension variation of the opening 130 and the amount of overlay define the width of the contact strip to be formed.

[0029] Figure 5CA recess 502 is shown aligned with the opening 500 in the interlayer dielectric 128 and etched into the semiconductor body 100. The recess 502 extends at least into the body region 118. The opening 500 in the interlayer dielectric 128 and the recess 502 etched into the semiconductor body 100 form a contact opening 130. The recess 502 may be etched completely through the body region 118 so that the contact opening 130 extends into the underlying drift region 120, for example, as in Figure 4 . In either case, the sidewalls 142 of the interlayer dielectric 128 formed by the openings 130 are etched back to define the thickness (t_s) of the electrically insulating spacers 138 to be formed. In one embodiment, the thickness of the electrically insulating spacers 138 is in a range between 10 nm and 30 nm. In one embodiment, the width of the semiconductor fins or strips 504 between each side of the contact openings 130 and the corresponding gate trenches 104 is less than 100 nm, for example, between 80 nm and 100 nm.

[0030] Figure 5D Electrically insulating spacers 138 are shown formed on a surface 144 of the interlayer dielectric 128 facing away from the semiconductor substrate 102, on etched-back sidewalls 142 of the interlayer dielectric 128, on the front surface 106 of the source / emitter region 116, and on the sidewalls 140 of a recess 502 formed in the semiconductor substrate 102 (which extends at least into the body region 118). Prior to depositing the conductive material 132, which fills the contact openings 130, the electrically insulating spacers 138 are removed from the bottom of the contact openings 130. The electrically insulating spacers 138 may also be removed from the front surface 106 of the source / emitter region 116 and along upper portions of the sidewalls 140 of the recess 502 formed in the semiconductor substrate 102, e.g., as in Figures 2 to 4 As shown in .

[0031] Figure 6 The picture is Figures 1 to 4 A partial top view of an embodiment of a semiconductor device is shown in FIG. Figure 6 The top half of the diagram is shown in Figure 1 1. The upper features of the semiconductor device 100 are shown in FIG. Figure 6 The bottom half of the diagram is shown in Figures 2 to 4 1 and 2. The upper features of the semiconductor devices 200, 300, 400 are shown in FIG. 1 . In each case, the gate trench 104 (at Figure 6 ), the source region 116 , the body region 118 , and the contact opening 130 are each strip-shaped and extend in the longitudinal direction of the semiconductor substrate 102 . Figure 6 The dashed line in demarcates the top and bottom halves of the figure.

[0032] Figure 7A partial cross-sectional view of an embodiment of a semiconductor device 700 having a body contact and dielectric spacers is shown. Figure 7 The embodiments shown in Figure 4 . However, the difference is that the second conductivity type column / pillar / strip region 702 is formed in the drift region 120 and abuts the highly doped body contact region 136 below the bottom of the contact opening 130. The second conductivity type column / pillar / strip region 702 extends to a greater depth into the semiconductor substrate 102 as measured from the front surface 106 than the gate trench 104 and the highly doped body contact region 136. In one embodiment, the second conductivity type column / pillar / strip region 702 extends to and abuts the drain / collector region 122 at the bottom surface 124 of the semiconductor substrate 102.

[0033] In addition, according to Figure 7 In the embodiment illustrated in FIG. 1 , an additional highly doped body contact region 202 of the second conductivity type is formed in a section of the body region 118 adjacent to the contact opening 130. The additional body contact region 202 is more heavily doped than the body region 118. The source / emitter region 116 adjoins a side surface 704 of the additional body contact region 202 facing the adjacent gate trench 104 and extends onto a front surface 706 of the additional body contact region 202. The conductive material filling the contact opening also adjoins the front surface of the additional body contact region.

[0034] Figure 8 A partial cross-sectional view of another embodiment of a semiconductor device 800 having a body contact and a dielectric spacer is shown. Figure 8 The embodiments shown in Figure 7 The embodiment shown in FIG. 1 is similar to that shown in FIG. 2 , however, the gate trench 104 does not include a field plate.

[0035] Fig. 9 A partial cross-sectional view of yet another embodiment of a semiconductor device 900 having a body contact and a dielectric spacer is shown. Fig. 9 The embodiments shown in Figure 7 104. However, the difference is that a column / pillar / strip region 902 of the first conductivity type is formed in the drift region 120 below each gate trench 104. The column / pillar / strip region 902 of the first conductivity type is laterally separated from the column / pillar / strip region 702 of the second conductivity type by a segment of the drift region 120. The column / pillar / strip region 902 of the first conductivity type extends to and is adjacent to the drain / collector region 122 at the back surface 124 of the semiconductor substrate 102. The drain / collector region 122 is more heavily doped than the column / pillar / strip region 902 of the first conductivity type.

[0036] Fig.10A partial cross-sectional view of yet another embodiment of a semiconductor device 1000 having a body contact and a dielectric spacer is shown. Fig.10 The embodiments shown in Figure 8 104. However, the difference is that a column / pillar / strip region 902 of the first conductivity type is formed in the drift region 120 below each gate trench 104. The column / pillar / strip region 902 of the first conductivity type is laterally separated from the column / pillar / strip region 702 of the second conductivity type by a segment of the drift region 120. The column / pillar / strip region 902 of the first conductivity type extends to and is adjacent to the drain / collector region 122 at the back surface 124 of the semiconductor substrate 102. The drain / collector region 122 is more heavily doped than the column / pillar / strip region 902 of the first conductivity type.

[0037] exist Figures 7 to 10 The semiconductor devices 700 , 800 , 900 , 1000 illustrated in FIG. 7 are shown as n-channel devices, but the conductivity type of the device regions may be reversed to implement p-channel devices instead.

[0038] Figures 11A to 11Q Picture made in Fig.10 An embodiment of a method of a semiconductor device 1000 is shown in FIG.

[0039] Fig.11A A semiconductor substrate 1100 is shown having an n+ region 1102 at a back surface 1101 of the substrate 1100 and an n- region 1104 adjacent to the n+ region 1102. The semiconductor substrate 1100 may include any type of semiconductor material, such as a single element semiconductor (e.g., Si, Ge, etc.), silicon on insulator, a binary semiconductor (e.g., SiC, GaN, GaAs, etc.), a ternary semiconductor, etc., with or without (one or more) epitaxial layers. The n- region 1104 may be formed, for example, as part of an epitaxial layer. A hard mask 1106 is formed on a front surface 1103 of the semiconductor substrate 1100. An opening 1108 is etched through the hard mask 1106, for example by using an anisotropic etching process, to expose a portion of the front surface 1103 of the semiconductor substrate 1100.

[0040] Fig. 11B The semiconductor substrate 1100 is shown after the portion of the semiconductor substrate 1100 exposed by the opening 1108 in the hard mask 1106 is recessed below the front surface 1103 of the substrate 1100. The depth of the recess 1110 may vary based on the application.

[0041] Fig. 11CThe semiconductor substrate 1100 is shown after the hard mask 1106 is removed and a spacer oxide 1112 is formed on the front surface 1103 of the substrate 1100. An opening 1114 is etched through the spacer oxide 1112 to expose a portion of the recessed surface 1110 of the semiconductor substrate 1100.

[0042] Fig.11D The semiconductor substrate 1100 is shown after a recess 1116 is etched into the exposed portion of the recessed surface 1110 of the semiconductor substrate 1100. The recess 1116 has sidewalls 1118 and a bottom 1120. The depth of the recess 1116 may vary depending on the application.

[0043] Fig.11E The semiconductor substrate 1100 is shown after forming a sacrificial oxide 1122 on the sidewalls 1118 and the bottom 1120 of the recess 1116 formed in the recessed surface 1110 of the semiconductor substrate 1100 .

[0044] Fig.11F Semiconductor substrate 1100 is shown after p-type pillar / column / stripe regions 1124 are implanted into n-layer 1104 through bottoms 1120 of recesses 1116 formed in recessed surface 1110 of semiconductor substrate 1100 .

[0045] Fig.11G The semiconductor substrate 1100 is shown after the spacer oxide 1112 and the sacrificial oxide 1122 are removed and the recessed portions of the substrate 1100 are filled with an oxide 1126. The spacer oxide 1112 and the sacrificial oxide 1122 are removed from the front surface 1103 of the semiconductor substrate 1100, for example, by a CMP (chemical mechanical polishing) process that stops on the semiconductor material of the substrate 1100.

[0046] Fig.11H The semiconductor substrate 1100 is shown after trenches 1128 have been etched into portions of the substrate 1100 that are not protected by the sacrificial oxide 1126. Each trench 1128 has sidewalls 1130 and a bottom 1132.

[0047] Fig.11I The semiconductor substrate 1100 is shown after forming a sacrificial oxide 1134 on the sidewalls 1130 and bottom 1132 of the trench 1128 .

[0048] Fig.11JSemiconductor substrate 1100 is shown after n-type pillars / pillars / strip regions 1136 are implanted into n-layer 1104 through bottom 1132 of each trench 1128. In one embodiment, p-type pillars / pillars / strip regions 1124 extend to n+ layer 1102 at back surface 1101 of semiconductor substrate, while n-type pillars / pillars / strip regions terminate in the n- layer before reaching the n+ layer.

[0049] Figure 11K The semiconductor substrate 1100 is shown after the sacrificial oxide 1134 is removed, a gate oxide is formed on the sidewalls 1130 and bottom 1132 of each trench 1128, and each trench 1128 is filled with a conductive material such as doped polysilicon. The gate oxide and the conductive material are planarized, for example, by a CMP (chemical mechanical polishing) process that stops on the semiconductor material of the substrate 1100. The resulting trench structure forms gate trenches 1138, each of which includes a gate electrode 1140 in the trench 1138 and a gate dielectric 1142 that separates the gate electrode 1140 from the semiconductor substrate 1100.

[0050] Fig.11L The semiconductor substrate 1100 is shown after the front surface of the substrate 1100 has been recessed between the gate trenches 1138, such as by dry and / or wet etching, thereby recessing the n-layer 1104 in this region of the substrate 1100. Furthermore, the gate electrode 1140 is covered with an oxide 1144.

[0051] Fig.11M The semiconductor substrate 1100 is shown after p-type body regions 1146 and n-type source / emitter regions 1148 are formed in the n-layer 1104 between the gate trenches 1138. P-type dopants are implanted into the semiconductor substrate 1100 between the gate trenches 1138 and annealed to form the p-type body regions 1146, and n-type dopants are implanted between the gate trenches 1138 and annealed to form the source / emitter regions 1148.

[0052] Fig.11NThe semiconductor substrate 1100 is shown after an interlayer dielectric 1150 is formed on the front surface of the semiconductor substrate 1100, an opening 1152 is formed in the interlayer dielectric 1150, and a groove 1154 is etched into the portion of the semiconductor substrate 1100 exposed by the opening 1152 in the interlayer dielectric 1150. The opening 1152 in the interlayer dielectric 1150 is wider than the contact groove 1154 etched in the semiconductor substrate 1100. The interlayer dielectric material is removed from the portion of the front face 1156 of the source / emitter region 1148 that is closest to the contact groove 1154 and from the side faces 1158 of the source / emitter region 1148 that face the contact groove 1154, thereby exposing those faces 1156, 1158 of the source / emitter region 1148. The interlayer dielectric material remains on the sidewalls 1160 of the contact recesses 1154 below the source / emitter regions 1148 to form dielectric spacers 1151 , but is removed from the bottoms 1162 of the contact recesses 1154 .

[0053] Fig.11O The semiconductor substrate 1100 is shown after the exposed surfaces 1156 , 1158 of the source / emitter regions 1148 are etched away to recess each source / emitter region 1148 laterally in a direction toward an adjacent gate trench 1138 , thereby exposing a portion of the front face 1164 of the body region 1146 nearest the contact recess 1166 .

[0054] Figure 11P The semiconductor substrate 1100 is shown after p-type dopants are implanted into exposed portions of the substrate 1100 and subsequently annealed to form a first highly doped (e.g., p+) body contact region 1168 at the bottom of each contact recess 1166 , and a second highly doped (e.g., p+) body contact region 1170 is formed in an exposed portion of the front face 1164 of each body region 1146 that is closest to the corresponding contact recess 1166 .

[0055] Figure 11Q The semiconductor substrate 1100 is shown after a conductive material 1172, such as a metal, is deposited over the substrate to fill the contact opening 1166. The conductive material adjoins the recessed portion of the semiconductor substrate 1100 and is planarized, for example, by a CMP process. Figures 11A to 11Q The semiconductor device region illustrated in FIG. 1 is shown as a device region of an n-channel device, but the conductivity type of the device region may be reversed to implement a p-channel device instead.

[0056] The superjunction charge balance structure formed by the p-type and n-type pillars / pillars / strips 1124, 1136 results in a reduced on-resistance while maintaining a desired breakdown voltage. By providing a dielectric spacer 1151 in the body contact opening to separate the channel region 1174 from the underlying p-type pillar / pillar / strip 1124, the required width of the p-type pillar / pillar / strip 1124 can be reduced, which in turn reduces the energy level required to implant the p-type pillar / pillar / strip 1124, which is used to form the superjunction structure and achieve charge balance. Using a deep body contact opening and a contact trench with an underlying p-type pillar / pillar / strip, the desired voltage can be maintained while also relocating the impact ionization location to the vicinity of the p-type pillar / pillar / strip. Such a configuration causes a greater portion of the avalanche current to flow directly through the p-type pillar / column / strip and spread to the source metal, and by doing so, effectively avoids high current density around the source / emitter region and subsequent turn-on of the parasitic BJT (which could otherwise destroy the device). The depth of the gate trench 1138 can be varied to adjust the gate charge and gate resistance.

[0057] Fig.12 A partial cross-sectional view of an embodiment of a semiconductor device 1200 having a body contact and a dielectric spacer is shown. Fig.12 The embodiments shown in Fig.10 and 11Q 1. However, the difference is that the semiconductor device 1200 also includes a Schottky barrier diode 1202 formed in the semiconductor substrate 102 between adjacent body contact openings / recesses 130 formed in the substrate 102. The Schottky barrier diode 1202 is spaced apart from each adjacent gate trench 104 by a corresponding contact opening / recess 130 extending along each longitudinal side of the Schottky barrier diode 1202. One sidewall 1204 of the semiconductor substrate 102 formed by each adjacent contact opening / recess 130 abuts the Schottky barrier diode 1202. The Schottky barrier diode 1202 includes a Schottky contact 1206 located on the front face 106 of the semiconductor substrate 102 between the adjacent contact openings / recesses 130 formed in the substrate 102. Any suitable metal or metal silicide can be used for the Schottky contact 1206. A guard ring 1208 of p+ semiconductor material may be provided around the edge of the Schottky barrier diode 1202, surrounding the Schottky contact 1206. During a transient event, the guard ring 1208 drives adjacent semiconductor regions into avalanche breakdown before the Schottky junction is damaged by large levels of reverse current flow.

[0058] The Schottky barrier diode 1202 has low leakage, low forward voltage, and low reverse recovery charge Qrr when combined with a power MOSFET. A gate trench 104 having an underlying superjunction structure formed by a column / pillar / strip region 702 of the second conductivity type and a drift region 120 of the first conductivity type is located on both sides of the gate region and the diode mesa. When the device 1200 is disconnected both at the Schottky barrier and at the body diode of the transistor, the superjunction structure below the body contact 136 at the bottom of the contact opening / recess 130 reduces leakage. The conductivity type of the device region is Fig.12 can be inverted to achieve a p-channel device instead of an n-channel device.

[0059] Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to those depicted in the figures. In addition, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, and the like, and are also not intended to be limiting. Throughout this description, similar terms refer to similar elements.

[0060] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0061] In view of the above range of variations and applications, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

1. A semiconductor device, comprising: a trench extending into the first major surface of the semiconductor substrate; a gate electrode and a gate dielectric in the trench, the gate dielectric separating the gate electrode from the semiconductor substrate; a first region having a first conductivity type, the first region being formed in the semiconductor substrate at a first surface and adjacent to the trench; a second region having a second conductivity type opposite to the first conductivity type and formed in the semiconductor substrate below the first region and adjacent to the trench; a third region having a first conductivity type, the third region being formed in the semiconductor substrate below the second region and adjacent to the trench; a contact opening in the semiconductor substrate, the contact opening extending into the second region, the contact opening forming at least one sidewall in the semiconductor substrate, the at least one sidewall comprising a first portion extending along the first region and a second portion extending along the second region; an electrically insulating spacer located on a sidewall of the semiconductor substrate formed by the contact opening, wherein the electrically insulating spacer covers the entire second portion of the at least one sidewall and leaves at least a portion of the first portion of the at least one sidewall exposed; as well as The same conductive material is located in the contact opening, electrically connected to the first region via an exposed portion in the first region of the at least one sidewall and adjoins an electrically insulating spacer on the sidewall of the semiconductor substrate formed by the contact opening. 2 . The semiconductor device according to claim 1 , wherein the electrically insulating spacer is recessed below the first main surface of the semiconductor substrate along a sidewall of the semiconductor substrate formed by the contact opening. 3 . The semiconductor device of claim 1 , wherein the contact opening terminates within the second region such that the conductive material is separated from the third region by a segment of the second region.

4. The semiconductor device according to claim 3 further comprises an additional region of the second conductivity type formed in the second region adjacent to the bottom of the contact opening, wherein the additional region is more heavily doped than the second region and adjoins the conductive material at the bottom of the contact opening. 5 . The semiconductor device of claim 1 , wherein the contact opening extends through the second region and into the third region such that the conductive material extends into the third region. 6 . The semiconductor device according to claim 5 , further comprising a first additional region of the second conductivity type, which is formed in the third region and adjoins the conductive material at the bottom of the contact opening. 7 .

7. The semiconductor device according to claim 6 further includes a second additional region of the second conductivity type formed in the third region, wherein the second additional region of the second conductivity type is adjacent to the first additional region of the second conductivity type below the bottom of the contact opening and extends to a greater depth in the semiconductor substrate as measured from the first main surface than both the trench and the first additional region of the second conductivity type, and wherein the first additional region of the second conductivity type is more heavily doped than the second additional region of the second conductivity type.

8. The semiconductor device according to claim 7 further comprises a first additional region of the first conductivity type formed at a second main surface of the semiconductor substrate opposite to the first main surface, wherein the first additional region of the first conductivity type is more heavily doped than the third region, and wherein a second additional region of the second conductivity type extends to and is adjacent to the first additional region of the first conductivity type.

9. The semiconductor device according to claim 8 further includes a second additional region of the first conductivity type formed in the third region below the trench, wherein the first additional region of the first conductivity type is more heavily doped than the second additional region of the first conductivity type, and wherein the second additional region of the second conductivity type is laterally separated from the second additional region of the first conductivity type by a segment of the third region. 10 . The semiconductor device of claim 9 , wherein the second additional region of the first conductivity type extends to and adjoins the first additional region of the first conductivity type. 11 . The semiconductor device of claim 9 , further comprising a field plate located in the trench below the gate electrode, wherein the field plate is electrically insulated from the gate electrode.

12. A semiconductor device according to claim 1, wherein a segment of the second zone extends to the first main surface of the semiconductor substrate, wherein the first zone is laterally arranged between the trench and the segment of the second zone extending to the first main surface of the semiconductor substrate, and wherein the contact opening is formed in the segment of the second zone extending to the first main surface of the semiconductor substrate.

13. The semiconductor device of claim 12 , wherein the electrically insulating spacer is recessed below the first main surface of the semiconductor substrate along sidewalls of a segment of the second region extending to the first main surface of the semiconductor substrate such that an upper portion of the sidewall is free of the electrically insulating spacer.

14. The semiconductor device according to claim 13 further includes a first additional region of a second conductivity type, which is formed in the second region adjacent to the upper portion of the side wall without the electrically insulating spacer, wherein the first additional region of the second conductivity type is more heavily doped than the second region and is adjacent to the conductive material along the upper portion of the side wall without the electrically insulating spacer. 15 . The semiconductor device of claim 14 , wherein the contact opening extends through the second region and into the third region such that the conductive material extends into the third region. 16 . The semiconductor device of claim 15 , further comprising a second additional region of the second conductivity type formed in the third region, wherein the second additional region of the second conductivity type is more heavily doped than the second region and adjoins the conductive material at a bottom of the contact opening. 17 . The semiconductor device of claim 14 , wherein the contact opening terminates within the second region such that the conductive material is separated from the third region by a segment of the second region.

18. The semiconductor device according to claim 17 further comprises a second additional region of the second conductivity type formed in the second region adjacent to the bottom of the contact opening, wherein the second additional region of the second conductivity type is more heavily doped than the second region and adjoins the conductive material at the bottom of the contact opening.

19. The semiconductor device according to claim 1 further includes an interlayer dielectric on the first main surface of the semiconductor substrate, wherein the contact opening extends through the interlayer dielectric and extends into the semiconductor substrate, and wherein the width of the contact opening in the interlayer dielectric is larger than that in the semiconductor substrate, so that the conductive material has a stepped profile in the contact opening.

20. The semiconductor device of claim 1 , further comprising an interlayer dielectric on a first main surface of the semiconductor substrate, wherein the contact opening extends through the interlayer dielectric and into the semiconductor substrate, and wherein the electrically insulating spacer extends onto the first main surface of the semiconductor substrate and along sidewalls of the interlayer dielectric formed by the contact opening.

21. The semiconductor device of claim 1, wherein the electrically insulating spacer extends onto the first main surface of the semiconductor substrate.

22. The semiconductor device according to claim 1 further comprises an additional region of a second conductivity type formed on a segment of the second zone adjacent to the contact opening, wherein the additional region of the second conductivity type is more heavily doped than the second zone, wherein the first zone is adjacent to the side surface of the additional region of the second conductivity type facing the groove and extends onto the front surface of the additional region of the second conductivity type, and wherein the conductive material is also adjacent to the front surface of the additional region of the second conductivity type.

23. The semiconductor device of claim 1, wherein the electrically insulating spacer comprises oxide, nitride, carbon or tetraethyl orthosilicate. 24 . The semiconductor device according to claim 1 , wherein a portion of a first main surface of the semiconductor substrate is recessed in a region adjacent to the contact opening, and wherein the conductive material adjoins the recessed portion of the first main surface.

25. The semiconductor device according to claim 1 further includes a Schottky barrier diode, which is formed in the semiconductor substrate at a side of the contact opening opposite to the trench, so that the Schottky barrier diode is separated from the trench by the contact opening, wherein one of the side walls of the semiconductor substrate formed by the contact opening is adjacent to the Schottky barrier diode.

26. The semiconductor device according to claim 25, further comprising: a first additional region of a first conductivity type formed at a second main surface of the semiconductor substrate opposite to the first main surface; as well as a first additional region of the second conductivity type formed in the third region below the contact opening and extending to the first additional region of the first conductivity type, Therein the first additional region of the first conductivity type is more heavily doped than said third region.

27. The semiconductor device according to claim 26, further comprising: an additional contact opening in the semiconductor substrate at a side of the Schottky barrier diode facing away from the trench; as well as A second additional region of the second conductivity type is formed in the third region below the additional contact opening and extends to the first additional region of the first conductivity type.

28. A semiconductor device according to claim 1, wherein the electrically insulating spacer is recessed below the first main surface of the semiconductor substrate along the sidewalls of the first region, wherein the first region includes a first additional region of a second conductivity type adjacent to the sidewalls of the first region, and wherein the first region forms a source or collector of the semiconductor device.

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