Double-channel planar gate silicon carbide LDMOS (laterally diffused metal oxide semiconductor)

Abstract

The utility model provides a double-channel planar gate silicon carbide LDMOS. The double-channel planar gate silicon carbide LDMOS is characterized in that a first N-type source region is connected with a silicon carbide substrate; the first channel region is connected with the silicon carbide substrate and the first N-type source region; the isolation region is respectively connected with the first channel region, the first N-type source region and the second N-type source region; the second channel region is connected to the isolation region and the first N-type source region; the P-type well region is connected with the isolation region and the second channel region, and the P-type well region is connected to the first N-type source region; the second N-type source region is arranged in the first through hole, the second N-type source region is connected to the isolation region, the body diode metal layer is arranged in the second through hole, and the body diode metal layer is connected to the isolation region; the gate dielectric layer is connected with the P-type well region, the source metal layer is arranged in the third through hole, and the source metal layer is connected to the second N-type source region and the body diode metal layer; the gate metal layer is connected to the gate dielectric layer; the drain metal layer is connected to the first N-type source region; double-channel structure design is carried out in the transverse power device, so that the on-resistance of the device is reduced.

Description

Technical Field

[0001] The utility model relates to a double-channel planar gate silicon carbide LDMOS. Background Art

[0002] LDMOS (Laterally Diffused Metal Oxide Semiconductor) is a special type of power MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) widely used in RF and microwave power amplifiers. LDMOS combines the advantages of bipolar transistors and MOSFETs, providing high gain, high durability, and good thermal stability.

[0003] LDMOS has a wide range of applications, including CDMA, W-CDMA, TETRA, digital terrestrial television, and other fields that require a wide frequency range, high linearity, and a long service life. With continuous technological advancements, LDMOS performance is also constantly improving. For example, Philips' fifth-generation LDMOS technology provides higher power density and efficiency. However, existing LDMOS still has relatively high on-resistance, and interference between channels reduces conductivity. Utility Model Content

[0004] The technical problem to be solved by the present invention is to provide a dual-channel planar gate silicon carbide LDMOS, which implements a dual-channel structure design in a lateral power device to reduce the on-resistance of the device.

[0005] In a first aspect, the present invention provides a dual-channel planar gate silicon carbide LDMOS, comprising:

[0006] Silicon carbide substrate,

[0007] a first N-type source region, wherein the lower side of the first N-type source region is connected to the upper side of the silicon carbide substrate;

[0008] a first channel region, wherein a lower side surface of the first channel region is connected to an upper side surface of the silicon carbide substrate, and an outer side surface of the first channel region is connected to an inner side surface of the first N-type source region;

[0009] an isolation region, wherein a lower side surface of the isolation region is connected to the first channel region and the first N-type source region respectively; and an outer side surface of the isolation region is connected to an inner side surface of the first N-type source region;

[0010] a second channel region, wherein a lower side surface of the second channel region is connected to an upper side surface of the isolation region, and a left side surface of the second channel region is connected to the first N-type source region;

[0011] a P-type well region, wherein the lower side of the P-type well region is connected to the isolation region, the left side of the P-type well region is connected to the right side of the second channel region, and the right side of the P-type well region is connected to the first N-type source region; and a first through hole is provided in the P-type well region;

[0012] a second N-type source region, the second N-type source region being disposed in the first through-hole, the lower side of the second N-type source region being connected to the upper side of the isolation region, and a second through-hole being disposed in the second N-type source region;

[0013] a body diode metal layer, wherein the body diode metal layer is disposed in the second through-hole, and a lower side of the body diode metal layer is connected to the isolation region;

[0014] a gate dielectric layer, the gate dielectric layer being connected to the P-type well region, and a third through hole being provided in the gate dielectric layer;

[0015] a source metal layer, the source metal layer being disposed in the third through-hole, the lower side of the source metal layer being connected to the upper side of the second N-type source region and the upper side of the body diode metal layer;

[0016] a gate metal layer connected to the gate dielectric layer;

[0017] and a drain metal layer connected to the first N-type source region.

[0018] The advantages of the present invention are:

[0019] 1. The present invention constructs a dual channel based on an N-type LDMOS device. By constructing a low-resistance first channel, the device on-state current can be effectively shunted to the top and inside of the device, thereby reducing the on-state resistance of the device.

[0020] Second, the present invention constructs a body diode metal layer just below the source metal of the device, which can allow electrons from the source to flow through it to the P-type isolation region and then to the first N-type source region when the device is not conducting, forming a parasitic body diode with the drain through the second channel;

[0021] 3. The gate structure of the present invention is distributed on the left and right sides of the source, with the left gate controlling the second channel region on the surface of the device, and the right gate controlling the first channel of the device;

[0022] Fourth, the present invention adopts a P-type silicon carbide substrate, which can effectively suppress the substrate leakage of the device;

[0023] 5. P-type isolation regions are set in the first channel region and the second channel region, which can effectively suppress the mutual interference between the second channel of the device and the second channel, and improve the conductivity of each channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0025] Figure 1 This is a schematic diagram of a dual-channel planar gate silicon carbide LDMOS according to the present invention.

[0026] Figure 2 This is a cross-sectional view of the process of a dual-channel planar gate silicon carbide LDMOS in this utility model. Figure 1 .

[0027] Figure 3 This is a cross-sectional view of the process of a dual-channel planar gate silicon carbide LDMOS in this utility model. Figure 2 .

[0028] Figure 4 This is a cross-sectional view of the process of a dual-channel planar gate silicon carbide LDMOS in this utility model. Figure 3 .

[0029] Figure 5 This is a cross-sectional view of the process of a dual-channel planar gate silicon carbide LDMOS in this utility model. Figure 4 .

[0030] Figure 6 This is a cross-sectional view of the process of a dual-channel planar gate silicon carbide LDMOS in this utility model. Figure 5 .

[0031] Figure 7 This is a cross-sectional view of the process of a dual-channel planar gate silicon carbide LDMOS in this utility model. Figure 6 .

[0032] Figure 8 This is a cross-sectional view of the process of a dual-channel planar gate silicon carbide LDMOS in this utility model. Figure 7 .

[0033] Figure 9 This is a cross-sectional view of the process of a dual-channel planar gate silicon carbide LDMOS in this utility model. Figure 8 .

[0034] Figure 10 This is a cross-sectional view of the process of a dual-channel planar gate silicon carbide LDMOS in this utility model. Figure 9 .

[0035] Figure 11 This is a cross-sectional view of the process of a dual-channel planar gate silicon carbide LDMOS in this utility model. Figure 10 .

[0036] Figure 12 This is a cross-sectional view of the process of a dual-channel planar gate silicon carbide LDMOS in this utility model. Figure 10 one. DETAILED DESCRIPTION

[0037] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0039] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0040] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0041] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] like Figure 1 As shown, the embodiment of the present application provides a dual-channel planar gate silicon carbide LDMOS, including:

[0043] silicon carbide substrate 101,

[0044] A first N-type source region 102 , wherein the lower side of the first N-type source region 102 is connected to the upper side of the silicon carbide substrate 101 ;

[0045] a first channel region 103 , wherein a lower side surface of the first channel region 103 is connected to an upper side surface of the silicon carbide substrate 101 , and an outer side surface of the first channel region 103 is connected to an inner side surface of the first N-type source region 102 ;

[0046] an isolation region 104 , wherein the lower side of the isolation region 104 is connected to the first channel region 103 and the first N-type source region 102 ; and the outer side of the isolation region 104 is connected to the inner side of the first N-type source region 102 ;

[0047] a second channel region 105 , wherein a lower side of the second channel region 105 is connected to an upper side of the isolation region 104 , and a left side of the second channel region 105 is connected to the first N-type source region 102 ;

[0048] a P-type well region 106, wherein the bottom side of the P-type well region 106 is connected to the isolation region 104, the left side of the P-type well region 106 is connected to the right side of the second channel region 105, and the right side of the P-type well region 106 is connected to the first N-type source region 102; a first through hole (not shown) is defined in the P-type well region 106;

[0049] A second N-type source region 107 is disposed in the first through-hole. The lower side of the second N-type source region 107 is connected to the upper side of the isolation region 104. A second through-hole (not shown) is disposed in the second N-type source region 107.

[0050] a body diode metal layer 108 , wherein the body diode metal layer 108 is disposed in the second through-hole, and a lower side of the body diode metal layer 108 is connected to the isolation region 104 ;

[0051] a gate dielectric layer 109 , the gate dielectric layer 109 being connected to the P-type well region 106 , and having a third through hole (not shown) defined therein;

[0052] a source metal layer 110 , wherein the source metal layer 110 is disposed in the third through-hole, and the lower side of the source metal layer 110 is connected to the upper side of the second N-type source region 107 and the upper side of the body diode metal layer 108 ;

[0053] a gate metal layer 111 , the gate metal layer 111 being connected to the gate dielectric layer 109 ;

[0054] and a drain metal layer 112 , wherein the drain metal layer 112 is connected to the first N-type source region 102 .

[0055] like Figures 1 to 12 As shown, the method for preparing the planar gate silicon carbide LDMOS comprises the following steps:

[0056] Step 1: forming a barrier layer 113 on the silicon carbide substrate 101, etching the barrier layer 113 to form a through hole, and performing ion implantation on the silicon carbide substrate 101 to form a first channel region 103, with the ion implantation energy being 230-330 keV;

[0057] Step 2: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and perform ion implantation on the silicon carbide substrate 101 to form a first N-type source region 102, with the ion implantation energy being 10-330 keV;

[0058] Step 3: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and perform ion implantation on the silicon carbide substrate 101 and the first N-type source region 102 to form an isolation region 104, with an ion implantation energy of 130-230 keV;

[0059] Step 4: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and perform ion implantation on the silicon carbide substrate 101 to form a second channel region 105, with the ion implantation energy being 10-130 keV;

[0060] Step 5: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and perform ion implantation on the silicon carbide substrate 101 and the first N-type source region 102 to form a P-type well region 106, with the ion implantation energy being 10-130 keV;

[0061] Step 6: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and perform ion implantation on the silicon carbide substrate 101 to form a second N-type source region 107, with an ion implantation energy of 10-130 keV;

[0062] Step 7: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, etch the silicon carbide substrate 101 to the upper side of the isolation region 104, and deposit metal to form a body diode metal layer 108;

[0063] Step 8: removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and depositing a gate dielectric layer 109;

[0064] Step 9: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and deposit metal to form a gate metal layer 111;

[0065] Step 10: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, deposit metal to form a source metal layer 110 and a drain metal layer 112 respectively, remove the barrier layer, and complete the preparation.

[0066] In this embodiment, preferably, the doping concentration of the first channel region 103 and the doping concentration of the second channel region 105 are both greater than the doping concentration of the isolation region 104 ; the doping concentration of the first channel region 103 is greater than the doping concentration of the second channel region 105 .

[0067] In this embodiment, preferably, the thickness of the second channel region 105 is greater than that of the first channel region 103 , and the thickness of the second channel region 105 is greater than that of the isolation region 104 ; the thickness of the first channel region 105 is equal to that of the isolation region 104 .

[0068] In this embodiment, preferably, the silicon carbide substrate 101 is of P type, the first channel region 103 and the second channel region 105 are both of N type, and the isolation region 104 is of P type.

[0069] The gate dielectric layer 109 is made of silicon dioxide, and the doping concentration of the silicon carbide substrate 101 is 1-5e17cm -3 The first channel region 103 is N-type doped with 1-3e18cm -3 The doping concentration of the first N-type source region 102 is 5-8e18cm -3 The doping concentration of the P-type isolation region 104 is 1-3e17cm -3 The second channel region 105 has a doping concentration of 5-9e17 cm -3The doping concentration of the second N-type source region 107 is 5-8e18cm -3 , the source metal layer 110 , the gate metal layer 111 , the drain metal layer and the body diode metal layer 108 may be one or more alloys of aluminum, nickel, and titanium;

[0070] The P-type silicon carbide substrate 101 is used to suppress reverse leakage of the device. Since the conductive path of the second channel region 105 is longer, the doping concentrations of the first channel region 103 and the first N-type source region 102 are used to reduce the on-resistance of the second channel region 105 and achieve better current shunting within the device. The doping concentration of the P-type isolation region 104 is used to ensure isolation between the first channel region 103 and the second channel region 105 while not affecting the conductive channel of the device and avoiding an increase in on-resistance. The first channel region 103 and the second N-type source region 107 are used to achieve a compromise between the on-resistance and withstand voltage of the device. The second N-type source region 107 and the first N-type source region 102 also form ohmic contacts with the drain metal layer 112 and the source metal layer 110.

[0071] The thickness of the P-type silicon carbide substrate 101 of the device is 300-500nm, which is to ensure the support of the subsequent structure preparation of the device. The thickness of the first channel region 103 is 300nm, which reserves the influence of the P-type isolation region 104 and the space charge region formed therewith on the on-resistance of the conductive channel. The thickness of the P-type isolation region 104 is 300nm. This is a compromise between achieving isolation function and avoiding influence on conductivity after comprehensive consideration of doping concentration and thickness. The thickness of the second channel region 105 is 400nm. This is because the doping concentration of the second channel region 105 is low, and it is designed to reduce the influence of the P-type isolation region 104 on it. The thickness of the first N-type source region 102 is 1000nm, which is to reduce the on-resistance of the second channel region 105 and achieve better shunting of the two channels. The thickness of the second N-type source region 107 is equal to that of the second channel region 105.

[0072] In traditional LDMOS, due to the limited gate thickness, the device current is mainly distributed at the top of the device. The present invention constructs a dual channel based on the N-type LDMOS device. By constructing a low-resistance first channel region 103, the device conduction current can be effectively divided between the top and inside of the device, thereby reducing the device's on-resistance.

[0073] A body diode metal layer 108 is constructed directly below the device source metal layer 110. When the device is not conducting, electrons from the source can flow through it to the P-type isolation region 104 and then to the first N-type source region 102. A parasitic body diode is formed with the drain through the second channel region 105 to complete the freewheeling when the device is not conducting.

[0074] The gate structure of the device is distributed on the left and right sides of the source. The left gate controls the second channel region 105 on the surface of the device, and the right gate controls the first channel region 103 of the device. The two gates are controlled by the same driving signal, avoiding the complexity of the driving.

[0075] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A dual-channel planar gate silicon carbide LDMOS, characterized by: include: Silicon carbide substrate, a first N-type source region, wherein the lower side of the first N-type source region is connected to the upper side of the silicon carbide substrate; a first channel region, wherein a lower side surface of the first channel region is connected to an upper side surface of the silicon carbide substrate, and an outer side surface of the first channel region is connected to an inner side surface of the first N-type source region; an isolation region, wherein a lower side surface of the isolation region is connected to the first channel region and the first N-type source region respectively; and an outer side surface of the isolation region is connected to an inner side surface of the first N-type source region; a second channel region, wherein a lower side surface of the second channel region is connected to an upper side surface of the isolation region, and a left side surface of the second channel region is connected to the first N-type source region; a P-type well region, wherein the lower side of the P-type well region is connected to the isolation region, the left side of the P-type well region is connected to the right side of the second channel region, and the right side of the P-type well region is connected to the first N-type source region; A first through hole is provided in the P-type well region; a second N-type source region, the second N-type source region being disposed in the first through-hole, the lower side of the second N-type source region being connected to the upper side of the isolation region, and a second through-hole being disposed in the second N-type source region; a body diode metal layer, wherein the body diode metal layer is disposed in the second through-hole, and a lower side of the body diode metal layer is connected to the isolation region; a gate dielectric layer, the gate dielectric layer being connected to the P-type well region, and a third through hole being provided in the gate dielectric layer; a source metal layer, the source metal layer being disposed in the third through-hole, the lower side of the source metal layer being connected to the upper side of the second N-type source region and the upper side of the body diode metal layer; a gate metal layer connected to the gate dielectric layer; and a drain metal layer connected to the first N-type source region.

2. The dual-channel planar gate silicon carbide LDMOS according to claim 1, wherein: The doping concentration of the first channel region and the doping concentration of the second channel region are both greater than the doping concentration of the isolation region.

3. The dual-channel planar gate silicon carbide LDMOS according to claim 1, wherein: The doping concentration of the first channel region is greater than the doping concentration of the second channel region.

4. The dual-channel planar gate silicon carbide LDMOS according to claim 1, wherein: The thickness of the second channel region is greater than that of the first channel region, and the thickness of the second channel region is greater than that of the isolation region.

5. The dual-channel planar gate silicon carbide LDMOS according to claim 1, wherein: The thickness of the first channel region is equal to the thickness of the isolation region.

6. The dual-channel planar gate silicon carbide LDMOS according to claim 1, wherein: The silicon carbide substrate is of P type.

7. The dual-channel planar gate silicon carbide LDMOS according to claim 1, wherein: The first channel region and the second channel region are both N-type, and the isolation region is P-type.

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