LDMOS device model and modeling method

Abstract

The LDMOS device model comprises a BSIM4 model, a plurality of segmented resistor models which are sequentially connected in series and a plurality of drain substrate diode models, and the segmented resistor models which are sequentially connected in series are connected to a drain electrode of the BSIM4 model in series. A drift region of an LDMOS is simulated through a plurality of segmented resistor models which are sequentially connected in series, and the input end of each segmented resistor model is connected with a corresponding drain substrate diode model. Due to the fact that the segmented resistor models are connected in series, changes of electrical characteristics of drain substrate diodes at different positions of a drift region are simulated, and then the simulation precision of the LDMOS device model on drain substrate parasitic capacitance and gate channel intrinsic capacitance of an LDMOS is improved. And the simulation precision of the reverse leakage current of the drain substrate diode is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor simulation, and in particular to a device model and modeling method for LDMOS. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOS) are widely used in modern power integrated circuits and radio frequency integrated circuits due to their excellent characteristics such as high breakdown voltage, good thermal stability, and excellent power handling capability. To ensure the reliability of circuit design, establishing an accurate LDMOS device model is crucial.

[0003] The BSIM4 model is currently the most widely used MOS model in manufacturing processes. However, the existing BSIM4 model cannot accurately simulate the characteristics of LDMOS. A drift region resistance model needs to be added to the BSIM4 model to improve the simulation accuracy of LDMOS. However, this results in significant discrepancies between the actual characteristics of the drain-drift-substrate diode and reality, severely affecting the simulation accuracy of parameters such as drain-substrate capacitance, turn-off current, and drain-substrate diode breakdown voltage. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a device model and modeling method for LDMOS, thereby improving the simulation accuracy of the LDMOS device model at a low cost.

[0005] According to a first aspect of the present invention, a device model of an LDMOS is provided, comprising: The BSIM4 model, wherein the gate of the BSIM4 model represents the gate of the LDMOS, the source of the BSIM4 model represents the source of the LDMOS, and the substrate of the BSIM4 model represents the substrate of the LDMOS; Several segmented resistor models are connected in series. The output of the first segmented resistor model is connected to the drain of the BSIM4 model, and the input of the last segmented resistor model represents the drain of the LDMOS. Several drain substrate diode models, each drain substrate diode model corresponding to one of the segmented resistor models, the negative terminal of the drain substrate diode model is connected to the input terminal of the corresponding segmented resistor model, and the positive terminal of the several drain substrate diode models is connected to the substrate of the BSIM4 model; Among them, the several segmented resistance models represent the equivalent resistance models of the drift region of LDMOS, and a segmented resistance model and the corresponding drain-substrate diode model represent a segment of the drift region of LDMOS.

[0006] Optionally, the model expression for the piecewise resistance model is: Ri = (1 + ai) * Rdrift / n Where Ri represents the i-th segmented resistance model, ai represents the segmentation coefficient of the i-th segmented resistance model, Rdrift represents the equivalent resistance model of the LDMOS drift region, and n represents the number of segmented resistance models; the sum of the segmentation coefficients of the n segmented resistance models is equal to 0.

[0007] Optionally, the number of segmented resistor models is determined based on the source-drain voltage drop of the LDMOS and the set withstand voltage across the segmented resistor model.

[0008] According to a second aspect of the present invention, a method for modeling an LDMOS device model is provided, comprising: An initial BSIM4 model is provided, wherein the drain substrate diode parameters of the initial BSIM4 model are zero; Obtain the electrical characteristic curves of the drain-substrate diode of the LDMOS and the current-voltage characteristic curves of the LDMOS; Based on the current-voltage characteristic curves, the BSIM4 model is obtained and the equivalent resistance model of the drift region of LDMOS is established. Based on the equivalent resistance model, multiple segmented resistance models corresponding to the drift region of the LDMOS are determined; Based on the electrical characteristic curve of the drain substrate diode, a drain substrate diode model corresponding to each segmented resistance model is established. The segmented resistance model and the corresponding drain substrate diode model represent a drift region of the LDMOS.

[0009] Optionally, the electrical characteristic curves include the current-voltage characteristic curve, capacitance-voltage characteristic curve, and reverse breakdown voltage characteristic curve of the drain-substrate diode. The method for establishing drain substrate diode models corresponding to each of the segmented resistance models based on the electrical characteristic curves of the drain substrate diode includes: The current-voltage characteristic curve, capacitance-voltage characteristic curve and reverse breakdown voltage characteristic curve of the drain substrate diode are fitted to obtain the initial drain substrate diode model. Determine the port voltage at the input of each segmented resistor model and the substrate voltage of the BSIM4 model; Based on the initial drain substrate diode model, and according to the port voltage and the substrate voltage of the BSIM4 model, each drain substrate diode model corresponding to each segmented resistance model is obtained, and each drain substrate diode model includes the electrical characteristics of the drain substrate diode.

[0010] Optionally, the step of obtaining each drain substrate diode model corresponding to each segmented resistance model based on the initial drain substrate diode model, according to each of the port voltages and the substrate voltage of the BSIM4 model, includes: Determine the junction area and junction perimeter of the drain substrate diode corresponding to each drift region of the LDMOS; Based on the initial drain substrate diode model, the electrical characteristics of the drain substrate diode model are obtained according to the port voltages and the substrate voltage of the BSIM4 model, as well as the junction area and junction perimeter.

[0011] Optionally, determining the junction area and junction perimeter of the drain substrate diode corresponding to each drift region of the LDMOS includes: Along the extension direction of the drift region of the LDMOS, obtain the length of the drift region and the number of segments of the drift region; The segment length of each sub-drift region is determined based on the drift region length of the LDMOS and the number of segments of the drift region; Based on the segment length of each drift region and the drift region width of the LDMOS, the junction area and junction perimeter of the drain substrate diode corresponding to each drift region are determined.

[0012] Optionally, methods for establishing the equivalent resistance model of the drift region of LDMOS include: The current-voltage characteristic curve of the LDMOS is fitted to obtain the equivalent resistance model of the drift region of the LDMOS.

[0013] Optionally, determining multiple segmented resistance models corresponding to the drift region of the LDMOS based on the equivalent resistance model includes: Based on the number of segments in the drift region of the LDMOS and the equivalent resistance model, multiple segmented resistance models corresponding to the drift region of the LDMOS are obtained; the model expression of the segmented resistance model is: Ri = (1 + ai) * Rdrift / n Wherein, Ri represents the i-th segmented resistance model, ai represents the segmentation coefficient of the i-th segmented resistance model, Rdrift represents the equivalent resistance model of the LDMOS drift region, n represents the number of segmented resistance models, the number of segmented resistance models is equal to the number of segments, and the sum of the segmentation coefficients of the n segmented resistance models is equal to 0.

[0014] Optionally, methods for determining the number of segments include: Obtain the source-drain voltage drop of the LDMOS and the set withstand voltage of the segmented resistance model; The number of segments in the drift region of the LDMOS is determined based on the source-drain voltage drop and the set withstand voltage.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The LDMOS device model and modeling method provided in this invention, based on the existing BSIM4 model (Berkeley Short-channel IGFET Model 4), additionally sets up several segmented resistor models connected in series. The output terminal of the first segmented resistor model is connected to the drain of the BSIM4 model, and the output terminal of each segmented resistor model is connected to the input terminal of the previous segmented resistor model. The input terminal of the last segmented resistor model represents the drain of the LDMOS (Lateral Diffused Metal-Oxide-Semiconductor). The sum of the resistance values ​​of the several segmented resistor models represents the equivalent resistance value of the drift region of the LDMOS, thus dividing the drift region of the LDMOS into several equal parts along the drift region's extension direction. According to the principle of resistor voltage division, from the last segmented resistor model to the first segmented resistor model, the input voltage of the segmented resistor model decreases sequentially, thereby simulating the voltage change at different positions of the drift region along the drift region's extension direction. The electrical characteristics of a diode change with the terminal voltage. Therefore, to better simulate the electrical characteristics of the drain substrate diode of an LDMOS, this invention additionally sets up several drain substrate diode models. Each drain substrate diode model corresponds to a segmented resistor model. The negative terminal of the drain substrate diode model is connected to the input terminal of the corresponding segmented resistor model, and the negative terminal of the drain substrate diode model is connected to the substrate of the BSIM4 model. Since the negative terminals of several drain substrate diode models are sequentially connected to the input terminal voltages of several segmented resistor models, the changes in the electrical characteristics of the drain substrate diode at different positions along the drift region extension direction are simulated. This improves the simulation accuracy of the LDMOS device model of this invention for the parasitic capacitance of the drain substrate and the intrinsic capacitance of the gate channel of the LDMOS, as well as the simulation accuracy of the reverse leakage current of the drain substrate diode. Finally, since the BSIM4 model is the mainstream compact transistor model in the industry, it has good convergence, compatibility with standard EDA tools, and high simulation speed. Therefore, modeling LDMOS based on the BSIM4 model inherits the beneficial effects of the BSIM4 model. At the same time, due to the maturity of the BSIM4 model, the design cost of modeling LDMOS based on the BSIM4 model is reduced.

[0016] Furthermore, the lengths of the segmented resistor models along the extension direction of the LDMOS drift region are all equal. Based on the resistor models that equally divide the drift region, different segmentation coefficients are set for each segmented resistor model to simulate the different equivalent resistance values ​​of the local structures of the drift region with the same length but at different positions along the extension direction of the LDMOS drift region. This improves the accuracy of the input voltage of the segmented resistor model, and further improves the simulation accuracy of the LDMOS device model for the parasitic capacitance of the drain substrate and the intrinsic capacitance of the gate channel, as well as the simulation accuracy of the reverse leakage current of the drain substrate diode. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 An equivalent circuit diagram of an embodiment of an LDMOS device model; Figure 2 This is a schematic cross-sectional view of an LDMOS embodiment. Figure 3 This is a schematic diagram of the equivalent circuit structure of the LDMOS device model provided in this embodiment; Figure 4 This is a schematic flowchart illustrating the modeling method for the LDMOS device model provided in this embodiment. Detailed Implementation

[0019] As described in the background section, existing LDMOS device models suffer from either high cost or poor accuracy. The following section uses an existing LDMOS device model to illustrate these problems.

[0020] Figure 1 This is an equivalent circuit diagram of an embodiment of an LDMOS device model. Figure 2 This is a schematic cross-sectional view of an LDMOS embodiment.

[0021] Because the existing BSIM4 model mainly models conventional MOSFET structures and lacks dedicated modeling support for the drift region structure unique to LDMOS, it cannot accurately simulate the electrical characteristics of LDMOS, especially the quasi-saturation region effect of LDMOS. This limitation seriously affects the simulation accuracy of LDMOS by the BSIM4 model.

[0022] Please refer to Figure 1 Compared to traditional solutions, Figure 1 This embodiment adds a customizable drift region equivalent resistor, Rdrift, in series at the drain of the BSIM4 model to simulate the drift region structure of LDMOS. By introducing this resistor, this embodiment accurately characterizes the quasi-saturation effect unique to LDMOS, thus effectively solving the problem that the traditional BSIM4 model cannot accurately simulate LDMOS characteristics while retaining the original advantages of the BSIM4 model (including good convergence, compatibility with standard EDA tools, and high simulation speed).

[0023] in, Figure 1 In the diagram, G represents the gate of the BSIM4 model, which is equivalent to the gate of the LDMOS model; B represents the substrate of the BSIM4 model, which is equivalent to the substrate of the LDMOS model; S represents the source of the BSIM4 model, which is equivalent to the source of the LDMOS model; D1 represents the drain of the BSIM4 model; D2 represents the drain of the LDMOS model; and d0 represents the drain substrate diode integrated into the BSIM4 model.

[0024] Please refer to Figure 2 In practical applications of LDMOS, the drift region structure of the LDMOS acts as the main voltage drop area of ​​the power supply. For example, if the power supply voltage is 35V, the drift region structure of the LDMOS will experience a voltage drop of about 30V. Therefore, along the extension direction of the drift region, different positions of the drift region will cause the drain substrate diode d0 to experience different terminal voltages, resulting in different electrical characteristics of the drain substrate diode d0 corresponding to different positions of the drift region, including the junction capacitance and leakage current characteristics of the diode.

[0025] However, this embodiment has the following problem: Please continue to refer to this. Figure 2 This embodiment only uses the voltage between point D1 and point B as the reverse bias voltage for modeling the drain substrate diode d0, which cannot characterize the voltage changes at different locations in the drift region. Therefore, the drain substrate diode d0 model in this embodiment cannot accurately simulate the electrical characteristics of the LDMOS drain substrate diode d0. For example, it cannot accurately simulate the parasitic capacitance of the LDMOS drain substrate and the intrinsic capacitance of the gate channel, as well as the reverse leakage current of the drain substrate diode d0. Furthermore, since the reverse leakage current of the drain substrate diode is an important component of the LDMOS turn-off current, a large simulation error in the reverse leakage current of the drain substrate diode will also lead to a large simulation error in the LDMOS turn-off current. In other words, the LDMOS model constructed in this embodiment cannot accurately simulate the characteristics of LDMOS and has a large simulation error.

[0026] In view of this, the technical solution of the present invention provides a new LDMOS device model, which may include a BSIM4 model, several segmented resistor models connected in series, and several drain substrate diode models. The several segmented resistor models connected in series are connected in series to the drain of the BSIM4 model to simulate the drift region of LDMOS. The input terminal of each segmented resistor model is connected to the negative terminal of the corresponding drain substrate diode model. Since the segmented resistor models are connected in series, the negative terminal voltage of each drain substrate diode model is different to simulate the changes in the electrical characteristics of the drain substrate diode at different positions in the drift region. This improves the simulation accuracy of the LDMOS device model of the present invention for the drain substrate parasitic capacitance and gate channel intrinsic capacitance of LDMOS, as well as the simulation accuracy of the reverse leakage current of the drain substrate diode.

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0030] Figure 3 This is a schematic diagram of the equivalent circuit structure of the LDMOS device model provided in this embodiment.

[0031] Please refer to Figure 3The LDMOS device model provided in this embodiment may include a BSIM4 model, several segmented resistor models R connected in series, and several drain substrate diode models.

[0032] Among them, the BSIM4 model is the mainstream compact transistor model in the industry, which can effectively characterize various physical phenomena of traditional MOSFETs, such as short-channel effects, quantum effects, and hot carrier effects. Furthermore, the BSIM4 model itself has good convergence, compatibility with standard EDA tools, and high simulation speed. Therefore, building an LDMOS device model based on the BSIM4 model will retain the advantages of BSIM4. At the same time, because the BSIM4 model technology is already very mature, compared to building an LDMOS device model from scratch, an LDMOS device model based on the BSIM4 model will reduce the design and development costs.

[0033] Specifically, the equivalent circuit of the BSIM4 model can include the gate (G), source (S), drain, and substrate (B) of a conventional MOSFET. In this embodiment, the gate (G), source (S), and substrate (B) of the equivalent circuit of the BSIM4 model represent the gate (G), source (S), and substrate (B) of an LDMOS, respectively.

[0034] Please continue to refer to this. Figure 3 In a series of segmented resistor models R connected in sequence, the output of the first segmented resistor model R is connected to the drain D1 of the BSIM4 model, the output of each segmented resistor model R is connected to the input of the previous segmented resistor model R, and the input of the last segmented resistor model R is connected to the drain D2 of the BSIM4 model.

[0035] In this embodiment, the number of segmented resistor models R is determined based on the source-drain voltage drop of the LDMOS and the set withstand voltage across the segmented resistor model. For example, if the source-drain voltage drop of the LDMOS is set to 20V and the set withstand voltage across the segmented resistor model is 5V, then the equivalent resistance model is divided into 4 segments, i.e., the number of segmented resistor models R is 4, and the number of drain substrate diode models d is also 4. Of course, the power supply voltage and the voltage difference between the negative terminals of adjacent drain substrate diode models d can be adjusted as needed, and are not limited here.

[0036] Since the segmented resistance models R connected in series in this embodiment are obtained by splitting the equivalent resistance model of the drift region of LDMOS along the extension direction of the drift region, the segmented resistance models represent the equivalent resistance model of the drift region of LDMOS.

[0037] The specific splitting method includes: dividing the LDMOS drift region equally according to its own extension direction and based on the length of the drift region to obtain multiple drift regions, that is, dividing the equivalent resistance model equally, with each drift region corresponding to a segmented resistance model.

[0038] It is understandable that the drift region lengths corresponding to the drift region extension directions of each segmented resistor model R are the same. Therefore, theoretically, each segmented resistor model R should also be the same. However, because the carrier concentration varies in different regions of the drift region under the conducting state—that is, from the drift region corresponding to the last segmented resistor model R4 to the drift region corresponding to the first segmented resistor model R1, the carrier concentration in the drift region gradually increases—the output resistance of the first segmented resistor model R1 is greater than that of the last segmented resistor model R4 under the same conditions. Therefore, each segmented resistor model R needs to be multiplied by the corresponding segmentation coefficient on top of the equivalent resistance model that equally divides the drift region, thereby improving the simulation accuracy of the LDMOS device model for LDMOS.

[0039] Specifically, the formula for the i-th piecewise resistor model R is as follows: Ri = (1 + ai) * Rdrift / n Formula (1) Where Ri represents the i-th segmented resistance model, ai represents the segmentation coefficient of the i-th segmented resistance model, Rdrift represents the equivalent resistance model of the LDMOS drift region, and n represents the number of segmented resistance models, which is equal to the number of segments in the LDMOS drift region.

[0040] Furthermore, ∑ai=0, i=1,2…,..n, to ensure that the sum of all piecewise resistance models R is equal to the equivalent resistance model.

[0041] Because there is a voltage drop in the drift region of an LDMOS transistor along its extension direction, the voltage varies at different locations within the drift region. This embodiment divides the equivalent resistance of the LDMOS drift region along its extension direction, forming several segmented resistors connected in series. This can be understood as replacing the original large resistor with several small resistors connected in series. Due to the voltage divider principle, the input voltage of each segmented resistor differs; that is, the input voltage of each segmented resistor decreases sequentially from the last segmented resistor to the first segmented resistor, thus simulating the voltage changes at different locations within the drift region.

[0042] Based on the decomposition of the equivalent resistance of the drift region, this embodiment provides several drain substrate diode models d, each corresponding to a segmented resistance model R. The negative terminal of each drain substrate diode model d is connected to the input terminal of the corresponding segmented resistance model R, and the negative terminal of each drain substrate diode model d is connected to the substrate of the BSIM4 model. Since the input voltage of different segmented resistance models R varies depending on their position within the drift region, the terminal voltage of different drain substrate diode models d also varies accordingly. This makes the terminal voltage of the drain substrate diode models d more consistent with the influence of the LDMOS drift region on the drain substrate diode, more closely reflecting the actual working principle of LDMOS. This improves the simulation accuracy of the LDMOS device model of this invention for the parasitic capacitance of the drain substrate and the intrinsic capacitance of the gate channel, as well as the simulation accuracy of the reverse leakage current of the drain substrate diode.

[0043] Specifically, the formula for the junction area of ​​the i-th drain-substrate diode model d is: Si=Li*W Formula (2) Wherein, Si represents the junction area of ​​the i-th drain substrate diode model d, Li represents the length of the i-th drain substrate diode model d along the drift region of the LDMOS, and W represents the width of the drift region of the LDMOS.

[0044] Specifically, the formula for the junction perimeter of the i-th drain substrate diode model d is: Ci = (Li + W) * 2 Formula (3) Where Ci represents the junction perimeter of the i-th drain substrate diode model d.

[0045] In summary, the LDMOS device model provided in this embodiment, based on the existing BSIM4 model, additionally includes several segmented resistor models R connected in series. The output of the first segmented resistor model R is connected to the drain D1 of the BSIM4 model. The output of each segmented resistor model R is connected to the input of the preceding segmented resistor model R. The input of the last segmented resistor model R represents the drain D2 of the LDMOS. The sum of the resistance values ​​of the segmented resistor models R represents the equivalent resistance value of the drift region of the LDMOS, thus dividing the drift region of the LDMOS into several equal parts along the drift region's extension direction. According to the principle of resistor voltage division, the input voltage of the segmented resistor model R decreases sequentially from the last segmented resistor model R to the first segmented resistor model R, thereby simulating the voltage changes at different positions of the drift region along the drift region's extension direction. The electrical characteristics of a diode change with the terminal voltage. Therefore, to better simulate the electrical characteristics of the drain substrate diode of an LDMOS, this invention additionally sets up several drain substrate diode models d. Each drain substrate diode model d corresponds to a segmented resistor model R. The negative terminal of the drain substrate diode model d is connected to the input terminal of the corresponding segmented resistor model R, and the negative terminal of the drain substrate diode model d is connected to the substrate of the BSIM4 model. Since the negative terminals of several drain substrate diode models d are sequentially connected to the input terminal voltages of several segmented resistor models R, the changes in the electrical characteristics of the drain substrate diode at different positions along the drift region extension direction are simulated. This improves the simulation accuracy of the LDMOS device model of this invention for the parasitic capacitance of the drain substrate and the intrinsic capacitance of the gate channel of the LDMOS, as well as the simulation accuracy of the reverse leakage current of the drain substrate diode. Finally, since the BSIM4 model is the mainstream compact transistor model in the industry, it has good convergence, compatibility with standard EDA tools, and high simulation speed. Therefore, modeling LDMOS based on the BSIM4 model inherits the beneficial effects of the BSIM4 model. At the same time, due to the maturity of the BSIM4 model, the design cost of modeling LDMOS based on the BSIM4 model is reduced.

[0046] Furthermore, the lengths of the segmented resistance models R along the extension direction of the LDMOS drift region are all equal. Based on the resistance models that equally divide the drift region, different segmentation coefficients are set for each segmented resistance model R to simulate the different equivalent resistance values ​​of the local structures of the drift region with the same length but at different positions along the extension direction of the LDMOS drift region. This improves the accuracy of the input voltage of the segmented resistance model R, and further improves the simulation accuracy of the LDMOS device model for the parasitic capacitance of the drain substrate and the intrinsic capacitance of the gate channel, as well as the simulation accuracy of the reverse leakage current of the drain substrate diode.

[0047] Please refer to Figure 3 and Figure 4 This embodiment also provides a modeling method for an LDMOS device model, which may include the following steps: S1: Provide an initial BSIM4 model, wherein the drain substrate diode parameters of the initial BSIM4 model are zero.

[0048] Since the drain substrate diode will be reset in the subsequent process, in order to avoid the drain substrate diode built into the BSIM4 model and the drain substrate diode set in this embodiment from being combined and affecting the simulation accuracy of LDMOS, the parameters of the drain substrate diode built into the initial BSIM4 model are set to zero before subsequent modeling.

[0049] It should be noted that the parameters in the initial BSIM4 model at this point are initial parameters and need to be obtained in subsequent data collection and parameter fitting.

[0050] S2: Obtain the electrical characteristic curves of the drain-substrate diode of the LDMOS and the current-voltage characteristic curves of the LDMOS.

[0051] Specifically, the electrical characteristic curves of the drain substrate diode of LDMOS in S2 include the current-voltage characteristic curve, capacitance-voltage characteristic curve and reverse breakdown voltage characteristic curve of the drain substrate diode.

[0052] S3: Based on the current-voltage characteristic curves, obtain the BSIM4 model and establish the equivalent resistance model of the drift region of LDMOS.

[0053] Specifically, in S3, obtaining the BSIM4 model and establishing the equivalent resistance model of the drift region of the LDMOS based on the current-voltage characteristic curve may include: fitting the current-voltage characteristic curve of the LDMOS to obtain the BSIM4 model and the equivalent resistance model of the drift region of the LDMOS.

[0054] In this embodiment, the BSIM4 model can be obtained by fitting the parameters of the initial BSIM4 model based on the current-voltage characteristic curve of the LDMOS.

[0055] Furthermore, the input parameters for the equivalent resistance model of the LDMOS drift region include: the voltage correlation coefficient between the drain D2 and the gate G of the LDMOS, the voltage correlation coefficient between the drain D2 and the body of the LDMOS, as well as the channel size deviation coefficient and temperature coefficient, etc., which are not limited here.

[0056] S4: Based on the equivalent resistance model, determine multiple segmented resistance models corresponding to the drift region of the LDMOS.

[0057] Specifically, the formula for each segmented resistance model R can be found in formula (1), which will not be repeated here.

[0058] The number of segmented resistor models R is related to the source-drain voltage drop of the LDMOS and the set withstand voltage of the segmented resistor models. For example, in this embodiment, the source-drain voltage drop of the LDMOS is set to 20V, and the set withstand voltage of the segmented resistor models is set to 5V. Therefore, the equivalent resistance model is divided into 4 segments, that is, the number of segmented resistor models R is 4, and the number of drain-substrate diode models d is also 4. Of course, the source-drain voltage drop of the LDMOS and the set withstand voltage of the segmented resistor models can be adjusted according to requirements, and are not limited here.

[0059] S5: Calibrate the segmentation coefficients for each segmented resistance model R.

[0060] Specifically, the calibration of the segmentation coefficients of each segmented resistor model R in S5 includes: calibrating the segmentation coefficients of each segmented resistor model R based on simulation data of LDMOS.

[0061] In this embodiment, calibrating the segmentation coefficients includes calibrating whether the sum of the segmentation coefficients is equal to 0, and calibrating whether the segmentation coefficients from the first segmented resistor model to the last segmented resistor model are decreasing and meet the drift region resistance characteristics requirements of LDMOS.

[0062] S6: Based on the electrical characteristic curve of the drain substrate diode, establish a drain substrate diode model corresponding to each of the segmented resistance models. The segmented resistance model and the corresponding drain substrate diode model represent a drift region of the LDMOS.

[0063] Specifically, the method in S6 for establishing the drain substrate diode model corresponding to each of the segmented resistance models based on the electrical characteristic curves of the drain substrate diode includes: S61: Fit the current-voltage characteristic curve, capacitance-voltage characteristic curve and reverse breakdown voltage characteristic curve of the drain substrate diode to obtain the initial drain substrate diode model.

[0064] S62: Determine the port voltage at the input of each segmented resistor model and the substrate voltage of the BSIM4 model.

[0065] S63: Based on the initial drain substrate diode model, according to the port voltage and the substrate voltage of the BSIM4 model, each drain substrate diode model corresponding to each segmented resistor model is obtained. Each drain substrate diode model includes the current-voltage characteristic curve, capacitance-voltage characteristic curve and reverse breakdown voltage characteristic curve of the drain substrate diode in LDMOS.

[0066] Further, in S63, the method for obtaining the drain substrate diode model corresponding to each of the segmented resistance models based on the initial drain substrate diode model, according to each of the port voltages and the substrate voltage of the BSIM4 model, includes: S631: Determine the junction area and junction perimeter of the drain substrate diode corresponding to each drift region of the LDMOS.

[0067] S632: Based on the initial drain substrate diode model, the electrical characteristics of the drain substrate diode model are obtained according to the port voltages and the substrate voltage of the BSIM4 model, as well as the junction area and junction perimeter.

[0068] Furthermore, the method for determining the junction area and junction perimeter of the drain substrate diode corresponding to each drift region of the LDMOS as described in S631 includes: Along the extension direction of the drift region of the LDMOS, obtain the length of the drift region and the number of segments of the drift region.

[0069] The segment length of each sub-drift region is determined based on the drift region length of the LDMOS and the number of segments of the drift region.

[0070] Based on the segment length of each drift region and the drift region width of the LDMOS, the junction area and junction perimeter of the drain substrate diode corresponding to each drift region are determined.

[0071] Furthermore, the junction area and junction perimeter of the drain substrate diode d corresponding to each drift region are respectively referred to in the above formulas (2) and (3), and will not be repeated here.

[0072] Furthermore, the formula for the port voltage at the input of each piecewise resistor model R is as follows: Vi=VDD-I*(Ri+1+Ri+2…Rn) Formula (4) Where Vi represents the port voltage at the input terminal of the i-th segmented resistor model R, VDD represents the power supply voltage input to the input terminal of the first segmented resistor model R, I represents the equivalent current flowing through the entire LDMOS drift region, and Ri+1+ Ri+2…Rn represent the segmented resistor models R below the i-th segmented resistor model R respectively.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A device model of LDMOS, characterized in that, include: The BSIM4 model, wherein the gate of the BSIM4 model represents the gate of the LDMOS, the source of the BSIM4 model represents the source of the LDMOS, and the substrate of the BSIM4 model represents the substrate of the LDMOS; Several segmented resistor models are connected in series. The output of the first segmented resistor model is connected to the drain of the BSIM4 model, and the input of the last segmented resistor model represents the drain of the LDMOS. Several drain substrate diode models, each drain substrate diode model corresponding to one of the segmented resistor models, the negative terminal of the drain substrate diode model is connected to the input terminal of the corresponding segmented resistor model, and the positive terminal of the several drain substrate diode models is connected to the substrate of the BSIM4 model; Among them, the several segmented resistance models represent the equivalent resistance models of the drift region of LDMOS, and a segmented resistance model and the corresponding drain-substrate diode model represent a segment of the drift region of LDMOS.

2. The LDMOS device model according to claim 1, characterized in that, The model expression for the segmented resistor model is: Ri = (1 + ai) * Rdrift / n Where Ri represents the i-th segmented resistance model, ai represents the segmentation coefficient of the i-th segmented resistance model, Rdrift represents the equivalent resistance model of the LDMOS drift region, and n represents the number of segmented resistance models; the sum of the segmentation coefficients of the n segmented resistance models is equal to 0.

3. The LDMOS device model according to claim 2, characterized in that, The number of segmented resistor models is determined based on the source-drain voltage drop of the LDMOS and the set withstand voltage across the segmented resistor model.

4. A modeling method for an LDMOS device model, characterized in that, include: An initial BSIM4 model is provided, wherein the drain substrate diode parameters of the initial BSIM4 model are zero; Obtain the electrical characteristic curves of the drain-substrate diode of the LDMOS and the current-voltage characteristic curves of the LDMOS; Based on the current-voltage characteristic curves, the BSIM4 model is obtained and the equivalent resistance model of the drift region of LDMOS is established. Based on the equivalent resistance model, multiple segmented resistance models corresponding to the drift region of the LDMOS are determined; Based on the electrical characteristic curves of the drain substrate diode, drain substrate diode models corresponding to each segmented resistance model are established. Each segmented resistance model and its corresponding drain substrate diode model characterize a drift region of the LDMOS.

5. The modeling method for the LDMOS device model according to claim 4, characterized in that, The electrical characteristic curves include the current-voltage characteristic curve, capacitance-voltage characteristic curve, and reverse breakdown voltage characteristic curve of the drain-substrate diode. The method for establishing drain substrate diode models corresponding to each of the segmented resistance models based on the electrical characteristic curves of the drain substrate diode includes: The current-voltage characteristic curve, capacitance-voltage characteristic curve and reverse breakdown voltage characteristic curve of the drain substrate diode are fitted to obtain the initial drain substrate diode model. Determine the port voltage at the input of each segmented resistor model and the substrate voltage of the BSIM4 model; Based on the initial drain substrate diode model, and according to the port voltage and the substrate voltage of the BSIM4 model, each drain substrate diode model corresponding to each segmented resistance model is obtained, and each drain substrate diode model includes the electrical characteristics of the drain substrate diode.

6. The modeling method for the LDMOS device model according to claim 5, characterized in that, The process of obtaining each drain substrate diode model corresponding to each segmented resistance model based on the initial drain substrate diode model, according to each port voltage and the substrate voltage of the BSIM4 model, includes: Determine the junction area and junction perimeter of the drain substrate diode corresponding to each drift region of the LDMOS; Based on the initial drain substrate diode model, the electrical characteristics of the drain substrate diode model are obtained according to the port voltages and the substrate voltage of the BSIM4 model, as well as the junction area and junction perimeter.

7. The modeling method for the LDMOS device model according to claim 6, characterized in that, The determination of the junction area and junction perimeter of the drain substrate diode corresponding to each drift region of the LDMOS includes: Along the extension direction of the drift region of the LDMOS, obtain the length of the drift region and the number of segments of the drift region; The segment length of each sub-drift region is determined based on the drift region length of the LDMOS and the number of segments of the drift region; Based on the segment length of each drift region and the drift region width of the LDMOS, the junction area and junction perimeter of the drain substrate diode corresponding to each drift region are determined.

8. The modeling method for the LDMOS device model according to claim 4, characterized in that, Based on the current-voltage characteristic curves, the methods for obtaining the BSIM4 model and establishing the equivalent resistance model of the drift region of LDMOS include: The current-voltage characteristic curves of the LDMOS were fitted to obtain the BSIM4 model and the equivalent resistance model of the drift region of the LDMOS.

9. The modeling method for the LDMOS device model according to claim 4, characterized in that, The determination of multiple segmented resistance models corresponding to the drift region of the LDMOS based on the equivalent resistance model includes: Based on the number of segments in the drift region of the LDMOS and the equivalent resistance model, multiple segmented resistance models corresponding to the drift region of the LDMOS are obtained; the model expression of the segmented resistance model is: Ri = (1 + ai) * Rdrift / n Wherein, Ri represents the i-th segmented resistance model, ai represents the segmentation coefficient of the i-th segmented resistance model, Rdrift represents the equivalent resistance model of the LDMOS drift region, n represents the number of segmented resistance models, the number of segmented resistance models is equal to the number of segments, and the sum of the segmentation coefficients of the n segmented resistance models is equal to 0.

10. The modeling method for the LDMOS device model according to claim 7 or 9, characterized in that, Methods for determining the number of segments include: Obtain the source-drain voltage drop of the LDMOS and the set withstand voltage of the segmented resistance model; The number of segments in the drift region of the LDMOS is determined based on the source-drain voltage drop and the set withstand voltage.

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