LDMOS device and preparation method thereof

Abstract

The invention provides an LDMOS device and a preparation method thereof, and belongs to the technical field of semiconductors, and the preparation method comprises the steps: providing a substrate, forming a first oxidation material with a preset thickness on the substrate, and forming a first oxidation layer; forming a dielectric material layer, and performing ion implantation on the substrate around the first oxide layer by using the dielectric material layer; a preset photomask is adopted to perform patterning on the dielectric material layer, the surface of the substrate is exposed, the remaining dielectric material layer covering the surface of the first oxide layer serves as a dielectric layer, the remaining dielectric material layer covering the side wall of the first oxide layer serves as a side wall layer, and the dielectric layer is connected with the side wall layer; a second oxide layer is formed on the surface of the substrate, the second oxide layer is connected with the side wall layer, and the thickness of the second oxide layer is smaller than the preset thickness; a conductive layer is formed, and a patterning process is performed to form a field oxide structure and a field plate. The performance of the ROX structure in the LDMOS device can be improved, and the preparation process of the ROX structure can be simplified.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to an LDMOS device and its fabrication method. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOS) are semiconductor devices widely used in power and radio frequency circuits. LDMOS devices have a simple structure, mature manufacturing process, and advantages such as low turn-on resistance, high voltage withstand capability, and good conduction characteristics.

[0003] In LDMOS devices, the ROX (Resurf Oxide) structure and its associated field plate structure play a crucial role in adjusting the surface potential distribution to optimize the electric field distribution and improve the breakdown voltage.

[0004] Currently, in LDMOS devices, multiple deposition and patterning processes are typically used to form the ROX structure. This not only makes the steps for forming the ROX structure numerous, but the multiple etching processes in the patterning process also result in poor thickness stability of the ROX structure. Summary of the Invention

[0005] In view of this, this application aims to provide an LDMOS device and a method for fabricating the same, so as to improve the performance of the LDMOS device and simplify the process.

[0006] The method for fabricating an LDMOS device provided in this application includes: A substrate is provided, a first oxide material of a predetermined thickness is formed on the substrate, and a predetermined photomask is used to pattern the first oxide material to form a first oxide layer; A dielectric material layer is formed to conformally cover the substrate surface and the outer wall of the first oxide layer, and ion implantation is performed on the substrate surrounding the first oxide layer using the dielectric material layer; The dielectric material layer is patterned using the preset photomask to expose the substrate surface. The remaining dielectric material layer covering the surface of the first oxide layer is used as a dielectric layer, and the remaining dielectric material layer covering the sidewalls of the first oxide layer is used as a sidewall layer. The dielectric layer is connected to the sidewall layer. A second oxide layer is formed on the surface of the substrate, the second oxide layer is connected to the sidewall layer, and the thickness of the second oxide layer is less than the preset thickness; A conductive layer is formed on the dielectric layer, the sidewall layer, and the second oxide layer, and a patterning process is performed to form a field oxide structure and a field plate. The field oxide structure includes the remaining dielectric layer, the second oxide layer, the sidewall layer, and the first oxide layer, and the field plate includes the remaining conductive layer.

[0007] Optionally, the dielectric material layer is made of a different material than the first oxide layer, and the dielectric constant of the dielectric material layer is greater than that of the first oxide layer.

[0008] Optionally, the dielectric material layer may be made of silicon nitride and / or silicon oxynitride.

[0009] Optionally, the preset thickness is 300 angstroms to 500 angstroms.

[0010] Optionally, the thickness of the dielectric material layer is less than the preset thickness, and / or the thickness of the dielectric material layer is 100 angstroms to 300 angstroms.

[0011] Optionally, the LDMOS device further includes a gate structure, wherein a gate oxide layer in the gate structure is simultaneously formed during the formation of the second oxide layer, the second oxide layer and the gate oxide layer having the same thickness and material, and... When forming the conductive layer, a gate conductive layer in the gate structure is also formed simultaneously. The conductive layer and the gate conductive layer have the same thickness and material.

[0012] Optionally, the steps of performing the graphical process include: A patterned mask layer is formed to cover a portion of the conductive layer; Using the patterned mask layer, the conductive layer, the dielectric layer, and the second oxide layer are etched sequentially to form the field plate, the field oxide structure, and the gate structure on the substrate. The field oxide structure includes the remaining dielectric layer, the second oxide layer, the sidewall layer, and the first oxide layer. The field plate includes the conductive layer on the field oxide structure.

[0013] Optionally, the gate structure is disposed separately from the field oxygen structure and the field plate.

[0014] Based on another aspect of this application, an LDMOS device is also provided, obtained using the fabrication method described above, the LDMOS device comprising: Substrate; A field oxygen structure includes a first oxide layer, a dielectric layer, a sidewall layer, and a second oxide layer. The first oxide layer, the sidewall layer, and the second oxide layer are all located on the substrate. The dielectric layer covers the surface of the first oxide layer, and the sidewall layer also covers the sidewall of the first oxide layer. The sidewall layer connects the first oxide layer, the second oxide layer, and the dielectric layer. The dielectric layer and the sidewall layer have the same material. The field plate is located on the surface of the dielectric layer, the sidewall layer, and the second oxide layer.

[0015] Optionally, the LDMOS device further includes a gate structure, wherein the sidewall layer covers the sidewall of the first oxide layer on the side closest to the gate structure.

[0016] In summary, the unexpected effect of this application is that by using a pre-set photomask to form the first oxide layer, and then using another pre-set photomask to form a dielectric layer on the surface of the first oxide layer and a sidewall layer under the sidewall of the first oxide layer, the thickness of the first oxide layer is not affected by subsequent processes because the dielectric layer and the sidewall layer cover the outer wall of the first oxide layer. This not only ensures the stability of the thickness of the first oxide layer, but also allows the dielectric layer to be used as part of the field oxide structure, reducing the thickness of the first oxide layer. Therefore, the first oxide material can be etched in only one etching step without damaging the substrate surface and ensuring the etching effect of the first oxide layer end face, thus simplifying the process flow and saving process steps. Furthermore, the sidewall layer connects the first oxide layer, the second oxide layer, and the dielectric layer, forming a smooth transition between them, which is more conducive to adjusting the surface potential distribution of the field plate, thereby enhancing the device's withstand voltage capability. In addition, the dielectric material layer covering the substrate surface can also be directly used as a masking layer for ion implantation of the substrate, saving the step of forming an additional masking layer. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a relatively thick first silicon oxide layer formed on a substrate.

[0018] Figure 2 This is a schematic diagram of thinning a portion of the first silicon oxide layer.

[0019] Figure 3 This is a schematic diagram of etching the entire first silicon oxide layer to expose the substrate.

[0020] Figure 4 This is a schematic diagram of forming a second silicon oxide layer on a substrate and performing ion implantation.

[0021] Figure 5 A schematic diagram showing the removal of the second silicon oxide layer and part of the first silicon oxide layer.

[0022] Figure 6 This is a schematic diagram of the formation of a third oxide layer on a substrate.

[0023] Figure 7 A schematic diagram illustrating the formation and patterning of a conductive layer.

[0024] Figure 8 This is a flowchart illustrating a method for fabricating an LDMOS device according to an embodiment of this application.

[0025] Figure 9 This is a schematic diagram of forming a first oxide material on a substrate, provided as an embodiment of this application.

[0026] Figure 10 This is a schematic diagram of the formation of the first oxide layer provided in an embodiment of this application.

[0027] Figure 11 This is a schematic diagram of the formation of a dielectric material layer provided in an embodiment of this application.

[0028] Figure 12 This is a schematic diagram of ion implantation performed using a dielectric material layer, provided as an embodiment of this application.

[0029] Figure 13 This is a schematic diagram of a patterned photoresist layer formed on a dielectric material layer, provided as an embodiment of this application.

[0030] Figure 14 This is a schematic diagram of the formation of the medium layer and the sidewall layer provided in the embodiments of this application.

[0031] Figure 15 This is a schematic diagram of the formation of the second oxide layer provided in an embodiment of this application.

[0032] Figure 16 This is a schematic diagram of the formation of a conductive layer provided in an embodiment of this application.

[0033] Figure 17 This is a schematic diagram of the forming plate provided in an embodiment of this application.

[0034] Figure 18 This is a schematic diagram of the formation of a field oxygen structure provided in an embodiment of this application.

[0035] exist Figures 1-7 In the middle: 10-substrate; 11-first silicon oxide layer; 12-second silicon oxide layer; 13-third silicon oxide layer; 14-conductive layer.

[0036] exist Figures 9-18 In the middle: 100-substrate; 111-first oxide material; 110-first oxide layer; 120-dielectric material layer; 130-patterned photoresist layer; 210-dielectric layer; 220-sidewall layer; 230-second oxide layer; 241-conductive layer; 240-field plate; 250-field oxide structure. Detailed Implementation

[0037] Figures 1-7 This is a schematic diagram of a ROX structure used in the fabrication of an LDMOS device.

[0038] like Figure 1 As shown, a relatively thick first silicon oxide layer 11 is formed on the substrate 10. The thickness of the first silicon oxide layer 11 is 1.5 to 2.5 times the thickness of the ROX structure to be formed, for example, 700 angstroms to 1000 angstroms.

[0039] like Figure 2 As shown, the first silicon oxide layer 11 is patterned, and the first silicon oxide layer 11 outside the ROX region (the region corresponding to the ROX structure) on the substrate 10 is thinned by a dry etching process, for example, the thickness is reduced to 100 angstroms to 200 angstroms.

[0040] like Figure 3 As shown, a wet process is performed to etch away a portion of the first silicon oxide layer 11, remove the first silicon oxide layer 11 outside the ROX region, expose the surface of the substrate 10, and simultaneously thin the first silicon oxide layer 11 in the ROX region. At this time, the thickness of the first silicon oxide layer 11 in the ROX region is 500 angstroms to 600 angstroms.

[0041] like Figure 4 As shown, a second silicon oxide layer 12 is formed on the substrate 10 using a furnace tube process as a masking layer for ion implantation, and ion implantation is performed. The second silicon oxide layer 12 covers the surface of the substrate 10 outside the ROX region. The furnace tube process also increases the thickness of the first silicon oxide layer 11 on the ROX region. At this time, the thickness of the first silicon oxide layer 11 on the ROX region is 600 angstroms to 700 angstroms.

[0042] like Figure 5 As shown, a wet process is used to remove the second silicon oxide layer 12 on the substrate 10, exposing the surface of the substrate 10 outside the ROX region, and at the same time, the first silicon oxide layer 11 on the ROX region is thinned. At this time, the thickness of the first silicon oxide layer 11 on the ROX region is 300 angstroms to 400 angstroms.

[0043] like Figure 6 As shown, a third silicon oxide layer 13 (i.e. a part of the gate silicon oxide layer) is formed on the surface of the substrate 10 using a furnace tube process. This furnace tube process also increases the first silicon oxide layer 11 on the ROX region, for example, by 400 angstroms to 500 angstroms. The first silicon oxide layer 11 and the third silicon oxide layer 13 at this time are used as the ROX structure.

[0044] like Figure 7 As shown, a conductive layer 14 is formed on the first silicon oxide layer 11 and the third silicon oxide layer 13 and patterned to form a field plate and a ROX structure (field oxygen structure). The field plate includes the remaining conductive layer 14 after patterning, and the field oxygen structure includes the remaining first silicon oxide layer 11 and the third silicon oxide layer 13 after patterning.

[0045] from Figures 1-7 It is not difficult to see that the process of preparing the ROX structure requires repeated furnace tube process and wet etching process, which not only makes the process complicated and consumes manpower and resources, but also causes process fluctuations in each process. The superposition of multiple processes leads to large fluctuations in the final ROX thickness, which affects the performance of the ROX structure.

[0046] In view of this, embodiments of this application provide an LDMOS device and a method for fabricating the same. The method includes: providing a substrate; forming a first oxide material of a predetermined thickness on the substrate; and patterning the first oxide material using a predetermined photomask to form a first oxide layer; forming a dielectric material layer conformally covering the surface of the substrate and the outer wall of the first oxide layer; and performing ion implantation on the substrate surrounding the first oxide layer using the dielectric material layer; patterning the dielectric material layer using a predetermined photomask to expose the substrate surface; using the remaining dielectric material layer covering the surface of the first oxide layer as a dielectric layer; and using the remaining dielectric material layer covering the sidewalls of the first oxide layer as a sidewall layer; the dielectric layer and the sidewall layer being connected; forming a second oxide layer on the surface of the substrate; the second oxide layer being connected to the sidewall layer; and the thickness of the second oxide layer being less than a predetermined thickness; forming a conductive layer on the dielectric layer, the sidewall layer, and the second oxide layer; and performing a patterning process to form a field oxide structure and a field plate. The field oxide structure includes the remaining dielectric layer, the second oxide layer, the sidewall layer, and the first oxide layer, and the field plate includes the remaining conductive layer. An unexpected benefit of this application is that by using a pre-set photomask to form the first oxide layer, and then again using a pre-set photomask to form a dielectric layer on the surface of the first oxide layer and a sidewall layer under the sidewall of the first oxide layer, the thickness of the first oxide layer is unaffected by subsequent processes, thanks to the dielectric layer and sidewall layer covering the outer wall of the first oxide layer. This not only ensures the stability of the first oxide layer thickness but also allows the dielectric layer to be used as part of the field oxide structure, reducing the thickness of the first oxide layer. Therefore, while ensuring no damage to the substrate surface and maintaining the etching effect on the end face of the first oxide layer, only one etching step is needed to etch the first oxide material, simplifying the process flow and saving process steps. Furthermore, the sidewall layer connects the first oxide layer, the second oxide layer, and the dielectric layer, forming a smooth transition between them, which is more conducive to adjusting the surface potential distribution of the field plate, thereby enhancing the device's withstand voltage capability. In addition, the dielectric material layer covering the substrate surface can also be directly used as a masking layer for ion implantation into the substrate, saving the step of forming an additional masking layer.

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] Figure 8 This is a flowchart illustrating a method for fabricating an LDMOS device according to an embodiment of this application. Figure 8 As shown, an embodiment of this application provides a method for fabricating an LDMOS device, including: S100: Provide a substrate, form a first oxide material of a predetermined thickness on the substrate, and perform patterning on the first oxide material using a predetermined photomask to form a first oxide layer; S200: A dielectric material layer is formed to conformally cover the surface of the substrate and the outer wall of the first oxide layer, and ion implantation is performed on the substrate surrounding the first oxide layer using the dielectric material layer; S300: The preset photomask is used to pattern the dielectric material layer to expose the substrate surface. The remaining dielectric material layer covering the surface of the first oxide layer is used as a dielectric layer, and the remaining dielectric material layer covering the sidewall of the first oxide layer is used as a sidewall layer. The dielectric layer is connected to the sidewall layer. S400: A second oxide layer is formed on the surface of the substrate, the second oxide layer is connected to the sidewall layer, and the thickness of the second oxide layer is less than the preset thickness; S500: A conductive layer is formed on the dielectric layer, the sidewall layer, and the second oxide layer, and a patterning process is performed to form a field oxide structure and a field plate, wherein the field oxide structure includes the remaining dielectric layer, the second oxide layer, the sidewall layer, and the first oxide layer, and the field plate includes the remaining conductive layer.

[0049] Figures 9-18 This is a schematic diagram of the corresponding steps in the fabrication method of the LDMOS device provided in an embodiment of this application. Next, we will combine... Figures 9-18 The fabrication method of the LDMOS device provided in this application is described in detail.

[0050] First, such as Figures 9-10 As shown, in step S100, a substrate 100 is provided, a first oxide material 111 of a preset thickness is formed on the substrate 100, and a preset photomask is used to pattern the first oxide material 111 to form a first oxide layer 110.

[0051] Specifically, such as Figure 9As shown, a first oxide material 111 of a predetermined thickness is formed on the substrate 100. The material of the substrate 100 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc., or it can be an organic semiconductor material or other semiconductor materials known in the art. In some examples, an epitaxial layer may also be formed on the surface of the substrate 100, and the first oxide material 111 is formed on the epitaxial layer, that is, a portion of the structure of the LDMOS device of this application is formed in the epitaxial layer.

[0052] In this application, a furnace tube process (thermal oxidation process) can be used to form a first oxide material 111 with a preset thickness, and the preset thickness can be set according to the thickness requirements of the first oxide layer in the subsequent field oxygen structure, that is, the preset thickness is the thickness of the first oxide layer in the subsequent field oxygen structure.

[0053] like Figure 10 As shown, a preset photomask is used to pattern the first oxide material 111 to form a first oxide layer 110. The steps of forming the first oxide layer 110 may include: performing a photolithography process using a preset photomask to form a patterned photoresist layer on the first oxide material 111; performing an etching process (e.g., dry etching process) using the patterned photoresist layer to remove the first oxide material 111 outside the patterned photoresist layer, exposing the surface of the substrate 100; removing the patterned photoresist layer; and leaving the remaining first oxide material 111 as the first oxide layer 110. At this time, the thickness of the first oxide layer 110 is a preset thickness.

[0054] Compared to forming a thicker oxide layer and using multiple different etching steps for patterning, in this application, the thickness of the first oxide material 111 is the same as the thickness of the first oxide layer in the final field oxide structure. This results in a thinner first oxide layer 110, for example, 300 to 500 angstroms. Therefore, while ensuring no damage to the substrate 100 (active region) surface and ensuring the etching effect of the end face, this application can use only one etching step to etch the first oxide material 111, thereby simplifying the process flow and saving process steps. It is understood that if the oxide layer is thick (e.g., greater than 700 angstroms), using only a dry process to etch such a thick oxide layer will easily damage the substrate surface, while using only a wet process to etch such a thick oxide layer will result in a poor end face effect after the oxide layer is etched.

[0055] Furthermore, in the LDMOS device provided in this application, a dielectric layer is also provided on the first oxide layer 110, and the first oxide layer 110 and the dielectric layer as a whole are used as a field oxygen structure. Therefore, the thickness of the first oxide layer 110 (first oxide material 111) can be further reduced to further simplify the process flow and save process steps.

[0056] Next, as Figures 11-12 As shown, in step S200, a dielectric material layer 120 is formed to conformally cover the surface of the substrate 100 and the outer wall of the first oxide layer 110, and ion implantation is performed on the substrate 100 surrounding the first oxide layer 110 using the dielectric material layer 120.

[0057] like Figure 11 As shown, a dielectric material layer 120 is formed to conformally cover the surface of the substrate 100 and the outer wall of the first oxide layer 110. The dielectric material layer 120 is an insulating material different from the first oxide layer 110, and its dielectric constant can be greater than that of the first oxide layer 110. Furthermore, the thickness of the dielectric material layer 120 can be relatively increased (increasing the overall thickness of the field oxide structure) while ensuring that the equivalent thickness of the first oxide layer 110 and the dielectric layer 210 remains unchanged, thereby enhancing the device's withstand voltage capability. On one hand, the thickness of the dielectric material layer 120 can be less than the thickness of the first oxide layer 110, i.e., less than a preset thickness. On the other hand, the thickness of the dielectric material layer 120 can also be greater than 100 angstroms, so that the dielectric material layer 120 can serve as a masking layer during ion implantation. In practice, the thickness of the dielectric material layer 120 can be specifically determined according to the thickness requirements of the field oxide structure and the withstand voltage requirements of the LDMOS device. In one example, the first oxide layer 110 is made of silicon oxide, the dielectric material layer 120 may be made of silicon nitride and / or silicon oxynitride, and the thickness of the dielectric material layer 120 is 100 angstroms to 300 angstroms.

[0058] like Figure 12 As shown, ion implantation is performed on the substrate 100 surrounding the first oxide layer 110 using the dielectric material layer 120. A corresponding patterned photoresist layer can also be formed on the dielectric material layer 120 to expose the corresponding area of ​​the dielectric material layer 120 for ion implantation, such as forming NW (N-type well), PW (P-type well), or DNW (deep N-type well). Compared to forming an additional oxide layer as a masking layer for ion implantation, this application uses the dielectric material layer 120 covering the surface of the substrate 100 as a masking layer for ion implantation, saving the step of forming an additional masking layer. Furthermore, since the dielectric material layer 120 covers the surface and sidewalls of the first oxide layer 110, it also protects the first oxide layer 110, preventing the thickness of the first oxide layer 110 from increasing or decreasing.

[0059] Next, as Figures 13-14 As shown, in step S300, a preset photomask is used to pattern the dielectric material layer 120 to expose the surface of the substrate 100. The remaining dielectric material layer 120 covering the surface of the first oxide layer 110 serves as the dielectric layer 210, and the remaining dielectric material layer 120 covering the sidewalls of the first oxide layer 110 serves as the sidewall layer 220. The dielectric layer 210 is connected to the sidewall layer 220.

[0060] like Figure 13 As shown, a photolithography process is performed using a preset photomask to pattern a photoresist layer 130 on the dielectric material layer 120. The patterned photoresist layer 130 covers the dielectric material layer 120 above the first oxide layer 110.

[0061] like Figure 14 As shown, an anisotropic etching process (dry etching process) is performed on the dielectric material layer 120 to expose the surface of the substrate 100. The remaining dielectric material layer 120 covering the surface of the first oxide layer 110 serves as the dielectric layer 210, and the remaining dielectric material layer 120 covering the sidewalls of the first oxide layer 110 serves as the sidewall layer 220. The dielectric layer 210 and the sidewall layer 220 are connected. During the above etching process, the dielectric material layer 120 always covers the surface and sidewalls of the first oxide layer 110 to protect the first oxide layer 110 and keep the thickness of the first oxide layer 110 substantially constant.

[0062] Next, as Figure 15 As shown, in step S400, a second oxide layer 230 is formed on the surface of the substrate 100. The second oxide layer 230 is connected to the sidewall layer 220, and the thickness of the second oxide layer 230 is less than a preset thickness.

[0063] A second oxide layer 230 can be formed on the surface of the substrate 100 using a thermal oxidation process (e.g., ISSG process). The thickness of the second oxide layer 230 is less than the thickness of the first oxide layer 110. The second oxide layer 230 and the first oxide layer 110 (and the dielectric layer 210) form a step difference. The sidewall layer 220 is connected between the first oxide layer 110 and the second oxide layer 230, and is connected to the dielectric layer 210 on the first oxide layer 110, so as to form a step structure with a smooth transition. Compared with the step structure, the step structure with a smooth transition of this application is more conducive to the field plate (subsequent conductive layer) to adjust the surface potential distribution.

[0064] Next, as Figures 16-18As shown, in step S500, a conductive layer 241 is formed on the dielectric layer 210, the sidewall layer 220 and the second oxide layer 230, and a patterning process is performed to form a field oxide structure 250 and a field plate 240. The field oxide structure 250 includes the remaining dielectric layer 210, the second oxide layer 230, the sidewall layer 220 and the first oxide layer 110, and the field plate 240 includes the remaining conductive layer 241.

[0065] like Figure 16 As shown, a conductive layer 241 is formed to conformally cover the surfaces of the second oxide layer 230, the sidewall layer 220, and the dielectric layer 210. The conductive layer 241 is used to form a field plate. The conductive layer 241 can be any suitable conductive material, such as polycrystalline silicon or metal.

[0066] like Figure 17 As shown, a patterned mask layer is formed, and a conductive layer 241 is etched to form a field plate 240 on the dielectric layer 210 and the second oxide layer 230, exposing the surfaces of a portion of the dielectric layer 210, a portion of the sidewall layer 220 and a portion of the second oxide layer 230. The field plate 240 includes the remaining conductive layer 241 after etching.

[0067] like Figure 18 As shown, using a patterned mask layer, the exposed dielectric layer 210, the first oxide layer 110, and the second oxide layer 230 are sequentially etched to expose the surface of the substrate 100, and the remaining portion of the first oxide layer 110, a portion of the second oxide layer 230, a portion of the dielectric layer 210, and the sidewall layer 220 serve as the field oxygen structure 250.

[0068] In one example, a second oxide layer 230 and a gate oxide material in the gate structure can be formed simultaneously, both having the same thickness and material. Next, a conductive layer 241 and a conductive material in the gate structure are formed simultaneously, both having the same thickness and material. The thickness of the conductive layer 241 can be determined based on the thickness requirements of the conductive material in the gate structure. The material of the conductive layer 241 can be polysilicon or doped polysilicon. Next, a patterned mask layer is formed, which can simultaneously define the areas corresponding to the field plate and the gate. Then, using the patterned… The mask layer is etched sequentially with a conductive layer 241, a dielectric layer 210, and a second oxide layer 230 to form a field plate 240, a field oxide structure 250, and a gate structure. The field oxide structure 250 may include the remaining dielectric layer 210, the second oxide layer 230, the sidewall layer 220, and the first oxide layer 110. The field plate 240 includes a conductive layer 241 on the field oxide structure 250. The gate oxide material and the gate conductive material on the gate region serve as the gate oxide layer and the gate conductive layer of the gate structure, respectively. The gate structure is separately disposed from the field oxide structure 250 and the field plate 240.

[0069] This application also provides an LDMOS device. Figure 18This is a schematic diagram of an LDMOS device provided in an embodiment of this application. Figure 18 As shown, an embodiment of this application provides an LDMOS device including a substrate 100, a field oxide structure 250, and a field plate 240. The field oxide structure 250 includes a first oxide layer 110, a dielectric layer 210, a sidewall layer 220, and a second oxide layer 230. The first oxide layer 110, the sidewall layer 220, and the second oxide layer 230 are all located on the substrate 100. The dielectric layer 210 covers the surface of the first oxide layer 110, and the sidewall layer 220 also covers the sidewalls of the first oxide layer 110. The sidewall layer 220 connects the first oxide layer 110, the second oxide layer 230, and the dielectric layer 210. The dielectric layer 210 and the sidewall layer 220 have the same material. The field plate 240 is located on the surface of the dielectric layer 210, the sidewall layer 220, and the second oxide layer 230.

[0070] The first oxide layer 110 is located in the drift region of the substrate 100. Figure 18 (Not shown in the diagram) A dielectric layer 210 covers the surface of the first oxide layer 110. One end of the first oxide layer 110 is near the drain end (not shown). A sidewall layer 220 and a second oxide layer 230 are sequentially disposed on the surface of the substrate 100 (drift region) at the other end of the first oxide layer 110 (near the gate structure or away from the drain end). One side of the sidewall layer 220 covers the sidewall of that end of the first oxide layer 110, and the other side of the sidewall layer 220 is connected to the second oxide layer 230. The sum of the thicknesses of the first oxide layer 110 and the dielectric layer 210 is greater than the thickness of the second oxide layer 230. The top of the sidewall side is also connected to the dielectric layer 210, and a stepped structure with a smooth transition is formed between the first oxide layer 110, the dielectric layer 210 and the second oxide layer 230, which is beneficial for the field plate 240 to adjust the surface potential distribution. The dielectric layer 210 and the sidewall layer 220 are made of the same material. The dielectric constant of the dielectric layer 210 is greater than that of the first oxide layer 110. The thickness of the dielectric material layer 120 can be increased relatively while ensuring that the equivalent thickness of the field oxide structure 250 (i.e., the first oxide layer 110 and the dielectric layer 210) remains unchanged, thereby enhancing the withstand voltage capability of the device.

[0071] In one example, the first oxide layer 110 and the second oxide layer 230 may be made of silicon oxide and may both be formed using a thermal oxidation process. The dielectric layer 210 may be made of silicon nitride and / or silicon oxynitride. The dielectric material layer 120 has a thickness of 100 angstroms to 300 angstroms, with a preset thickness of 300 angstroms to 500 angstroms. In another example, a gate structure is also provided on the substrate 100. The gate structure is separately disposed from the field oxide structure 250 and the field plate 240. The gate structure includes a gate oxide layer and a gate conductive layer. The second oxide layer 230 and the gate oxide layer have the same thickness and material, and the field plate 240 (conductive layer) and the gate conductive layer have the same thickness and material. The sidewall layer 220 covers the sidewall of the first oxide layer 110 near the gate structure, and similarly, the second oxide layer 230 covers the portion of the substrate 100 surface of the first oxide layer 110 near the gate structure.

[0072] In summary, this application provides an LDMOS device and its fabrication method. The fabrication method includes: providing a substrate; forming a first oxide material of a predetermined thickness on the substrate; and patterning the first oxide material using a predetermined photomask to form a first oxide layer; forming a dielectric material layer conformally covering the substrate surface and the outer wall of the first oxide layer; and performing ion implantation on the substrate surrounding the first oxide layer using the dielectric material layer; patterning the dielectric material layer using a predetermined photomask to expose the substrate surface; the remaining dielectric material layer covering the surface of the first oxide layer serving as a dielectric layer; and the remaining dielectric material layer covering the sidewalls of the first oxide layer serving as a sidewall layer; the dielectric layer and the sidewall layer being connected; forming a second oxide layer on the substrate surface; the second oxide layer being connected to the sidewall layer; and the thickness of the second oxide layer being less than a predetermined thickness; forming a conductive layer on the dielectric layer, the sidewall layer, and the second oxide layer; and performing a patterning process to form a field oxide structure and a field plate. The field oxide structure includes the remaining dielectric layer, the second oxide layer, the sidewall layer, and the first oxide layer, and the field plate includes the remaining conductive layer. An unexpected benefit of this application is that by using a pre-set photomask to form the first oxide layer, and then again using a pre-set photomask to form a dielectric layer on the surface of the first oxide layer and a sidewall layer under the sidewall of the first oxide layer, the thickness of the first oxide layer is unaffected by subsequent processes, thanks to the dielectric layer and sidewall layer covering the outer wall of the first oxide layer. This not only ensures the stability of the first oxide layer thickness but also allows the dielectric layer to be used as part of the field oxide structure, reducing the thickness of the first oxide layer. Therefore, while ensuring no damage to the substrate surface and maintaining the etching effect on the end face of the first oxide layer, only one etching step is needed to etch the first oxide material, simplifying the process flow and saving process steps. Furthermore, the sidewall layer connects the first oxide layer, the second oxide layer, and the dielectric layer, forming a smooth transition between them, which is more conducive to adjusting the surface potential distribution of the field plate, thereby enhancing the device's withstand voltage capability. In addition, the dielectric material layer covering the substrate surface can also be directly used as a masking layer for ion implantation into the substrate, saving the step of forming an additional masking layer.

[0073] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0074] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0075] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0076] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for fabricating an LDMOS device, characterized in that, include: A substrate is provided, a first oxide material of a predetermined thickness is formed on the substrate, and a predetermined photomask is used to pattern the first oxide material to form a first oxide layer; A dielectric material layer is formed to conformally cover the substrate surface and the outer wall of the first oxide layer, and ion implantation is performed on the substrate surrounding the first oxide layer using the dielectric material layer; The dielectric material layer is patterned using the preset photomask to expose the substrate surface. The remaining dielectric material layer covering the surface of the first oxide layer is used as a dielectric layer, and the remaining dielectric material layer covering the sidewalls of the first oxide layer is used as a sidewall layer. The dielectric layer is connected to the sidewall layer. A second oxide layer is formed on the surface of the substrate, the second oxide layer is connected to the sidewall layer, and the thickness of the second oxide layer is less than the preset thickness; A conductive layer is formed on the dielectric layer, the sidewall layer, and the second oxide layer, and a patterning process is performed to form a field oxide structure and a field plate. The field oxide structure includes the remaining dielectric layer, the second oxide layer, the sidewall layer, and the first oxide layer, and the field plate includes the remaining conductive layer.

2. The method for fabricating an LDMOS device according to claim 1, characterized in that, The dielectric material layer is made of a different material than the first oxide layer, and the dielectric constant of the dielectric material layer is greater than that of the first oxide layer.

3. The method for fabricating an LDMOS device according to claim 2, characterized in that, The dielectric material layer is made of silicon nitride and / or silicon oxynitride.

4. The method for fabricating an LDMOS device according to claim 1, characterized in that, The preset thickness is 300 angstroms to 500 angstroms.

5. The method for fabricating an LDMOS device according to claim 1 or 4, characterized in that, The thickness of the dielectric material layer is less than the preset thickness, and / or the thickness of the dielectric material layer is 100 angstroms to 300 angstroms.

6. The method for fabricating an LDMOS device according to claim 1, characterized in that, The LDMOS device further includes a gate structure. During the formation of the second oxide layer, a gate oxide layer is simultaneously formed in the gate structure. The second oxide layer and the gate oxide layer have the same thickness and material. When forming the conductive layer, a gate conductive layer in the gate structure is also formed simultaneously. The conductive layer and the gate conductive layer have the same thickness and material.

7. The method for fabricating an LDMOS device according to claim 6, characterized in that, The steps of performing the graphical process include: A patterned mask layer is formed to cover a portion of the conductive layer; Using the patterned mask layer, the conductive layer, the dielectric layer, and the second oxide layer are etched sequentially to form the field plate, the field oxide structure, and the gate structure on the substrate. The field oxide structure includes the remaining dielectric layer, the second oxide layer, the sidewall layer, and the first oxide layer. The field plate includes the conductive layer on the field oxide structure.

8. The method for fabricating an LDMOS device according to claim 7, characterized in that, The gate structure is separately disposed from the field oxygen structure and the field plate.

9. An LDMOS device, characterized in that, The LDMOS device is obtained by the fabrication method according to any one of claims 1 to 8, and comprises: Substrate; A field oxygen structure includes a first oxide layer, a dielectric layer, a sidewall layer, and a second oxide layer. The first oxide layer, the sidewall layer, and the second oxide layer are all located on the substrate. The dielectric layer covers the surface of the first oxide layer, and the sidewall layer also covers the sidewall of the first oxide layer. The sidewall layer connects the first oxide layer, the second oxide layer, and the dielectric layer. The dielectric layer and the sidewall layer have the same material. The field plate is located on the surface of the dielectric layer, the sidewall layer, and the second oxide layer.

10. The LDMOS device according to claim 9, characterized in that, The LDMOS device further includes a gate structure, wherein the sidewall layer covers the sidewall of the first oxide layer on the side closest to the gate structure.

Images