Semiconductor device structure, CMOS structure and its fabrication method

Abstract

This application discloses a semiconductor device structure, a CMOS structure, and a method for fabricating the same, relating to the field of semiconductor device technology. The semiconductor device structure employs two buried oxide layers interleaved within a three-layer silicon SOI substrate. The epitaxial initiation layer of the source / drain regions is transferred from the top silicon layer of the SOI substrate to an intermediate or supporting silicon layer within the SOI substrate. This solves a series of process problems arising from the development of SOI technology nodes, particularly in epitaxially growing source / drain regions on a thinner top silicon layer, thus improving the epitaxial growth quality and structural stability of the source / drain regions. Furthermore, the parallel overlap length between the source / drain regions and the gate structure is reduced, significantly decreasing the parasitic capacitance between the source / drain regions and the gate structure. Moreover, the source / drain regions can directly contact the channel, enhancing the contact reliability between the source / drain regions and the channel, enabling stress control of the channel, and improving channel mobility, thus possessing significant application value.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to semiconductor device structures, CMOS structures and their fabrication methods. Background Technology

[0002] SOI (Silicon-On-Insulator) substrates are multilayer substrate structures that effectively isolate the silicon substrate from the surface silicon device layers by embedding a buried oxide layer between the top silicon layer and the supporting silicon layer. Semiconductor devices fabricated based on SOI substrates, such as FD-SOI (Fully Depleted Silicon On Insulator) devices, have advantages such as excellent short-channel effect control and extremely low static power consumption, and are widely used in fields such as the Internet of Things and mobile communications.

[0003] In current SOI device fabrication processes, source / drain regions are typically obtained through homoepitaxial growth on the top silicon layer of the SOI substrate. To ensure successful epitaxial growth of the source / drain regions, the top silicon layer must have a certain thickness. However, with the continuous evolution of SOI technology nodes, the thickness of the top silicon layer is also continuously decreasing. While this trend helps with device miniaturization and performance improvement, it also foreseeably brings greater process challenges to the epitaxial growth of the source / drain regions. For example, problems such as decreased nucleation stability of the source / drain epitaxial layer, increased defect density, and weakened stress transfer efficiency may occur. Furthermore, etching to form the source / drain regions after epitaxy of the top silicon layer can easily penetrate the top silicon layer, leading to excessively high contact resistance.

[0004] Therefore, new structures and processes are urgently needed to solve the above problems. Summary of the Invention

[0005] This application provides a semiconductor device structure, a CMOS structure, and a method for fabricating the same, to address a series of process problems arising from the thinning of the top silicon layer of the SOI substrate as SOI technology nodes develop.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] In a first aspect, this application provides a semiconductor device structure, including:

[0008] SOI substrate, the SOI substrate comprising a first silicon layer, a first buried oxide layer, a second silicon layer, a second buried oxide layer and a third silicon layer stacked together;

[0009] A gate structure is disposed on the surface of the third silicon layer away from the second buried oxide layer, and the gate structure has sidewalls on opposite sides.

[0010] The source region and drain region are respectively disposed in the SOI substrate on opposite sides of the gate structure. The SOI substrate has a groove on one side of the third silicon layer. The groove penetrates at least through the third silicon layer and the second buried oxide layer to expose a portion of the second silicon layer. Alternatively, the groove penetrates at least through the third silicon layer to the first buried oxide layer to expose a portion of the first silicon layer. The source region and the drain region are respectively epitaxially filled in the corresponding groove.

[0011] Optionally, the surface of the source region facing away from the SOI substrate is not lower than the surface of the third silicon layer facing away from the second buried oxide layer;

[0012] The surface of the drain region away from the SOI substrate is not lower than the surface of the third silicon layer away from the second buried oxide layer.

[0013] Optionally, the surface of the source region facing away from the SOI substrate is higher than the surface of the third silicon layer facing away from the second buried oxide layer;

[0014] The surface of the drain region away from the SOI substrate is higher than the surface of the third silicon layer away from the second buried oxide layer.

[0015] Optionally, the material of the source region includes at least one of SiGe and SiC;

[0016] The material of the leak region includes at least one of SiGe and SiC.

[0017] Optionally, in a cross-section perpendicular to the plane of the SOI substrate, the groove is a rectangular groove, a U-shaped groove, or a rhomboid groove.

[0018] Optionally, the surface of the source region facing away from the SOI substrate is concave, convex, or planar;

[0019] The surface of the drain region facing away from the SOI substrate is concave, convex, or planar.

[0020] Secondly, this application provides a method for fabricating a semiconductor device structure, comprising:

[0021] S10: Provide an SOI substrate, the SOI substrate comprising a first silicon layer, a first buried oxide layer, a second silicon layer, a second buried oxide layer and a third silicon layer stacked together;

[0022] S11: A gate structure is formed on the surface of the third silicon layer that is away from the second buried oxide layer;

[0023] S12: Deposit a dielectric layer, the dielectric layer covering the gate structure and the third silicon layer;

[0024] S13: Etch the dielectric layer and part of the SOI substrate on both sides of the gate structure to form a groove. The groove penetrates at least the third silicon layer and the second buried oxide layer to expose part of the second silicon layer. Alternatively, the groove penetrates at least the third silicon layer to the first buried oxide layer to expose part of the first silicon layer. Part of the dielectric layer is retained on both sides of the gate structure to form sidewalls.

[0025] S14: The source region is epitaxially filled inside and outside one of the grooves on opposite sides of the gate structure, and the drain region is epitaxially filled inside and outside the other groove.

[0026] Optionally, when the source region is filled inside and outside the corresponding groove, the source region grows epitaxially from the bottom of the corresponding groove, or the source region grows epitaxially from both the bottom and sidewall of the corresponding groove simultaneously.

[0027] When the drain area is filled by extending along the inner and outer sides of the corresponding groove, the drain area grows extending along the bottom of the corresponding groove, or the drain area grows extending along both the bottom and sidewall of the corresponding groove.

[0028] Thirdly, this application provides a CMOS structure, including an NMOS device structure and a PMOS device structure, wherein the NMOS device structure adopts any of the above-mentioned semiconductor device structures, and / or the PMOS device structure adopts any of the above-mentioned semiconductor device structures.

[0029] The NMOS device structure and the PMOS device structure share the same SOI substrate, which has a deep trench isolation structure located between the NMOS device structure and the PMOS device structure to isolate them.

[0030] Fourthly, this application provides a method for fabricating a CMOS structure, comprising:

[0031] S20: Provide an SOI substrate, the SOI substrate including a first silicon layer, a first buried oxide layer, a second silicon layer, a second buried oxide layer and a third silicon layer stacked together, and the SOI substrate including a first device region and a second device region that are isolated from each other;

[0032] S21: A gate structure is formed on the surface of the third silicon layer in the first device region and the second device region, respectively;

[0033] S22: Deposit a first dielectric layer, the first dielectric layer covering the gate structure and the third silicon layer;

[0034] S23: Deposit a first photoresist layer, and expose and develop the first photoresist layer so that the first photoresist layer exposes the dielectric layer and the gate structure corresponding to the first device region;

[0035] S24: Etch the dielectric layers on both sides of the exposed gate structure and part of the SOI substrate to form a groove. The groove penetrates at least the third silicon layer and the second buried oxide layer to expose part of the second silicon layer. Alternatively, the groove penetrates at least the third silicon layer to the first buried oxide layer to expose part of the first silicon layer. Part of the dielectric layer is retained on both sides of the exposed gate structure to form sidewalls.

[0036] S25: A source region is epitaxially filled inside and outside one of the grooves on opposite sides of the exposed gate structure, and a drain region is epitaxially filled inside and outside the other groove;

[0037] S26: Remove the first photoresist layer and deposit a second dielectric layer, the second dielectric layer covering the gate structure, the formed source region and the drain region, and the first dielectric layer;

[0038] S27: Deposit a second photoresist layer, and expose and develop the second photoresist layer so that the second photoresist layer exposes the dielectric layer and the gate structure corresponding to the second device region;

[0039] Repeat steps S24 and S25 to remove the second photoresist layer and form a CMOS structure including an NMOS device structure and a PMOS device structure, wherein the first device region corresponds to one of the NMOS device structure and the PMOS device structure, and the second device region corresponds to the other of the NMOS device structure and the PMOS device structure.

[0040] Compared with existing technologies, the above technical solution has the following advantages:

[0041] The semiconductor device structure provided in this application includes an SOI substrate, which comprises a first silicon layer (supporting silicon layer), a first buried oxide layer, a second silicon layer (intermediate silicon layer), a second buried oxide layer, and a third silicon layer (top silicon layer) stacked together. That is, the SOI substrate has two buried oxide layers interleaved and embedded in the three silicon layers. The gate structure is disposed on the surface of the third silicon layer facing away from the second buried oxide layer, and the gate structure has sidewalls on opposite sides. Unlike existing SOI devices where the source and drain regions are epitaxially grown on the top silicon layer, in the semiconductor device structure provided in this application, the source and drain regions are respectively disposed in the SOI substrate on opposite sides of the gate structure. Specifically, a groove is etched on one side of the third silicon layer (top silicon layer) of the SOI substrate, the groove penetrating at least the third silicon layer and the second buried oxide layer to expose a portion of the second silicon layer, or... The groove penetrates at least through the third silicon layer to the first buried oxide layer, exposing a portion of the first silicon layer. That is, the bottom of the groove is an exposed second silicon layer or the first silicon layer. Then, source and drain regions are formed by epitaxial filling inside and outside the corresponding grooves, respectively. In other words, this application transfers the epitaxial starting layer of the source and drain regions from the top silicon layer of the SOI substrate to the intermediate silicon layer or support silicon layer inside the SOI substrate. Since the thickness of the intermediate silicon layer and support silicon layer of the SOI substrate can be relatively larger than that of the top silicon layer, this solves a series of process problems caused by the thinning of the top silicon layer of the SOI substrate as SOI technology nodes develop. This improves the epitaxial growth quality and structural stability of the source and drain regions, while avoiding the risk of easily penetrating the top silicon layer and causing excessive contact resistance when etching to form the source and drain regions after epitaxy of the top silicon layer.

[0042] Furthermore, in the semiconductor device structure provided in this application, since the source and drain regions are epitaxially filled in the corresponding grooves of the SOI substrate, the parallel overlap length between the source / drain regions and the gate structure located on the surface of the top silicon layer of the SOI substrate is reduced, thereby significantly reducing the parasitic capacitance between the source / drain regions and the gate structure.

[0043] Furthermore, in the semiconductor device structure provided in this application, since the source and drain regions are epitaxially filled in the corresponding grooves of the SOI substrate, the source / drain regions can directly contact the channel of the third silicon layer or even the channel of the second silicon layer, thereby enhancing the contact reliability between the source / drain regions and the channel. In addition, by controlling the epitaxial material of the source / drain regions and the etching morphology of the corresponding grooves, the stress of the channel can be controlled, which is beneficial to improving the channel mobility.

[0044] Therefore, the semiconductor device structure provided in this application is suitable for advanced SOI node processes. It not only improves the epitaxial growth quality and structural stability of the source / drain regions at the process level, enhances the contact reliability between the source / drain regions and the channel, and enhances the stress control of the channel, but also reduces the parasitic capacitance between the source / drain regions and the gate structure and achieves high channel mobility in terms of device electrical performance, which has significant application value. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of an SOI device structure in related technologies;

[0047] Figure 2 This is a schematic diagram of another SOI device structure in related technologies;

[0048] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device structure provided in an embodiment of this application;

[0049] Figure 4 This is a cross-sectional schematic diagram of another semiconductor device structure provided in an embodiment of this application;

[0050] Figure 5 A microscopic image of a semiconductor device structure provided in an embodiment of this application;

[0051] Figure 6 , Figure 7 , Figure 8a and Figure 8b This is a cross-sectional schematic diagram of the device structure corresponding to each step in a method for fabricating a semiconductor device structure provided in this application embodiment;

[0052] Figure 9 This is a cross-sectional schematic diagram of a CMOS structure provided in an embodiment of this application;

[0053] Figures 10-18 This is a cross-sectional schematic diagram of the device structure corresponding to each step in a method for fabricating a CMOS device structure provided in an embodiment of this application;

[0054] Explanation of reference numerals in the attached figures:

[0055] SOI substrate 10; gate structure 20; source region 31; drain region 32; first silicon layer 11; first buried oxide layer 12; second silicon layer 13; second buried oxide layer 14; third silicon layer 15; sidewall 40; trench T; dielectric layer 50; first dielectric layer 51; second dielectric layer 52; deep trench isolation structure 60; first photoresist layer 71; second photoresist layer 72; first device region A1; second device region A2; NMOS device structure 100; PMOS device structure 200; support silicon layer 01; buried oxide layer 02; top silicon layer 03. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0057] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0058] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the accompanying drawings illustrating the device structure may be partially enlarged, not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0059] Figure 1 and Figure 2 The diagram shows the structural schematics of two SOI devices in the related technology, such as... Figure 1 and Figure 2 As shown, the SOI substrate 10 of existing SOI devices is mostly embedded with a buried oxide layer 02 between the supporting silicon layer 01 and the top silicon layer 03, and the source region 31 and the drain region 32 are usually obtained by homoepitaxial growth on the top silicon layer 03 of the SOI substrate 10.

[0060] As described in the background section, with the continuous evolution of SOI technology nodes, the thickness of the top silicon layer 03 is also continuously decreasing. While this trend helps with device miniaturization and performance improvement, it is also foreseeable that it will bring greater process challenges to the epitaxial growth of the source / drain regions. For example, problems such as decreased nucleation stability of the source / drain epitaxial layer, increased defect density, and weakened stress transfer efficiency may occur. Furthermore, when etching to form the source / drain regions after epitaxy of the top silicon layer 03, it is easy to etch through the top silicon layer 03, resulting in excessive contact resistance.

[0061] In view of this, embodiments of this application provide a semiconductor device structure, such as... Figure 3 and Figure 4 As shown, the semiconductor device structure includes an SOI substrate 10, a gate structure 20, a source region 31, and a drain region 32.

[0062] The SOI substrate 10 includes a first silicon layer 11, a first buried oxide layer 12, a second silicon layer 13, a second buried oxide layer 14, and a third silicon layer 15 stacked together. The first silicon layer 11 is a supporting silicon layer, the second silicon layer 13 is an intermediate silicon layer, and the third silicon layer 15 is a top silicon layer. The first buried oxide layer 12 and the second buried oxide layer 14 are insulating layers, such as silicon dioxide layers, which play a role in electrical isolation. That is, the SOI substrate 10 has a structure in which two buried oxide layers are interspersed and embedded in three silicon layers.

[0063] The gate structure 20 is disposed on the surface of the third silicon layer 15 away from the second buried oxide layer 14, and the gate structure 20 has sidewalls 40 on opposite sides. This application does not limit the specific structure of the gate structure 20. Optionally, the gate structure 20 may include a gate oxide layer, a polysilicon layer and a metal layer stacked sequentially along the direction away from the third silicon layer 15.

[0064] Unlike existing SOI devices where the source and drain regions are epitaxially grown on the top silicon layer, in the semiconductor device structure provided in this application embodiment, the source region 31 and drain region 32 are respectively disposed in the SOI substrate 10 on opposite sides of the gate structure 20. Specifically, the positions of the source region 31 and drain region 32 in the SOI substrate 10 include the following two cases:

[0065] The first type, such as Figure 3As shown, the SOI substrate 10 has a groove T on one side of the third silicon layer 15. The groove T penetrates at least the third silicon layer 15 and the second buried oxide layer 14 to expose a portion of the second silicon layer 13. At this time, the bottom of the groove T can be located at the interface between the second buried oxide layer 14 and the second silicon layer 13 to expose a portion of the second silicon layer 13, or it can penetrate the third silicon layer 15 and the second buried oxide layer 14 and also penetrate a portion of the second silicon layer 13 to expose a portion of the second silicon layer 13. Then, source region 31 and drain region 32 are formed by epitaxial filling inside and outside the corresponding groove T, respectively. The epitaxial starting layer of source region 31 and drain region 32 is the second silicon layer 13 (intermediate silicon layer) inside the SOI substrate.

[0066] The second type, such as Figure 4 As shown, the SOI substrate 10 has a groove T on one side of the third silicon layer 15. The groove T penetrates at least through the third silicon layer 15 to the first buried oxide layer 12 (i.e., it penetrates at least through the third silicon layer 15, the second buried oxide layer 14, the second silicon layer 13, and the first buried oxide layer 12) and exposes a portion of the first silicon layer 11. At this time, the bottom of the groove T can be located at the interface between the first buried oxide layer 12 and the first silicon layer 11 and expose a portion of the first silicon layer 11, or it can penetrate the third silicon layer 15 to the first buried oxide layer 12 and also penetrate a portion of the first silicon layer 11 to expose a portion of the first silicon layer 11. Then, source region 31 and drain region 32 are formed by epitaxial filling inside and outside the corresponding groove T, respectively. The epitaxial starting layer of source region 31 and drain region 32 is the first silicon layer 11 (supporting silicon layer) inside the SOI substrate 10.

[0067] It is understandable that, regardless of Figure 3 The first device structure shown is still Figure 4 In the second device structure shown, when the source region 31 and drain region 32 are formed by epitaxial filling inside and outside the corresponding groove T, the source region 31 and drain region 32 can be epitaxially grown from the bottom of the corresponding groove T, or the source region 31 and drain region 32 can be epitaxially grown from the bottom and sidewall of the corresponding groove T at the same time. The epitaxially formed source region 31 and drain region 32 are in contact with the silicon layer at the bottom of the corresponding groove T and in contact with the sidewall of the corresponding groove T.

[0068] Therefore, in the semiconductor device structure provided in this application embodiment, the epitaxial starting layer of the source region 31 and the drain region 32 is transferred from the top silicon layer of the SOI substrate 10 to the intermediate silicon layer or the support silicon layer inside the SOI substrate 10. Since the thickness of the intermediate silicon layer and the support silicon layer of the SOI substrate 10 can be relatively larger than that of the top silicon layer, a series of process problems caused by the thinning of the top silicon layer of the SOI substrate 10 as SOI technology nodes develop are solved. This improves the epitaxial growth quality and structural stability of the source and drain regions, and avoids the risk of easily penetrating the top silicon layer and causing excessive contact resistance when etching to form the source and drain regions after epitaxy of the top silicon layer.

[0069] Furthermore, regarding the gate-drain parasitic capacitance (C) of the device... gd In terms of SOI devices in related technologies, although it is possible to... Figure 2 As shown, the source region 31 and drain region 32 are made into structures with specific inclined surfaces to increase the angle between the source / drain region and the gate structure 20, or the sidewalls 40 on both sides of the gate structure 20 are made of low-K material, thereby alleviating the parasitic capacitance problem to some extent; however, as the device is miniaturized, for example, the thickness of the sidewalls 40 is inevitably reduced, so the improvement effect of these methods on parasitic capacitance is always limited.

[0070] In the semiconductor device structure provided in this application embodiment, since the source region 31 and drain region 32 are epitaxially filled in the corresponding groove T of the SOI substrate 10, the source / drain regions are further away from the gate structure 20 in the vertical direction of the device structure. The parallel overlap length between the source / drain regions and the gate structure 20 located on the surface of the top silicon layer is reduced. Specifically, as shown... Figure 1 As shown, in existing SOI devices, the parallel overlap length between the source / drain region and the gate structure 20 is d1. Furthermore... Figure 3 and Figure 4 As shown, in the semiconductor device structure provided in this application embodiment, the parallel overlap length between the source / drain region and the gate structure 20 is d2, which is significantly smaller than d1, thereby significantly reducing the parasitic capacitance between the source / drain region and the gate structure 20.

[0071] Furthermore, in SOI devices of related technologies, such as Figure 1 and Figure 2 As shown, the source / drain regions do not directly contact the channel (i.e., the region in the top silicon layer corresponding to the gate structure). Instead, they need to connect to the channel through a portion of the corresponding source / drain region in the top silicon layer. This results in the stress transmission path from the epitaxial growth of the source / drain regions to the channel being blocked, and the stress that can be provided to the channel is limited. As a result, the effect on improving the channel mobility is not significant. Moreover, the stress distribution of this type of device structure is complex, making analysis and modeling more difficult, which further increases the challenge of process optimization.

[0072] In the semiconductor device structure provided in this application embodiment, when the groove T at least penetrates the third silicon layer 15 and the second buried oxide layer 14 and exposes a portion of the second silicon layer 13, such as Figure 3 As shown, the source / drain regions are in direct contact with the channel region of the gate structure 20 corresponding to the third silicon layer 15; when the groove T penetrates at least through the third silicon layer 15 to the first buried oxide layer 12 and exposes a portion of the first silicon layer 11, as... Figure 4As shown, if only the region of the third silicon layer 15 corresponding to the gate structure 20 is a channel, then the source / drain regions are in direct contact with the channel region of the third silicon layer 15 corresponding to the gate structure 20; if the channel region of the third silicon layer 15 corresponding to the gate structure 20 and the channel region of the second silicon layer 13 corresponding to the gate structure 20 can be turned on sequentially by controlling the applied voltage of the gate structure 20, then the source / drain regions can also be in direct contact with the channel regions of the third silicon layer 15 corresponding to the gate structure 20 and the channel regions of the second silicon layer 13 corresponding to the gate structure 20.

[0073] In other words, in the semiconductor device structure provided in this application embodiment, the source / drain regions can directly contact the channel of the third silicon layer 15 or even the channel of the second silicon layer 13, thereby enhancing the contact reliability between the source / drain regions and the channel. Furthermore, by controlling the epitaxial material of the source / drain regions and the etching morphology of the corresponding grooves T, stress regulation of the channel can be achieved, which is beneficial to improving the channel mobility.

[0074] In summary, the semiconductor device structure provided in this application embodiment is suitable for advanced SOI node processes. It not only improves the epitaxial growth quality and structural stability of the source / drain regions at the process level, enhances the contact reliability between the source / drain regions and the channel, and enhances the stress control of the channel, but also reduces the parasitic capacitance between the source / drain regions and the gate structure 20 and achieves high channel mobility in terms of device electrical performance, which has significant application value.

[0075] Furthermore, it is understood that in the semiconductor device structure provided in the embodiments of this application, when the groove T at least penetrates the third silicon layer 15 and the second buried oxide layer 14 and exposes a portion of the second silicon layer 13, such as Figure 3 As shown, the epitaxial initiation layer of the source region 31 and the drain region 32 is the second silicon layer 13 (intermediate silicon layer) inside the SOI substrate 10. The second silicon layer 13 and the first silicon layer 11 are still electrically isolated by the first buried oxide layer 12, so a certain bias can still be applied to the first silicon layer 11 as needed. When the groove T penetrates at least through the third silicon layer 15 to the first buried oxide layer 12 and exposes a portion of the first silicon layer 11, such as... Figure 4 As shown, since the source region 31 and the drain region 32 are connected to the first silicon layer 11, it is no longer suitable to apply a bias to the first silicon layer 11.

[0076] Regarding the filling configuration of the source region 31 and drain region 32 within the corresponding recesses in the SOI substrate 10, options include, for example... Figure 3 and Figure 4As shown, the surface of the source region 31 facing away from the SOI substrate 10 is not lower than the surface of the third silicon layer 15 facing away from the second buried oxide layer 14; the surface of the drain region 32 facing away from the SOI substrate 10 is not lower than the surface of the third silicon layer 15 facing away from the second buried oxide layer 14. That is, the top of the source / drain regions is higher than the surface of the third silicon layer 15 (i.e., higher than the opening of the corresponding recess T), or flush with the surface of the third silicon layer 15 (i.e., flush with the opening of the corresponding recess T). It can be understood that the channel is the region of the third silicon layer 15 corresponding to the gate structure 20. In order to ensure that the source region 31 and the drain region 32 are in full contact with the channel, the top of the source region 31 and the drain region 32 is as close as possible to the surface of the third silicon layer 15.

[0077] Furthermore, such as Figure 3 and Figure 4 As shown, the surface of the source region 31 facing away from the SOI substrate 10 is higher than the surface of the third silicon layer 15 facing away from the second buried oxide layer 14; the surface of the drain region 32 facing away from the SOI substrate 10 is higher than the surface of the third silicon layer 15 facing away from the second buried oxide layer 14. That is, the tops of the source region 31 and the drain region 32 are higher than the surface of the third silicon layer 15 (i.e., higher than the opening of the corresponding groove T). This is because, in actual processes, since the source region 31 and the drain region 32 are epitaxially grown, it is difficult to precisely control the tops of the source region 31 and the drain region 32 to be flush with the surface of the third silicon layer 15. It is easier to control the tops of the source region 31 and the drain region 32 to extend slightly beyond the surface of the third silicon layer 15 to ensure sufficient contact between the source / drain region and the channel.

[0078] Alternatively, the tops of the source region 31 and the drain region 32 may be lower than the opening of the corresponding groove T, meaning that the source / drain region does not completely fill the corresponding groove T; it is only necessary to ensure that the source region 31 and the drain region 32 are in full contact with the channel.

[0079] For the shape of the top surface of the source region 31 and the drain region 32, optionally, the surface of the source region 31 facing away from the SOI substrate 10 is concave, convex, or planar; the surface of the drain region 32 facing away from the SOI substrate 10 is concave, convex, or planar. Specifically, when the source region 31 and the drain region 32 are epitaxially grown inside and outside the corresponding groove T, if the source region 31 and the drain region 32 grow vertically upwards from the bottom of the groove T, the top surface of the formed source region 31 and the drain region 32 can be planar; if the source region 31 and the drain region 32 grow simultaneously from the bottom and sidewall of the groove T, the top surface of the formed source region 31 and the drain region 32 may be concave or convex.

[0080] For the epitaxial materials of the source region 31 and the drain region 32, the material of the source region 31 may include at least one of SiGe and SiC; the material of the drain region 32 may include at least one of SiGe and SiC. Thus, by selecting the epitaxial materials of the source region 31 and the drain region 32, stress control of the channel can be achieved, which is beneficial to improving the channel mobility. For example, for PMOS devices, compressive stress is preferred, as it is beneficial to the transport of holes in the channel. Therefore, selecting SiGe as the epitaxial material for the source region 31 and the drain region 32 makes it easier to form compressive stress. For NMOS devices, tensile stress is preferred, as it is beneficial to the transport of electrons in the channel. Therefore, selecting SiC as the epitaxial material for the source region 31 and the drain region 32 makes it easier to form tensile stress.

[0081] For the etching morphology of the grooves T corresponding to the source region 31 and the drain region 32, the shape of the grooves T can optionally be a rectangular groove, a U-shaped groove, or a rhomboid groove. Since the grooves T of the SOI substrate 10 are formed through an etching process, different groove morphologies can be obtained by controlling the etching process, and different groove morphologies can provide more stress sources for the channel. A microscopic image of the device structure with a rhomboid groove is shown below. Figure 5 As shown, the area within the dashed box is a diamond-shaped groove.

[0082] Accordingly, embodiments of this application also provide a method for fabricating a semiconductor device structure, the method comprising:

[0083] S10: Reference Figure 6 As shown, an SOI substrate 10 is provided, which includes a first silicon layer 11, a first buried oxide layer 12, a second silicon layer 13, a second buried oxide layer 14 and a third silicon layer 15 stacked together.

[0084] S11: As Figure 6 As shown, a gate structure 20 is formed on the surface of the third silicon layer 15 facing away from the second buried oxide layer 14.

[0085] This application does not limit the specific structure of the gate structure 20. Optionally, the gate structure 20 may include a gate oxide layer, a polysilicon layer and a metal layer stacked sequentially along the direction away from the third silicon layer 15.

[0086] S12: As Figure 7 As shown, a dielectric layer 50 is deposited, which covers the gate structure 20 and the third silicon layer 15.

[0087] S13: As Figure 8a and Figure 8b As shown, the dielectric layers 50 on both sides of the gate structure 20 and a portion of the SOI substrate 10 are etched to form a groove T. The groove T penetrates at least the third silicon layer 15 and the second buried oxide layer 14, exposing a portion of the second silicon layer 13 (e.g., Figure 8a(as shown), or, the groove T at least penetrates the third silicon layer 15 to the first buried oxide layer 12 and exposes a portion of the first silicon layer 11 (as shown). Figure 8b As shown in the figure, the gate structure 20 has a portion of dielectric layer 50 on both sides to form sidewalls 40.

[0088] During the etching process, an anisotropic dry etching process can be used, performing only vertical etching and almost no lateral etching. This removes the dielectric layer 50 deposited along the horizontal direction, as well as part of the SOI substrate, while retaining the gate structure 20 and portions of the dielectric layer 50 (i.e., sidewalls 40) on both sides of the gate structure 20, resulting in... Figure 8a or Figure 8b The structure shown is such that, in order to protect the gate structure 20, the top of the gate structure 20 usually has an etching protection layer. For example, when the gate structure 20 includes a gate oxide layer, a polysilicon layer and a metal layer stacked sequentially in a direction away from the third silicon layer 15, the metal layer on the top of the gate structure 20 can protect the gate structure 20 from being etched.

[0089] For the etching morphology of the groove T, the shape of the groove T can optionally be a rectangular groove, a U-shaped groove, or a rhomboid groove. By controlling the etching process, different shapes of the groove T can be obtained, and different groove morphologies can provide more stress sources for the channel. Among them, a microscopic image of the device structure with a rhomboid groove is shown below. Figure 5 As shown, the dashed area represents a diamond-shaped groove.

[0090] S14: Source region 31 is epitaxially filled inside and outside one groove T on opposite sides of gate structure 20, and drain region 32 is epitaxially filled inside and outside the other groove T, resulting in... Figure 3 Or such as Figure 4 The structure shown.

[0091] Regarding the filling configuration of the source region 31 and drain region 32 within the corresponding recesses in the SOI substrate 10, options include, for example... Figure 3 and Figure 4 As shown, the surface of the source region 31 facing away from the SOI substrate 10 is not lower than the surface of the third silicon layer 15 facing away from the second buried oxide layer 14. The surface of the drain region 32 facing away from the SOI substrate 10 is not lower than the surface of the third silicon layer 15 facing away from the second buried oxide layer 14. That is, the top of the source / drain regions is higher than the surface of the third silicon layer 15 (i.e., higher than the opening of the corresponding groove T) or flush with the surface of the third silicon layer 15 (i.e., flush with the opening of the corresponding groove T), so that the source region 31 and the drain region are in full contact with the channel in the third silicon layer 15.

[0092] Alternatively, the tops of the source region 31 and the drain region 32 may be lower than the opening of the corresponding groove T, meaning that the source / drain region does not completely fill the corresponding groove T; it is only necessary to ensure that the source region 31 and the drain region 32 are in full contact with the channel.

[0093] As can be seen from the foregoing, when forming the groove T, if the bottom of the groove T is the second silicon layer 13, then the sidewalls of the groove T are the second buried oxide layer 14 and the third silicon layer 15; when the bottom of the groove T is the first silicon layer 11, the sidewalls of the groove T are the first buried oxide layer 12, the second silicon layer 13, the second buried oxide layer 14 and the third silicon layer 15. That is, the bottom and sidewalls of the groove T will expose silicon layers. Therefore, when the source / drain regions are epitaxially grown based on the silicon layer in the corresponding groove T, the source / drain regions are epitaxially grown from the bottom of the corresponding groove T, and the top surfaces of the formed source region 31 and drain region 32 can be planar; or, the source / drain regions are epitaxially grown from the bottom and sidewalls of the corresponding groove T at the same time, and the top surfaces of the formed source region 31 and drain region 32 may be concave or convex.

[0094] For the epitaxial materials of the source region 31 and the drain region 32, the material of the source region 31 may include at least one of SiGe and SiC; the material of the drain region 32 may include at least one of SiGe and SiC. Thus, by selecting the epitaxial materials of the source region 31 and the drain region 32, stress control of the channel can be achieved, which is beneficial to improving the channel mobility. For example, for PMOS devices, compressive stress is preferred, as it is beneficial to the transport of holes in the channel. Therefore, selecting SiGe as the epitaxial material for the source region 31 and the drain region 32 makes it easier to form compressive stress. For NMOS devices, tensile stress is preferred, as it is beneficial to the transport of electrons in the channel. Therefore, selecting SiC as the epitaxial material for the source region 31 and the drain region 32 makes it easier to form tensile stress.

[0095] The semiconductor device structure prepared by the above method transfers the epitaxial initiation layers of the source region 31 and drain region 32 from the top silicon layer of the SOI substrate 10 to an intermediate silicon layer or support silicon layer inside the SOI substrate 10. Compared with directly growing the source / drain regions on the top silicon layer, the thickness of the intermediate silicon layer and support silicon layer can be relatively thicker. This solves a series of process problems caused by the thinning of the top silicon layer of the SOI substrate 10 as SOI technology nodes develop, which leads to the epitaxial growth of source / drain regions on a thinner top silicon layer. This improves the epitaxial growth quality and structural stability of the source / drain regions, while avoiding the risk of easily penetrating the top silicon layer and causing excessive contact resistance when etching to form the source / drain regions after epitaxy on the top silicon layer. Furthermore, the parallel overlap area between the formed drain / drain regions and the gate structure 20 is significantly reduced, thereby reducing the parasitic capacitance between the source / drain regions and the gate structure 20. Furthermore, the source / drain regions can directly contact the channel of the third silicon layer 15 or even the channel of the second silicon layer 13, thereby enhancing the contact reliability between the source / drain regions and the channel. In addition, by controlling the epitaxial material of the source / drain regions and the etching morphology of the corresponding grooves T, stress regulation of the channel can be achieved, which is beneficial to improving the channel mobility.

[0096] This application also provides a CMOS structure, such as... Figure 9 As shown, the CMOS structure includes an NMOS device structure 100 and a PMOS device structure 200, wherein the NMOS device structure 100 adopts the semiconductor device structure provided in any of the foregoing embodiments, and / or the PMOS device structure 200 adopts the semiconductor device structure provided in any of the foregoing embodiments.

[0097] like Figure 9 As shown, in the CMOS structure, the NMOS device structure 100 and the PMOS device structure 200 have the same SOI substrate 10. The same SOI substrate 10 has a deep trench isolation structure 60, which is located between the NMOS device structure 100 and the PMOS device structure 200 to isolate the NMOS device structure 100 and the PMOS device structure 200.

[0098] Optionally, in the CMOS structure, both the NMOS device structure 100 and the PMOS device structure 200 adopt the semiconductor device structure provided in any of the foregoing embodiments. Specifically, the NMOS device structure 100 can adopt... Figure 3 or Figure 4 The semiconductor device structure shown, PMOS device structure 200 can also be adopted. Figure 3 or Figure 4 The semiconductor device structure shown, Figure 9 This is only one possible combination, namely, both NMOS device structure 100 and PMOS device structure 200 are... Figure 3 The semiconductor device structure shown is provided. All other combinations are within the scope of protection of this application and will not be described in detail here.

[0099] In the CMOS device structure provided in this application embodiment, the NMOS device structure 100 and / or PMOS device structure 200 transfer the epitaxial initiation layer of the source region 31 and drain region 32 from the top silicon layer of the SOI substrate 10 to the intermediate silicon layer or support silicon layer inside the SOI substrate 10. This not only improves the epitaxial growth quality and structural stability of the source / drain regions, but also reduces the parasitic capacitance between the source / drain regions and the gate structure 20, and achieves high channel mobility, thereby significantly improving the performance of the CMOS device structure.

[0100] Accordingly, embodiments of this application also provide a method for fabricating a CMOS structure, the method comprising:

[0101] S20: As Figure 10 As shown, an SOI substrate 10 is provided. The SOI substrate 10 includes a first silicon layer 11, a first buried oxide layer 12, a second silicon layer 13, a second buried oxide layer 14 and a third silicon layer 15 stacked together, and the SOI substrate 10 includes a first device region A1 and a second device region A2 that are isolated from each other.

[0102] The first device region A1 can correspond to either an NMOS device structure or a PMOS device structure, and the second device region A2 can correspond to either an NMOS device structure or a PMOS device structure.

[0103] S21: As Figure 11 As shown, a gate structure 20 is formed on the surface of the third silicon layer 15 in the first device region A1 and the second device region A2, respectively.

[0104] S22: As Figure 12 As shown, a first dielectric layer 51 is deposited, which covers the gate structure 20 and the third silicon layer 15.

[0105] S23: As Figure 13 As shown, a first photoresist layer 71 is deposited, and the first photoresist layer 71 is exposed and developed, so that the first photoresist layer 71 exposes the dielectric layer (i.e., the first dielectric layer 51) and the gate structure 20 corresponding to the first device region A1.

[0106] It is worth noting that at this time, the dielectric layer corresponding to the first device region A1 exposed by the first photoresist layer 71 is the first dielectric layer 51. Because the first dielectric layer 51 corresponding to the first device region A1 and part of the SOI substrate 10 need to be etched, the first photoresist layer 71 is used to protect the relevant structure of the second device region A2.

[0107] S24: As Figure 14 As shown, the dielectric layers (i.e., the first dielectric layer 51) on both sides of the exposed gate structure 20 and a portion of the SOI substrate 10 are etched to form a trench T. The trench T penetrates at least the third silicon layer 15 and the second buried oxide layer 14, exposing a portion of the second silicon layer 13 (see reference). Figure 8a (as shown), or, the groove T at least penetrates the third silicon layer 15 to the first buried oxide layer 12, exposing a portion of the first silicon layer 11 (see reference). Figure 8b As shown in the figure, the exposed gate structure 20 has a portion of dielectric layer on each side forming a sidewall 40.

[0108] S25: As Figure 15 As shown, a source region 31 is epitaxially filled inside and outside one groove T on opposite sides of the exposed gate structure 20, and a drain region 32 is epitaxially filled inside and outside the other groove T.

[0109] As mentioned above, the epitaxial material filling the source region 31 and the drain region 32 includes at least one of SiGe and SiC, and the appropriate epitaxial material can be selected according to the actual device stress requirements.

[0110] S26: As Figure 16As shown, the first photoresist layer 71 is removed, and a second dielectric layer 52 is deposited. The second dielectric layer 52 covers the gate structure 20, the formed source region 31 and drain region 32, and the first dielectric layer 51.

[0111] It is understandable that the deposited second dielectric layer 52 protects the already formed source region 31 and drain region 32, as well as the gate structure 20, corresponding to the first device region A1.

[0112] S27: As Figure 17 As shown, a second photoresist layer 72 is deposited, and the second photoresist layer 72 is exposed and developed, so that the second photoresist layer 72 exposes the dielectric layer (the stack of the first dielectric layer 51 and the second dielectric layer 52) and the gate structure 20 corresponding to the second device region A2.

[0113] It should be noted that since the first dielectric layer 51 corresponding to the second device region A2 was previously protected by the first photoresist layer 71, the dielectric layer corresponding to the second device region A2 exposed by the second photoresist layer 72 at this time is a stack of the first dielectric layer 51 and the second dielectric layer 52.

[0114] Repeat step S24, as follows Figure 18 As shown, the dielectric layers 50 (i.e., the first dielectric layer 51 and the second dielectric layer 52) on both sides of the exposed gate structure 20 and a portion of the SOI substrate 10 are etched to form a trench T. The trench T penetrates at least through the third silicon layer 15 and the second buried oxide layer 14, exposing a portion of the second silicon layer 13 (see reference). Figure 8a (as shown), or, the groove T at least penetrates the third silicon layer 15 to the first buried oxide layer 12, exposing a portion of the first silicon layer 11 (see reference). Figure 8b As shown in the figure, the exposed gate structure 20 has a portion of dielectric layer on each side forming a sidewall 40.

[0115] Repeat step S25, as follows Figure 9 As shown, a source region 31 is epitaxially filled in one groove T on opposite sides of the exposed gate structure 20, and a drain region 32 is epitaxially filled in the other groove T. Then, the second photoresist layer 72 is removed to form a CMOS structure including an NMOS device structure 100 and a PMOS device structure 200.

[0116] Using the above method, a CMOS structure with source region 31 and drain region 32 epitaxially grown from the intermediate silicon layer or supporting silicon layer inside the SOI substrate 10 can be obtained on the same SOI substrate 10. Furthermore, when fabricating one of the NMOS devices and PMOS devices in the CMOS structure, a photolithography process is used to protect the other of the NMOS devices and PMOS devices. The resulting CMOS structure has smaller parasitic capacitance, better channel stress control capability, and better channel conduction capability compared to conventional CMOS structures, resulting in a significant improvement in device performance.

[0117] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0118] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor device structure, characterized in that, include: SOI substrate, the SOI substrate comprising a first silicon layer, a first buried oxide layer, a second silicon layer, a second buried oxide layer and a third silicon layer stacked together; A gate structure is disposed on the surface of the third silicon layer away from the second buried oxide layer, and the gate structure has sidewalls on opposite sides. The source region and drain region are respectively disposed in the SOI substrate on opposite sides of the gate structure. The SOI substrate has a groove on one side of the third silicon layer. The groove penetrates at least through the third silicon layer and the second buried oxide layer to expose a portion of the second silicon layer. Alternatively, the groove penetrates at least through the third silicon layer to the first buried oxide layer to expose a portion of the first silicon layer. The source region and the drain region are respectively epitaxially filled in the corresponding groove.

2. The semiconductor device structure according to claim 1, characterized in that, The surface of the source region away from the SOI substrate is not lower than the surface of the third silicon layer away from the second buried oxide layer; The surface of the drain region away from the SOI substrate is not lower than the surface of the third silicon layer away from the second buried oxide layer.

3. The semiconductor device structure according to claim 2, characterized in that, The surface of the source region away from the SOI substrate is higher than the surface of the third silicon layer away from the second buried oxide layer; The surface of the drain region away from the SOI substrate is higher than the surface of the third silicon layer away from the second buried oxide layer.

4. The semiconductor device structure according to claim 1, characterized in that, The material of the source region includes at least one of SiGe and SiC; The material of the leak region includes at least one of SiGe and SiC.

5. The semiconductor device structure according to claim 1, characterized in that, Within a cross-section perpendicular to the plane of the SOI substrate, the groove is a rectangular groove, a U-shaped groove, or a rhomboid groove.

6. The semiconductor device structure according to claim 1, characterized in that, The surface of the source region facing away from the SOI substrate is concave, convex, or planar. The surface of the drain region facing away from the SOI substrate is concave, convex, or planar.

7. A method for fabricating a semiconductor device structure, characterized in that, include: S10: Provide an SOI substrate, the SOI substrate comprising a first silicon layer, a first buried oxide layer, a second silicon layer, a second buried oxide layer and a third silicon layer stacked together; S11: A gate structure is formed on the surface of the third silicon layer that is away from the second buried oxide layer; S12: Deposit a dielectric layer, the dielectric layer covering the gate structure and the third silicon layer; S13: Etch the dielectric layer and part of the SOI substrate on both sides of the gate structure to form a groove. The groove penetrates at least the third silicon layer and the second buried oxide layer to expose part of the second silicon layer. Alternatively, the groove penetrates at least the third silicon layer to the first buried oxide layer to expose part of the first silicon layer. Part of the dielectric layer is retained on both sides of the gate structure to form sidewalls. S14: The source region is epitaxially filled inside and outside one of the grooves on opposite sides of the gate structure, and the drain region is epitaxially filled inside and outside the other groove.

8. The method for fabricating a semiconductor device structure according to claim 7, characterized in that, When the source region is filled inside and outside the corresponding groove, the source region grows epitaxially from the bottom of the corresponding groove, or the source region grows epitaxially from both the bottom and sidewall of the corresponding groove. When the drain area is filled by extending into and out of the corresponding groove, the drain area grows outward from the bottom of the corresponding groove, or the drain area grows outward from both the bottom and the sidewall of the corresponding groove.

9. A CMOS structure, characterized in that, It includes an NMOS device structure and a PMOS device structure, wherein the NMOS device structure adopts the semiconductor device structure according to any one of claims 1-6, and / or the PMOS device structure adopts the semiconductor device structure according to any one of claims 1-6; The NMOS device structure and the PMOS device structure share the same SOI substrate, which has a deep trench isolation structure located between the NMOS device structure and the PMOS device structure to isolate them.

10. A method for fabricating a CMOS structure, characterized in that, include: S20: Provide an SOI substrate, the SOI substrate including a first silicon layer, a first buried oxide layer, a second silicon layer, a second buried oxide layer and a third silicon layer stacked together, and the SOI substrate including a first device region and a second device region that are isolated from each other; S21: A gate structure is formed on the surface of the third silicon layer in the first device region and the second device region, respectively; S22: Deposit a first dielectric layer, the first dielectric layer covering the gate structure and the third silicon layer; S23: Deposit a first photoresist layer, and expose and develop the first photoresist layer so that the first photoresist layer exposes the dielectric layer and the gate structure corresponding to the first device region; S24: Etch the dielectric layers on both sides of the exposed gate structure and part of the SOI substrate to form a groove. The groove penetrates at least the third silicon layer and the second buried oxide layer to expose part of the second silicon layer. Alternatively, the groove penetrates at least the third silicon layer to the first buried oxide layer to expose part of the first silicon layer. Part of the dielectric layer is retained on both sides of the exposed gate structure to form sidewalls. S25: A source region is epitaxially filled inside and outside one of the grooves on opposite sides of the exposed gate structure, and a drain region is epitaxially filled inside and outside the other groove; S26: Remove the first photoresist layer and deposit a second dielectric layer, the second dielectric layer covering the gate structure, the formed source region and the drain region, and the first dielectric layer; S27: Deposit a second photoresist layer, and expose and develop the second photoresist layer so that the second photoresist layer exposes the dielectric layer and the gate structure corresponding to the second device region; Repeat steps S24 and S25 to remove the second photoresist layer and form a CMOS structure including an NMOS device structure and a PMOS device structure, wherein the first device region corresponds to one of the NMOS device structure and the PMOS device structure, and the second device region corresponds to the other of the NMOS device structure and the PMOS device structure.

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