LDMOS device capable of reducing on-resistance and manufacturing method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device for reducing on-resistance and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate, a drift region, a source region, a drain region and a gate structure, wherein the drift region, the source region and the drain region are formed in the semiconductor substrate. The key point is that a high carrier mobility layer is formed in the drift region, and the layer forms a part of a conductive path between the channel and the drain region. The high carrier mobility layer can be a selective epitaxial growth silicon germanium layer, and can also be a germanium-containing layer formed by ion implantation. By introducing the high mobility layer, the migration rate of carriers in the drift region is remarkably improved, the drift region resistance and the total on-resistance of the device are effectively reduced, and meanwhile, the influence on the breakdown voltage is small. According to the LDMOS device, the restrictive relation between the on-resistance and the breakdown voltage in a traditional LDMOS device is broken, low on-resistance and high breakdown voltage are achieved at the same time, and the power efficiency and the overall performance of the device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a LDMOS device with reduced on-resistance and a manufacturing method thereof. BACKGROUND

[0002] Lateral Diffused Metal Oxide Semiconductor (LDMOS) device, as an important power device, is widely used in power management integrated circuits, radio frequency power amplifiers, automotive electronics and display drivers, etc. due to its advantages of being able to be integrated in standard CMOS process, fast switching speed, high power gain, etc.

[0003] In the design of LDMOS device, two core performance indicators are on-resistance (Rs) or specific on-resistance (Rsp) and breakdown voltage (BV). An ideal high-performance LDMOS device needs to have as low on-resistance as possible and as high breakdown voltage as possible at the same time. However, in the traditional LDMOS device structure, there is usually a mutual restrictive relationship between the two key parameters.

[0004] In order to obtain a higher breakdown voltage, the drift region of the LDMOS device usually needs to adopt a lower doping concentration and a longer length to withstand a higher voltage. However, the low-doped and long-distance drift region is the main component of the on-resistance, and its higher resistivity will significantly increase the overall on-resistance of the device, thereby causing greater on-state loss and heat generation, and reducing the overall efficiency of the device. Conversely, if the doping concentration of the drift region is increased or its length is shortened in order to reduce the on-resistance, the electric field intensity in the drift region will sharply increase in the off-state, causing the breakdown voltage of the device to decrease significantly, limiting its reliability in high-voltage applications.

[0005] This effect between on-resistance and breakdown voltage has become the main technical bottleneck restricting the further improvement of the performance of LDMOS device. The existing technology usually optimizes the drift region doping distribution (such as using RESURF technology), introduces field plate structure, etc. to alleviate this contradiction, but these methods mainly optimize in the aspect of electric field regulation, and the conductivity of the drift region material itself is limited, so it is difficult to significantly reduce the on-resistance without sacrificing the breakdown voltage.

[0006] Therefore, there is an urgent need in the art for a new technical solution to break the inherent restrictive relationship between on-resistance and breakdown voltage in the traditional LDMOS device, effectively reduce the on-resistance while maintaining or even improving the breakdown voltage performance of the device. SUMMARY

[0007] The technical problem solved by the present application is that the existing lateral diffusion metal oxide semiconductor (LDMOS) device has inherent constraints when pursuing low on-resistance and high breakdown voltage, and it is difficult to optimize both at the same time.

[0008] To solve the above technical problems, the present application provides an LDMOS device with reduced on-resistance, comprising:

[0009] a semiconductor substrate;

[0010] a drift region, a source region and a drain region formed in the semiconductor substrate;

[0011] a gate structure formed above the semiconductor substrate, the gate structure being located above a channel region for forming a channel between the source region and the drift region; and

[0012] a high-carrier-mobility layer formed in the drift region, the high-carrier-mobility layer constituting part of a conduction path between the channel and the drain region.

[0013] Preferably, the high-carrier-mobility layer is a silicon germanium layer or a strained silicon carbide layer.

[0014] Preferably, a trench is defined in the drift region, and the high-carrier-mobility layer is filled in the trench.

[0015] Preferably, a silicon cap layer is further formed on top of the high-carrier-mobility layer, and part of the gate structure is located on the silicon cap layer.

[0016] Preferably, the high-carrier-mobility layer is a germanium-containing layer formed by implanting germanium ions into a surface layer of the drift region.

[0017] Preferably, the drift region is an N-type well drift region.

[0018] Preferably, the LDMOS device is an N-type LDMOS device or a P-type LDMOS device.

[0019] The present application also provides a manufacturing method of an LDMOS device with reduced on-resistance, comprising:

[0020] Step one, providing a semiconductor substrate and forming a drift region for the LDMOS device in the semiconductor substrate;

[0021] Step two, forming a trench in the drift region;

[0022] Step three, selectively epitaxially growing a high-mobility semiconductor layer in the trench;

[0023] Step four, forming a gate structure based on the high-mobility semiconductor layer and the drift region, and forming a source region and a drain region in the substrate to constitute the LDMOS device.

[0024] Preferably, after step three and before step four, further comprising: forming a silicon cap layer on the high mobility semiconductor layer; and the gate structure in step four is formed based on the silicon cap layer and the drift region.

[0025] Preferably, after forming the silicon cap layer and before forming the gate structure, further comprising: performing chemical mechanical polishing on the surface of the silicon cap layer to achieve surface planarization.

[0026] Preferably, in step three, the high mobility semiconductor layer is a silicon germanium layer or a strained silicon carbide layer.

[0027] Preferably, in step two, the trench is formed in the drift region at a location originally used for forming a shallow trench isolation structure.

[0028] The present application also provides a method for manufacturing a low on-resistance LDMOS device, comprising:

[0029] Step one, providing a semiconductor substrate and forming a drift region for the LDMOS device in the semiconductor substrate;

[0030] Step two, forming a high mobility surface layer containing germanium in the drift region by an ion implantation process;

[0031] Step three, forming a gate structure based on the high mobility surface layer and the drift region, and forming a source region and a drain region in the substrate to constitute the LDMOS device.

[0032] Preferably, after step two and before step three, further comprising: forming a silicon cap layer on the high mobility surface layer; and the gate structure in step three is formed based on the silicon cap layer and the drift region.

[0033] Preferably, after forming the silicon cap layer and before forming the gate structure, further comprising: performing chemical mechanical polishing on the surface of the silicon cap layer to achieve surface planarization.

[0034] Preferably, the drift region is an N-type well drift region.

[0035] As described above, the low on-resistance LDMOS device and the method for manufacturing the same have the following beneficial effects:

[0036] The present application introduces a layer of high carrier mobility material in the drift region of LDMOS device, which forms part of the conduction path, significantly improving the carrier transport efficiency in the drift region. This directly reduces the drift region resistance, which is the main part of the on-resistance of the device, thereby effectively reducing the overall on-resistance of the LDMOS device. This design optimizes the on-state characteristics of the device, while having little effect on the critical region electric field distribution that determines the breakdown voltage, thus successfully decoupling the traditional constraint relationship between on-resistance and breakdown voltage, enabling lower on-resistance while maintaining high breakdown voltage, improving the overall performance and power efficiency of the device. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 A process flow diagram showing an embodiment of the semiconductor device manufacturing method of the present application;

[0038] Figure 2 A process flow diagram showing an embodiment of the semiconductor device manufacturing method of the present application;

[0039] Figure 3 A schematic diagram of the semiconductor device structure of the present application. DETAILED DESCRIPTION

[0040] The embodiments of the present application will be described in detail with specific reference to particular examples. Those skilled in the art will easily understand other advantages and effects of the present application from the description of the present application. The present application can also be implemented or applied in other different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0041] Figure 1 A process flow diagram showing an embodiment of the semiconductor device manufacturing method of the present application; Figure 2 A process flow diagram showing an embodiment of the semiconductor device manufacturing method of the present application; Figure 3 A schematic diagram of the final structure formed according to any embodiment.

[0042] The present application provides a lateral diffusion metal oxide semiconductor (LDMOS) device. Referring to Figure 3 , the device includes a semiconductor substrate. The substrate serves as the physical and electrical foundation of the device, and its selection directly affects the performance, cost and integration of the device. In most standard power IC processes, the most commonly used substrate is a bulk silicon (Bulk Silicon) substrate. Specifically, a P-type doped silicon wafer is usually selected, and its resistivity is selected according to the breakdown voltage and isolation requirements. In order to further optimize the performance of the device, a low-resistance N+ buried layer 101 can be formed on the substrate in advance, which can serve as a low-resistance path to reduce the collector series resistance of the NLDMOS device and help suppress the latch-up effect.

[0043] The device also includes a drift region 106, a source region 111, a drain region 112, and a P+ body contact 110 formed in the semiconductor substrate. The device is electrically isolated from other devices by a complete isolation ring, which is composed of a deep P-type buried layer (PBL) 104, a P-well (PWELL) 105, and a P+ implant 113 on top, forming a continuous P-type isolation wall from the substrate deep down to the surface in the vertical direction.

[0044] The device also includes a gate structure 109 formed above the semiconductor substrate, which is above a channel region (on the surface of the P-type well region 107) for forming a channel between the source region 111 and the drift region 106.

[0045] The device is characterized in that it further includes a high carrier mobility layer 114 formed within the drift region 106, which forms part of the conduction path between the channel and the drain region 112. By introducing this high carrier mobility layer 114 in the critical conduction path of the drift region 106, the mobility of the carriers (e.g., electrons) in this region can be significantly improved. This design can effectively reduce the drift region resistance, which is the main contributor to the on-resistance Rs of the LDMOS device, without changing the doping concentration and geometry of the drift region 106, thereby reducing the on-resistance Rs of the entire LDMOS device. More importantly, this structure successfully breaks the trade-off between on-resistance and breakdown voltage in traditional LDMOS devices, as optimizing the drift region conductivity mainly affects the on-state performance, while having little effect on the breakdown field distribution at the edges of the device, thus achieving low on-resistance and high breakdown voltage, improving the power efficiency and overall performance of the device.

[0046] In some embodiments, the high carrier mobility layer 114 is a silicon germanium (SiGe) layer or a strained silicon carbide (SiC) layer. Both of these materials have higher carrier mobility than pure silicon. In particular, the silicon germanium layer, by introducing germanium atoms with larger atomic radius into the silicon lattice, effectively changes the band structure of silicon, thereby significantly improving the mobility of electrons and / or holes, making it an ideal choice for high-performance power devices. In addition to SiGe and SiC, other high-mobility materials such as strained silicon or III-V semiconductor materials (such as InGaAs, etc.) can also be considered depending on the specific application and process platform, although the latter is more complex to integrate with standard silicon processes.

[0047] In some embodiments, the high carrier mobility layer 114 is a silicon germanium layer, typically with a germanium atomic percentage in the range of 10% to 40%. This range of germanium content is considered to be an optimized interval that provides sufficient lattice strain to significantly enhance carrier mobility, while ensuring good crystal quality and process stability. If the germanium content is lower than 10%, the mobility enhancement effect is not significant, and the contribution to reducing on-resistance is limited. If the germanium content is higher than 40%, the lattice mismatch may be too large, introducing too many dislocations and other crystal defects, which may become carrier scattering centers and affect the long-term reliability of the device.

[0048] In some embodiments, a trench is defined in the drift region 106, and the high carrier mobility layer 114 is filled in the trench. This trench-filled structure can accurately limit the high mobility material to the most critical current path in the device, thereby maximizing its effect on reducing resistance. At the same time, this structure also simplifies integration with existing CMOS processes, and has strong process feasibility.

[0049] In some embodiments, a silicon cap layer is formed on top of the high carrier mobility layer 114, and a portion of the gate structure 109 is located on the silicon cap layer. The silicon cap layer mainly plays two key roles: first, as a protective layer, protecting the underlying high carrier mobility layer 114 (such as a SiGe layer) from oxidation or composition segregation during subsequent high-temperature processes (such as thermal growth of gate oxide); second, providing a pure silicon interface for the growth of a high-quality gate dielectric layer.

[0050] In other embodiments, the high carrier mobility layer is a germanium-containing layer formed by implanting germanium ions into the surface layer of the drift region. This provides an alternative technical solution to epitaxial growth. The ion implantation method typically does not require additional etching trench steps, simplifying the process flow and helping to reduce manufacturing costs. By subsequent annealing process to activate the implanted germanium ions and repair lattice damage, a high electron mobility region can also be formed in the surface layer of the drift region, achieving the purpose of reducing on-resistance.

[0051] In some embodiments, the drift region 106 is an N-type well (N-well) drift region. This corresponds to the typical structure of an N-type LDMOS (NLDMOS) device, whose conductive carriers are electrons, so introducing a high electron mobility material (such as SiGe) will obtain significant performance improvement.

[0052] In some embodiments, the LDMOS device is an N-type LDMOS device or a P-type LDMOS device. The technical concept of the present application is universal and is equally applicable to P-type LDMOS (PLDMOS) devices. In a PLDMOS, the drift region is P-type and the conducting carriers are holes. By introducing a material that can enhance the mobility of holes (e.g. by applying compressive strain to a high-germanium-content SiGe), the on-resistance can also be effectively reduced.

[0053] The present application also provides a process for reducing the on-resistance of a lateral diffusion metal oxide semiconductor (LDMOS) device. The following will be described in detail through two embodiments.

[0054] Embodiment One: Trench Epitaxy Method

[0055] As shown in FIG. 1, the present embodiment provides a manufacturing method for constructing a high-mobility semiconductor layer using a "trench formation and selective epitaxial growth" process. The specific steps are as follows: Figure 1 Step One: Provide a semiconductor substrate and form a drift region for an LDMOS device in the semiconductor substrate.

[0056] This step is the basic construction stage of the device. First, a substrate containing an N+ buried layer 101 and a P-type body region 102 is provided, and an N-type epitaxial layer 103 is epitaxially grown thereon. Subsequently, a series of ion implantation and diffusion processes are performed to define an N-type drift region 106 and a P-type well region 107 in the epitaxial layer 103. Deep portions of the isolation ring, such as a deep P-type buried layer PBL 104 and a P-well PWELL 105, are also typically formed at this stage through high-energy ion implantation and corresponding annealing processes.

[0057] In some embodiments, the drift region formed in this step is an N-type well drift region.

[0058] Step Two: Form a trench in the drift region.

[0059] After the main well region implantation is completed, a trench pattern is defined on a predetermined surface area of the N-type drift region 106 through a photolithography process, and then a dry etching technique such as reactive ion etching (RIE) is used to etch a trench of a specific depth. The position and size of the trench determine the formation area of the subsequent high-carrier-mobility layer.

[0060] In some embodiments, in Step Two, the trench is formed in the position originally used to form a shallow trench isolation (STI) structure in the drift region. This design allows the present application to be easily integrated into existing process flows, and the existing photomask layout can be modified or the STI formation step can be replaced with the step of the present application in the standard process flow, thereby reducing the complexity and cost of process development.

[0061] In some embodiments, in Step Two, the trench is formed in the position originally used to form a shallow trench isolation (STI) structure in the drift region. This design allows the present application to be easily integrated into existing process flows, and the existing photomask layout can be modified or the STI formation step can be replaced with the step of the present application in the standard process flow, thereby reducing the complexity and cost of process development.

[0062] Step three, selectively epitaxially grow a high mobility semiconductor layer in the trench.

[0063] A high carrier mobility layer 114 is grown in the trench formed in step two using a selective epitaxial growth (SEG) technique. This process ensures that the high mobility material only grows on the silicon surface at the bottom of the trench and does not deposit on the surrounding dielectric layer, thus achieving precise self-aligned fill.

[0064] In some embodiments, in step three, the high mobility semiconductor layer is a silicon germanium layer or a strained silicon carbide layer.

[0065] Step four, form a silicon cap layer on the high mobility semiconductor layer.

[0066] A thin silicon cap layer is typically grown immediately after the epitaxial growth to protect the underlying newly grown high carrier mobility layer 114 and to form a high quality gate dielectric interface thereon.

[0067] In some embodiments, after forming the silicon cap layer, further comprising: performing a chemical mechanical polishing (CMP) process on the surface of the silicon cap layer to achieve surface planarization. Since the selective epitaxial growth can cause the surface topography to be uneven, the CMP step is beneficial to remove the excess growth material and achieve a globally planar wafer surface. The planar surface is a condition to ensure that the subsequent photolithography, gate dielectric growth, and polysilicon gate deposition processes have good uniformity and high quality, and directly affects the yield and performance consistency of the device.

[0068] Step five, form a gate structure based on the silicon cap layer and the drift region, and form a source region and a drain region in the substrate to constitute an LDMOS device.

[0069] This step is the last stage of device formation. First, shallow trench isolation 108 is formed. The formation of gate structure 109 can be done using either a "gate-last" or a "gate-first" process. For example, the formation of the gate dielectric layer can include thermal growth of silicon dioxide (Si02), or deposition of a high-k material such as hafnium oxide (Hf02), zirconium oxide (Zr02), etc. using atomic layer deposition (ALD) or other methods. The formation of the gate electrode can include deposition of doped polysilicon, or for more advanced processes, a metal gate can be used, which typically includes a work function metal layer (such as titanium nitride TiN, tantalum nitride TaN, etc.) and a low-resistance fill metal layer (such as tungsten W, aluminum Al, etc.). After the gate dielectric and electrode materials are deposited, photolithography and etching are used to form the gate pattern. Subsequently, ion implantation is performed to form N+ source region 111, P+ body region contact 110, and N+ drain region 112, using gate structure 109 as a mask. P+ implant region 113 on top of the isolation ring is typically formed in the same implantation process as P+ body region contact 110. Finally, after activation anneal and metallization, etc., the device is completed Figure 3 as shown in the device structure.

[0070] Example Two: Ion Implantation Method

[0071] As shown in the device structure. Figure 2 This embodiment provides another method of manufacturing, using an "ion implantation" process to build the high-mobility semiconductor layer, with a simpler flow. The steps are as follows:

[0072] Step One: Provide a semiconductor substrate, and form a drift region for the LDMOS device in the semiconductor substrate.

[0073] This step is identical to Step One in Example One. That is, the semiconductor substrate (on which N+ buried layer 101 and P-type body region 102 have been formed), epitaxial layer 103, N-type drift region 106, P-type well region 107, and deep isolation structures PBL 104 and PWELL 105 are prepared.

[0074] In some embodiments, the drift region formed in this step is an N-type well drift region.

[0075] Step Two: Using an ion implantation process, implant germanium into the surface layer of the predetermined region of the drift region, to form a high-mobility surface layer containing germanium.

[0076] This is the core step of the embodiment. First, a photoresist mask is formed by a photolithography process, exposing only the target area in the N-type drift region 106 where the high mobility layer is to be formed. Then, germanium (Ge) ions are implanted into the surface layer of the exposed area by an ion implanter. The implantation energy and dose are precisely controlled to form a layer of a specific concentration and depth of germanium-containing region in the surface layer of the drift region, which is the high carrier mobility layer 114.

[0077] In some embodiments, after step two and before step three, further comprising: forming a silicon cap layer on the high mobility surface layer.

[0078] After ion implantation and subsequent activation annealing, a thin silicon cap layer can be grown by epitaxy, which aims to provide a better, damage-free pure silicon interface for the subsequent formation of high-quality gate dielectric, thereby further improving the reliability and electrical performance of the device.

[0079] In some embodiments, after forming the silicon cap layer, further comprising: performing chemical mechanical polishing on the surface of the silicon cap layer to achieve surface planarization.

[0080] Step three, forming a gate structure based on the high mobility surface layer and the drift region, and forming source and drain regions in the substrate to constitute an LDMOS device.

[0081] After implantation, a high-temperature annealing process (such as rapid thermal annealing RTA) is first performed to activate the implanted germanium ions and repair the lattice damage caused during implantation. Subsequently, subsequent processes similar to step five of embodiment one are performed: forming a shallow trench isolation 108, constructing a gate structure 109 (the materials and formation methods are as described in embodiment one), implanting to form an N+ source region 111, a P+ body region contact 110, an N+ drain region 112, and an isolation ring P+ region 113. Finally, the device is completed by processes such as metallization. Figure 3 The device shown.

[0082] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the application in a schematic manner, and only show the components related to the application in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be arbitrarily changed in terms of its type, number and proportion, and the layout pattern of the components may also be more complex.

[0083] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not intended to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the application should be covered by the claims of the application.

Claims

1. An LDMOS device with reduced on-resistance, characterized in that, Comprising: a semiconductor substrate; a drift region, a source region and a drain region formed in the semiconductor substrate; and a gate structure formed over the semiconductor substrate, the gate structure being located over a channel region for forming a channel between the source region and the drift region; a high carrier mobility layer formed within the drift region, the high carrier mobility layer constituting a portion of a conductive path between the channel and the drain region. The high carrier mobility layer is a silicon germanium layer or a strained silicon carbide layer.

2. The LDMOS device with reduced on-resistance of claim 1, wherein: The drift region has a trench defined therein, the high carrier mobility layer being filled in the trench.

3. The LDMOS device with reduced on-resistance of claim 1, wherein: Further comprising a silicon cap layer formed on top of the high carrier mobility layer, a portion of the gate structure being located on the silicon cap layer.

4. The LDMOS device with reduced on-resistance of claim 1, wherein: The high carrier mobility layer is a germanium-containing layer formed by implanting germanium ions into a surface layer of the drift region.

5. The LDMOS device with reduced on-resistance of claim 1, wherein: The drift region is an N-type well drift region.

6. The LDMOS device with reduced on-resistance of claim 1, wherein: The LDMOS device is an N-type LDMOS device or a P-type LDMOS device.

7. The LDMOS device with reduced on-resistance of claim 1, wherein: Comprising:

8. A method of manufacturing an LDMOS device with reduced on-resistance, characterized by, Step one, providing a semiconductor substrate and forming a drift region for the LDMOS device in the semiconductor substrate; Step two, forming a trench in the drift region; Step three, selectively epitaxially growing a high mobility semiconductor layer in the trench; Step four, forming a gate structure based on the high mobility semiconductor layer and the drift region, and forming a source region and a drain region in the substrate to constitute the LDMOS device. In step three, the high mobility semiconductor layer is a silicon germanium layer or a strained silicon carbide layer.

9. The method of fabricating a low on-resistance LDMOS device of claim 8, wherein: After step three and before step four, further comprising forming a silicon cap layer on the high mobility semiconductor layer; and the gate structure in step four is formed based on the silicon cap layer and the drift region.

10. The method of fabricating a low on-resistance LDMOS device of claim 8, wherein: After forming the silicon cap layer and before forming the gate structure, further comprising subjecting a surface of the silicon cap layer to a chemical mechanical polishing process to achieve surface planarization.

11. The method of fabricating a low on-resistance LDMOS device of claim 10, wherein: In step two, the trench is formed in the drift region at a location originally intended for forming a shallow trench isolation structure.

12. The method of fabricating a low on-resistance LDMOS device of claim 8, wherein: Comprising:

13. A method of manufacturing an LDMOS device with reduced on-resistance, characterized by, Step one, providing a semiconductor substrate and forming a drift region for the LDMOS device in the semiconductor substrate; Step two, implanting germanium elements into a surface layer of a predetermined region of the drift region by an ion implantation process to form a germanium-containing high mobility surface layer; Step three, forming a gate structure based on the high mobility surface layer and the drift region, and forming a source region and a drain region in the substrate to constitute the LDMOS device. After step two and before step three, further comprising forming a silicon cap layer on the high mobility surface layer; and the gate structure in step three is formed based on the silicon cap layer and the drift region.

14. The method of fabricating a low on-resistance LDMOS device of claim 13, wherein: After forming the silicon cap layer and before forming the gate structure, further comprising subjecting a surface of the silicon cap layer to a chemical mechanical polishing process to achieve surface planarization.

15. The method of fabricating a low on-resistance LDMOS device of claim 14, wherein: The drift region is an N-type well drift region.

16. The method of claim 8 or 13, wherein: ​

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