Communication optimization for distributed machine learning

Abstract

The embodiments described herein provide a system for configuring distributed training of a neural network, the system comprising: a memory for storing data to facilitate data transfer during distributed training of the neural network; a network interface for sending and receiving configuration data associated with a set of worker nodes configured to perform distributed training of the neural network; and a processor for executing instructions provided by the memory, the instructions causing the processor to create one or more sets of worker nodes based on a communication pattern of messages transmitted between the worker nodes during distributed training of the neural network.

Description

Technical Field

[0001] The embodiments generally relate to logic for performing processing operations using a general-purpose graphics processing unit. More specifically, the embodiments relate to communication optimizations for distributed machine learning. Background Technology

[0002] Neural network models can be implemented as a collection of nodes (neurons) connected in a non-cyclic graph. One type of neural network, the "feedforward network," receives input (a single vector) at the input layer of its nodes and maps the input to values ​​in the output layer of the nodes through a series of hidden layers. Each layer in the network consists of a set of neurons, where each neuron is fully connected to all neurons in the (multiple) adjacent layers, and neurons within a layer do not share any connections. If the network is modeling classification, each node in the output layer can represent one of the possible categories to which an entity belongs, and the value of each output node can represent the probability that the input entity belongs to that category. Convolutional Neural Networks (CNNs) are another type of neural network model that models feature detection by performing convolution operations on input data. For example, in image processing, a CNN can take raw image data as input and then output a set of feature maps that represent an abstraction of the raw data.

[0003] Current parallel graphics data processing involves developing systems and methods for performing specific operations on graphics data, such as linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Furthermore, programmable general-purpose graphics processors can be configured to perform a wide variety of operations for processing vertex and fragment data, as well as for performing general-purpose parallel processing operations. For example, parallel graphics processors with a single-instruction multithreaded (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, multiple sets of parallel threads attempt to execute program instructions together synchronously as often as possible to improve processing efficiency. A general overview of the software and hardware used in SIMT architectures can be found in Shane Cook's *CUDA Programming*, Chapter 3, pages 37–51 (2013) and / or Nicholas Wilt's *CUDA Handbook, A Comprehensive Guide to GPU Programming*, Chapters 2.6.2–3.1.2 (June 2013). Attached Figure Description

[0004] To enable a detailed understanding of the features described above in this embodiment, the briefly summarized embodiments can be described in more detail by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments and should not be considered as limiting its scope.

[0005] Figure 1 This is a block diagram of the processing system according to an embodiment;

[0006] Figure 2 This is a block diagram of a processor according to an embodiment;

[0007] Figure 3 This is a block diagram of a graphics processor according to an embodiment;

[0008] Figure 4 This is a block diagram of a graphics processing engine for a graphics processor according to some embodiments;

[0009] Figure 5 This is a block diagram of the hardware logic of a graphics processor core according to some embodiments described herein;

[0010] Figures 6A-6B The diagram illustrates thread execution logic including an array of processing elements employed in a graphics processor core, according to embodiments described herein.

[0011] Figure 7 This is a block diagram illustrating a graphics processor instruction format according to some embodiments;

[0012] Figure 8 This is a block diagram of a graphics processor according to another embodiment;

[0013] Figures 9A-9B The graphics processor command format and command sequence according to some embodiments are shown;

[0014] Figure 10 An exemplary graphical software architecture of a data processing system according to some embodiments is shown;

[0015] Figure 11A This is a block diagram illustrating an IP core development system according to an embodiment;

[0016] Figure 11B A cross-sectional side view of an integrated circuit package assembly according to some embodiments described herein is shown;

[0017] Figure 12 This is a block diagram illustrating an exemplary system-on-a-chip integrated circuit according to an embodiment;

[0018] Figures 13A-13BThis is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein;

[0019] Figures 14A-14B Additional exemplary graphics processor logic according to embodiments described herein is illustrated;

[0020] Figure 15 A machine learning software stack according to an embodiment is shown;

[0021] Figures 16A-16B The layers of an exemplary deep neural network are shown;

[0022] Figure 17 An exemplary recurrent neural network is shown;

[0023] Figure 18 The training and deployment of deep neural networks are illustrated;

[0024] Figure 19 This is a block diagram illustrating distributed learning;

[0025] Figures 20A-20E The communication patterns used during distributed machine learning computation operations performed across multiple computing nodes, according to embodiments described herein, are illustrated.

[0026] Figures 21A-21B The architectural details of the machine learning scaling library provided by the embodiments described herein are shown;

[0027] Figure 22 A multi-node training network according to an embodiment is shown;

[0028] Figure 23 The process of enabling the topology-aware algorithm to perform flexible node grouping according to an embodiment is illustrated;

[0029] Figures 24A-24B A processing system according to an embodiment described herein is shown;

[0030] Figure 25 The process for managing the QoS of communication between and within parallel processor computing nodes according to an embodiment is illustrated;

[0031] Figure 26 An additional multi-chassis computing system according to an embodiment is shown;

[0032] Figure 27 A host interface switch according to an embodiment is shown;

[0033] Figures 28A-28C A system for implementing persistent deep learning communication is shown;

[0034] Figures 29A-29CThe hardware and associated software processes for implementing serverless accelerator pooling for inference, according to embodiments described herein, are illustrated.

[0035] Figure 30A The generation of recovery points for a training or data model according to an embodiment is illustrated;

[0036] Figure 30B A machine learning processing system with multiple redundancies is illustrated according to an embodiment;

[0037] Figure 31 The computational logic associated with an additional algorithm for handling sudden hardware failures on ASDV, according to an embodiment, is illustrated.

[0038] Figure 32 This is a block diagram of a data processing system according to embodiments described herein;

[0039] Figure 33 This is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0040] Figures 34A-34D A parallel processor component according to an embodiment is shown;

[0041] Figures 35A-35B This is a block diagram of a graphics multiprocessor according to an embodiment;

[0042] Figures 36A-36G An exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors is shown;

[0043] Figure 37 A graphics processing pipeline according to an embodiment is shown. Detailed Implementation

[0044] For purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the various embodiments described below. However, it will be apparent to those skilled in the art that embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are illustrated in block diagram form to avoid obscuring the fundamental principles and to provide a more thorough understanding of the embodiments. Although some of the embodiments described below are referenced to graphics processors, the techniques and teachings described herein can be applied to various types of circuits or semiconductor devices, including general-purpose processing devices or graphics processing devices. The references to “an embodiment” or “embodiment” herein indicate that a particular feature, structure, or characteristic described in conjunction with or in association with that embodiment may be included in at least one such embodiment. However, the appearance of the phrase “in an embodiment” in various places throughout this specification does not necessarily refer to the same embodiment.

[0045] In the following description and claims, the terms “coupled” and “connected” and their derivatives may be used. It should be understood that these terms are not intended to be synonyms with each other. “Coupled” is used to indicate that two or more elements cooperate or interact with each other, and they may or may not be in direct physical or electrical contact with each other. “Connected” is used to indicate the establishment of communication between two or more elements coupled to each other.

[0046] In the following description, Figure 1-1 4 provides an overview of exemplary data processing systems and graphics processor logic that includes or relates to various embodiments. Figure 15-3 Section 5 provides specific details of the various embodiments. Some aspects of the following embodiments are described with reference to graphics processing units (GPUs), while others are described with respect to general-purpose processors such as central processing units (CPUs). Similar techniques and teachings can be applied to other types of circuits or semiconductor devices, including but not limited to one or more instances of integrated many-core processors, GPU clusters, or field-programmable gate arrays (FPGAs). In general, these teachings are applicable to any processor or machine that manipulates or processes images (e.g., samples, pixels), vertex data, or geometric data.

[0047] System Overview

[0048] Figure 1 This is a block diagram of a processing system 100 according to an embodiment. In various embodiments, system 100 includes one or more processors 102 and one or more graphics processors 108, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile devices, handheld devices, or embedded devices.

[0049] In one embodiment, system 100 may include or incorporate a server-based gaming platform, a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 100 is a mobile phone, smartphone, tablet computing device, or mobile internet device. Processing system 100 may also include a wearable device (such as a smartwatch, smart glasses, augmented reality, or virtual reality device), coupled to or integrated into the wearable device. In some embodiments, processing system 100 is a television or set-top box device having one or more processors 102 and a graphical interface generated by one or more graphics processors 108.

[0050] In some embodiments, each of the one or more processors 102 includes one or more processor cores 107 for processing instructions that, when executed, perform operations on the system and user software. In some embodiments, each of the one or more processor cores 107 is configured to process a dedicated instruction set 109. In some embodiments, the instruction set 109 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). Multiple processor cores 107 may each process a different instruction set 109, which may include instructions for facilitating emulation of other instruction sets. Processor cores 107 may also include other processing devices, such as digital signal processors (DSPs).

[0051] In some embodiments, processor 102 includes cache memory 104. Depending on the architecture, processor 102 may have a single internal cache or multiple levels of internal caches. In some embodiments, cache memory is shared among components of processor 102. In some embodiments, processor 102 also uses an external cache (e.g., a Level 3 (L3) cache or a Last Level Cache (LLC)) (not shown), which can be shared among processor core 107 using known cache coherence techniques. Additionally, register file 106 is included in processor 102, which may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). Some registers may be general-purpose registers, while others may be dedicated to the design of processor 102.

[0052] In some embodiments, one or more processors 102 are coupled to one or more interface buses 110 for transmitting communication signals, such as address, data, or control signals, between the processors 102 and other components in the system 100. In one embodiment, the interface bus 110 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. However, the processor bus is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In one embodiment, the processor(s) 102 include an integrated memory controller 116 and a platform controller hub (PCH) 130. The memory controller 116 facilitates communication between memory devices and other components of the system 100, while the platform controller hub (PCH) 130 provides connectivity to I / O devices via a local I / O bus.

[0053] Memory device 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with suitable performance for use as processing memory. In one embodiment, memory device 120 may operate as system memory of system 100 for storing data 122 and instructions 121 for use when the one or more processors 102 execute an application or process. Memory controller 116 is also coupled to an optional external graphics processor 112, which may communicate with the one or more graphics processors 108 in processor 102 to perform graphics and media operations. In some embodiments, display device 111 may be connected to processor(s) 102. Display device 111 may be one or more of the following: an internal display device, such as in a mobile electronic device or laptop device; or an external display device attached via a display interface (e.g., a display port, etc.). In one embodiment, display device 111 may be a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) or augmented reality (AR) applications.

[0054] In some embodiments, the platform controller hub 130 enables peripheral devices to connect to the memory device 120 and the processor 102 via a high-speed I / O bus. I / O peripheral devices include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, and a data storage device 124 (e.g., a hard disk drive, flash memory, etc.). The data storage device 124 may be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI Express). The touch sensor 125 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. The firmware interface 128 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). The network controller 134 enables network connectivity to a wired network. In some embodiments, a high-performance network controller (not shown) is coupled to the interface bus 110. In one embodiment, the audio controller 146 is a multi-channel high-definition audio controller. In one embodiment, the system 100 includes an optional legacy I / O controller 140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. The platform controller hub 130 may also be connected to one or more Universal Serial Bus (USB) controllers 142 to connect input devices, such as a keyboard and mouse combination 143, a camera 144, or other USB input devices.

[0055] It will be appreciated that the illustrated system 100 is exemplary and not limiting, as other types of data processing systems configured differently may also be used. For example, instances of the memory controller 116 and platform controller hub 130 may be integrated into a discrete external graphics processor, such as external graphics processor 112. In one embodiment, the platform controller hub 130 and / or memory controller 160 may be external to the one or more processors 102. For example, system 100 may include an external memory controller and a platform controller hub, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset communicating with the processor(s) 102.

[0056] Figure 2 This is a block diagram of an embodiment of processor 200, which has one or more processor cores 202A to 202N, an integrated memory controller 214, and an integrated graphics processor 208. Figure 2 Those elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 200 may include, and include, additional cores 202N, indicated by dashed boxes. Each processor core 202A to 202N includes one or more internal cache units 204A to 204N. In some embodiments, each processor core may also access one or more shared cache units 206.

[0057] Internal cache units 204A to 204N and shared cache unit 206 represent the cache memory hierarchy within processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest-level cache is classified as LLC before external memory. In some embodiments, cache coherence logic maintains coherence between each cache unit 206 and 204A to 204N.

[0058] In some embodiments, the processor 200 may further include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI or PCI Fast buses. The system agent core 210 provides management functions for each processor component. In some embodiments, the system agent core 210 includes one or more integrated memory controllers 214 for managing access to various external memory devices (not shown).

[0059] In some embodiments, one or more of processor cores 202A to 202N include support for simultaneous multithreading. In this embodiment, system agent core 210 includes components for coordinating and operating cores 202A to 202N during multithreaded processing. Additionally, system agent core 210 may also include a power control unit (PCU) including logic and components for regulating the power states of processor cores 202A to 202N and a graphics processor 208.

[0060] In some embodiments, processor 200 further includes a graphics processor 208 for performing graphics processing operations. In some embodiments, graphics processor 208 is coupled to a shared cache unit 206 and a system proxy core 210, the system proxy core including one or more integrated memory controllers 214. In some embodiments, system proxy core 210 further includes a display controller 211 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 211 may also be a separate module coupled to the graphics processor via at least one interconnect, or it may be integrated within graphics processor 208.

[0061] In some embodiments, ring-based interconnect units 212 are used to couple internal components of processor 200. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art, may be used. In some embodiments, graphics processor 208 is coupled to ring interconnect 212 via I / O link 213.

[0062] Exemplary I / O link 213 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and a high-performance embedded memory module 218 (such as an eDRAM module). In some embodiments, each of the processor cores 202A to 202N and the graphics processor 208 uses the embedded memory module 218 as a shared final-level cache.

[0063] In some embodiments, processor cores 202A to 202N are homogeneous cores executing the same instruction set architecture. In another embodiment, processor cores 202A to 202N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 202A to 202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 202A to 202N are homogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled to one or more power cores with lower power consumption. Additionally, processor 200 can be implemented on one or more chips or implemented as a SoC integrated circuit having, among other components, the components shown.

[0064] Figure 3 This is a block diagram of a graphics processing unit 300, which may be a discrete graphics processing unit or a graphics processing unit integrated with multiple processing cores. In some embodiments, the graphics processing unit communicates with memory via a mapped I / O interface to registers on the graphics processing unit and using commands placed in processor memory. In some embodiments, the graphics processing unit 300 includes a memory interface 314 for accessing memory. The memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0065] In some embodiments, the graphics processor 300 further includes a display controller 302 for driving display output data to a display device 320. The display controller 302 includes hardware for one or more overlapping planes of the display and a multi-layer video or user interface element. The display device 320 may be an internal or external display device. In one embodiment, the display device 320 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, the graphics processor 300 includes a video codec engine 306 for encoding, decoding, or converting media codes to, from, or between one or more media encoding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Decoding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Group of Picture Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG)).

[0066] In some embodiments, the graphics processor 300 includes a block image transfer (BLIT) engine 304 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 310. In some embodiments, the GPE 310 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0067] In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering 3D images and scenes using processing functions acting on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 312 includes programmable and fixed functional elements that perform various tasks within elements and / or generated execution threads of the 3D / media subsystem 315. While the 3D pipeline 312 can be used to perform media operations, embodiments of GPE 310 also include a media pipeline 316 specifically for performing media operations such as video post-processing and image enhancement.

[0068] In some embodiments, the media pipeline 316 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterleaving, and video encoding acceleration, in place of or on behalf of the video codec engine 306. In some embodiments, the media pipeline 316 further includes a thread generation unit to generate threads for execution on the 3D / media subsystem 315. The generated threads perform calculations on media operations on one or more graphics execution units included in the 3D / media subsystem 315.

[0069] In some embodiments, the 3D / media subsystem 315 includes logic for executing threads generated by the 3D pipeline 312 and the media pipeline 316. In one embodiment, the pipelines send thread execution requests to the 3D / media subsystem 315, the 3D / media subsystem including thread dispatch logic for arbitrating and dispatching requests to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) for sharing data between threads and for storing output data.

[0070] Graphics processing engine

[0071] Figure 4This is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is... Figure 3 The image shows a version of GPE 310. Figure 4 Those elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. For example, shown Figure 3 The 3D pipeline 312 and media pipeline 316 are included. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example, and in at least one embodiment, a separate media and / or image processor is coupled to the GPE 410.

[0072] In some embodiments, GPE 410 is coupled to or includes command stream converter 403, which provides command streams to 3D pipeline 312 and / or media pipeline 316. In some embodiments, command stream converter 403 is coupled to memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command stream converter 403 receives commands from memory and sends these commands to 3D pipeline 312 and / or media pipeline 316. The commands are instructions obtained from a ring buffer storing instructions for 3D pipeline 312 and media pipeline 316. In one embodiment, the ring buffer may additionally include a batch command buffer storing multiple batches of commands. Commands for 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex data and geometry data for 3D pipeline 312 and / or image data and memory objects for media pipeline 316. The 3D pipeline 312 and the media pipeline 316 process the commands and data by performing operations via logic within their respective pipelines or by dispatching one or more execution threads to the execution graphics core array 414. In one embodiment, the graphics core array 414 includes one or more graphics core blocks (e.g., multiple graphics cores 415A, multiple graphics cores 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources, which includes: general-purpose execution logic and graphics-specific execution logic for performing graphics and computational operations; and fixed-function texture processing logic and / or machine learning and artificial intelligence acceleration logic.

[0073] In various embodiments, the 3D pipeline 312 includes fixed-function logic and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified block of execution resources for use in processing these shader programs. The multipurpose execution logic (e.g., execution units) within the graphics core(s)(s)415A to 414B of the graphics core array 414 includes support for various 3D API shader languages ​​and can execute multiple synchronous execution threads associated with multiple shaders.

[0074] In some embodiments, the graphics core array 414 further includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit also includes general-purpose logic programmable to perform parallel general-purpose computing operations. The general-purpose logic can be... Figure 1 (Multiple) processor cores 107 or Figure 2 The general logic within the cores 202A to 202N performs processing operations in parallel or in combination.

[0075] Output data generated by threads executing on the graphics core array 414 can be output to memory in a uniform return buffer (URB) 418. URB 418 can store data from multiple threads. In some embodiments, URB 418 can be used to send data between different threads executing on the graphics core array 414. In some embodiments, URB 418 can also be used for synchronization between threads on the graphics core array and fixed-function logic within shared-function logic 420.

[0076] In some embodiments, the graphics core array 414 is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of the GPE 410. In one embodiment, the execution resources are dynamically scalable, allowing them to be enabled or disabled as needed.

[0077] The graphics core array 414 is coupled to shared function logic 420, which includes multiple resources shared among the graphics cores in the graphics core array. The shared functions within the shared function logic 420 are hardware logic units that provide dedicated supplementary functions to the graphics core array 414. In various embodiments, the shared function logic 420 includes, but is not limited to, sampler 421, math 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more caches 425 within the shared function logic 420.

[0078] Shared functionality is implemented where the demand for a given dedicated function is insufficient to be contained within the graphics core array 414. Instead, a single instance of the dedicated function is implemented as a separate entity within shared function logic 420 and shared among execution resources within the graphics core array 414. The exact set of functions shared and included within the graphics core array 414 varies across embodiments. In some embodiments, dedicated shared functions widely used by the graphics core array 414 within shared function logic 420 may be included within shared function logic 416 within the graphics core array 414. In various embodiments, shared function logic 416 within the graphics core array 414 may include some or all of the logic within shared function logic 420. In one embodiment, all logic elements within shared function logic 420 may be repeated within shared function logic 416 of the graphics core array 414. In one embodiment, shared function logic 420 is executed to support shared function logic 416 within the graphics core array 414.

[0079] Figure 5 This is a block diagram of the hardware logic of a graphics processor core 500 according to some embodiments described herein. Figure 5 Elements having the same reference numerals (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. In some embodiments, the illustrated graphics processor core 500 is included Figure 4 Within the graphics core array 414. A graphics processor core 500 (sometimes referred to as a core chip) can be one or more graphics cores within a modular graphics processor. Graphics processor core 500 is an exemplary graphics core chip, and a graphics processor as described herein may include multiple graphics core chips based on target power and performance envelopes. Each graphics core 500 may include a fixed-function block 530 coupled to multiple sub-cores 501A-501F (also referred to as sub-chips), these sub-cores comprising modular blocks of general-purpose and fixed-function logic. It will be understood that, as described herein, references to “logic” may include, for example, software, hardware, firmware, or any combination thereof configured to perform the described operations.

[0080] In some embodiments, the fixed-function block 530 includes a geometry / fixed-function pipeline 536, which may be shared by all sub-cores of the graphics processor 500, for example, in low-performance and / or low-power graphics processor implementations. In various embodiments, the geometry / fixed-function pipeline 536 includes a 3D fixed-function pipeline (e.g., as in...). Figure 3 and Figure 4 The 3D pipeline (312), video front-end unit, thread deriver and thread dispatcher, and management such as Figure 4The unified return buffer manager includes unified return buffers such as the unified return buffer 418.

[0081] In one embodiment, fixed function block 530 further includes a graphics SoC interface 537, a graphics microcontroller 538, and a media pipeline 539. The graphics SoC interface 537 provides an interface between the graphics core 500 and other processor cores within the system-on-a-chip integrated circuit. The graphics microcontroller 538 is a programmable subprocessor configurable to manage various functions of the graphics processor 500, including thread dispatch, scheduling, and pre-emption. The media pipeline 539 (e.g., Figure 3 and Figure 4 The media pipeline 316 includes logic for facilitating the decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. The media pipeline 539 performs media operations via requests for computation or sampling logic within subcores 501 to 501F.

[0082] In one embodiment, SoC interface 537 enables graphics core 500 to communicate with a general-purpose application processor core (e.g., CPU) and / or other components within the SoC, including memory-level architecture elements such as shared final-level cache memory, system RAM, and / or embedded on-chip or package-based DRAM. SoC interface 537 may also enable communication with fixed-function devices within the SoC, such as camera imaging pipelines, and enable the use and / or implementation of global memory atoms that can be shared between graphics core 500 and the CPU within the SoC. SoC interface 537 may also implement power management control for graphics core 500 and enable interfacing between the clock domain of graphics core 500 and other clock domains within the SoC. In one embodiment, SoC interface 537 enables the receipt of command buffers from a command stream converter and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. When a media operation is about to be executed, these commands and instructions can be dispatched to the media pipeline 539, or when a graphics processing operation is about to be executed, these commands and instructions can be dispatched to the geometry and fixed-function pipelines (e.g., geometry and fixed-function pipeline 536, geometry and fixed-function pipeline 514).

[0083] The graphics microcontroller 538 can be configured to perform various scheduling and management tasks for the graphics core 500. In one embodiment, the graphics microcontroller 538 can perform graphics and / or computational workload scheduling for the various parallel graphics engines within the execution unit (EU) arrays 502A to 502F and 504A to 504F of the sub-cores 501A to 501F. In this scheduling model, host software executing on the CPU core of the SoC including the graphics core 500 can submit workloads via one of a plurality of graphics processor doorbells, which invokes scheduling operations for the appropriate graphics engine. The scheduling operations include: determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In one embodiment, the graphics microcontroller 538 may also facilitate a low-power or idle state of the graphics core 500, thereby providing the graphics core 500 with the ability to save and restore registers within the graphics core 500 across low-power state transitions, independent of the operating system and / or the graphics driver software on the system.

[0084] The graphics core 500 may have more or fewer sub-cores 501A to 501F shown, up to N modular sub-cores. For each group of N sub-cores, the graphics core 500 may also include shared function logic 510, shared memory and / or cache memory 512, geometry / fixed function pipeline 514, and additional fixed function logic 516 for accelerating various graphics and computational processing operations. Figure 4 The shared functional logic 420 is associated with logic units (e.g., sampler logic, mathematical logic, and / or inter-thread communication logic). Shared memory and / or cache memory 512 can be the final-level cache for the set of N sub-cores 501A to 501F within the graphics core 500, and can also act as shared memory accessible by multiple sub-cores. A geometry / fixed-function pipeline 514 can be included within the fixed-function block 530 instead of the geometry / fixed-function pipeline 536, and can include the same or similar logic units.

[0085] In one embodiment, the graphics core 500 includes additional fixed-function logic 516, which may include various fixed-function acceleration logics for use by the graphics core 500. In one embodiment, the additional fixed-function logic 516 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are two geometry pipelines: a full geometry pipeline within geometry / fixed-function pipelines 516 and 536; and a picking pipeline, which is an additional geometry pipeline that may be included within the additional fixed-function logic 516. In one embodiment, the picking pipeline is a simplified version of the full geometry pipeline. The full pipeline and the picking pipeline can execute different instances of the same application, each with a separate context. Position-only shading can hide longer picking runs of discarded triangles, thereby enabling earlier shading completion in some instances. For example, and in one embodiment, the picking pipeline logic within the attached fixed-function logic 516 can execute the position shader in parallel with the main application and typically generates key results faster than a full pipeline, because a full pipeline only extracts and shades the position attributes of vertices without performing rasterization and rendering of pixels to the frame buffer. The picking pipeline can use the generated key results to compute visibility information for all triangles, regardless of whether those triangles were picked. A full pipeline (which may be referred to as the replay pipeline in this example) can consume visibility information to skip picked triangles and shade only the visible triangles that are ultimately passed to the rasterization stage.

[0086] In one embodiment, the additional fixed-function logic 516 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic, for implementations including machine learning training or inference.

[0087] Each graphics subcore 501A to 501F includes a set of execution resources that can be used to perform graphics operations, media operations, and computational operations in response to requests from the graphics pipeline, media pipeline, or shader program. The graphics subcores 501A to 501F include: multiple EU arrays 502A to 502F, 504A to 504F; thread dispatch and inter-thread communication (TD / IC) logic 503A to 503F; 3D (e.g., texture) samplers 505A to 505F; media samplers 506A to 506F; shader processors 507A to 507F; and shared local memory (SLM) 508A to 508F. EU arrays 502A to 502F and 504A to 504F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations to serve graphics operations, media operations, or computational operations, including graphics programs, media programs, or computational shader programs. TD / IC logic 503A to 503F performs local thread dispatch and thread control operations for execution units within the subcore and facilitates communication between threads executing on the execution units of the subcore. 3D samplers 505A to 505F can read textures or other 3D graphics-related data into memory. The 3D samplers can read texture data in different ways based on the configured sample state and the texture format associated with a given texture. Media samplers 506A to 506F can perform similar read operations based on the type and format associated with media data. In one embodiment, each graphics subcore 501A to 501F may alternately include unified 3D and media samplers. Threads executing on execution units within each of subcores 501A to 501F can utilize shared local memory 508A to 508F within each subcore, so that threads executing within a thread group can use a common on-chip memory pool for execution.

[0088] Execution unit

[0089] Figures 6A to 6B Thread execution logic 600, including an array of processing elements employed in a graphics processor core, is illustrated according to embodiments described herein. Figures 6A to 6B Those elements having the same reference numerals (or names) as those in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Figure 6A An overview of thread execution logic 600 is shown, which may include what is shown as having Figure 5 Variants of the hardware logic for each of the 501A to 501F sub-cores. Figure 6B Exemplary internal details of the execution unit are shown.

[0090] like Figure 6A As shown, in some embodiments, thread execution logic 600 includes a shader processor 602, a thread dispatcher 604, an instruction cache 606, a scalable execution unit array including multiple execution units 608A to 608N, a sampler 610, a data cache 612, and a data port 614. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 608A, 608B, 608C, 608D, up to 608N-1 and 608N) based on workload computational needs. In one embodiment, the included components are interconnected via an interconnect structure linking to each component. In some embodiments, thread execution logic 600 includes one or more connections to memory (such as system memory or cache memory) via one or more of the instruction cache 606, data port 614, sampler 610, and execution unit arrays 608A to 608N. In some embodiments, each execution unit (e.g., 608A) is an independent programmable general-purpose computing unit capable of executing multiple synchronous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 608A to 608N is scalable to include any number of individual execution units.

[0091] In some embodiments, execution units 608A to 608N are primarily used to execute shader programs. Shader processor 602 can handle various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 604. In one embodiment, the thread dispatcher includes logic for arbitrating thread initiation requests from the graphics and media pipeline and instantiating the requested threads on one or more execution units 608A to 608N. For example, a geometry pipeline can dispatch vertex processing, tessellation, or geometry processing threads to thread execution logic for processing. In some embodiments, thread dispatcher 604 can also handle runtime thread generation requests from executing shader programs.

[0092] In some embodiments, execution units 608A to 608N support instruction sets that include native support for many standard 3D graphics shader instructions, enabling minimal conversion to execute shader programs from graphics libraries (e.g., Direct3D and OpenGL). These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., computation and media shaders). Each of the execution units 608A to 608N is capable of executing multiple-issue single-instruction multiple-data (SIMD), and multithreaded operation enables an efficient execution environment in the face of high-latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. For pipelines with integer, single-precision floating-point and double-precision floating-point operations, SIMD branching capabilities, logical operations, transcendental operations, and other hybrid operations, execution is multiple-issue per clock cycle. While waiting for data from memory or a shared function, dependency logic within execution units 608A to 608N causes the waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during the latency associated with vertex shader operations, the execution unit may perform operations on a pixel shader, a fragment shader, or another type of shader program that includes different vertex shaders.

[0093] Each execution unit in the execution units 608A to 608N operates on an array of data elements. The number of data elements is the "execution size," or the number of instruction channels. An execution channel is a logical unit that performs data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 608A to 608N support both integer and floating-point data types.

[0094] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process these elements based on their data size. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in registers, and the execution unit operates on the vector as four individual 64-bit compressed data elements (four times the word length (QW) size), eight individual 32-bit compressed data elements (double the word length (DW) size), sixteen individual 16-bit compressed data elements (word length (W) size), or thirty-two individual 8-bit data elements (byte (B) size). However, different vector widths and register sizes are possible.

[0095] In one embodiment, one or more execution units can be combined into fused execution units 609A to 609N, which have common thread control logic (607A to 607N) for fused EUs. Multiple EUs can be fused into a group of EUs. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU group can vary depending on the embodiment. Additionally, different SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32, can be executed for each EU. Each fused graphics execution unit 609A to 609N includes at least two execution units. For example, fused execution unit 609A includes a first EU 608A, a second EU 608B, and common thread control logic 607A for the first EU 608A and the second EU 608B. Thread control logic 607A controls the threads executing on the fused graphics execution unit 609A, thereby allowing each EU within the fused execution units 609A to 609N to execute using a common instruction pointer register.

[0096] One or more internal instruction caches (e.g., 606) are included in the thread execution logic 600 to cache thread instructions of the execution unit. In some embodiments, one or more data caches (e.g., 612) are included for caching thread data during thread execution. In some embodiments, sampler 610 is included for providing texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 610 includes dedicated texture or media sampling functions to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0097] During execution, the graphics and media pipeline sends thread initiation requests to thread execution logic 600 via thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic within shader processor 602 (e.g., pixel shader logic, fragment shader logic, etc.) is invoked to further compute output information and write the results to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In some embodiments, the pixel shader or fragment shader computes values ​​for vertex attributes interpolated across the rasterized object. In some embodiments, the pixel processor logic within shader processor 602 then executes a pixel or fragment shader program provided by an application programming interface (API). To execute the shader program, shader processor 602 dispatches threads to execution units (e.g., 608A) via thread dispatcher 604. In some embodiments, shader processor 602 uses texture sampling logic in sampler 610 to access texture data in a texture map stored in memory. Arithmetic operations are performed on the texture data and the input geometry data to calculate the pixel color data of each geometric fragment, or to discard one or more pixels without further processing.

[0098] In some embodiments, data port 614 provides a memory access mechanism for thread execution logic 600 to output processed data to memory for further processing on the graphics processor output pipeline. In some embodiments, data port 614 includes or is coupled to one or more cache memories (e.g., data cache 612) to cache data via the data port for memory access.

[0099] like Figure 6B As shown, the graphics execution unit 608 may include an instruction fetch unit 637, a general-purpose register file array (GRF) 624, an architecture register file array (ARF) 626, a thread arbiter 622, a send unit 630, a branch unit 632, a set of SIMD floating-point units (FPUs) 634, and a set of dedicated integer SIMD ALUs 635 in one embodiment. The GRF 624 and ARF 626 include the set of general-purpose register files and architecture register files associated with each synchronized hardware thread that may be active in the graphics execution unit 608. In one embodiment, per-thread architecture state is maintained in the ARF 626, while data used during thread execution is stored in the GRF 624. The execution state of each thread, including the instruction pointer of each thread, may be maintained in thread-specific registers in the ARF 626.

[0100] In one embodiment, the graphics execution unit 608 has an architecture that is a combination of synchronous multithreading (SMT) and fine-grained interleaved multithreading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on the target number of synchronous threads and the target number of registers per execution unit, in which execution unit resources are partitioned across logic used to execute multiple synchronous threads.

[0101] In one embodiment, the graphics execution unit 608 can issue multiple instructions, which can each be different instructions. The thread arbiter 622 of the graphics execution unit thread 608 can dispatch instructions to one of the following for execution: sending unit 630, branching unit 642, or (multiple) SIMD FPUs 634. Each execution thread can access 128 general-purpose registers within the GRF 624, where each register can store 32 bytes accessible as a SIMD 8-element vector with 32-bit data elements. In one embodiment, each execution unit thread accesses 4 kilobytes within the GRF 624, but the embodiment is not limited to this, and more or fewer register resources may be provided in other embodiments. In one embodiment, up to seven threads can execute synchronously, but the number of threads per execution unit may also vary depending on the embodiment. In an embodiment where seven threads can access 4 kilobytes, the GRF 624 can store a total of 28 kilobytes. Flexible addressing modes allow multiple registers to be addressed simultaneously, thereby efficiently constructing wider registers or representing straddle rectangular block data structures.

[0102] In one embodiment, memory operations, sampler operations, and other long-latency system communications are dispatched via a "send" instruction executed by message sending unit 630. In one embodiment, branch instructions are dispatched to dedicated branch unit 632 to facilitate SIMD divergence and eventual convergence.

[0103] In one embodiment, the graphics execution unit 608 includes one or more SIMD floating-point units (FPUs) 634 for performing floating-point operations. In one embodiment, the FPU(s) 634 also support integer computation. In one embodiment, the FPU(s) 634 can perform up to M 32-bit floating-point (or integer) operations in SIMD, or up to 2M 16-bit integer or 16-bit floating-point operations in SIMD. In one embodiment, at least one of the FPUs provides extended mathematical capabilities that support high throughput beyond mathematical functions and double-precision 64-bit floating-point. In some embodiments, a set of 8-bit integer SIMD ALUs 635 also represents and can be specifically optimized to perform operations associated with machine learning computations.

[0104] In one embodiment, an array of multiple instances of the graphics execution unit 608 can be instantiated when graphics subcores are grouped (e.g., sub-slices). For scalability, the product architecture can select the exact number of execution units per subcore group. In one embodiment, the execution unit 608 can execute instructions across multiple execution channels. In a further embodiment, each thread executed on the graphics execution unit 608 is executed on a different channel.

[0105] Figure 7 This is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having multiple instruction formats. Solid lines represent components typically included in the execution unit instructions, while dashed lines represent optional components or components included only in subsets of the instructions. In some embodiments, the instruction format 700 described and illustrated are macro instructions, as they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction is processed).

[0106] In some embodiments, the graphics processor execution unit natively supports instructions using a 128-bit instruction format 710. A 64-bit compact instruction format 730 can be used for some instructions based on the selected instruction, multiple instruction options, and the number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted to the 64-bit format 730. The native instructions available in the 64-bit format 730 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in an index field 713. The execution unit hardware references a set of compression tables based on the index values ​​and uses the output of the compression tables to reconstruct the native instructions using the 128-bit instruction format 710.

[0107] For each format, the instruction opcode 712 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a synchronous add operation across each color channel, which represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 714 enables control over certain execution options, such as channel selection (e.g., prediction) and data channel ordering (e.g., blending). For instructions using the 128-bit instruction format 710, the execution size field 716 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 716 is not available for the 64-bit compact instruction format 730.

[0108] Some execution unit instructions have up to three operands, including two source operands (src0 720, src1 722) and a destination 718. In some embodiments, the execution unit supports dual-destination instructions, where one of these destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 724), where the instruction opcode 712 determines the number of source operands. The last source operand of the instruction may be an on-the-fly (e.g., hard-coded) value passed using the instruction.

[0109] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726, which specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

[0110] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, in a first mode, the instruction can use byte-aligned addressing for both source and destination operands, and in a second mode, the instruction can use 16-byte aligned addressing for both source and destination operands.

[0111] In one embodiment, the address mode portion of the access / address mode field 726 determines whether the instruction uses direct or indirect addressing. When using direct register addressing mode, bits in the instruction directly provide the register addresses of one or more operands. When using indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate number field in the instruction.

[0112] In some embodiments, instructions are grouped based on the 712-bit opcode field to simplify opcode decoding 740. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely exemplary. In some embodiments, the move and logic opcode group 742 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 742 shares five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb, and logic instructions are in the form of 0001xxxxb. The flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The promiscuous instruction group 746 includes a mixture of instructions, including synchronous instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). Parallel math instruction set 748 includes component-based arithmetic instructions (e.g., add, multiply) in the form 0100xxxxb (e.g., 0x40). Parallel math set 748 performs arithmetic operations in parallel across data channels. Vector math set 750 includes arithmetic instructions (e.g., dp4) in the form 0101xxxxb (e.g., 0x50). Vector math set performs arithmetic operations on vector operands, such as dot product.

[0113] Graphics Pipeline

[0114] Figure 8 This is a block diagram of another embodiment of the graphics processor 800. Figure 8 Those elements having the same reference numerals (or names) as those in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0115] In some embodiments, the graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a rendering output pipeline 870. In some embodiments, the graphics processor 800 is a graphics processor within a multi-core processing system including one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 800 via a ring interconnect 802. In some embodiments, the ring interconnect 802 couples the graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 802 are interpreted by a command stream converter 803, which supplies instructions to individual components of the geometry pipeline 820 or the media pipeline 830.

[0116] In some embodiments, a command stream converter 803 directs the operation of a vertex acquirer 805, which reads vertex data from memory and executes vertex processing commands provided by the command stream converter 803. In some embodiments, the vertex acquirer 805 provides vertex data to a vertex shader 807, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex acquirer 805 and the vertex shader 807 execute vertex processing instructions by dispatching execution threads to execution units 852A to 852B via a thread dispatcher 831.

[0117] In some embodiments, execution units 852A to 852B are vector processor arrays having an instruction set for performing graphics and media operations. In some embodiments, execution units 852A to 852B have an attached L1 cache 851, which is dedicated to each array or shared between arrays. The cache may be configured as a data cache, an instruction cache, or a single cache partitioned to contain data and instructions in different partitions.

[0118] In some embodiments, the geometry pipeline 820 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable shell shader 811 configures the tessellation operation. A programmable domain shader 817 provides back-end evaluation of the tessellation output. A tessellation unit 813 operates in the direction of the shell shader 811 and includes dedicated logic for generating a detailed set of geometric objects based on a rough geometry model that is provided as input to the geometry pipeline 820. In some embodiments, if tessellation is not used, the tessellation components (e.g., shell shader 811, tessellation unit 813, domain shader 817) can be bypassed.

[0119] In some embodiments, the complete geometry object may be processed by the geometry shader 819 via one or more threads dispatched to the execution units 852A to 852B, or it may proceed directly to the clipper 829. In some embodiments, the geometry shader operates on the entire geometry object (rather than vertices or vertex patches such as those in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 819 receives input from the vertex shader 807. In some embodiments, the geometry shader 819 may be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0120] Prior to rasterization, clipper 829 can process vertex data. Clipper 829 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader capabilities. In some embodiments, the rasterizer and depth testing unit 873 in the rendering output pipeline 870 dispatch pixel shaders to convert geometry objects into per-pixel representations. In some embodiments, pixel shader logic is included in thread execution logic 850. In some embodiments, the application can bypass the rasterizer and depth testing unit 873 and access the unrasterized vertex data via outgoing unit 823.

[0121] The graphics processor 800 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be transferred among the main components of the graphics processor. In some embodiments, execution units 852A to 852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) are interconnected via data port 856 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, sampler 854, caches 851, 858, and execution units 852A to 852B each have a separate memory access path. In one embodiment, texture cache 858 may also be configured as a sampler cache.

[0122] In some embodiments, the rendering output pipeline 870 includes a rasterizer and a depth testing unit 873 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / mask unit for performing fixed-function triangle and line rasterization. Associated rendering cache 878 and depth cache 879 are also available in some embodiments. Pixel manipulation unit 877 performs pixel-based operations on the data; however, in some instances, pixel operations associated with 2D operations (e.g., using mixed bit-block image passing) are performed by the 2D engine 841, or alternatively by the display controller 843 using an overlay display plane at display time. In some embodiments, a shared L3 cache 875 is available for all graphics components, allowing data to be shared without using main system memory.

[0123] In some embodiments, the graphics processor media pipeline 830 includes a media engine 837 and a video front-end 834. In some embodiments, the video front-end 834 receives pipeline commands from a command stream converter 803. In some embodiments, the media pipeline 830 includes a separate command stream converter. In some embodiments, the video front-end 834 processes media commands before sending them to the media engine 837. In some embodiments, the media engine 837 includes a thread generation function for generating threads for dispatch to thread execution logic 850 via a thread dispatcher 831.

[0124] In some embodiments, the graphics processor 800 includes a display engine 840. In some embodiments, the display engine 840 is external to the processor 800 and coupled to the graphics processor via a ring interconnect 802, or some other interconnect bus or mechanism. In some embodiments, the display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, the display engine 840 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 843 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0125] In some embodiments, the geometry pipeline 820 and media pipeline 830 may be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, the graphics processor's driver software translates API schedules specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for all Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and computing APIs from the Khronos Group. In some embodiments, support may also be provided for Microsoft's Direct3D library. In some embodiments, combinations of these libraries may be supported. Support may also be provided for the open-source computer vision library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a pipeline mapping from future APIs to the graphics processor's pipeline can be made.

[0126] Graphical Pipeline Programming

[0127] Figure 9A This is a block diagram illustrating a graphics processor command format 900 according to some embodiments. Figure 9B This is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment. Figure 9ASolid lines in the diagram represent components that are typically included in the drawing command, while dashed lines represent components that are optional or included only in a subset of the drawing command. Figure 9A An exemplary graphics processor command format 900 includes data fields for identifying the client 902, a command operation code (opcode) 904, and data 906 for the command. Some commands also include a sub-opcode 905 and a command size 908.

[0128] In some embodiments, client 902 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and route command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads opcode 904 and sub-opcode 905 (if present) to determine the operation to be performed. The client unit uses information within data field 906 to execute the command. For some commands, an explicit command size 908 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands in the command based on the command opcode. In some embodiments, commands are aligned via multiples of double word length.

[0129] Figure 9B The flowchart illustrates an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system characterized by an embodiment of a graphics processor uses a version of the illustrated command sequence to initiate, execute, and terminate a set of graphics operations. Sample command sequences are shown and described for illustrative purposes only, and embodiments are not limited to these specific commands or this command sequence. Moreover, the commands may be issued as a batch of commands in a command sequence, such that the graphics processor will process the command sequence in at least partially simultaneous manner.

[0130] In some embodiments, the graphics processor command sequence 910 may begin with a pipeline dump clearing command 912 to cause any active graphics pipeline to complete its current pending commands. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate simultaneously. Pipeline dump clearing is performed to cause the active graphics pipeline to complete any pending commands. In response to pipeline dump clearing, the command parser for the graphics processor will stop command processing until the active rendering engine completes its pending operations and invalidates the associated read cache. Optionally, any data marked as 'dirty' in the render cache may be dumped and cleared into memory. In some embodiments, pipeline dump clearing command 912 may be used for pipeline synchronization or before placing the graphics processor into a low-power state.

[0131] In some embodiments, a pipeline selection command 913 is used when a sequence of commands requires the graphics processor to explicitly switch between pipelines. In some embodiments, only one pipeline selection command 913 is required in an execution context before a pipeline command is issued, unless the context requires issuing commands for two pipelines. In some embodiments, a pipeline dump clearing command 912 is required exactly before the pipeline switch via pipeline selection command 913.

[0132] In some embodiments, pipeline control command 914 configures a graphics pipeline for operation and programs the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control command 914 configures the pipeline state of an active pipeline. In one embodiment, pipeline control command 914 is used for pipeline synchronization and for clearing data from one or more cache memories within an active pipeline before processing a batch of commands.

[0133] In some embodiments, the return buffer state command 916 is used to configure a set of return buffers for corresponding pipelined write data. Some pipelined operations require allocating, selecting, or configuring one or more return buffers, in which intermediate data is written during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers for a set of pipelined operations.

[0134] The remaining commands in the command sequence vary based on the active pipeline used for the operation. Based on pipeline determination 920, the command sequence is tailored for either the 3D pipeline 922 starting at 3D pipeline state 930, or the media pipeline 924 starting at media pipeline state 940.

[0135] Commands for configuring 3D pipeline states 930 include 3D state setting commands for vertex buffer states, vertex element states, constant color states, depth buffer states, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 930 commands can also selectively disable or bypass specific pipeline components (if those components will not be used).

[0136] In some embodiments, the 3D primitive 932 command is used to submit 3D primitives to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 932 command are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 932 command data to generate multiple vertex data structures. These vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive 932 command is used to perform vertex operations on the 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 922 dispatches shader execution threads to the graphics processor execution unit.

[0137] In some embodiments, the 3D pipeline 922 is triggered by executing command 934 or an event. In some embodiments, register writing triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, pipeline synchronization commands are used to trigger command execution so that the command sequence is cleared via a graphics pipeline dump. The 3D pipeline performs geometry processing on 3D primitives. Once the operation is complete, the resulting geometry is rasterized, and the pixel engine shades the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for these operations.

[0138] In some embodiments, when performing media operations, a sequence of graphics processor commands 910 follows the media pipeline 924 path. Generally, the specific purpose and manner of programming the media pipeline 924 depends on the media or computational operation to be performed. During media decoding, dedicated media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and media decoding can be performed wholly or partially using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using computation shader programs that are not explicitly associated with rendering graphics primitives.

[0139] In some embodiments, the media pipeline 924 is configured in a manner similar to that of the 3D pipeline 922. A set of commands for configuring media pipeline states 940 is dispatched or placed in a command queue before the media object commands 942. In some embodiments, the commands 940 for media pipeline states include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the commands 940 for media pipeline states also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0140] In some embodiments, media object command 942 supplies pointers to a media object for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 942. Once the pipeline states are configured and media object command 942 is queued, media pipeline 924 is triggered via execution command 944 or an equivalent execution event (e.g., register write). The output from media pipeline 924 can then be post-processed by operations provided by 3D pipeline 922 or media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0141] Graphical software architecture

[0142] Figure 10 An exemplary graphics software architecture of a data processing system 1000 according to some embodiments is illustrated. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, the processor 1030 includes a graphics processor 1032 and one or more general-purpose processor cores 1034. The graphics application 1010 and the operating system 1020 each execute in the system memory 1050 of the data processing system.

[0143] In some embodiments, the 3D graphics application 1010 includes one or more shader programs, which include shader instructions 1012. The shader language instructions may employ a high-level shader language, such as High-Level Shading Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 1014, which employ a machine language suitable for execution by a general-purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

[0144] In some embodiments, the operating system 1020 is from Microsoft Corporation. The operating system 1020 may be a dedicated UNIX-like operating system or an open-source UNIX-like operating system using a variant of the Linux kernel. The operating system 1020 may support graphics APIs 1022, such as the Direct3D API, OpenGL API, or Vulkan API. When the Direct3D API is in use, the operating system 1020 uses a front-end shader compiler 1024 to compile any shader instructions 1012 in HLSL into a lower-level shader language. This compilation may be just-in-time (JIT) compilation or pre-compilation of the application-executable shaders. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate form, such as a version of the standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0145] In some embodiments, the user-mode graphics driver 1026 includes a back-end shader compiler 1027 for translating shader instructions 1012 into a hardware-specific representation. When using the OpenGL API, shader instructions 1012 in the GLSL high-level language are passed to the user-mode graphics driver 1026 for compilation. In some embodiments, the user-mode graphics driver 1026 uses operating system kernel-mode functionality 1028 to communicate with the kernel-mode graphics driver 1029. In some embodiments, the kernel-mode graphics driver 1029 communicates with the graphics processor 1032 to dispatch commands and instructions.

[0146] IP core implementation

[0147] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logic within a processor. When read by a machine, these instructions can cause the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as “IP cores”) are reusable units of logic for an integrated circuit, which can be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model can be supplied to various consumers or manufacturing facilities that load the hardware model onto manufacturing machines that manufacture integrated circuits. Integrated circuits can be manufactured such that the circuits perform the operations described in association with any of the embodiments described herein.

[0148] Figure 11A This is a block diagram illustrating an IP core development system 1100 that can be used to manufacture integrated circuits to perform operations, according to an embodiment. The IP core development system 1100 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SOC integrated circuits). Design facility 1130 can generate software simulations 1110 of the IP core design using a high-level programming language (e.g., C / C++). Software simulation 1110 can be used to design, test, and verify the behavior of the IP core using simulation model 1112. Simulation model 1112 can include functional, behavioral, and / or timing simulations. Register transfer level (RTL) designs 1115 can then be created or synthesized from simulation model 1112. RTL design 1115 is an abstraction of the behavior of an integrated circuit (including associated logic performed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to RTL design 1115, lower-level designs at logic or transistor levels can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0149] The RTL design 1115 or an equivalent can be further synthesized into a hardware model 1120 by the design facility. This hardware model may employ a Hardware Description Language (HDL) or some other representation of the physical design data. The HDL can be further simulated or tested to validate the IP core design. The IP core design can be stored in non-volatile memory 1140 (e.g., hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 1165. Alternatively, the IP core design can be transmitted (e.g., via the Internet) through a wired connection 1150 or a wireless connection 1160. The manufacturing facility 1165 can then fabricate an integrated circuit at least partially based on the IP core design. The fabricated integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0150] Figure 11BA cross-sectional side view of an integrated circuit package assembly 1170 according to some embodiments described herein is shown. The integrated circuit package assembly 1170 illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly 1170 includes a plurality of hardware logic units 1172, 1174 connected to a substrate 1180. The logic units 1172, 1174 may be implemented at least partially in configurable logic or fixed-function logic hardware and may include one or more portions of a processor core(s), a graphics processor(s), or any other accelerator device described herein. Each logic unit 1172, 1174 may be implemented within a semiconductor die and coupled to the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic units 1172, 1174 and the substrate 1180 and may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, interconnect structure 1173 may be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of logic 1172, 1174. In some embodiments, substrate 1180 is an epoxy-based laminated substrate. In other embodiments, package substrate 1180 may include other suitable types of substrates. Package assembly 1170 may be connected to other electrical devices via package interconnect 1183. Package interconnect 1183 may be coupled to the surface of substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0151] In some embodiments, logic cells 1172, 1174 are electrically coupled to bridge 1182, which is configured to route electrical signals between logic cells 1172, 1174. Bridge 1182 may be a dense interconnect structure that provides routing for electrical signals. Bridge 1182 may include a bridge substrate made of glass or a suitable semiconductor material. Circuitry features may be formed on the bridge substrate to provide chip-to-chip connections between logic cells 1172, 1174.

[0152] Although two logic units 1172 and 1174 and a bridge 1182 are shown, the embodiments described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, since bridge 1182 can be excluded when logic is included on a single die. Alternatively, multiple dies or logic units may be connected by one or more bridges. Furthermore, multiple logic units, dies, and bridges may be connected together in other possible configurations, including a three-dimensional configuration.

[0153] Exemplary System-on-Chip Integrated Circuit

[0154] Figures 12 to 1 Section 4 illustrates exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to those shown, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0155] Figure 12 This is a block diagram illustrating an exemplary system-on-a-chip integrated circuit 1200 that can be fabricated using one or more IP cores according to an embodiment. The exemplary integrated circuit 1200 includes one or more application processors 1205 (e.g., CPU), at least one graphics processor 1210, and may additionally include an image processor 1215 and / or a video processor 1220, any of which can be modular IP cores from the same or multiple different design facilities. The integrated circuit 1200 includes peripheral or bus logic, including a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I / O controller 1220. 2 S / I 2 C controller 1240. Additionally, the integrated circuit may include a display device 1245 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1250 and a Mobile Industry Processor Interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 1265 to access SDRAM or SRAM memory devices. Furthermore, some integrated circuits also include an embedded security engine 1270.

[0156] Figures 13A to 13B This is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 13A An exemplary graphics processor 1310, which can be fabricated using one or more IP cores according to an embodiment, is shown. Figure 13B An additional exemplary graphics processor 1340 of a system-on-a-chip integrated circuit, which can be fabricated using one or more IP cores according to an embodiment, is shown. Figure 13A The graphics processor 1310 is an example of a low-power graphics processor core. Figure 13B The graphics processor 1340 is an example of a higher-performance graphics processor core. Each of the graphics processors 1310 and 1340 can be... Figure 12 A variant of the 1210 graphics processor.

[0157] like Figure 13AAs shown, the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A to 1315N (e.g., 1315A, 1315B, 1315C, 1315D, up to 1315N-1 and 1315N). The graphics processor 1310 can execute different shader programs via separate logic, such that the vertex processor 1305 is optimized to perform vertex shader program operations, while the one or more fragment processors 1315A to 1315N perform fragment (e.g., pixel) shading operations for use in fragment or pixel shader programs. The vertex processor 1305 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processors (multiple) 1315A to 1315N use the primitive and vertex data generated by the vertex processor 1305 to produce frame buffers displayed on a display device. In one embodiment, fragment processors (multiple) 1315A to 1315N are optimized to execute fragment shader programs provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0158] Additionally, the graphics processor 1310 includes one or more memory management units (MMUs) 1320A to 1320B, one or more caches 1325A to 1325B, and one or more circuit interconnects 1330A to 1330B. The one or more MMUs 1320A to 1320B provide virtual-to-physical address mappings for the graphics processor 1310, including vertex processors 1305 and / or (multiple) fragment processors 1315A to 1315N. Besides vertex or image / texture data stored in the one or more caches 1325A to 1325B, the virtual-to-physical address mappings may also reference vertex or image / texture data stored in memory. In one embodiment, the one or more MMUs 1320A to 1320B may interact with system interconnects including those within the same memory. Figure 12 The synchronization of one or more MMUs, including one or more MMUs associated with the one or more application processors 1205, image processor 1215, and / or video processor 1220, enables each processor 1205 to 1220 to participate in a shared or unified virtual memory system. According to an embodiment, the one or more circuit interconnects 1330A to 1330B enable the graphics processor 1310 to interact with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0159] like Figure 13B As shown, the graphics processor 1340 includes Figure 13AThe graphics processor 1310 includes one or more MMUs 1320A to 1320B, caches 1325A to 1325B, and circuit interconnects 1330A to 1330B. The graphics processor 1340 includes one or more shader cores 1355A to 1355N (e.g., 1455A, 1355B, 1355C, 1355D, 1355E, 1355F, up to 1355N-1 and 1355N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary in embodiments and implementations. Additionally, the graphics processor 1340 includes an inter-core task manager 1345, which acts as a thread dispatcher for assigning execution threads to one or more shader cores 1355A to 1355N and a chunking unit 1358 for accelerating chunked operations for chunked rendering, in which rendering operations for a particular scene are subdivided in the image space, for example to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0160] Figures 14A to 14B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. Figure 14A A graphics core 1400 is shown, which can be included in... Figure 12 The graphics processor 1210 can be as follows Figure 13B The unified shader cores in the 1355A to 1355N. Figure 14B The 1430 is a highly parallel general-purpose graphics processing unit suitable for deployment on multi-chip modules.

[0161] like Figure 14AAs shown, the graphics core 1400 includes a shared instruction cache 1402, texture units 1418, and cache memory / shared memory 1420 common to the execution resources within the graphics core 1400. The graphics core 1400 may include multiple slices 1401A to 1401N or per core partition, and the graphics processor may include multiple instances of the graphics core 1400. Slices 1401A to 1401N may include supporting logic, including local instruction caches 1404A to 1404N, thread schedulers 1406A to 1406N, thread dispatchers 1408A to 1408N, and a set of registers 1410A. To perform logical operations, slices 1401A to 1401N may include a set of additional functional units (AFU1412A to 1412N), floating-point units (FPU 1414A to 1414N), integer arithmetic logic units (ALU1416 to 1416N), addressing calculation units (ACU 1413A to 1413N), double-precision floating-point units (DPFPU 1415A to 1415N), and matrix processing units (MPU 1417A to 1417N).

[0162] Some of these compute units operate with specific precision. For example, FPUs 1414A to 1414N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while DPFPUs 1415A to 1415N perform double-precision (64-bit) floating-point operations. ALUs 1416A to 1416N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. MPUs 1417A to 1417N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. MPUs 1417 to 1417N can perform a wide variety of matrix operations to accelerate machine learning application frameworks, including enabling accelerated Generalized Matrix-to-Matrix Multiplication (GEMM). AFUs 1412A to 1412N can perform additional logical operations not supported by floating-point or integer units, including trigonometric function operations (e.g., sine, cosine, etc.).

[0163] like Figure 14BAs shown, the General Purpose Processing Unit (GPGPU) 1430 can be configured to perform highly parallel computational operations by the graphics processing unit array. Additionally, the GPGPU 1430 can be directly linked to other instances of GPGPUs to create multi-GPU clusters, thereby improving the training speed, particularly for deep neural networks. The GPGPU 1430 includes a host interface 1432 for implementing connectivity with a host processor. In one embodiment, the host interface 1432 is a PCI Express interface. However, the host interface can also be a provider-specific communication interface or communication structure. The GPGPU 1430 receives commands from the host processor and uses a global scheduler 1434 to distribute the execution threads associated with those commands to a group of compute clusters 1436A to 1436H. Compute clusters 1436A to 1436H share a cache memory 1438. The cache memory 1438 can act as a higher-level cache of the cache memory within the compute clusters 1436A to 1436H.

[0164] The GPGPU 1430 includes memories 1434A to 1434B coupled to computing clusters 1436A to 1436H via a set of memory controllers 1442A to 1442B. In various embodiments, memories 1434A to 1434B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0165] In one embodiment, computing clusters 1436A to 1436H each include a set of graphics cores, such as Figure 14A The graphics core 1400 may include various types of integer logic units and floating-point logic units, which can perform computational operations suitable for machine learning within a certain precision range. For example, in one embodiment, at least a subset of the floating-point units in each of the computing clusters 1436A to 1436H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0166] Multiple instances of GPGPU 1430 can be configured to operate as a computing cluster. The computing mechanisms used by the computing cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 1430 communicate via host interface 1432. In one embodiment, GPGPU 1430 includes an I / O hub 1439 that couples GPGPU 1430 to GPU links 1440 that implement direct connections to other instances of GPGPU. In one embodiment, GPU link 1440 is coupled to a dedicated GPU-to-GPU bridge that implements communication and synchronization between multiple instances of GPGPU 1430. In one embodiment, GPU link 1440 is coupled to a high-speed interconnect for transmitting and receiving data to and from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 1430 reside in a separate data processing system and communicate via a network device accessible via host interface 1432. In one embodiment, in addition to or as an alternative to host interface 1432, GPU link 1440 can be configured to implement a connection to a host processor.

[0167] While the illustrated configuration of the GPGPU 1430 can be configured to train neural networks, one embodiment provides an alternative configuration of the GPGPU 1430 that can be deployed within a high-performance or low-power inference platform. In the inference configuration, the GPGPU 1430 includes fewer compute clusters from compute clusters 1436A to 1436H associated with the training configuration. Additionally, the memory technology associated with memories 1434A to 1434B can differ between the inference and training configurations, with higher-bandwidth memory technology dedicated to the training configuration. In one embodiment, the inference configuration of the GPGPU 1430 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are typically used during the inference operations of the deployed neural network.

[0168] Machine Learning Overview

[0169] Machine learning algorithms are algorithms that can learn from a set of data. Implementations of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output numerical values ​​given input; and pattern recognition algorithms can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0170] One example type of machine learning algorithm is a neural network. Many types of neural networks exist; a simple type is the feedforward network. A feedforward network can be implemented as an acyclic graph, where nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer, separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating the output in the output layer. Network nodes are fully connected to nodes in adjacent layers via edges, but there are no edges between nodes within a single layer. Data received at the nodes in the input layer of the feedforward network is propagated (i.e., “feedforward”) to the nodes in the output layer via activation functions that compute the state of nodes in each consecutive layer of the network based on coefficients (“weights”) associated with each of the edges connecting these layers. Depending on the specialized model represented by the algorithm being executed, the output from a neural network algorithm can take various forms.

[0171] Before a machine learning algorithm can be used to model a specific problem, it is trained using a training dataset. Training a neural network involves: selecting a network topology; using a set of training data representing the problem being modeled by the network; and adjusting the weights until the network model exhibits minimum error for all instances in the training dataset. For example, during supervised learning training for a neural network, the output generated by the network in response to inputs representing instances in the training dataset is compared to the “correct” labeled output of those instances; an error signal representing the difference between the output and the labeled output is calculated; and the weights associated with the connections are adjusted to minimize the error as the error signal is backpropagated through the layers of the network. The network is considered “trained” when the error of each output generated from the instances in the training dataset is minimized.

[0172] The accuracy of machine learning algorithms is greatly affected by the quality of the dataset used to train them. The training process can be computationally intensive and may take a significant amount of time on a conventional general-purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the computations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementation. Specifically, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0173] Figure 15This is a generalized graph of machine learning software stack 1500. Machine learning application 1502 can be configured to train a neural network using a training dataset or to achieve machine intelligence using a trained deep neural network. Machine learning application 1502 may include training and inference capabilities for the neural network and / or dedicated software, which can be used to train the neural network prior to deployment. Machine learning application 1502 can achieve any type of machine intelligence, including but not limited to: image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0174] Hardware acceleration for machine learning applications 1502 can be achieved via machine learning framework 1504. Machine learning framework 1504 provides a library of machine learning primitives. Machine learning primitives are the fundamental operations typically performed by machine learning algorithms. Without machine learning framework 1504, developers of machine learning algorithms would need to create and optimize the main computational logic associated with their algorithms, and then re-optimize that computational logic when a new parallel processor is developed. Instead, machine learning applications can be configured to use primitives provided by machine learning framework 1504 to perform the necessary computations. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). Machine learning framework 1504 can also provide primitives for implementing basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0175] Machine learning framework 1504 can process input data received from machine learning application 1502 and generate appropriate input for computing framework 1506. Computing framework 1506 can abstract the low-level instructions provided to GPGPU driver 1508, enabling machine learning framework 1504 to utilize hardware acceleration via GPGPU hardware 1510 without requiring machine learning framework 1504 to be very familiar with the architecture of GPGPU hardware 1510. Furthermore, computing framework 1506 can implement hardware acceleration for machine learning framework 1504 across various types and generations of GPGPU hardware 1510.

[0176] Machine learning neural network implementation methods

[0177] The computational architectures provided by the embodiments described herein can be configured to perform these types of parallel processing, which are particularly well-suited for training and deploying neural networks for machine learning. Neural networks can be generalized as networks of functions with graph relationships. As is known in the art, there are various types of neural network implementations used in machine learning. One exemplary type of neural network is the feedforward network as previously described.

[0178] The second exemplary type of neural network is the Convolutional Neural Network (CNN). A CNN is a specialized feedforward neural network designed for processing data with a known, grid-like topology (e.g., image data). Therefore, CNNs are commonly used in computer vision and image recognition applications, but they can also be used in other types of pattern recognition, such as speech and language processing. Nodes in the input layer of a CNN are organized as a set of “filters” (feature detectors inspired by receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The computation for a CNN involves applying convolutional mathematics to each filter to produce the output of that filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function related to convolution can be referred to as the input, and the second function can be referred to as the convolution kernel. The output can be referred to as a feature map. For example, the input to a convolutional layer can be a multidimensional array of data that defines various color components of the input image. The convolution kernel can be a multidimensional array of parameters, which are adapted through a training process for the neural network.

[0179] Recurrent Neural Networks (RNNs) are a type of feedforward neural network that includes feedback connections between layers. RNNs enable the modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes loops. These loops represent the effect of the current value of a variable on its own value at future times, because at least a portion of the output data from the RNN is used as feedback to process subsequent inputs in the sequence. This variable nature of language data makes RNNs particularly useful for language processing.

[0180] The diagrams described below illustrate exemplary feedforward, CNN, and RNN networks, and describe the general process for training and deploying each of those types of networks respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any particular embodiment described herein, and that the concepts shown can generally be applied to deep neural networks and machine learning techniques.

[0181] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning performed using deep neural networks. In contrast to shallow neural networks that contain only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output error compared to shallow machine learning techniques.

[0182] Deep neural networks used in deep learning typically include a front-end network for performing feature recognition coupled to a back-end network representing a mathematical model, which can then perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to the model. Deep learning enables machine learning to be performed without requiring manual feature engineering on the model. Instead, deep neural networks can learn features based on statistical structure or correlations within the input data. The learned features can be provided to a mathematical model, which can then map the detected features to the output. The mathematical model used by the network is typically specialized for a specific task to be performed, and different models will be used to perform different tasks.

[0183] Once a neural network is structured, a learning model can be applied to it to train it to perform a specific task. The learning model describes how weights are adjusted within the model to reduce the network's output error. Backpropagation of error is a common method used to train neural networks. An input vector is presented to the network for processing. The network's output is compared to the expected output using a loss function, and an error value is calculated for each neuron in the output layer. These error values ​​are then backpropagated until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm (e.g., stochastic gradient descent) to update the neural network's weights.

[0184] Figures 16A-16B This demonstrates an exemplary convolutional neural network. Figure 16A Show the individual layers within a CNN. For example... Figure 16A As shown, an exemplary CNN for modeling image processing can receive input 1602, which describes the red, green, and blue (RGB) components of an input image. Input 1602 can be processed by multiple convolutional layers (e.g., a first convolutional layer 1604, a second convolutional layer 1606). Optionally, the output from the multiple convolutional layers can be processed by a set of fully connected layers 1608. Neurons in a fully connected layer have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The output from the fully connected layer 1608 can be used to generate an output from the network. Matrix multiplication can be used instead of convolution to compute the activation functions within the fully connected layer 1608. Not all CNN implementations use fully connected layers 1608. For example, in some implementations, a second convolutional layer 1606 can generate the CNN output.

[0185] Convolutional layers are sparsely connected, unlike the traditional neural network configuration found in fully connected layers (1608). Traditional neural network layers are fully connected, such that each output unit interacts with each input unit. However, convolutional layers are sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state value of each node in the receptive field) is fed to nodes in subsequent layers, as illustrated. The kernels associated with the convolutional layers perform convolution operations, the output of which is sent to the next layer. Dimensionality reduction performed within convolutional layers is one aspect that enables CNNs to scale to handle large images.

[0186] Figure 16B This illustrates an exemplary computational phase within a convolutional layer of a CNN. The input 1612 to the convolutional layer of the CNN can be processed in three phases within convolutional layer 1614. These three phases may include a convolutional phase 1616, a detector phase 1618, and a pooling phase 1620. Convolutional layer 1614 can then output the data to successive convolutional layers. The last convolutional layer of the network can generate output feature map data or provide input to fully connected layers, for example, to generate classification values ​​for the input to the CNN.

[0187] Several convolutions are performed in parallel within convolutional stage 1616 to produce a set of linear activation functions. Convolutional stage 1616 may include affine transformations, which are any transformations that can be specified as a linear transformation plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolutional stage computes the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron computes the dot product between the neuron's weights and a region in the local input to which the neuron is connected. The output from convolutional stage 1616 defines a set of linear activation functions processed by successive stages of convolutional layer 1614.

[0188] Linear activation functions can be processed by detector stage 1618. In detector stage 1618, each linear activation function is processed by a nonlinear activation function. Nonlinear activation functions add nonlinearity to the overall network without affecting the receptive field of the convolutional layers. Several types of nonlinear activation functions can be used. One specific type is the Modified Linear Unit (ReLU), which uses an activation function defined as f(x) = max(0, x) such that the activation function is thresholded to zero.

[0189] Pooling stage 1620 uses a pooling function that replaces the output of the second convolutional layer 1606 with a generalized statistical value of the nearby output. The pooling function can be used to introduce translation invariance into the neural network, such that slight translations to the input do not change the pooling output. Local translation invariance can be useful when the presence of features in the input data is more important than the precise location of the features. Various types of pooling functions can be used during pooling stage 1620, including max pooling, average pooling, and L2-norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations use an additional convolutional stage with a larger stride relative to the previous convolutional stage.

[0190] The output from convolutional layer 1614 can then be processed by the next layer 1622. The next layer 1622 can be either an additional convolutional layer or a fully connected layer 1608. For example, Figure 16A The first convolutional layer 1604 can output to the second convolutional layer 1606, and the second convolutional layer can output to the first layer in the fully connected layer 1608.

[0191] Figure 17 An exemplary recurrent neural network is shown. In a recurrent neural network (RNN), the network's previous state influences the output of the network's current state. RNNs can be constructed in a wide variety of ways using a variety of functions. The use of RNNs often revolves around using mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict an upcoming word given a previous sequence of words. The RNN 1700 shown can be described as having the following components: an input layer 1702 that receives an input vector; a hidden layer 1704 for implementing the recurrent function; a feedback mechanism 1705 for implementing a 'memory' of previous states; and an output layer 1706 for outputting the result. RNN 1700 operates based on time steps. The state of the RNN at a given time step is influenced by the feedback mechanism 1705 based on previous time steps. For a given time step, the state of the hidden layer 1704 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1704. The second input (x2) can be processed by hidden layer 1704 using the state information determined during the processing of the initial input (x1). The given state can be computed as s. t =f(Ux t +Ws t-1), where U and W are parameter matrices. The function f is typically nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or the correction function f(x) = max(0, x). However, the specific mathematical function used in hidden layer 1704 can vary depending on the specific implementation details of the RNN 1700.

[0192] In addition to the basic CNN and RNN networks described, variations of those networks can be implemented. An example RNN variant is the Long Short-Term Memory (LSTM) RNN. LSTM RNNs are capable of learning long-term dependencies necessary for processing longer language sequences. A CNN variant is the Convolutional Deep Belief Network, which has a similar structure to a CNN and is trained in a similar manner to a deep belief network. A deep belief network (DBN) is a generative neural network consisting of multiple layers of stochastic (random) variables. A DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining an optimal set of initial weights for the neural network.

[0193] Figure 18 This demonstrates the training and deployment of deep neural networks. Once a given network has been structured for a task, it is trained using the training dataset 1802. Various training frameworks have been developed to accelerate the training process using hardware. For example, Figure 15 The machine learning framework 1504 can be configured as a training framework 1804. The training framework 1804 can be hooked into an untrained neural network 1806, enabling the use of the parallel processing resources described herein to train the untrained neural network to generate a trained neural network 1808. To begin the training process, initial weights can be selected randomly or through pre-training using a deep belief network. The training loop is then performed in a supervised or unsupervised manner.

[0194] Supervised learning is a learning method in which training is performed as an arbitration operation, such as when the training dataset 1802 includes inputs (which are paired with the expected outputs of said inputs), or when the training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs with a set of expected or desired outputs. The error is then backpropagated through the system. The training framework 1804 can be tuned to adjust the weights controlling the untrained neural network 1806. The training framework 1804 can provide tools for monitoring the extent to which the untrained neural network 1806 converges to a model suitable for generating correct answers based on known input data. The training process occurs repeatedly as the network weights are adjusted to improve the outputs generated by the neural network. The training process can continue until the neural network reaches the statistically expected accuracy associated with the trained neural network 1808. The trained neural network 1808 can then be deployed to implement any number of machine learning operations.

[0195] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Therefore, for unsupervised learning, the training dataset 1802 would include input data without any associated output data. The untrained neural network 1806 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall dataset. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1807 capable of performing operations useful in data dimensionality reduction. Unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the input dataset that deviate from the normal pattern of the data.

[0196] Variations in supervised and unsupervised training can also be employed. Semi-supervised learning is a technique where the training dataset 1802 comprises a mixture of labeled and unlabeled data with the same distribution. Incremental learning is a variant of supervised learning where the input data is continuously used for further training of the model. Incremental learning enables the trained neural network 1808 to adapt to new data 1812 without forgetting the knowledge embedded within the network during the initial training.

[0197] Whether supervised or unsupervised, training very deep neural networks can be computationally too intensive for a single computing node. A distributed network of computing nodes can be used instead of a single node to accelerate the training process.

[0198] Figure 19This is a block diagram illustrating distributed learning. Distributed learning trains a model using multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. Each of these distributed computing nodes may include one or more host processors and general-purpose processing nodes. As shown, distributed learning can perform model parallelization 1902, data parallelization 1904, or a combination of model and data parallelization 1904.

[0199] In Model Parallelism 1902, different computing nodes in a distributed system can perform training computations on different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes in a distributed system. Benefits of model parallelism include the ability to scale to exceptionally large models. Splitting the computations associated with different layers of a neural network makes it possible to train very large neural networks, where the weights of all layers are not fitted into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0200] In data parallelization 1904, different nodes in a distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. While different approaches to data parallelization are possible, all data-parallel training methods require a technique for combining the results and synchronizing the model parameters across each node. Exemplary methods for combining data include parameter averaging and update-based data parallelization. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update-based data parallelization is similar to parameter averaging, except that model updates are passed instead of parameters from nodes to a parameter server. Additionally, update-based data parallelization can be performed in a distributed manner, where updates are compressed and passed between nodes.

[0201] For example, combined model and data parallelism can be implemented in a distributed system, where each computing node includes multiple GPUs. Each node can have a complete instance of the model, with individual GPUs within each node used to train different parts of the model.

[0202] Distributed training incurs increased overhead compared to training on a single machine. However, the parallel processors and GPGPUs described in this paper can each implement techniques to reduce the overhead of distributed training, including techniques for enabling high-bandwidth GPU-to-GPU data transfer and accelerating remote data synchronization.

[0203] Exemplary machine learning applications

[0204] Machine learning can be applied to solve a wide range of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual abilities (e.g., recognizing faces) to creating new categories of visual abilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables the training of computer vision applications using training datasets significantly larger than previously feasible ones, and allows the deployment of inference systems using low-power parallel processors.

[0205] Parallel processor-accelerated machine learning has applications in autonomous driving, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described in this paper enable the rapid training of increasingly sophisticated neural networks for autonomous driving solutions and allow the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0206] Parallel processor-accelerated deep neural networks have been implemented as machine learning methods for Automatic Speech Recognition (ASR). ASR involves creating functions that compute the most probable language sequence given an input speech sequence. Accelerated machine learning using deep neural networks has replaced previous Hidden Markov Models (HMMs) and Gaussian Mixture Models (GMMs) used for ASR.

[0207] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automated learning programs can use statistical inference algorithms to generate models that are robust to errors or unfamiliar inputs. Exemplary natural language processor applications include automated machine translation between human languages.

[0208] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training, while deployment machine learning (e.g., inference) platforms typically include lower-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0209] Scalable distributed machine learning abstraction layer

[0210] Currently, data scientists developing applications leveraging distributed deep learning need to explicitly implement communication systems between computing nodes. Implementing the underlying communication system for distributed deep learning requires knowledge of distributed or networked computing node communication technologies, including the libraries needed to implement these technologies. For example, to implement distributed deep learning models, such as data parallelism, model parallelism, or hybrid parallelism (a combination of data and model parallelism), application developers may need to explicitly build the communication infrastructure using low-level communication libraries, such as Message Passing Interface (MPI) libraries. Application developers will then be asked to determine the specific units of data to be transmitted and the specific nodes that will transmit and receive such information. Because deep learning application developers may not be domain experts in building distributed computing infrastructure, many best practices and optimizations may not be included in the communication implementation developed for a given deep learning application.

[0211] Distributed machine learning can be implemented using various parallelism patterns, such as data parallelism, model parallelism, or a hybrid of data and model parallelism, such as... Figure 19 As shown. (Regarding...) Figure 19 The data parallelism described uses the same model for each compute node, where each node processes a different part of the data. The model parallelism uses the same data for each compute node, where the model is split across the compute nodes.

[0212] To enable communication, various low-level communication modes are used to transfer data between nodes. Table 1 below shows the low-level communication modes used.

[0213] Table 1 - Low-level communication operations

[0214]

[0215] Figures 20A-20E The communication patterns used during distributed machine learning computation operations performed across multiple computing nodes, according to embodiments described herein, are illustrated. Figure 20A The data transfer method used for machine learning computations using data parallelism is shown. Figure 20B The data transfer method used for distributed machine learning computation using model parallelism is shown. Figure 20C This demonstrates how to partition machine learning computations across multiple nodes using hybrid parallelism. Figure 20D This demonstrates distributed machine learning computation using hybrid parallelism across multiple nodes and multiple layers. Figure 20E A set of exemplary message-passing patterns that can be used for distributed machine learning are illustrated. Figures 20A to 20E In each of the graphs, the input data 2002 is processed by a machine learning model with a set of weights 2004 to generate a set of activations 2008 or partial activations 2006.

[0216] like Figure 20A As shown, data parallelism can be achieved where the input data 2002 is split along the mini-batch dimension and the same model is replicated on each node. The mini-batch is split across several computation nodes, with each node responsible for computing gradients for all model parameters using a subset of samples from the mini-batch. Forward propagation is performed independently on each node. In one embodiment, only one communication is performed during the backpropagation to compute the average gradient for the learnable parameters. A full reduction operation 2005 is used to update the weights of each layer for the next forward propagation. In one embodiment, distributed weight updates can be enabled, where a reduction-spread operation is used to compute the average gradient before performing stochastic gradient descent, and a full aggregation operation is used after stochastic gradient descent to synchronize the weights across nodes.

[0217] like Figure 20B As shown, model parallelism can be achieved by splitting the model or a set of weights across multiple nodes. Typically, model parallelism executes different parts of the model's computation simultaneously on different nodes within the same batch of examples. For model parallelism, the input data is also split (e.g., along the channel dimension), such as... Figure 20B As shown in the diagram. Using the method shown, a reduction operation is performed to calculate the total number of activations to obtain the actual output, and the activations are then spread to calculate the activations for the next layer. A reduction_spread2007 operation can be performed to pass data in a single communication operation. In the backpass, a full aggregation operation is performed to combine the gradient bars calculated at each node.

[0218] like Figure 20C As shown, hybrid parallelism can be performed, where partitioning occurs on activations and weights to minimize the skew matrix. For a layer of the neural network, input data 2002, weight data 2004, and / or activation data 2006 are partitioned and distributed across multiple computation nodes (e.g., nodes 0-3). Node 0 receives a first input data block 2002A and weight data 2004A. Computation is performed at node 0 to generate a first partial activation 2006A. Similarly, node 1 receives a second input data block 2002B and weight data 2004B. Computation is performed at node 1 to generate a second partial activation 2006B. Node 2 can perform computation on a third input data 2002C and weight data 2004C to generate a third partial activation 2006C. Node 3 can perform computation on a fourth input data 2002D and weight data 2004D to generate a fourth partial activation 2006D.

[0219] Figure 20DThe transfer of partial activation data 2006A-2006B from a given layer (layer N-1) of a neural network to subsequent layers (layer N) is illustrated. A set of partial activations 2006A-2006B is generated via multiple nodes (node ​​0, node 1) based on the application of mathematical operations (e.g., convolution) to the input data 2002A-2002B and the weight data 2004A-2004B. For example, in one embodiment, a reduction-spreading operation 2010 is used, which performs a reduction operation on the partial activations 2006A-2006B from layer N-1 from multiple nodes and spreads the result to multiple nodes as activations for use in layer N of the neural network.

[0220] Figure 20E An exemplary communication operation is illustrated for passing data during the distributed training of a neural network for machine learning operations. A low-level messaging library is used to enable data passing for weights and activation data during the distributed training of the neural network. An exemplary neural network with N layers 2021A, 2021B, 2021N (e.g., layers 1, 2 to N) can be distributed trained by performing consecutive forward computation operations on consecutive layers to enable forward propagation 2026 through the activation data of the neural network. During forward propagation 2026, for example, when the first layer and consecutive layers are hidden layers or non-output layers, the activation data is passed from the first layer 2021A to the consecutive layer 2021B using a full interchange 2009 communication operation. The full interchange 2009 operation passes unique data from the computation node that generates activation or partial activation data to all available receivers that use the activation data as input data for operations on consecutive layers. When data is passed to the final layer (e.g., layer N), a reduction spread operation 2010 is performed, which combines... Figure 20B The process is described as follows: During backpropagation 2028, distributed stochastic gradient descent is performed to generate updated weight data. An initial full reduction operation 2012 is performed on layer N, and a set of full reduction operations 2011A, 2011B, and 2011N are performed to update the weights of each layer for the next forward pass. A full reduction operation is a type of reduction operation whose results are broadcast or transmitted to the receive buffers of all processes in the communication group. Backpropagation 2028 may also include full aggregation 2013 and full swapping 2014 communication operations. For full aggregation operation 2013, data is aggregated from all tasks and the combined data is distributed to all tasks. For full swapping operation 2014, data from all processes is transmitted to all processes.

[0221] The data transfer required to perform distributed computing operations for machine learning can be implemented using any low-level messaging library (such as MPI, gRPC, or zeroMQ). However, implementing exemplary communication operations can be difficult without domain-level expertise in multiprocessor communication libraries. Furthermore, scaling these operations to a very large number of nodes can be challenging. Without domain-specific knowledge of distributed computing technologies, implementing a scalable communication system capable of handling communication between hundreds or thousands of nodes for machine learning applications can significantly extend development time.

[0222] The embodiments described herein provide various techniques to abstract the details of distributed communication systems for deep learning applications. In one embodiment, a Machine Learning Extension Library (MLSL) is provided, which enables deep learning application developers to develop distributed deep learning applications without requiring knowledge of the specific communication details needed to enable multi-node deep learning. Deep learning application developers can use deep learning domain-specific terminology to specify the type of distributed computing system used by the applications and library techniques provided by the embodiments described herein, and can implement the specific low-level communication methods required to enable the requested distributed computing system.

[0223] Figures 21A-21B The architectural details of the machine learning extension library provided by the embodiments described herein are shown. Figure 21A An exemplary machine learning architecture stack 2100 is shown. Figure 21B Details of the MLSL architecture 2111 are shown.

[0224] Figure 21A An exemplary machine learning architecture stack 2100 is shown, which can be Figure 15 This is a variant of the machine learning software stack 1500. The machine learning architecture stack 2100 includes multiple software and hardware layers from input data 2102 provided by a sensor array to hardware elements 2114 that perform various computational, storage, or communication operations. Each layer of the exemplary machine learning architecture stack 2100 can be an opaque abstraction layer that hides the implementation details of the higher layers while using functions provided by the lower layers to implement the functions required by the higher layers.

[0225] Input data 2102 is provided to application layer 2104. In one embodiment, input data 2102 is multimodal input, including but not limited to video and / or image data, data from multiple sensors, and external signal data. Application 2104 includes a multimodal fusion and decision application that can process the input to enable machine learning tasks such as image understanding, video summarization, speech and natural language processing, path planning, navigation, or any other machine learning implementation described herein. Application 2104 communicates with one or more machine learning frameworks 2106 (such as, but not limited to, Caffe, Theano, Torch, TensorFlow, or any other script-based machine learning framework) to implement machine learning-specific operations. Machine learning framework 2106 enables machine learning operations to be performed using any number of neural network topologies 2108, including but not limited to CNNs, RNNs, LSTMs, general-purpose deep neural networks, and reinforcement learning networks. Machine learning framework 2106 implements neural network topologies 2108 via one or more building blocks 2110. Exemplary building block 2110 includes a Single-Precision Floating-Point General Matrix Multiplication (SGEMM) block, a convolution building block, a Fast Fourier Transform / Winograd block, a Single-Source Shortest Path (SSSP) computation block, a Sparse Matrix-Matrix Multiplication (SpGEMM) block, and a Machine Learning Extension Library (MLSL) 2111 provided by the embodiments described herein. Building block 2110 may each implement various algorithms 2112 to enable computational operations requested by the machine learning framework 2106 to implement the neural network topology 2108. Algorithms 2112 include optimizations to enhance statistical and architectural efficiency, enable cloud deployment, and enable scaling to a large number of nodes. In one embodiment, MLSL 2111 includes algorithm 2112 to enable scaling machine learning operations to a large number of nodes. In one embodiment, building block 2110 may be implemented via a software library that can be accelerated by one or more elements of hardware 2114. In one embodiment, at least a portion of building block 2110 may be implemented within hardware 2114. For example, FPGA- or ASIC-based accelerators may include custom logic to enable a portion or one or more GEMM libraries of MLSL 2111.

[0226] Various components of hardware 2114 can be used to implement higher-level functions of the machine learning architecture stack 2100. Components of hardware 2114 include, but are not limited to, a CPU or another general-purpose processor whose task is to perform computations related to computing and / or the operating system. Hardware 2114 also includes parallel processing systems based on integrated many-core (MIC) or general-purpose GPUs. In some embodiments, hardware 2114 includes a deep learning accelerator based on an FPGA or ASIC. The interconnect components of hardware 2114 enable high-speed communication between various components and high-bandwidth volatile or non-volatile memory. Volatile memory technologies can include any graphics memory technologies described herein, including HBM and GDDR memory. Non-volatile memory technologies can include flash memory (including 3D NAND flash memory) or other memory technologies (such as 3D Xpoint memory).

[0227] Figure 21B Details of the MLSL architecture 2111 according to an embodiment are shown. The MLSL architecture 2111 includes an abstraction layer with machine learning-specific abstractions 2113 and non-machine learning-specific abstractions 2115. The abstractions interface with a communication module 2117 that drives the underlying messaging library 2119. The messaging library 2119 uses optimized low-level communication routines to transmit data through a high-performance communication structure 2121.

[0228] The MLSL architecture 2111 enables developers of machine learning software to develop scalable machine learning applications using machine learning-specific abstractions 2113. In one embodiment, the machine learning-specific abstractions 2113 enable application developers to use machine learning domain-specific knowledge to drive scalable performance of computational operations for neural network layers. The machine learning-specific abstractions 2113 allow applications to be developed in a way that is transparent to the underlying architecture, enabling machine learning applications to automatically adapt to any number of hardware 2114 components, including various types of computational and structural components. In addition to the machine learning-specific abstractions 2113, the MLSL architecture 2111 may also provide a set of non-machine learning-specific abstractions 2115. These non-machine learning-specific abstractions 2115 enable developers of machine learning applications to define one or more non-machine learning details of the application at a higher level of abstraction, such as one or more implementation-specific details or operating system details unrelated to machine learning.

[0229] In one embodiment, the machine learning-specific abstraction 2113 enables neural network layers to support multiple types of parallelism (e.g., data, machine, hybrid). The machine learning-specific abstraction 2113 also supports layer-to-layer communication abstractions to allow developers to easily implement communication patterns for different layer types and parallelisms. Different layer types and parallelisms are defined using machine learning-specific terminology, which utilizes the machine learning-specific abstraction 2113, and communication for those layer types is enabled through communication module 2117, messaging library 2119, and high-performance communication architecture 2121. The machine learning-specific abstraction 2113 also enables intelligent message scheduling across defined neural network layers, while abstracting the data layout and transformations required to implement machine learning techniques at the application level.

[0230] In one embodiment, communication module 2117 includes logic driving the underlying messaging library 2119. Communication module 2117 includes various optimizations to efficiently drive the network while transmitting machine learning data between compute nodes used for performing distributed machine learning. Communication module 2117 includes logic for optimizing network bandwidth and enabling low-latency communication. Machine learning-specific abstraction 2113 and / or non-machine learning-specific abstraction 2115 may specify or prove interfaces to allow application developers to specify processor resources for managing distributed communication. In one embodiment, a specific processor may be specified. In one embodiment, the number of processors associated with communication may be specified. In one embodiment, a mix of compute and communication resources may be specified. In one embodiment, communication module 2117 includes logic for adaptively allocating processor cores for driving and performing operations for communication module 2117 and / or messaging library 2119. In one embodiment, communication module 2117 may adaptively allocate processing resources for communication without requiring explicit instructions from machine learning-specific abstraction 2113 or non-machine learning-specific abstraction 2115. In one embodiment, the communication module 2117 may adaptively adjust or allocate processing resources to attempt to fully saturate available network resources, thereby minimizing the latency impact of communication within the distributed system. For example, if the communication module 2117 determines that the high-performance communication architecture 2121 is not fully saturated, additional processors or processor cores may be allocated to perform network tasks if the overall throughput of the distributed computing system will increase. In one embodiment, the amount of computing resources allocated to drive the message delivery library 2119 may vary based on the bandwidth of the high-performance communication architecture. For higher bandwidth architectures, more computing resources may be required to saturate the network. The high-performance communication architecture 2121 can be implemented using any number of high-speed network connectivity technologies, including but not limited to Ethernet, unlimited bandwidth technologies, omnidirectional path interconnects, or networks via point-to-point interconnects such as NVLink.

[0231] In one embodiment, the communication module 2117 includes logic to ensure the forward execution of distributed computing operations by enabling asynchronous communication between processing nodes. The asynchronous communication enabled by the communication module 2117 allows for overlapping computing and communication operations, which are efficiently interleaved to optimize computing and communication efficiency and throughput. In one embodiment, the communication module 2117 also supports prioritized communication channels to enable prioritized resolution of competing communication requests.

[0232] The messaging library 2119 uses optimized low-level communication routines to transmit data over the high-performance communication structure 2121. The MLSL architecture 2111 is agnostic to both the underlying messaging library 2119 and the high-performance communication structure 2121. In one embodiment, the messaging library is an MPI-based library. In such an embodiment, MPI functions (e.g., MPI_Alltoall, MPI_Allreduce, MPI_Allgather, etc.) are used to implement the communication patterns used by machine learning applications. In some embodiments, the gRPC or zeroMQ library and associated functions are used for messaging. In one embodiment, routines from the Nvidia Collective Communication Library (NCCL) can also be used. NCCL provides communication routines, such as full aggregation, reduction, and broadcasting, to accelerate multi-GPU machine learning training across multiple GPGPUs and enables multi-GPU and multi-GPU / multi-node communication.

[0233] Topology-aware algorithm for flexible node grouping

[0234] DL neural networks can have a large number of convolutional layers. Training such networks over a reasonable timeframe may require multi-node training. Multi-node training can experience bottlenecks in the form of communication latency. A large number of parallel processor nodes operating simultaneously can lead to performance issues due to extensive concurrent communication. Excessive communication can cause congestion in certain areas of the network.

[0235] Existing techniques for multi-node training include using purely distributed training, where each node can directly interact with every other node on the network. Alternatively, one or more parameter servers can be used to distribute updated parameters to each node. Parameter server-based approaches allow for topology flexibility because nodes communicate directly with the parameter servers rather than with each other. Using parameter servers also introduces resilience. If a parameter server fails, the system can easily instantiate a different node as a parameter server. The remaining nodes can then subsequently begin communicating with the new parameter server.

[0236] However, purely distributed training has advantages over parameter servers because higher performance can be achieved if the network topology is constructed with purely distributed training in mind. In other words, the type of network topology that can be used is limited to one where each node in the system can easily communicate with every other node in the system. Otherwise, bottlenecks may form within the network, thus reducing overall performance.

[0237] For example, when a full reduction operation is performed using a set of nodes, the performance of the operation may become sensitive to latency spikes within the network.

[0238] This paper describes a communication system that utilizes topology-aware algorithms for flexible node grouping. In one embodiment, the distributed training system can be constructed in a manner sensitive to the existing network topology of worker nodes, allowing local nodes to be assembled into computation groups based on the network topology. Nodes within a computation group communicate with each other using operations such as full reduction, while remote nodes are bridged via synchronization operations performed using a parameter server. In one embodiment, the communication framework associated with the distributed training network can utilize topology-aware algorithms to flexibly and transparently adjust node grouping based on the current set of communication operations to be performed. Different node groupings can be used depending on the type of communication operation being performed. For example, when a communication framework facilitating message passing between nodes (e.g., such as...) Figure 21B When the communication module 2117 in the framework determines that a series of latency-sensitive communication operations need to be performed, the communication framework can adjust the node grouping accordingly.

[0239] Figure 22 A multi-node training network 2200 according to an embodiment is illustrated. The multi-node training network 2200 may include multiple groups of worker nodes 2216A-2216B, 2236A-2236B. When performing latency-sensitive communication operations such as full reduction operations on the multi-mode training network 2200, the communication framework may dynamically adjust the node groupings based on the network topology. In the illustrated multi-node training network 2200, the communication framework may determine the worker node set 2216A-2216B that experiences relatively low communication latency when exchanging data (compared to the communication latency observed when communicating with other worker node sets 2236A-2236B). To exchange model data parameters (such as gradient updates) among worker nodes, the communication framework may establish multiple groups of worker nodes. For example, the communication framework may create a first group (2210) of worker nodes, which may include worker node sets 2216A-2216B with low mutual latency. The communication framework can then create a second group (2230) of worker nodes, which may include an additional set of worker nodes 2236A-2236B with low mutual latency. The specific number of groups created can vary based on the network topology. One or more parameter servers 2220 can then be instantiated. The parameter servers can then be configured to enable effective inter-group communication between the various groups 2210, 2230.

[0240] Figure 23 A process 2300 is illustrated that enables a topology-aware algorithm to perform flexible node grouping according to an embodiment. Process 2300 can be performed by a communication framework as described herein, such as, but not limited to, [examples omitted]. Figure 21BThe communication module 2117 is included. In one embodiment, process 2300 includes initializing the distributed training system, as shown in block 2302. Process 2300 additionally includes operations for determining whether the current network topology of the linked nodes is known, as shown in block 2303. If the network topology is known, the communication framework or another logic element configured to perform process 2300 can retrieve network topology information, as shown in block 2305. In one embodiment, network topology information can be retrieved from network topology unit 2808 as shown in Figure 28 below. If the current network topology is unknown, as determined in block 2303, operations can be performed to initiate a set of sample training iterations, as shown in block 2304. During the sample training iterations, the communication logic can monitor network latency between nodes to determine an approximate network topology, as shown in block 2306.

[0241] Process 2300 further includes creating groups of topology-local worker nodes, as shown in box 2308. For example, the communication framework may create groups in box 2308 based on the network topology retrieved in box 2305 or an approximate network topology determined in box 2306. In the case of a known network topology, local worker nodes are grouped under the assumption that they experience relatively low communication latency; however, in one embodiment, latency measurements can be objectively performed to verify this assumption, even when the network topology is known at network initialization time.

[0242] Process 2300 additionally includes creating one or more parameter servers to bridge the node group, as shown in box 2310. One or more parameter servers can be created by repurposing one or more worker nodes and reinitializing the repurposed nodes as parameter servers. Process 2300 additionally includes adjusting communication paths to bridge the worker node group to the parameter servers, as shown in box 2312. In one embodiment, process 2300 additionally includes transparently adjusting the communication paths between worker nodes based on the communication pattern to be performed.

[0243] Optimize intra-chassis and inter-chassis communication

[0244] Some embodiments described herein provide systems and methods for implementing Quality of Service (QoS) for intra-chassis and inter-chassis communication between GPUs within a distributed training cluster. One embodiment provides a standardized platform QoS counter that provides software visibility into hardware-level performance details. Exposing such a QoS counter allows software to make better decisions regarding intra-chassis data communication relative to inter-chassis communication. A higher share of existing bandwidth can be dedicated to higher-priority applications or latency-sensitive applications. During resource contention, less latency-sensitive applications can be restricted or tuned. In one embodiment, based on platform QoS counter data, the communication module of a machine learning framework can adjust bandwidth allocation between applications at the scheduler, thereby granting higher scheduler priority to higher-priority applications. In one embodiment, processor cache QoS functionality can be utilized to manage communication latency for inter-chassis and intra-chassis communication, allowing data associated with high-priority applications to be prioritized in CPU, GPU, and architecture processor caches. To prioritize data in CPU, GPU, and architecture processor caches, data in the cache can be tagged and the eviction probability of tagged data can be reduced.

[0245] Figures 24A-24B Processing systems 2400 and 2430 according to embodiments described herein are shown. Figure 24A A processing system 2400 for performing inter-node communication is shown. Figure 24B A processing system 2430 for performing inter-node and intra-node communication is shown.

[0246] like Figure 24A As shown, the processing system 2400 includes two or more processors 2402, 2404. In one embodiment, processors 2402, 2404 are general-purpose multi-core processors, such as application processors or central processing units (CPUs). Processors 2402, 2404 are coupled to a parallel processor computing system 2410, which includes a parallel computing cluster 2420 and a set of platform interface switches 2411A-2411D. Platform interface switches 2411A-2411D enable the parallel computing cluster 2420 to interconnect with processors 2402, 2402, which can be linked to the parallel processor computing system 2410 via a platform interconnect bus 2406. In one embodiment, the platform interconnect bus 2406 and platform interface switches 2411A-2411D each support a version of the Peripheral Component Interconnect Fast (PCIe) bus standard, including but not limited to PCIe 3.0, 3.1, 4.0, 5.0, etc.

[0247] In some embodiments, the parallel computing cluster 2420 includes multiple general-purpose graphics processing units (GPGPUs) 2422A-2422D, 2424A-2424D. In other embodiments, the parallel computing cluster 2420 may also include other types of parallel processors, such as MIC processors, FPGAs, or custom ASIC processors. In one embodiment, where the parallel computing cluster 2420 includes GPGPUs 2422A-2422D, 2424A-2424D, the GPUs of the parallel computing cluster 2420 may be interconnected via point-to-point interconnect links (e.g., 2423), such as, but not limited to, Nvidia High Speed ​​Signaling Technology (NVHS) (e.g., NVLink). The point-to-point interconnect links may include multiple sets of differential pairs, wherein multiple differential pairs may be combined to form links. In one embodiment, performance metrics of data transmitted through each point-to-point link may be monitored and reported to processors 2402, 2404, along with communication metrics of data transmitted through platform interface switches 2411A-2411D. Performance metrics for data transmission may include metrics for data transactions over each point-to-point link and metrics for data transactions performed via platform interface switches 2411A-2411D. In one embodiment, performance metrics include raw throughput, effective throughput taking into account overhead, instantaneous latency, and average latency.

[0248] like Figure 24B As shown, the processing system 2430 includes two or more processors 2432, 2434, which can be similar to Figure 24A The processors 2402 and 2404 are included. The processing system 2430 also includes two parallel processor computing systems 2440 and 2460, each of which can be similar to... Figure 24AThe parallel processor computing system 2410 includes one or more platform interconnect buses 2472 and 2474 for coupling the parallel processor computing systems 2440 and 2460 to processors 2432 and 2434. Parallel processor computing system 2440 includes a set of platform interface switches 2441A-2441D. Parallel processor computing system 2460 includes a set of platform interface switches 2461A-2461D. Platform interface switches 2441A-2441D couple processors 2432 and 2434 to a parallel computing cluster 2450. Platform interface switches 2461A-2461D couple processors 2432 and 2434 to a parallel computing cluster 2470. In one embodiment, the parallel computing cluster 2450 includes GPGPUs 2452A-2452D and GPGPUs 2454A-2454D. The parallel computing cluster 2470 includes GPGPUs 2472A-2472B and GPGPUs 2472A-2474D. GPGPUs 2452A-2452D and GPGPUs 2454A-2454D can communicate via point-to-point interconnects (such as point-to-point interconnect 2453). GPGPUs 2472A-2472D and 2474A-2474D can also communicate via point-to-point interconnects (such as point-to-point interconnect 2473). The GPGPUs can record data communication metrics and send these metrics to processors 2432 and 2434. They can also report data transfer metrics via platform interface switches 2441A-2441D and 2461A-2461D to processors 2432 and 2434. These metrics can be used to manage the QoS of intra-chassis and inter-chassis communications to manage the bandwidth associated with communications within each chassis and between chassis (e.g., between parallel processor computing system 2440 and parallel processor computing system 266) on one or more platform interconnect buses 2472, 2474.

[0249] Figure 25 A process 2500 for managing QoS of communication between and within parallel processor computing nodes according to an embodiment is illustrated. Process 2500 can be executed by platform QoS logic configured to manage inter-process and intra-process communication between the GPU and CPU, such as in... Figure 24A In the processing system 2400 and Figure 24B In the processing system 2430.

[0250] In one embodiment, process 2500 includes, at a machine learning framework as described herein, tracking the communication behavior of applications communicating on the machine learning platform via a QoS counter exposed by a central processor within the machine learning platform, as shown in box 2502.

[0251] Process 2500 can determine the relative share of intra-chassis and inter-chassis communication bandwidth consumed by each application managed by the machine learning framework, as shown in box 2504. The relative share of intra-chassis and inter-chassis communication can be determined by monitoring platform QoS counters exposed by various processors within the system. QoS counter data can be aggregated at one or more control processors in the system, which can adjust bandwidth allocation or scheduling priorities for communication tasks associated with various applications executing on the system based on application-associated priorities or application latency sensitivity. For example, when communication links between parallel processor computing systems and processors, or between parallel processor computing systems and parallel processor computing systems in different chassis, are congested, a communication library managing intra-chassis data transfer can prioritize intra-chassis communication over inter-chassis communication during the data transfer cycle. Alternatively, when inter-chassis communication is congested, intra-chassis communication can be prioritized.

[0252] In one embodiment, process 2500 additionally includes identifying congestion points within intra-chassis and inter-chassis communication links as described herein, as shown in block 2506. Congestion points can be identified when data communication demand exceeds the available throughput of a given link. For example, depending on the protocol used in a given system implementation, a communication link for inter-chassis communication may have a lower bandwidth link relative to a communication link for intra-chassis communication. Process 2500 may then adjust application communication scheduling and routing based on the relative share of communication bandwidth and congestion points within the intra-chassis and inter-chassis communication links, as shown in block 2508. Adjusting application communication scheduling may include, for example, delaying the scheduling of a set of inter-chassis messages during inter-chassis congestion and instead scheduling the transmission of intra-chassis messages. Adjusting application communication scheduling may also include delaying a set of intra-chassis messages during intra-chassis congestion and instead scheduling inter-chassis messages. However, in the case of intra-chassis congestion, the adjustment may also include adjusting the routing of intra-chassis messages to be relayed. In one embodiment, the adjustment may additionally include dynamically adjusting the cache QoS model to prioritize data for latency-sensitive applications, as shown in box 2510.

[0253] Figure 26 An additional multi-chassis computing system 2600 according to an embodiment is shown. Each chassis of the multi-node computing system 2600 is similar to, for example... Figure 24BThe processing system 2430 is housed within a chassis. General Purpose Graphics Processing Units (GPGPUs) communicate within and between chassis. For example, GPGPUs 2604A-2604D are interconnected via a set of point-to-point GPU links 2614. GPGPUs 2606A-2606D are interconnected via point-to-point GPU links 2616. GPGPUs 2604A-2604D can each communicate with processor 2603 via host interface switch 2602. GPGPUs 2606A-2606D can communicate with processor 2605 via host interface switch 2604. GPGPUs 2604A-2604D and 2606A-2606C can be directly interconnected without point-to-point GPU links, but in one embodiment, they can communicate via an interconnect 2607 between host interface switches 2602 and 2604, which can each be, for example, PCIe switches.

[0254] In one embodiment, the data throughput provided by host interface switches 2602 and 2604, as well as the throughput on interconnect 2607, may be a lower bandwidth interconnect relative to point-to-point GPU links 2614 and 2616. This interconnect can be used where processors 2603 and 2605 do not include support for point-to-point GPU links 2614 and 2616. In an alternative embodiment, inter-chassis communication can be accelerated via an enhanced host interface switch that enables point-to-point GPU links (such as, but not limited to, NVLink) to be implemented within a host interface switch as described herein. For example, in one embodiment, host interface switches 2602 and 2604 may be implemented as NVLink switches, which can be used to interconnect GPUs in different chassis. In one embodiment, processors 2603 and 2605 may reside in a different chassis than GPGPUs 2604A-2604D or GPGPUs 2606A-2606D. Host interface switch 2602 and host interface switch 2604 can facilitate chassis-to-chassis interconnection between processor chassis and GPGPU chassis.

[0255] Figure 27 A host interface switch 2700 according to an embodiment is illustrated. In one embodiment, the host interface switch 2700 can be used to enable a converted point-to-point interconnect for connecting a multi-chassis GPU cluster. The illustrated host interface switch 2700 is an example of one embodiment and is not intended to limit all embodiments. In one embodiment, the host interface switch 2700 can be used as... Figure 26The host interface switch 2603 or host interface switch 2604 is shown in the figure. For example, the host interface switch 2700 shown in the figure implements a switch for point-to-point interconnection (e.g., NVLink) by using multiple NVLink to PCIe bridges 2705, 2515 and a high-bandwidth, low-latency cross switch 2710 (e.g., a PCIe cross switch implementing PCIe 4.0 or PCIe 5.0 interconnect). A set of point-to-point link endpoints 2702A-2702D can be coupled to bridging circuitry 2705, which can electrically or logically bridge the point-to-point links to cross switch 2710. In one embodiment, data can be routed through cross switch 2710 to a second connection bridging circuitry 2715, which can electrically or logically bridge the protocol of cross switch 2710 with the protocol of point-to-point link endpoints 2772A-2772D. When point-to-point endpoints 2702A-2702D and 2722A-2722D use NVHS technology, endpoint signaling is configured to be non-return-to-zero. In one embodiment, bridges 2705 and 2715 are configured to convert the non-return-to-zero signaling of the point-to-point link endpoints into differential signaling used by cross switch 2710, and to convert the differential signaling used by cross switch 2710 into non-return-to-zero signaling of the point-to-point link endpoints.

[0256] In one embodiment, the number of links used to bridge point-to-point endpoints 2702A-2702D and 2722A-2722D to cross switch 2710 can vary based on the protocol implemented at cross switch 2710. For example, to avoid bridging bottlenecks, bridges 2705 and 2715 can use a variable ratio of point-to-point links relative to PCIe links when connected to cross switch 2710. For example, a PCIe 4.0 interconnect can have a transmission rate of 16 GT / s (gigabits per second) per channel, while an NVLink 2.0 interconnect can have a transmission rate of 25 GT / s per channel. Therefore, more than one PCIe 4.0 channel can be used for each NVLink channel within NVLink to PCIe bridges 2705, 2715 to ensure that the bridge does not experience a transmission bottleneck. A fabrication processor 2730 is also present. In one embodiment, the structure processor 2730 is coupled to and configures each bridge 2705, 2715 and cross switch 2710 according to the power and performance requirements specified by the system.

[0257] Hardware support for persistent deep learning communication

[0258] In current machine learning frameworks, even if the communication graph between nodes is static, the framework still performs communication between nodes as if the system were using a dynamic graph. Figure 1This increases the overhead of communication tasks between nodes. For example, when performing communication operations across multiple nodes, memory and network device resources are allocated, used, and deallocated for each operation. In some systems, bandwidth allocation for communication operations can be performed on a per-transaction basis. If the network communication framework can be configured to take a static node graph, allowing some allocations to be persistent, the efficiency of network communication operations can be increased.

[0259] One embodiment described herein implements a persistent communication channel for networked inter-node communication in distributed machine learning. When configuring a distributed machine learning training system, the communication pattern between nodes is pre-specified, thereby specifying a list of communication operations and associated nodes. This list of communication operations is repeated throughout the distributed training process as forward and backward propagation computations are performed and gradients are distributed across nodes. Instead of paying the runtime cost associated with performing the communication operation on the network or communication structure each time an operation is executed, a persistent machine learning communication graph can be requested. The persistent machine learning communication graph allows the allocation of runtime network resources to be performed as a one-time cost. Resource allocation persists during the distributed training session. When the distributed training session completes, the allocated resources can be deallocated.

[0260] Implementing such embodiments involves modifications to the hardware and software within the architecture or network communication stack. For example, the software of a machine learning communication framework may instruct the communication hardware on specific sets of operations that should be persistent, as it may not be desirable for all operations to be persistent. For instance, certain setup, check pointers, and error correction operations may not be expected to be persistent. Furthermore, it may be advantageous to maintain non-persistence for some weight gradients or activation transfer functions. Therefore, the communication framework and communication hardware can be modified to include support for establishing persistent communication sessions between specific nodes on the network, and to include a list of operations that should be performed persistently during the duration of these sessions.

[0261] Figures 28A-28C A system for implementing persistent deep learning communication is shown. Figure 28A A persistent communication stack 2800 according to an embodiment is shown. Figure 28B The operation of persistent deep learning communication logic 2830 according to an embodiment is illustrated. Figure 28C The operation of resource management logic 2840 of a persistent deep learning communication system according to an embodiment is illustrated.

[0262] Figure 28A The persistent communication stack 2800 can be Figures 21A-21BThis is part of the machine learning scaling architecture shown. For example, in one embodiment, the communication module 2117 includes a persistent connection unit 2802, a network topology unit 2804, and a bandwidth / QoS unit 2806, each of which can be configured to interact with the communication module 2117 and the messaging library 2119 and the high-performance communication structure 2121 as described herein.

[0263] In one embodiment, persistent connection unit 2802 can set up communication buffers and communication scheduling at the start of a network communication session and reuse the communication context instead of repeatedly establishing and tearing down network connections during distributed training. Persistent connection unit 2802 can interact with network topology unit 2804 to associate network topology with a given communication pattern. Network nodes associated with distributed training operations can be identified, enumerated, and provided to persistent connection unit 2802. Persistent connection unit 2802 can communicate with persistent connection interface 2812 in message delivery library 2119. Persistent connection interface 2812 provides a mechanism by which resources of message delivery library 2119 can be indicated as persistent for a given communication session. When session resources are indicated as persistent, data, context, and configuration subsequently created for messages during the distributed training session are persistently allocated and maintained, whereby resource allocation is performed and maintained until the persistent session is indicated to be complete.

[0264] The communication architecture interface 2820 includes software and hardware elements for implementing communication via the high-performance communication architecture 2121. In one embodiment, the communication architecture interface 2820 includes a persistent connection interface 2822, a memory registration unit 2824, a network context unit 2826, and a flow control unit 2828. The communication architecture interface 2820 may additionally include other components associated with architecture interfaces known in the art, such as a control processor, memory, a forwarding ASIC, etc. In response to messages and / or commands received via a messaging library, the persistent connection interface 2822 can configure the hardware and software resources associated with the high-performance communication architecture 2121 to be allocated persistently, such that resources that will be cyclically allocated and deallocated will be maintained during a communication session.

[0265] The specific resources and contexts that become persistent can vary based on the type of communication structure interface 2820. In one embodiment, memory registration unit 2824 can persistently register memories for message transmission and reception. Memory registration includes pinning a virtual memory address associated with a memory buffer containing data to be transmitted or data to be received. In one embodiment, memory registration includes performing physical address translation on the virtual memory address associated with the memory buffer. In one embodiment, memory registration unit 2824 can store a record of persistently allocated memory buffers. In one embodiment, metadata for allocated buffers can indicate that a given buffer is persistently allocated. Deallocation of these buffers can be bypassed, and previously allocated buffers can be reused during subsequent network transmissions in a session.

[0266] In one embodiment, network context unit 2826 can persistently allocate network context information for message transmission and reception via the high-performance communication structure. For example, deallocation of persistently allocated context memory used for processing data associated with transport protocols can be bypassed. Previously allocated memory can be reused if it will be reallocated in another manner. In one embodiment, flow control unit 2828 can manage the rate of data transmission and reception via high-performance communication structure 2121. Typically, the network layer of high-performance communication structure 2121 utilizes flow control to prevent buffer overflow at the receiver. In one embodiment, a credit-based flow control system is used to track available slots within the receive buffer. When received data is pulled from the receive buffer, credits can be sent back to the sender of the received data. Since the sender and receiver groups within a session are known in advance, the flow control data structure can be established as a one-time cost before large-scale data transmission begins across nodes within the distributed training cluster.

[0267] like Figure 28B As shown, persistent deep learning communication logic 2830 can configure communication software and hardware for persistent memory allocation, network context, and hardware context information for network communication sessions executed during distributed training of a neural network. Logic 2830 can be configured by, for example... Figure 28A This is achieved through the communication module 2117, message transmission library 2119, and / or communication structure interface 2820 shown.

[0268] In one embodiment, logic 2830 may receive the identifier of the node to which a persistent network communication session is to be established, as shown in box 2831. A persistent session can be established with one or more nodes, and a set of identifiers specifying each node associated with the persistent communication session can be received. Logic 2830 may then resolve one or more network addresses of the nodes and persistently store one or more resolved network addresses, as shown in box 2832. In box 2834, logic 2830 may receive an indication that a set of network operations for which resource allocation will be persistent. It may not be desirable for all operations to be persistent, as it might be optimal if some setup and error checking operations were non-persistent. Logic 2830 may allocate resources for communicating with the nodes and mark the resources as persistent, as shown in box 2836. Resources can be marked as persistent by storing the resource's identifier in a data structure, or the resource's metadata can indicate that the resource will be persistently allocated. As shown in box 2837, logic 2830 may perform the requested network operations using the identified one or more nodes while maintaining the resource allocation associated with the operations marked as persistent. At box 2837, logic 2830 can deallocate persistently allocated resources after receiving an indication that the persistent session has ended.

[0269] like Figure 28C As shown, the operation of resource management logic 2840 in the persistent deep learning communication system may include: receiving a request at the communication framework to perform an operation associated with a persistent distributed training session, as shown in box 2841. If it is determined at box 2843 that the operation is marked as persistent, then logic 2840 may access resources previously allocated for that operation. If it is determined at box 2843 that the operation is not marked as persistent, then logic 2840 may perform a new resource allocation for that operation, as shown in box 2844. In some embodiments, the operation is not marked as persistent, but may be listed in a data structure or database of operations that are persistent for the communication session.

[0270] Serverless accelerator pooling for inference

[0271] A major challenge posed during machine learning inference is latency. While computational throughput is crucial for machine learning training, inference operations, though having lower computational requirements, are highly sensitive to latency, with optimal timeframes for inference execution typically measured in milliseconds. This latency sensitivity stems from the increasingly real-time nature of inference deployments. For example, inference requests are executed continuously through autonomous driving and navigation systems, and through computer vision or remote sensing systems associated with them. Furthermore, digital assistants can be configured to perform machine learning inference in response to user requests. Any latency exhibited by the system when inference is performed as part of an interactive user experience can negatively impact the user experience.

[0272] Large-scale, user-oriented inference can be implemented as a cloud-based, data center-based solution. When performing machine learning operations in the data center, data can be collected and pooled from a large number of clients (e.g., consumer devices) and sent to data center CPU servers or CPU clusters. The data is then transformed or modified into a format acceptable to the deployed machine learning framework or data model, and processed on parallel processing clusters (such as GPGPU clusters). In implementations where GPU-to-GPU architectures outperform GPU-to-controller architectures, CPU servers / clusters can introduce latency bottlenecks into data center inference systems.

[0273] Some embodiments described herein enable serverless accelerator pooling for inference operations. In one embodiment, an inference accelerator pool, which may be a GPGPU accelerator, FPGA accelerator, custom ASIC, or other type of inference accelerator, can be coupled to a high-bandwidth, low-latency switching fabric. The accelerator pool can be a “serverless” pool because a main CPU server and associated operating system are absent. Instead, a set of programmable network interfaces, low-power processors, and / or programmable fabric interfaces can be pre-configured by a fabric-attached CPU server. Once the network, fabric interfaces, or low-power processor systems on the accelerator pool are configured, the CPU server can be removed from the critical path, where inference requests are received directly at the accelerator pool and processed by the accelerator pool. In one embodiment, the accelerator pool can be virtualized, enabling device-level access as a virtual device within a virtual server scheme implemented within a data center.

[0274] Figures 29A-29C The hardware and associated software processes for implementing serverless accelerator pooling for inference, according to embodiments described herein, are illustrated. Figure 29A A data center 2900 including a serverless accelerator pool is shown according to an embodiment. Figure 29B An example of a CPU server and accelerator pool system according to an embodiment is shown. Figure 29C A process 2930 for configuring a serverless accelerator pool for inference, according to an embodiment, is shown.

[0275] like Figure 29AAs shown, data center 2900 may include front-end 2902, through which processing requests are received. Front-end 2902 may interface with a group of CPU servers 2904A-2904N. Each CPU server, such as CPU server 2904N, includes a set of network interface controllers (e.g., NIC 2914), memory 2912, application execution cluster 2910, and infrastructure interface 2807. The network interface controller including NIC 2914 can be used to connect CPU servers 2904A-2904B to front-end 2902. In various embodiments, various types of network interface controllers may be used, including but not limited to Ethernet, wireless bandwidth technology, omnidirectional path interconnect, or other high-speed network protocols. Memory 2912 is high-speed volatile or non-volatile random access memory and may be any type of system memory described herein. Application execution cluster 2910 includes one or more multi-core server processors configured to execute applications including virtual machines. The application execution cluster can execute machine learning applications that can utilize one or more inference accelerator pools (e.g., GPU pools 2908A-2908N), or the inference accelerator pools can be configured to directly respond to requests received via front-end 2902. The architecture interface 2907 in the CPU servers 2904A-2904N enables the application execution cluster 2910 to connect to the high-bandwidth switching architecture 2906. The high-bandwidth switching architecture 2906 can be any high-speed interconnect described herein, such as, but not limited to, PCIe or NVHS / NVLink.

[0276] In one embodiment, the inference accelerator pool is a GPU accelerator within GPU pools 2908A-2908N. Each GPU pool may include, for example, as in GPU pool 2908, memory 2922, one or more network interfaces (e.g., NIC 2924), one or more optional low-power processors 2920, GPU compute cluster 2918, and architecture interface 2917. In various embodiments, memory 2922 may be volatile or non-volatile system memory similar to memory 2912, or it may be a graphics memory pool, such as graphics DDR memory (e.g., GDDR5, GDDR5X, GDDR6, etc.). The network interface controller (e.g., NIC 2924) may be a network interface controller known in the art, such as NIC 2914. In one embodiment, the network interface controller of GPU pools 2908A-2908N includes additional programmable or processing elements to facilitate serverless operation of GPU pools 2908A-2908N. For example, one of the CPU servers 2904A-2904N may be configured with a set of addresses and static routes for the duration of an inference session. An optional low-power processor 2920 may reside in one or more of the GPU pools 2908A-2908N to facilitate data movement between memory 2922 and architecture interface 2917. Alternatively, architecture interface 2917 may include programmable resources and / or processing resources to perform operations that would otherwise be performed by a server processor (such as one of the processors in application execution cluster 2910 of CPU servers 2904A-2904N).

[0277] like Figure 29B As shown, the GPU-based accelerator pool 2908 can be used with, for example... Figure 24A The processing system 2400 is constructed in a similar manner, in which Figure 24A Processors 2402 and 2404 are removed from the chassis. Instead, the GPU computing cluster 2918 may include multiple general-purpose graphics processors (GPGPUs) 2422A-2422D and 2424A-2424D, which may be interconnected via a point-to-point interconnect network such as NVHS / NVLink (e.g., NVLink, NVLink 2.0, etc.). The GPU cluster 2918 may be interconnected with a high-bandwidth switching structure 2906 via fabric interfaces 2917A-2917D. One of the CPU servers (e.g., CPU server 2904A) may provide fabric interfaces 2917A-2917D, which may be programmable interfaces with processor logic.

[0278] The specific nature of the interaction between CPU servers 2904A-2904N and GPU pool 2908 can vary across embodiments. In one embodiment, GPU pool 2908 can be configured to couple GPGPUs 2422A-2422D, 2424A-2424D as a device client to one of CPU servers 2904A-2904N, as if the GPGPUs were located within the chassis of the respective coupled CPU server. In one embodiment, a single CPU server (e.g., CPU server 2904A) can configure GPU pool 2908 as an independent computing processor that can directly receive inference requests via high-bandwidth switching structure 2904 or via a network interface controller (e.g., NIC 2924).

[0279] Once CPU server 2904A is configured with GPU pool 2908, CPU server 2904A can be removed from the critical inference path. GPU pool 2908 can then directly receive inference requests for processing. For example, inference client 2901, such as an autonomous vehicle, voice processing client, virtual assistant, etc., can send formatted data directly to GPU pool 2908 for processing via network 2903 (e.g., the Internet), bypassing CPU servers 2904A-2904N.

[0280] In one embodiment, to achieve reduced latency for data center inference implementation, GPU pool 2908 may be located at the edge of the data center rather than at the data center core. In another embodiment, a serverless GPU pool with lower total cost of ownership and lower power requirements may be located closer to the inference request source than existing server / GPU pool deployments.

[0281] like Figure 29C As shown, the process 2930 for configuring the serverless accelerator pool for inference can be implemented by a CPU server. Once the accelerator pool is configured, the CPU server can be removed from the inference critical path. Alternatively, a single CPU server can be coupled to multiple accelerator pools. Although Figures 29A-29B The diagram shows a GPU pool, but the accelerator pool can be configured to use various types of machine learning optimized processing elements, including but not limited to GPGPUs, FPGAs, ASICs, or other types of computing elements optimized for machine learning computations.

[0282] In one embodiment, as shown in block 2932, process 2930 includes: the CPU server receiving a request to allocate one or more accelerator pools for operation within a data center. In block 2933, the CPU server may determine whether the accelerator pools will have an autonomous serverless pool configuration. For an autonomous serverless pool configuration, the CPU server may allocate programmable network and infrastructure interfaces to the accelerator pools to directly receive inference requests from clients, as shown in block 2934. Receiving a direct inference request at the accelerator pool means receiving an inference request from a client device, bypassing the use of the CPU server and its associated CPU server operating system. If no direct serverless configuration is requested, the CPU server may allocate programmable network and infrastructure interfaces of one or more accelerator pools to a client device acting as a CPU server, as shown in block 2935. In this configuration, multiple accelerator pools can be connected to a single CPU server via a high-bandwidth switching infrastructure. Multiple accelerator pools can then operate as accelerator clients acting as CPU servers, allowing a single CPU server to directly use a larger number of accelerators. The overhead associated with configuring programmable network interfaces for specific workloads is amortized over long-running workloads because the accelerator pool may remain in its allocated configuration for a period of time. This configuration reduces the number of CPU servers in the data center, where the reduced number of CPU servers can potentially be replaced by the accelerator pool.

[0283] Handling unexpected hardware malfunctions in autonomous vehicles

[0284] In distributed machine learning systems, if a graphics processing unit (GPU) within the system fails, alternative emergency routes for neural network operations can be enabled. Alternative communication graphs can be used to configure the communication framework that enables communication between compute nodes and GPUs within each compute node. If a CPU or GPU fails within the distributed training network, the computational operations of the neural network can be rebalanced across the functional parts of the distributed training network, where model or parameter data associated with the failed part is redistributed to other nodes. However, it is crucial that inference systems, including distributed inference systems, can recover from sudden hardware failures, especially when such failures occur during operation within an autonomous vehicle (ASDV). If a hardware failure occurs within an ASDV inference system, particularly when passengers are present, the system may need to recover in a manner that keeps the vehicle's passengers safe, while also considering the safety of passengers in other nearby vehicles. Therefore, multi-layered hardware failover mechanisms may be required to ensure the vehicle at least navigates to a safe location and reaches a safe stop. In vehicles with driver control, one available option for the system is to notify the driver to take control of the vehicle. In fully autonomous vehicles with passenger control, the machine learning system must be able to navigate until a safe stop.

[0285] This document describes hardware and software that enable an inference system to handle or recover from sudden hardware failures in an emergency mode. In one embodiment, cascading fault recovery techniques are enabled, where error recovery is attempted at the software level. If the software effort fails to restore the inference system to at least partial functionality, hardware-based measures can be taken.

[0286] If a software fault is detected (e.g., corruption within the software stack), the system will attempt to reconstruct the data model based on captured checkpoints to maintain the data model's current operational state. This technique is particularly useful when any aspect of the current data model has been adjusted relative to the stored data model, for example, if any form of neural network retraining has been performed or is currently underway. Figure 30A As shown, several portions of the training or data model 3002 can be saved as recovery / tracking points 3004, which can be used to rebuild the data model in the event of software or data corruption (e.g., due to software failure or a one-time hardware failure event). Recovery / tracking points 3004 can be used to rebuild or recover data, for example, if it is necessary to migrate processing operations to different processors or nodes within the computing system for inference or retraining.

[0287] Figure 30B A machine learning processing system 3000 with multiple redundancies according to an embodiment is illustrated. In one embodiment, the machine learning processing system 3000 is a processing system for deployment, for example, at least a semi-autonomous self-driving vehicle. The machine learning processing system 3000 includes a set of inference processors 3010A-3010B, wherein a first inference processor 3010A is a main processor, and a second inference processor 3010B is reserved as a backup processor. The inference processors 3010A-3010B may each reside on an on-chip system integrated circuit and may access shared memory and a storage system.

[0288] Inference processors 3010A-3010B are coupled to interconnect 3012. The interconnect can also connect to external network interface 3018, failsafe controller 3016, infotainment processor 3014, and general-purpose processor 3015 (such as an application processor or central processing unit (CPU)). External network interface 3018 can be a wireless data interface, such as an LTE or GSM interface. External network interface 3018 can enable communication with cloud server 3020. Infotainment processor 3014 can be a graphics processor dedicated to rendering graphics for implementing the virtual cockpit, virtual measurement system, mapping and navigation system, and / or multimedia interface of ASDV. General-purpose processor 3015 can be an application processor for executing applications provided by ASDV and can work in conjunction with infotainment processor 3014. In one embodiment, the fail-safe controller 3016 may be a microcontroller or a low-power processor capable of performing a subset of the functions provided by the inference processors 3010A-3010B, the infotainment processor 3014, and / or the general-purpose processor 3015. If a software or hardware error renders these processors inoperable, the fail-safe controller can temporarily replace such processors. Furthermore, the fail-safe controller 3016 can coordinate the switching of processing operations between compatible processors in the event of a hardware failure.

[0289] Handling unexpected hardware failures in autonomous vehicles can be performed as a multi-stage process. For example... Figure 30A The recovery / tracking point 3004 shown can be periodically sent to the cloud server 3020 via an external network interface. Furthermore, the cloud server 3020 can maintain an emergency algorithm for safe driving, which can be retrieved via the external network interface 3018 in the event of loss of critical data or hardware functionality, allowing the machine learning processing system 3000 to at least navigate the ASDV to a safe parking spot in a safe location, such as on the side of the road and avoiding traffic flow.

[0290] Figure 31 The diagram illustrates computational logic 3100 associated with additional algorithms for handling sudden hardware failures on ASDV. In one embodiment, computational logic 3100 (which may be composed of...) Figure 30B The firmware executed on the fail-safe controller 3016 provides the ability to monitor machine learning processing systems (such as...). Figure 30B The operation of various software and hardware processes within the machine learning processing system (3000).

[0291] In one embodiment, the fail-safe controller can detect a critical fault in a component of the autonomous driving neural network processing system, as shown in box 3102. The fail-safe controller can then trigger a software system reset on the faulty component and attempt to reload the data model from previously saved checkpoints, as shown in box 3104. Previously saved checkpoints can be loaded from local storage. If local storage is unavailable, previously saved checkpoints can be loaded from a cloud server via an external network interface. In one embodiment, reloading the data model from the cloud server may also include prefetching algorithms for safe driving, which could later be used during the recovery process. If the fail-safe controller determines at box 3105 that the system has recovered due to the software system reset performed at box 3104, the fail-safe controller can warn of a recoverable error at box 3106. The warning can be displayed to the ASDV operator, logged in the logging system, and / or reported to the cloud server. Repeated recoverable errors may indicate an impending critical hardware failure.

[0292] If the system is not restored at box 3105, the failover controller can determine at box 3107 whether any shared computing resources exist for the failed system. If shared resources are available, as determined at box 3107, the failover controller can migrate neural network processing to the shared computing resources, as shown in box 3108. If shared computing resources are unavailable, as determined at box 3107, the failover controller can migrate the neural network or data model to the failover controller, which can be configured with sufficient processing power to simply navigate and drive the ASDV to a safe parking spot away from traffic flow.

[0293] The specific capabilities of the processor to which the neural network processing is migrated can be determined at box 3110. In response to the detected capabilities, the fail-safe controller or the current master processor can adjust autonomous characteristics based on the current capabilities, as shown at box 3112. If equivalent computing resources are available, for example, if inference processor 3010B is available in the event of a failure of inference processor 3010A, operation can continue normally, although a faulty component warning can be given and the ASDV can be flagged for service purposes. Migration can still be performed even when non-equivalent shared computing resources are available, although operation may continue at a potentially degraded service level. For example, referring to Figure 30, if a hardware error causes both inference processors 3010A and 3010B to fail, operation can continue by utilizing the general-purpose processor 3015 and / or the infotainment processor 3014 to perform some of the inference operations, although overall system functionality may be limited. For example, a lower maximum speed may be imposed on the ASDV due to the reduced available computing throughput level. In this operating mode, multimedia or infotainment functions may be limited. Furthermore, autonomous operation may be limited to navigating the ASDV to a safe location for recovery. In one embodiment, an algorithm for safe driving previously retrieved from cloud server 3020 can be loaded onto general-purpose processor 3015 and / or infotainment processor 3014, wherein the algorithm has been specifically optimized to operate on backup processing hardware.

[0294] Figure 32This is a block diagram of a data processing system 3200 according to embodiments described herein. The data processing system 3200 is a heterogeneous processing system having a processor 3202, a unified memory 3210, and a GPGPU 3220 including machine learning acceleration logic. The processor 3202 and GPGPU 3220 can be either a processor as described herein or a GPGPU / parallel processor. The processor 3202 can execute instructions stored in system memory 3212 for a compiler 3215. The compiler 3215 executes on the processor 3202 to compile source code 3214A into compiled code 3214B. The compiled code 3214B can include code executable by the processor 3202 and / or code executable by the GPGPU 3220. During compilation, the compiler 3215 can perform operations to insert metadata, including hints about the level of data parallelization present in the compiled code 3214B and / or hints about data locality associated with threads that will be dispatched based on the compiled code 3214B. The compiler 3215 may include the information necessary to perform such operations, or may perform such operations with the assistance of a runtime library 3216, such as the Machine Learning Extension Library (MLSL) described herein. The runtime library 3216 may also facilitate the compiler 3215 in compiling source code 3214A and includes instructions that, at runtime, are associated with compiled code 3214B to facilitate the execution of compiled instructions on the GPGPU 3220.

[0295] Unified memory 3210 represents a unified address space accessible by processor 3202 and GPGPU 3220. Unified memory includes system memory 3212 and GPGPU memory 3218. GPGPU memory 3218 includes GPGPU local memory 3228 within GPGPU 3220, and may also include some or all of the memory in system memory 3212. For example, compiled code 3214B stored in system memory 3212 may also be mapped to GPGPU memory 3218 for access by GPGPU 3220.

[0296] The GPGPU 3220 includes multiple compute blocks 3224A-3224N, each comprising one or more parallel processing clusters. The GPGPU 3220 also includes a set of registers 3224, a cache memory 3226, and a power and performance module 3225, which can be used as a shared resource for the compute blocks 3224A-3224N. The power and performance module 3225 can be configured to regulate the power delivery and clock frequency of the compute blocks 3224A-3224N for power gate management of idle components within the compute blocks 3224A-3224N under heavy workloads. The GPGPU 3220 includes GPGPU local memory 3228, which is a physical memory shared with the GPGPU 3220 on the graphics card or multi-chip module.

[0297] In one embodiment, the GPGPU 3220 includes graphics and computation acceleration logic, which includes an instruction fetch and decode unit 3221, a scheduler unit 3222, and a machine learning fixed-function unit 3223. The fetch and decode unit 3221 is a fetch and decode unit that includes logic for fetching and decoding instructions to be computed by the GPGPU 3220. In one embodiment, the instructions to be executed may be ordered and / or serialized via the scheduler unit 3222 for a set of operations and / or micro-operations to be executed via computation blocks 3224A-3224N and / or the machine learning fixed-function unit 3223.

[0298] In one embodiment, the machine learning fixed-function unit 3223 is an application-specific integrated circuit (ASIC) explicitly and specifically configured to perform a large number of parallel matrix multiplication operations. In one embodiment, the machine learning fixed-function unit 3223 is configured to perform matrix multiplication on a convolutional filter having a non-power-four filter size. In another embodiment, the machine learning fixed-function unit 3223 is a field-programmable gate array (FPGA) that provides fixed-function logic that can be updated between workloads.

[0299] In some embodiments, the GPGPU 3220 includes an integrated architecture interface 3230 and an architecture interface cache 3232. In one embodiment, the integrated architecture interface 3230 additionally includes an MLSL architecture module 3231, which enables the architecture interface to provide hardware acceleration for certain MLSL operations. The architecture interface 3230 may be... Figure 28AThis is a variant of the high-performance communication architecture 1521. The architecture interface 3230 has an address space mapped to at least a portion of the GPGPU local memory 3228, and in one embodiment, it can participate in the unified memory 3210 shared by the processor 3202 and the GPGPU 3220. The architecture interface cache 3232 is used to cache data received from or to be sent to the communication architecture, which enables data communication between compute nodes. In one embodiment, when a computation result is computed by the GPGPU 3220 and stored in the GPGPU local memory 3228, the architecture interface 3230 can send data from the GPGPU local memory 3228 to other compute nodes. In such an embodiment, it is not necessary to send data to the system memory 3212 unless the data is needed for use by an application executing on the processor 3202.

[0300] MLSL architecture module 3231 is configured to facilitate low-latency data transfer between nodes. In one embodiment, MLSL architecture module 3231 may receive a set of addresses within GPGPU local memory 3228 associated with data objects managed by the MLSL runtime (e.g., runtime library 3216). For example, an address range for storing an output buffer to store activation data to be generated by GPGPU 3220 may be provided to MLSL architecture module 3231. MLSL architecture module 3231 may then be configured to monitor updates in the address range. When the address range receives a write of activation data output by GPGPU 3220, MLSL architecture module 3231 may directly schedule a pass to architecture interface 3230 to deliver the output activation data. MLSL architecture module 3231 may also be used to implement the fine-grained communication and point-to-point hardware communication techniques described herein.

[0301] The protocols supported by the structure interface 3230 can be varied. In one embodiment, the structure interface 3230 is a high-speed Ethernet interface. In one embodiment, the structure interface 3230 is an omnidirectional path interconnect interface. In one embodiment, the structure interface 3230 is an unlimited bandwidth technology interface. In one embodiment, the structure interface 3230 is a version of the NVLink interface. Other structure interface technologies may also be supported.

[0302] It should be understood that, for some implementations, systems equipped with fewer or more components than those described above may be preferred. Therefore, the configuration of the data computing system 3200 varies between implementations depending on numerous factors such as price constraints, performance requirements, technological improvements, or other factors. The embodiments described herein can be widely applied in high-performance computing and machine learning training environments. Therefore, this specification anticipates that the data processing system 3200, as well as other data processing and computing systems described herein, will be implemented as a high-performance server or server array within a distributed computing system. Such a distributed computing system can be implemented within a data center or server cluster. However, the embodiments are not limited to such implementations, and the techniques described herein can also be used in large-scale distributed computing systems for lower-performance devices, such as, but not limited to, mobile or handheld devices, tablet computing devices, or connected consumer electronic devices.

[0303] Additional example graphics processing systems

[0304] The details of the embodiments described above can be incorporated into the graphics processing system and device described below. Figures 33 to 37 The graphics processing systems and devices shown illustrate any and all of the technologies described above, including systems and graphics processing hardware.

[0305] System Overview

[0306] Figure 33 This is a block diagram illustrating a computer system 3300 configured to implement one or more aspects of the embodiments described herein. The computing system 3300 includes a processing subsystem 3301 having one or more processors 3302 and a system memory 3304, the one or more processors and the system memory communicating via an interconnect path, the interconnect path including a memory hub 3305. The memory hub 3305 may be a separate component within a chipset assembly or integrated within one or more processors 3302. The memory hub 3305 is coupled to an I / O subsystem 3311 via a communication link 3306. The I / O subsystem 3311 includes an I / O hub 3307 that enables the computing system 3300 to receive input from one or more input devices 3308. Additionally, the I / O hub 3307 enables a display controller (which may be included in one or more processors 3302) to provide output to one or more display devices 3310A. In one embodiment, one or more display devices 3310A coupled to the I / O hub 3307 may include local display devices, internal display devices, or embedded display devices.

[0307] In one embodiment, the processing subsystem 3301 includes one or more parallel processors 3312 coupled to a memory hub 3305 via a bus or other communication link 3313. The communication link 3313 can be one of any number of standards-based communication link technologies or protocols (such as, but not limited to, PCI Express), or a vendor-specific communication interface or communication architecture. In one embodiment, the one or more parallel processors 3312 form a computation-centric parallel or vector processing system including a large number of processing cores and / or processing clusters such as integrated many-core (MIC) processors. In one embodiment, the one or more parallel processors 3312 form a graphics processing subsystem that can output pixels to one of one or more display devices 3310A coupled via an I / O hub 3307. The one or more parallel processors 3312 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 3310B.

[0308] Within the I / O subsystem 3311, system storage unit 3314 can be connected to I / O hub 3307 to provide storage for computing system 3300. I / O switch 3316 can be used to provide an interface mechanism to enable connections between I / O hub 3307 and other components that can be integrated into the platform, such as network adapter 3318 and / or wireless network adapter 3319, as well as various other devices that can be added via one or more plug-in devices 3320. Network adapter 3318 can be an Ethernet adapter or another wired network adapter. Wireless network adapter 3319 can include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more radio devices.

[0309] The computing system 3300 may include other components not explicitly shown, such as USB or other port connectors, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 3307. Figure 33 The communication paths for interconnecting various components can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or (multiple) other bus or point-to-point communication interfaces and / or protocols such as NV-Link high-speed interconnect or interconnect protocols known in the art.

[0310] In one embodiment, one or more parallel processors 3312 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and said circuitry constitutes a graphics processing unit (GPU). In another embodiment, one or more parallel processors 3312 incorporate circuitry optimized for general-purpose processing while retaining the underlying computing architecture described in more detail herein. In yet another embodiment, components of the computing system 3300 may be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 3312, a memory hub 3305, processor(s)3302, and an I / O hub 3307 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 3300 may be integrated into a single package to form a system-in-package (SIP) configuration. In other embodiments, at least a portion of the components of the computing system 3300 may be integrated into a multi-chip module (MCM) that may interconnect with other MCMs to form a modular computing system.

[0311] It should be understood that the computing system 3300 shown herein is exemplary and variations and modifications are possible. The connection topology can be modified as needed, including the number and arrangement of bridges, the number of processors(multiple) 3302, and the number of parallel processors(multiple) 3312. For example, in some embodiments, system memory 3304 is connected directly to processors(multiple) 3302 instead of via bridges, while other devices communicate with system memory 3304 via memory hub 3305 and processors(multiple) 3302. In other alternative topologies, parallel processors(multiple) 3312 are connected to I / O hub 3307 or directly to one or more processors 3302, instead of to memory hub 3305. In other embodiments, I / O hub 3307 and memory hub 3305 may be integrated into a single chip. Some embodiments may include two or more groups of processors(multiple) 3302 attached via multiple sockets, which may be coupled to two or more instances of parallel processors(multiple) 3312.

[0312] Some specific components shown in this document are optional and may not be included in all implementations of the computing system 3300. For example, any number of plug-in cards or peripheral devices may be supported, or some components may be omitted. Furthermore, some architectures may be described using different terminology. Figure 33 Similar components are shown. For example, in some architectures, the memory hub 3305 may be referred to as the Northbridge, while the I / O hub 3307 may be referred to as the Southbridge.

[0313] Figure 34AA parallel processor 3400 according to an embodiment is illustrated. Various components of the parallel processor 3400 can be implemented using one or more integrated circuit devices such as a programmable processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). According to an embodiment, the illustrated parallel processor 3400 is... Figure 33 The above are variations of one or more parallel processors 3312.

[0314] In one embodiment, the parallel processor 3400 includes a parallel processing unit 3402. The parallel processing unit includes an I / O unit 3404 that enables communication with other devices, including other instances of the parallel processing unit 3402. The I / O unit 3404 may be directly connected to other devices. In one embodiment, the I / O unit 3404 is connected to other devices via a hub or switch interface, such as a memory hub 3305. The connection between the memory hub 3305 and the I / O unit 3404 forms a communication link 3313. Within the parallel processing unit 3402, the I / O unit 3404 is connected to a host interface 3406 and a memory crossbar switch 3416, wherein the host interface 3406 receives commands relating to performing processing operations, and the memory crossbar switch 3416 receives commands relating to performing memory operations.

[0315] When host interface 3406 receives a command buffer via I / O unit 3404, host interface 3406 can route work operations for executing those commands to front end 3408. In one embodiment, front end 3408 is coupled to scheduler 3410, which is configured to assign commands or other work items to processing cluster array 3412. In one embodiment, scheduler 3410 ensures that processing cluster array 3412 is correctly configured and in an active state before assigning tasks to processing clusters in processing cluster array 3412. In one embodiment, scheduler 3410 is implemented via firmware logic executed on a microcontroller. Microcontroller-implemented scheduler 3410 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 3412. In one embodiment, host software can validate workloads scheduled on processing array 3412 via one of a plurality of graphics processing doorbell mechanisms. These workloads can then be automatically distributed by the scheduler 3412 logic within the scheduler microcontroller across the processing array 3410.

[0316] The processing cluster array 3412 may include up to "N" processing clusters (e.g., cluster 3414A, cluster 3414B, up to cluster 3414N). Each cluster 3414A through 3414N of the processing cluster array 3412 can execute a large number of concurrent threads. The scheduler 3410 may use various scheduling and / or work distribution algorithms to allocate work to the clusters 3414A through 3414N of the processing cluster array 3412, and these algorithms may vary depending on the workload caused by each type of program or computation. Scheduling may be handled dynamically by the scheduler 3410, or it may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 3412. In one embodiment, the different clusters 3414A through 3414N of the processing cluster array 3412 may be assigned to process different types of programs or to perform different types of computations.

[0317] The processing cluster array 3412 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 3412 is configured to perform general-purpose parallel computing operations. For example, the processing cluster array 3412 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0318] In one embodiment, the processing cluster array 3412 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 3400 is configured to perform graphics processing operations, the processing cluster array 3412 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic, tessellation logic, and other vertex processing logic for performing texture operations. Additionally, the processing cluster array 3412 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 3402 may transfer data from system memory via I / O unit 3404 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 3422) and then written back to system memory.

[0319] In one embodiment, when the parallel processing unit 3402 is used to perform graphics processing, the scheduler 3410 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations across multiple clusters 3414A to 3414N of the processing cluster array 3412. In some embodiments, portions of the processing cluster array 3412 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 3414A to 3414N can be stored in a buffer to allow intermediate data to be transferred between the clusters 3414A to 3414N for further processing.

[0320] During operation, the processing cluster array 3412 may receive processing tasks to be executed via scheduler 3410, which receives commands defining the processing tasks from front end 3408. For graphics processing operations, processing tasks may include data to be processed, such as surface (patch) data, graph data, vertex data, and / or pixel data, as well as state parameters defining how the data is processed and indices of commands (e.g., which program to execute). Scheduler 3410 may be configured to retrieve indices corresponding to tasks or may receive indices from front end 3408. Front end 3408 may be configured to ensure that processing cluster array 3412 is configured to be active before a workload specified by an incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0321] Each of one or more instances of the parallel processing unit 3402 may be coupled to the parallel processor memory 3422. The parallel processor memory 3422 may be accessed via a memory crossbar switch 3416, which receives memory requests from the processing cluster array 3412 and the I / O unit 3404. The memory crossbar switch 3416 may access the parallel processor memory 3422 via a memory interface 3418. The memory interface 3418 may include a plurality of partition units (e.g., partition units 3420A, 3420B, up to partition units 3420N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 3422. In one implementation, the number of partition units 3420A to 3420N is configured to be equal to the number of memory cells, such that a first partition unit 3420A has a corresponding first memory cell 3424A, a second partition unit 3420B has a corresponding memory cell 3424B, and the Nth partition unit 3420N has a corresponding Nth memory cell 3424N. In other embodiments, the number of partition units 3420A to 3420N may not be equal to the number of memory devices.

[0322] In various embodiments, memory cells 3424A to 3424N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory cells 3424A to 3424N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will understand that the specific implementation of memory cells 3424A to 3424N can vary and can be selected from one of a variety of conventional designs. Render targets, such as frame buffers or texture maps, may be stored on memory cells 3424A to 3424N, thereby allowing partitioning cells 3420A to 3420N to write portions of each render target in parallel to efficiently utilize the available bandwidth of parallel processor memory 3422. In some embodiments, to support a unified memory design utilizing system memory along with local cache memory, local instances of parallel processor memory 3422 may be excluded.

[0323] In one embodiment, any one of the clusters 3414A to 3414N of the processing cluster array 3412 can process data to be written to any one of the memory cells 3424A to 3424N within the parallel processor memory 3422. The memory crossbar switch 3416 can be configured to pass the output of each cluster 3414A to 3414N to any partition cell 3420A to 3420N or another cluster 3414A to 3414N, which can perform additional processing operations on the output. Each cluster 3414A to 3414N can communicate with the memory interface 3418 via the memory crossbar switch 3416 to perform read or write operations for various external memory devices. In one embodiment, the memory crossbar switch 3416 may be connected to the memory interface 3418 to communicate with the I / O unit 3404, and may be connected to a local instance of the parallel processor memory 3422, thereby enabling processing units within different processing clusters 3414A to 3414N to communicate with system memory or other memory that is not local to the parallel processing unit 3402. In one embodiment, the memory crossbar switch 3416 may use virtual channels to separate traffic flows between clusters 3414A to 3414N and partition units 3420A to 3420N.

[0324] While a single instance of the parallel processing unit 3402 is shown within the parallel processor 3400, any number of instances of the parallel processing unit 3402 can also be included. For example, multiple instances of the parallel processing unit 3402 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. Even if different instances have different numbers of processing cores, different amounts of local parallel processor storage, and / or other configuration differences, different instances of the parallel processing unit 3402 can be configured to operate interactively. For example, in one embodiment, some instances of the parallel processing unit 3402 may include higher precision floating-point units relative to other instances. Systems incorporating one or more instances of the parallel processing unit 3402 or the parallel processor 3400 can be implemented in various configurations and form factors, including but not limited to desktop computers, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0325] Figure 34B This is a block diagram of a partitioning system 3420 according to an embodiment. In one embodiment, the partitioning system 3420 is... Figure 34AAn example of one of partition units 3420A to 3420N. As shown, partition unit 3420 includes an L2 cache 3421, a frame buffer interface 3425, and a ROP 3426 (raster operation unit). The L2 cache 3421 is a read / write cache configured to perform load and store operations received from memory crossbar switch 3416 and ROP 3426. Read miss and urgent write-back requests are output from the L2 cache 3421 to the frame buffer interface 3425 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 3425 for processing. In one embodiment, the frame buffer interface 3425 interacts with one of the memory cells in the parallel processor memory, such as memory cells 3424A to 3424N of FIG. 34 (e.g., within parallel processor memory 3422).

[0326] In graphics applications, the ROP 3426 is a processing unit that performs raster operations such as stencil printing, z-testing, blending, etc. The ROP 3426 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, the ROP 3426 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. The type of compression performed by the ROP 3426 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, Δ color compression is performed on the depth and color data on a tile-by-tile basis.

[0327] In some embodiments, ROP 3426 is included within each processing cluster (e.g., clusters 3414A to 3414N of FIG. 34) instead of within partition unit 3420. In this embodiment, read and write requests for pixel data are transmitted via memory crossbar switch 3416 instead of pixel fragment data. The processed graphics data can be displayed on a display device such as... Figure 33 On one or more display devices 3310, routed by processor(s) 3302 for further processing, or by... Figure 34A One of the processing entities within the parallel processor 3400 is routed for further processing.

[0328] Figure 34CThis is a block diagram of a processing cluster 3414 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 3414A to 3414N of FIG. 34. The processing cluster 3414 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific input dataset. In some embodiments, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of substantially synchronous threads using a common instruction unit configured to issue instructions to a set of processing engines within each of the processing cluster. Unlike the SIMD execution mechanism, where all processing engines typically execute the same instructions, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing mechanism represents a subset of the functionality of the SIMT processing mechanism.

[0329] The operation of the processing cluster 3414 can be controlled via a pipeline manager 3432 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 3432 receives instructions from the scheduler 3410 of Figure 34 and manages the execution of those instructions via the graphics multiprocessor 3434 and / or texture units 3436. The graphics multiprocessor 3434 shown is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included within the processing cluster 3414. One or more instances of the graphics multiprocessor 3434 can be included within the processing cluster 3414. The graphics multiprocessor 3434 can process data, and a data crossover switch 3440 can be used to distribute the processed data to one of several possible destinations, including other shading units. The pipeline manager 3432 can facilitate the distribution of processed data by specifying destinations for the data to be distributed via the data crossover switch 3440.

[0330] Each graphics multiprocessor 3434 within the processing cluster 3414 may include the same group of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). The functional execution logic can be configured in a pipelined manner, where new instructions can be issued before completing previous instructions. The functional execution logic supports various operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and calculations of various algebraic functions. In one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units can exist.

[0331] Instructions transmitted to the processing cluster 3414 constitute threads. A group of threads executing on a set of parallel processing engines is a thread group. Thread groups execute the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 3434. A thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 3434. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle of processing the thread group. A thread group may also include more threads than the number of processing engines within the graphics multiprocessor 3434. When a thread group includes more threads than the number of processing engines within the graphics multiprocessor 3434, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 3434.

[0332] In one embodiment, the graphics multiprocessor 3434 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 3434 may forgo the internal cache and instead use a cache memory (e.g., L1 cache 3408) within the processing cluster 3414. Each graphics multiprocessor 3434 may also access an L2 cache within a partition unit (e.g., partition units 3420A to 3420N of FIG. 34) shared across all processing clusters 3414, and this cache can be used to transfer data between threads. The graphics multiprocessor 3434 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory outside the parallel processing unit 3402 may be used as global memory. Embodiments where the processing cluster 3414 includes multiple instances of the graphics multiprocessor 3434 may share common instructions and data that can be stored in the L1 cache 3408.

[0333] Each processing cluster 3414 may include an MMU 3445 (Memory Management Unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 3445 may reside within the memory interface 3418 of FIG. 34. The MMU 3445 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses and optionally cache line indexes. The MMU 3445 may include an address translation lookahead buffer (TLB) or cache that may reside within the graphics multiprocessor 3434 or the L1 cache or processing cluster 3414. Physical addresses are processed to distribute surface data access locality to achieve efficient request interleaving between partition units. Cache line indexes can be used to determine whether a request for a cache line is a hit or a miss.

[0334] In graphics and computing applications, processing cluster 3414 can be configured such that each graphics multiprocessor 3434 is coupled to texture unit 3436 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 3434, and is retrieved as needed from an L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 3434 outputs a processed task to data crossover switch 3440 to provide the processed task to another processing cluster 3414 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via memory crossover switch 3416. Pre-ROP (Pre-Raster Operation Unit) 3442 is configured to receive data from the graphics multiprocessor 3434 and direct the data to ROP units, which can be located using partitioned units (e.g., partitioned units 3420A to 3420N of FIG. 34) as described herein. The preROP 3442 unit can optimize color blending, organize pixel color data, and perform address translation.

[0335] It should be understood that the core architecture described herein is exemplary and variations and modifications are possible. For example, any number of processing units such as graphics multiprocessors 3434, texture units 3436, preROP 3442, etc., can be included within the processing cluster 3414. Furthermore, although only one processing cluster 3414 is shown, the parallel processing units as described herein can include any number of instances of the processing cluster 3414. In one embodiment, each processing cluster 3414 can be configured to operate independently of other processing clusters 3414 using separate and different processing units, L1 caches, etc.

[0336] Figure 34D A graphics multiprocessor 3434 according to one embodiment is illustrated. In such an embodiment, the graphics multiprocessor 3434 is coupled to a pipeline manager 3432 of a processing cluster 3414. The graphics multiprocessor 3434 has an execution pipeline including, but not limited to, an instruction cache 3452, an instruction unit 3454, an address mapping unit 3456, a register file 3458, one or more general-purpose graphics processing unit (GPGPU) cores 3462, and one or more load / store units 3466. The GPGPU cores 3462 and the load / store units 3466 are coupled to a cache memory 3472 and a shared memory 3470 via a memory and cache interconnect 3468.

[0337] In one embodiment, instruction cache 3452 receives a stream of instructions to be executed from pipeline manager 3432. These instructions are cached in instruction cache 3452 and dispatched for execution by instruction unit 3454. Instruction unit 3454 can dispatch instructions as thread groups (e.g., threads), with each thread in the thread group assigned to a different execution unit within GPGPU core 3462. Instructions can access any of the local, shared, or global address spaces by specifying an address within a unified address space. Address mapping unit 3456 can be used to translate addresses in the unified address space into different memory addresses accessible by load / store unit 3466.

[0338] Register file 3458 provides a set of registers for the functional units of graphics multiprocessor 3424. Register file 3458 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 3424 (e.g., GPGPU core 3462, load / store unit 3466). In one embodiment, register file 3458 is partitioned among each of the functional units such that each functional unit is allocated a dedicated portion of register file 3458. In one embodiment, register file 3458 is partitioned between different meridians being executed by graphics multiprocessor 3424.

[0339] Each GPGPU core 3462 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 3424. According to embodiments, the architecture of the GPGPU core 3462 may be similar or different. For example, in one embodiment, a first portion of the GPGPU core 3462 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 floating-point arithmetic standard or enable variable-precision floating-point arithmetic. Additionally, the graphics multiprocessor 3424 may also include one or more fixed-function or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also contain fixed-function or special-function logic.

[0340] In one embodiment, the GPGPU core 3462 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 3462 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0341] The memory and cache interconnect 3468 is an interconnect network that connects each of the functional units of the graphics multiprocessor 3424 to the register file 3458 and the shared memory 3470. In one embodiment, the memory and cache interconnect 3468 is a cross-switch interconnect that allows the load / store unit 3466 to perform load and store operations between the shared memory 3470 and the register file 3458. The register file 3458 can operate at the same frequency as the GPGPU core 3462, thus data transfer between the GPGPU core 3462 and the register file 3458 has very low latency. The shared memory 3470 can be used to implement communication between threads executing on functional units within the graphics multiprocessor 3434. For example, the cache memory 3472 can be used as a data cache to cache texture data communicated between functional units and texture units 3436. The shared memory 3470 can also be used as a cached, managed program. In addition to the automatically cached data stored in cache memory 3472, threads executing on GPGPU core 3462 can also programmatically store data in shared memory.

[0342] Figures 35A to 35B An additional graphics multiprocessor according to an embodiment is shown. The graphics multiprocessors 3525 and 3550 shown are... Figure 34C Variants of the 3434 graphics multiprocessor. The 3525 and 3550 graphics multiprocessors shown can be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0343] Figure 35A A graphics multiprocessor 3525 according to an additional embodiment is shown. The graphics multiprocessor 3525 includes, relative to... Figure 34DThe graphics multiprocessor 3434 includes multiple additional instances of its execution resource units. For example, the graphics multiprocessor 3525 may include multiple instances of instruction units 3532A to 3532B, register files 3534A to 3534B, and multiple texture units 3544A to 3544B. The graphics multiprocessor 3525 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 3536A to 3536B, GPGPU cores 3537A to 3537B, GPGPU cores 3538A to 3538B) and multiple sets of load / store units 3540A to 3540B. In one embodiment, the execution resource units have a common instruction cache 3530, a texture and / or data cache memory 3542, and a shared memory 3546.

[0344] Various components can communicate via interconnect fabric 3527. In one embodiment, interconnect fabric 3527 includes one or more cross switches to enable communication between components of the graphics multiprocessor 3525. In another embodiment, interconnect fabric 3527 is a separate, high-speed network structure layer on which each component of the graphics multiprocessor 3525 is stacked. Components of the graphics multiprocessor 3525 communicate with remote components via interconnect fabric 3527. For example, GPGPU cores 3536A-3536B, 3537A-3537B, and 35378A-3538B can each communicate with shared memory 3546 via interconnect fabric 3527. Interconnect fabric 3527 can arbitrate communication within the graphics multiprocessor 3525 to ensure fair bandwidth allocation among components.

[0345] Figure 35B A graphics multiprocessor 3550 according to an additional embodiment is shown. Figure 34D and Figure 35A As shown, the graphics processor includes multiple sets of execution resources 3556A to 3556D, each set of execution resources including multiple instruction units, register files, GPGPU cores, and load memory units. Execution resources 3556A to 3556D can work with (multiple) texture units 3560A to 3560D to perform texture operations, while sharing instruction cache 3554 and shared memory 3562. In one embodiment, execution resources 3556A to 3556D can share instruction cache 3554, shared memory 3562, and multiple instances of texture and / or data cache memories 3558A to 3558B. Various components can be connected via... Figure 35A The interconnect structure 3527 communicates with the interconnect structure 3552 similar to the interconnect structure 3552.

[0346] Those skilled in the art will understand that Figure 33 , Figures 34A to 34Dand Figures 35A to 35B The architecture described herein is descriptive and does not limit the scope of the embodiments of the invention. Therefore, the techniques described herein can be implemented on any appropriately configured processing unit, including but not limited to: one or more mobile application processors; one or more desktop computer or server central processing units (CPUs), including multi-core CPUs; one or more parallel processing units such as the parallel processing unit 3402 of FIG. 34; and one or more graphics processors or dedicated processing units, without departing from the scope of the embodiments described herein.

[0347] In some embodiments, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0348] Technologies for GPU-to-host processor interconnects

[0349] Figure 36A An exemplary architecture is shown in which multiple GPUs 3610 to 3613 are communicatively coupled to multiple multi-core processors 3605 to 3606 via high-speed links 3640 to 3643 (e.g., bus, point-to-point interconnect, etc.). In one embodiment, the high-speed links 3640 to 3643 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the invention are not limited to any particular communication protocol or throughput.

[0350] Furthermore, in one embodiment, two or more of GPUs 3610 to 3613 are interconnected via high-speed links 3644 to 3645, which can be implemented using the same or different protocols / links as those used for high-speed links 3640 to 3643. Similarly, two or more of multi-core processors 3605 to 3606 can be connected via high-speed link 3633, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, Figure 36AAll communication between the various system components shown can be accomplished using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the invention are not limited to any particular type of interconnect technology.

[0351] In one embodiment, each multi-core processor 3605 to 3606 is communicatively coupled to processor memories 3601 to 3602 via memory interconnects 3630 to 3631, and each GPU 3610 to 3613 is communicatively coupled to GPU memories 3620 to 3623 via GPU memory interconnects 3650 to 3653. Memory interconnects 3630 to 3631 and 3650 to 3653 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 3601 to 3602 and GPU memories 3620 to 3623 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-RAM. In one embodiment, one portion of the memory may be volatile memory, while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0352] As described below, although the various processors 3605 to 3606 and GPUs 3610 to 3613 can each be physically coupled to specific memories 3601 to 3602 and 3620 to 3623 respectively, a unified memory architecture can be implemented, in which the same virtual system address space (also known as the “effective address” space) is distributed across all the various physical memories. For example, processor memories 3601 to 3602 can each include 64GB of system memory address space, and GPU memories 3620 to 3623 can each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory space in the example described).

[0353] Figure 36B Additional details are shown regarding the interconnection between a multi-core processor 3607 and a graphics acceleration module 3646 according to one embodiment. The graphics acceleration module 3646 may include one or more GPU chips integrated on a line card coupled to the processor 3607 via a high-speed link 3640. Alternatively, the graphics acceleration module 3646 may be integrated on the same package or chip as the processor 3607.

[0354] The processor 3607 shown in Figure 36 includes multiple cores 3660A to 3660D, each having a translational backstop buffer 3661A to 3661D and one or more caches 3662A to 3662D. These cores may include various other components (e.g., instruction fetch units, branch prediction units, decoders, execution units, reordering buffers, etc.) for executing instructions and processing data not shown to avoid obscuring the basic principles of the invention. Caches 3662A to 3662D may include Level 1 (L1) and Level 2 (L2) caches. Furthermore, one or more shared caches 3626 may be included in the cache hierarchy and shared by the respective groups of cores 3660A to 3660D. For example, one embodiment of the processor 3607 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 3607 and graphics accelerator integrated module 3646 are connected to the system memory 3641, which may include processor memories 3601 to 3602.

[0355] Consistency is maintained for data and instructions stored in various caches 3662A to 3662D, 3656 and system memory 3641 via inter-core communication through the consistency bus 3664. For example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 3664 in response to a detected read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented via the consistency bus 3664 to snoop on cache accesses. Cache snooping / consistency techniques will be well understood by those skilled in the art, and to avoid obscuring the basic principles of the invention, they will not be described in detail here.

[0356] In one embodiment, proxy circuitry 3625 communicatively couples graphics acceleration module 3646 to coherence bus 3664, thereby allowing graphics acceleration module 3646 to participate in cache coherence protocols as a peer of the core. Specifically, interface 3635 provides connectivity to proxy circuitry 3625 via high-speed link 3640 (e.g., PCIe bus, NVLink, etc.), and interface 3637 connects graphics acceleration module 3646 to link 3640.

[0357] In one implementation, the accelerator integrated circuit 3636 provides cache management, memory access, context management, and interrupt management services for multiple graphics processing engines 3631, 3632, and N representing the graphics acceleration module 3646. The graphics processing engines 3631, 3632, and N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 3631, 3632, and N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and block image transfer engines. In other words, the graphics acceleration module can be a GPU with multiple graphics processing engines 3631, 3632, and N, or the graphics processing engines 3631 to 3632, and N can be separate GPUs integrated into a common package, line card, or chip.

[0358] In one embodiment, the accelerator integrated circuit 3636 includes a memory management unit (MMU) 3639 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 3641. The MMU 3639 may also include a translation back buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 3638 stores commands and data for efficient access by graphics processing engines 3631 to 3632, N. In one embodiment, the data stored in cache 3638 and graphics memories 3633 to 3634, N is kept consistent with core caches 3662A to 3662D, 3656 and system memory 3611. As mentioned, this can be accomplished via proxy circuitry 3625, which participates in cache coherency mechanisms on behalf of cache 3638 and memories 3633 to 3634, N (e.g., sending updates to cache 3638 related to modifications / accesses to cache lines on processor caches 3662A to 3662D, 3656 and receiving updates from cache 3638).

[0359] A set of registers 3645 stores context data for threads executed by graphics processing engines 3631 to 3632, N, and context management circuitry 3648 manages the thread context. For example, context management circuitry 3648 can perform save and restore operations to save and restore the context of various threads during context switching (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 3648 can store the current register value to a designated area in memory (e.g., identified by a context pointer). The context management circuitry can restore the register value upon returning to the context. In one embodiment, interrupt management circuitry 3647 receives and processes interrupts received from system devices.

[0360] In one implementation, the MMU 3639 translates the virtual / effective address from the graphics processing engine 3631 into a physical / actual address in system memory 3611. One embodiment of the accelerator integrated circuit 3636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 3646 and / or other accelerator devices. The graphics accelerator module 3646 may be dedicated to a single application executing on the processor 3607, or it may be shared among multiple applications. In one embodiment, a virtual graphics execution environment is presented, where the resources of the graphics processing engines 3631 to 3632, N are shared with multiple applications or virtual machines (VMs). Resources may be subdivided into “shards” allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0361] Therefore, the accelerator integrated circuit acts as a bridge for the system of the graphics acceleration module 3646, and provides address translation and system memory caching services. Furthermore, the accelerator integrated circuit 3636 can provide virtualization facilities for the host processor to manage the virtualization of the graphics processing engine, interrupts, and memory management.

[0362] Because the hardware resources of the graphics processing engines 3631 to 3632, N are explicitly mapped to the actual address space seen by the host processor 3607, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 3636 is the physical separation of the graphics processing engines 3631 to 3632, N, allowing them to appear as independent units on the system.

[0363] As mentioned, in the illustrated embodiment, one or more graphics memories 3633 to 3634, M are coupled to each of the graphics processing engines 3631 to 3632, N, respectively. Graphics memories 3633 to 3634, M store instructions and data being processed by each of the graphics processing engines 3631 to 3632, N. Graphics memories 3633 to 3634, M can be volatile memories such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3D XPoint or Nano-RAM.

[0364] In one embodiment, to reduce data traffic on link 3640, a biasing technique is used to ensure that the data stored in graphics memories 3633 to 3634, M is the data most frequently used by graphics processing engines 3631 to 3632, N, and preferably not used (or at least infrequently used) by cores 3660A to 3660D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not graphics processing engines 3631 to 3632, N) within the caches 3662A to 3662D, 3656 of the cores and system memory 3611.

[0365] Figure 36C Another embodiment in which the accelerator integrated circuit 3636 is integrated within the processor 3607 is shown. In this embodiment, graphics processing engines 3631 to 3632, N communicate directly with the accelerator integrated circuit 3636 via high-speed link 3640 through interfaces 3637 and 3635 (this can also utilize any form of bus or interface protocol). The accelerator integrated circuit 3636 can perform operations related to... Figure 36B The operation described is the same, but given its close proximity to the coherence bus 3662 and caches 3662A to 3662D, 3626, it may operate at a higher throughput.

[0366] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model may include a programming model controlled by the accelerator integrated circuit 3636 and a programming model controlled by the graphics acceleration module 3646.

[0367] In one embodiment of the dedicated process model, graphics processing engines 3631 to 3632, N are dedicated to a single application or process within a single operating system. A single application can centralize requests from other applications to graphics engines 3631 to 3632, N, thereby providing virtualization within a VM / partition.

[0368] In a dedicated process programming model, graphics processing engines 3631 to 3632, N can be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize the graphics processing engines 3631 to 3632, N, allowing access by each operating system. For a single-partition system without a hypervisor, the graphics processing engines 3631 to 3632, N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 3631 to 3632, N to provide access to each process or application.

[0369] For a shared programming model, the graphics acceleration module 3646 or the individual graphics processing engines 3631 to 3632, N use a process handle to select process elements. In one embodiment, the process elements are stored in system memory 3611 and can be addressed using the effective address to physical address translation techniques described herein. The process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 3631 to 3632, N (i.e., invoking system software to add a process element to the process element list). The lower 16 bits of the process handle may be the offset of the process element within the process element list.

[0370] Figure 36D An exemplary accelerator integration slice 3690 is shown. As used herein, a “slice” refers to a designated portion of the processing resources of the accelerator integrated circuit 3636. The application-effective address space 3682 within system memory 3611 stores process elements 3683. In one embodiment, process element 3683 is stored in response to a GPU call 3681 from an application 3680 executing on processor 3607. Process element 3683 contains the processing state of the corresponding application 3680. The job descriptor (WD) 3684 contained in process element 3683 may be a single job requested by the application, or it may contain a pointer to a job queue. In the latter case, WD 3684 is a pointer to a job request queue in the application address space 3682.

[0371] The graphics acceleration module 3646 and / or individual graphics processing engines 3631 to 3632, N can be shared by all or some processes in the system. Embodiments of the invention include infrastructure for establishing a processing state and sending a WD3684 to the graphics acceleration module 3646 to begin work in a virtual environment.

[0372] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 3646 or a separate graphics processing engine 3631. Since the graphics acceleration module 3646 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 3636 to obtain its assigned partition, and the operating system initializes the accelerator integrated circuit 3636 to obtain its assigned process when the graphics acceleration module 3646 is allocated.

[0373] In operation, the WD acquisition unit 3691 in the accelerator integration slice 3690 acquires the next WD 3684, which includes instructions for work to be performed by one of the graphics processing engines of the graphics acceleration module 3646. As shown, data from the WD 3684 can be stored in register 3645 and used by the MMU 3639, interrupt management circuitry 3647, and / or context management circuitry 3646. For example, one embodiment of the MMU 3639 includes segment / page walk circuitry for accessing segment / page tables 3686 within the OS virtual address space 3685. The interrupt management circuitry 3647 can handle interrupt events 3692 received from the graphics acceleration module 3646. When performing graphics operations, the effective address 3693 generated by the graphics processing engines 3631 to 3632, N is translated into an actual address by the MMU 3639.

[0374] In one embodiment, the same set of registers 3645 is copied for each graphics processing engine 3631 to 3632, N and / or graphics acceleration module 3646, and this set of registers can be initialized by a hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 3690. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0375] Table 1 - Supervisor Initialization Registers

[0376] 1 Slice Control Register 2 Real Address (RA) Scheduler Region Pointer 3 Authorization mask override register 4 Interruption vector table entry offset 5 Interruption vector table entry limit 6 Status Register 7 Logical partition ID 8 The Real Address (RA) management accelerator utilizes record pointers 9 Storage description register

[0377] Table 2 shows exemplary registers that can be initialized by the operating system.

[0378] Table 2 - Operating System Initialization Registers

[0379] 1 Process and thread identifiers 2 Valid Address (EA) Context Save / Restore Pointer 3 Virtual Address (RA) accelerators utilize record pointers 4 Virtual Address (RA) segment table pointer 5 Authorization mask 6 Job descriptor

[0380] In one embodiment, each WD 3684 is specific to a particular graphics acceleration module 3646 and / or graphics processing engines 3631 to 3632, N. The WD contains all the information required for the graphics processing engines 3631 to 3632, N to complete their work, or the WD may be a pointer to a memory location where the application has established a queue of work commands to be completed.

[0381] Figure 36E Additional details of one embodiment of the shared model are shown. This embodiment includes a hypervisor physical address space 3698 in which a list of process elements 3699 is stored. The hypervisor physical address space 3698 is accessible via a hypervisor 3696 that virtualizes the graphics acceleration module engine of operating system 3695.

[0382] The shared programming model allows all or some processes from all or some partitions of the system to use the graphics acceleration module 3646. There are two programming models in which the graphics acceleration module 3646 is shared by multiple processes and partitions: time-sliced ​​sharing and direct graphics sharing.

[0383] In this model, the hypervisor 3696 owns the graphics acceleration module 3646 and makes its functionality available to all operating systems 3695. For the graphics acceleration module 3646 to support the virtualization of the hypervisor 3696, the graphics acceleration module 3646 must meet the following requirements: 1) Application job requests must be autonomous (i.e., no need to maintain state between jobs), or the graphics acceleration module 3646 must provide context saving and restoration mechanisms. 2) The graphics acceleration module 3646 guarantees completion of application job requests within a specified time, including any translation errors, or the graphics acceleration module 3646 provides the ability to preempt job processing. 3) When operating in a direct shared programming model, fairness of the graphics acceleration module 3646 within the process must be guaranteed.

[0384] In one embodiment, for the shared model, application 3680 is required to make an operating system 3695 system call using the graphics acceleration module 3646 type, working descriptor (WD), authorization mask register (AMR) value, and context save / restore region pointer (CSRP). The graphics acceleration module 3646 type describes the target acceleration function of the system call. The graphics acceleration module 3646 type can be a system-specific value. The WD is specifically formatted for the graphics acceleration module 3646 and can be in the following forms: graphics acceleration module 3646 command; valid address pointer to a user-defined structure; valid address pointer to a command queue; or any other data structure describing the work to be performed by the graphics acceleration module 3646. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to that of the application setting the AMR. If the implementation of the accelerator integrated circuit 3636 and the graphics acceleration module 3646 does not support the User Authorization Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Before placing the AMR in process element 3683, hypervisor 3696 may optionally apply the Current Authorization Mask Override Register (AMOR) value. In one embodiment, CSRP is one of registers 3645 containing the effective address of a region in application address space 3682 for the graphics acceleration module 3646 to save and restore context state. This pointer is optional if saving state between jobs is not required or when a job is preempted. The context save / restore region may be plugged-in system memory.

[0385] Upon receiving a system call, the operating system 3695 can verify that application 3680 has been registered and authorized to use the graphics acceleration module 3646. The operating system 3695 then uses the information shown in Table 3 to invoke the hypervisor 3696.

[0386] Table 3 - Operating System Call Parameters for the Hypervisor

[0387] 1 Working Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual address (VA) accelerators utilize record pointers (AURP). 6 Virtual address of the segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0388] Upon receiving a call from the management program, the management program 3696 can verify that the operating system 3695 has been registered and authorized to use the graphics acceleration module 3646. The management program 3696 then places the process element 3683 into the process element linked list according to the corresponding graphics acceleration module 3646 type. The process element may contain the information shown in Table 4.

[0389] Table 4 - Process Element Information

[0390]

[0391]

[0392] In one embodiment, the hypervisor initializes multiple registers 3649 of the accelerator integration slice 3690.

[0393] like Figure 36F As shown, one embodiment of the invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 3601-3602 and GPU memories 3620-3623. In this implementation, operations performed on GPUs 3610-3613 utilize the same virtual / effective memory address space to access processor memories 3601-3602 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 3601, a second portion to second processor memory 3602, a third portion to GPU memory 3620, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 3601-3602 and GPU memories 3620-3623, thereby allowing any processor or GPU to access any physical memory having a virtual address mapped to said memory.

[0394] In one embodiment, the bias / coherence management circuitry 3694A to 3694E within one or more of the MMUs 3639A to 3639E ensures cache coherence between the host processor (e.g., 3605) and the caches of the GPUs 3610 to 3613, and implements a biasing technique that indicates the physical memory where certain types of data should be stored. Although in Figure 36F Several instances of bias / coherence management circuits 3694A to 3694E are shown, but bias / coherence circuits can also be implemented within the MMU of one or more host processors 3605 and / or within the accelerator integrated circuit 3636.

[0395] One embodiment allows GPU-attached memories 3620 to 3623 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, without suffering the typical performance drawbacks associated with system-wide cache coherence. The ability to access GPU-attached memories 3620 to 3623 as system memory avoids heavy cache coherence overhead, providing a favorable operating environment for GPU offloading. This arrangement allows host processor 3605 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. These traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory accesses. Furthermore, the ability to access GPU-attached memories 3620 to 3623 without cache coherence overhead can be critical for offloading computation execution time. For example, in scenarios with heavy streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 3610 to 3613. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation all play a crucial role in determining the effectiveness of GPU offloading.

[0396] In one implementation, the choice between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a page-granular structure comprising 1 or 2 bits per GPU-attached memory page (i.e., controlled at the memory page level). The bias table can be implemented within the stolen memory range of one or more GPU-attached memories 3620 to 3623, with or without a bias cache in GPUs 3610 to 3613 (e.g., caching frequently / recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0397] In one implementation, the bias table entries associated with each access to GPU-attached memories 3620-3623 are accessed before the actual access to GPU memory, such that: First, local requests from GPUs 3610-3613 that find their pages in the GPU bias are directly forwarded to the corresponding GPU memories 3620-3623. Local requests from GPUs that find their pages in the host bias are forwarded to processor 3605 (e.g., via a high-speed link as described above). In one embodiment, a request from processor 3605 that finds the requested page in the host processor bias completes like a normal memory read. Alternatively, requests for GPU-biased pages can be forwarded to GPUs 3610-3613. If the GPU is not currently using the page, the GPU can convert the page to host processor bias.

[0398] The page bias state can be changed through software-based mechanisms, hardware-assisted software mechanisms, or, for a finite set of cases, hardware-only mechanisms.

[0399] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn invokes the GPU device driver. The driver then sends a message to the GPU (or enqueues a command descriptor), thereby instructing the GPU to change its bias state. For certain transitions, a cache dump clearing operation is performed on the host machine. This cache dump clearing operation is necessary for transitions from host processor 3605 bias to GPU bias, but not necessary for the reverse transition.

[0400] In one embodiment, cache coherence is maintained by temporarily presenting GPU bias pages that the host processor 3605 cannot cache. To access these pages, the processor 3605 can request access from the GPU 3610, which may grant access immediately or not, depending on its implementation. Therefore, to reduce communication between the processor 3605 and the GPU 3610, it is advantageous to ensure that the GPU bias pages are pages needed by the GPU but not by the host processor 3605, and vice versa.

[0401] Figure 36GA multi-GPU computing system according to an embodiment is illustrated. The multi-GPU computing system may include a processor 3603 coupled to a plurality of GPUs 3614A-3614D via a host interface switch 3604. In one embodiment, the host interface switch 3604 is a PCI Express switch device that couples the processor 3603 to a PCI Express bus, through which the processor 3603 can communicate with the group of GPUs 3614A-3614D. The GPUs 3614A-3614D may be interconnected via a set of high-speed point-to-point GPU-GPU links 3616. The high-speed GPU-to-GPU links may be connected to each of the GPUs 3614A-3614D via dedicated GPU links 3616, enabling direct communication between each of the GPUs 3614A-3614D without requiring communication via the host interface bus to which the processor 3603 is connected. Utilizing GPU-to-GPU traffic directed to the P2P GPU link, the host interface bus remains available for system memory access or communication with other instances of the multi-GPU computing system 3600, for example, via one or more network devices. While in the illustrated embodiment, GPUs 3614A-3614D are connected to processor 3603 via host interface switch 3604, in one embodiment, processor 3603 includes direct support for the P2P GPU link 3616 and can be directly connected to GPUs 3614A-3614D.

[0402] Graphics processing pipeline

[0403] Figure 37 A graphics processing pipeline 3700 according to an embodiment is illustrated. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 3700. The graphics processor may be included within a parallel processing subsystem such as the parallel processor 3400 of FIG. 34, as described herein. In one embodiment, the parallel processor is... Figure 33Variations of the (multiple) parallel processors 3312. As described herein, various parallel processing systems can implement the graphics processing pipeline 3700 via one or more instances of parallel processing units (e.g., parallel processing unit 3402 of FIG. 34). For example, a shader unit (e.g., graphics multiprocessor 3534 of FIG. 35) can be configured to perform the functions of one or more of the vertex processing unit 3704, tessellation control processing unit 3708, tessellation evaluation processing unit 3712, geometry processing unit 3716, and fragment / pixel processing unit 3724. The functions of the data assembler 3702, primitive assemblers 3706, 3714, 3718, tessellation unit 3710, rasterizer 3722, and raster operation unit 3726 can also be performed by other processing engines and corresponding partitioning units (e.g., partitioning units 3420A to 3420N of FIG. 34) within the processing cluster (e.g., processing cluster 3514 of FIG. 35). The graphics processing pipeline 3700 can also be implemented using one or more dedicated processing units. In one embodiment, one or more portions of the graphics processing pipeline 3700 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 3700 may access on-chip memory (e.g., the parallel processor memory 3422 shown in FIG. 34) via a memory interface 3728, which may be an instance of the memory interface 3418 of FIG. 34.

[0404] In one embodiment, the data assembler 3702 is a processing unit that collects vertex data of surfaces and primitives. The data assembler 3702 then outputs vertex data, including vertex attributes, to the vertex processing unit 3704. The vertex processing unit 3704 is a programmable execution unit that executes a vertex shader program to illuminate and transform vertex data as specified by the vertex shader program. The vertex processing unit 3704 reads data stored in a cache, local, or system memory for processing vertex data and can be programmed to transform vertex data from an object-based coordinate representation to world space coordinate space or normalized device coordinate space.

[0405] The first instance of the primitive assembler 3706 receives vertex attributes from the vertex processing unit 3700. The primitive assembler 3706 reads the stored vertex attributes as needed and constructs graphic primitives for processing by the tessellation control processing unit 3708. Graphic primitives include triangles, line segments, points, patches, etc., supported by various graphics processing application programming interfaces (APIs).

[0406] The tessellation control processing unit 3708 treats input vertices as control points for a geometric patch. These control points are transformed from an input representation of the patch (e.g., the patch's basis) into a representation suitable for surface evaluation by the tessellation evaluation processing unit 3712. The tessellation control processing unit 3708 can also calculate tessellation factors for the edges of the geometric patch. The tessellation factor is applied to a single edge and quantifies the view-dependent level of detail associated with the edge. The tessellation unit 3710 is configured to receive the tessellation factors for the edges of the patch and subdivide the patch into multiple geometric primitives, such as lines, triangles, or quadrilaterals, which are then transmitted to the tessellation evaluation processing unit 3712. The tessellation evaluation processing unit 3712 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes associated with each vertex of the geometric primitive.

[0407] A second instance of the primitive assembler 3714 receives vertex attributes from the tessellation evaluation processing unit 3712, reads stored vertex attributes as needed, and constructs graphic primitives for processing by the geometry processing unit 3716. The geometry processing unit 3716 is a programmable execution unit that executes a geometry shader program to transform the graphic primitives received from the primitive assembler 3714 as specified by the geometry shader program. In one embodiment, the geometry processing unit 3716 is programmed to subdivide the graphic primitives into one or more new graphic primitives and calculate parameters for rasterizing the new graphic primitives.

[0408] In some embodiments, the geometry processing unit 3716 can add or remove elements from the geometry flow. The geometry processing unit 3716 outputs parameters and vertices specifying new graphic primitives to the primitive assembler 3718. The primitive assembler 3718 receives the parameters and vertices from the geometry processing unit 3716 and constructs graphic primitives for processing by the viewport scaling, picking, and clipping unit 3720. The geometry processing unit 3716 reads data stored in the parallel processor memory or system memory for processing the geometry data. The viewport scaling, picking, and clipping unit 3720 performs clipping, picking, and viewport scaling, and outputs the processed graphic primitives to the rasterizer 3722.

[0409] Rasterizer 3722 can perform depth picking and other depth-based optimizations. Rasterizer 3722 also performs scan transformations on new graphic primitives to generate segments and outputs these segments and associated overlay data to segment / pixel processing unit 3724. Segment / pixel processing unit 3724 is a programmable execution unit configured to execute segment shader programs or pixel shader programs. Segment / pixel processing unit 3724 transforms segments or pixels received from rasterizer 3722 as specified by the segment or pixel shader program. For example, segment / pixel processing unit 3724 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded segments or pixels output to raster operation unit 3726. Segment / pixel processing unit 3724 can read data stored in parallel processor memory or system memory for use when processing segment data. Segment or pixel shader programs can be configured to shade at sample, pixel, tile, or other granularities according to a sampling rate configured for the processing unit.

[0410] The raster operation unit 3726 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, and blending, and outputs pixel data as processed graphic data for storage in a graphics memory (e.g., the parallel processor memory 3422 in FIG. 34, and / or such as...). Figure 33 The system memory 3304 is used for display on one or more display devices 3310 or for further processing by one or more processors 3302 or (a plurality of) parallel processors 3312. In some embodiments, the raster operation unit 3726 is configured to compress z or color data written to memory and decompress z or color data read from memory.

[0411] The embodiments described herein can be implemented as any or a combination of the following: one or more microchips or integrated circuits using motherboard interconnects, hard-wired logic, software stored in a memory device and executed by a microprocessor, firmware, application-specific integrated circuits (ASICs), and / or field-programmable gate arrays (FPGAs). As an example, the term "logic" can include software or hardware and / or a combination of software and hardware. Generally, throughout this document, the terms "logic," "module," "component," "engine," "mechanism," "tool," "circuit," and "circuit system" are used interchangeably and, as examples, can include software, hardware, firmware, or any combination thereof.

[0412] The embodiments may be provided as, for example, computer program products, which may include one or more machine-readable media having machine-executable instructions stored thereon, which, when executed by one or more machines (such as a computer, a network of computers, or other electronic devices), cause the one or more machines to perform operations according to the embodiments described herein. Machine-readable media may include, but are not limited to: floppy disks, optical disks, CD-ROMs (compact disc read-only memory) and magneto-optical disks, ROMs, RAMs, EPROMs (erasable programmable read-only memory), EEPROMs (electrically erasable programmable read-only memory), magnetic cards or optical cards, flash memory, or other types of non-transient machine-readable media suitable for storing machine-executable instructions.

[0413] The following terms and / or examples relate to specific embodiments or examples thereof. Details from the examples may be used anywhere in one or more embodiments. Various features of different embodiments or examples may be combined in various ways with some of the included features and others that are excluded to suit a variety of different applications. Examples may include subjects such as: methods, means for performing actions of said methods, at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the actions of said methods, or the operation of a device or system according to the embodiments and examples described herein. Various components may be means for performing the described operations or functions.

[0414] One embodiment provides a system for configuring distributed training of a neural network, the system comprising: a memory for storing data to facilitate data transfer during distributed training of the neural network; a network interface for enabling the sending and receiving of configuration data associated with a set of worker nodes configured to perform distributed training of the neural network; and a processor for executing instructions provided by the memory, the instructions causing the processor to create one or more sets of worker nodes based on a communication pattern of messages transmitted between the worker nodes during distributed training of the neural network.

[0415] One embodiment provides a non-transient machine-readable medium storing instructions that, when executed by one or more processors, cause the processors to perform operations including: tracking the communication behavior of applications communicating on the machine learning platform via a Quality of Service (QoS) counter exposed at a machine learning framework via one of the one or more processors; determining the relative share of intra-chassis and inter-chassis communication bandwidth consumed by each application managed by the machine learning framework; identifying congestion points within intra-chassis and inter-chassis communication links; adjusting application communication scheduling based on the relative share of communication bandwidth and congestion points within intra-chassis and inter-chassis communication links; and dynamically adjusting the cache QoS models of the one or more processors to prioritize data associated with latency-sensitive applications.

[0416] One embodiment provides a multi-chassis computing device, including a general-purpose processing unit in a first chassis and a first group of graphics processing units in a second chassis. The second chassis includes a host interface switch for coupling the second chassis to the first chassis. The host interface switch enables communication between the general-purpose processing unit and the first group of graphics processing units, the first group of graphics processing units communicating via a point-to-point interconnect. The host interface switch enables switching communication between the first group of graphics processing units and the general-purpose processing unit via the point-to-point interconnect.

[0417] One embodiment provides a method for establishing a persistent communication session for distributed machine learning across multiple computing nodes. The method includes: receiving an identifier of a node to which a persistent network communication session will be established, the persistent network communication session being established during distributed training of a neural network; resolving one or more network addresses of the node and persistently storing the one or more resolved network addresses; receiving an instruction for a set of network operations, the resource allocation for which the network operations will be persistent; allocating resources for communicating with the node and marking the resources as persistent; and performing the requested network operations using the node while maintaining the resource allocation associated with the operations marked as persistent.

[0418] The foregoing description and accompanying drawings should be considered illustrative rather than restrictive. Those skilled in the art will understand that various modifications and changes can be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Claims

1. A system for configuring distributed training of a neural network, the system comprising: A memory for storing data, the memory being used to facilitate data transfer during distributed training of the neural network; A network interface is provided for sending and receiving configuration data associated with a set of worker nodes configured to perform distributed training of the neural network, wherein each worker node includes one or more graphics processors to perform computational operations associated with the machine learning framework workflow. as well as A processor is configured to execute instructions provided by the library, the instructions being configured to cause the processor to create multiple sets of worker nodes, the multiple sets of worker nodes being created based on a communication pattern of messages transmitted between the worker nodes during the distributed training of the neural network, the instructions being configured to cause the processor to receive a request to send parameter data using a first communication pattern, and in response to the request, to transparently adjust the communication paths between the worker nodes based on the first communication pattern.

2. The system as described in claim 1, characterized in that, The first communication mode is the full reduction mode.

3. The system as described in claim 2, characterized in that, The instructions cause the processor to group the worker nodes into one or more groups of topology-local worker nodes and perform full reduction synchronization of parameter data among the worker nodes within the group.

4. The system as described in claim 3, characterized in that, The instruction causes the processor to synchronize parameter data between groups via a parameter server.

5. The system as described in claim 4, characterized in that, The instruction is used to instruct the processor to configure worker nodes as parameter servers.

6. The system as described in claim 5, characterized in that, The instructions are used to enable the processor to synchronize parameter data among multiple sets via multiple parameter servers.

7. The system as described in claim 5, characterized in that, The instructions are used to cause the processor to retrieve a known network topology of the network that interconnects the group of worker nodes, and to group the worker nodes into one or more groups of topology local worker nodes based on the known network topology.

8. The system as described in claim 5, characterized in that, The instructions are used to cause the processor to initiate sample training iterations on the set of worker nodes and to group the worker nodes into one or more groups of worker nodes based on the observed latency metric of communication between the set of worker nodes.

9. A non-transient machine-readable medium storing instructions, said instructions, when executed by one or more processors, causing said one or more processors to perform operations including: At the machine learning framework, the communication behavior of applications communicating on the machine learning platform is tracked via a Quality of Service (QoS) counter exposed by one or more processors of the machine learning platform. Determine the relative share of in-chassis communication bandwidth and inter-chassis communication bandwidth consumed by each application managed by the machine learning framework; Identify congestion points in communication links within and between chassis; Application communication scheduling is adjusted based on the relative share of communication bandwidth and congestion points within intra-chassis communication links and inter-chassis communication links. The adjustment of application communication scheduling includes scheduling inter-chassis messages instead of intra-chassis messages in response to determining the existence of intra-chassis congestion. The cache QoS model of one or more processors is dynamically adjusted to prioritize data associated with latency-sensitive applications.

10. The non-transient machine-readable medium as claimed in claim 9, characterized in that, Prioritizing data associated with the latency-sensitive application includes reducing the probability of that data being evicted.

11. The non-transient machine-readable medium as claimed in claim 9, characterized in that, The operation additionally includes adjusting the communication routing of application messages between the one or more processors of the machine learning platform.

12. A data processing system comprising a non-transient machine-readable medium as claimed in any one of claims 9-11.

13. An apparatus comprising: Interconnect switches are configured to couple to multiple graphics processors via multiple point-to-point interconnects; as well as One or more processors, including a graphics processor, said graphics processor being coupled to the interconnect switch via a point-to-point interconnect of the plurality of point-to-point interconnects, said graphics processor comprising: A graphics multiprocessor cluster, configured for single-instruction multithreaded (SIMT) operation, is interconnected via a data interconnect and configured to exchange data via the data interconnect. The graphics multiprocessor cluster includes graphics multiprocessors configured to: During the execution of operations associated with the second thread group, data associated with the first thread group to be executed is received via the graphics multiprocessor. This data is received via a point-to-point interconnect coupled to the interconnect switch and is associated with a communication pattern of messages that will be transmitted between worker nodes in the first group of worker nodes, which are configured to perform distributed training of a neural network. as well as During the execution of operations associated with the first thread group, data processed by the second thread group is transmitted via the point-to-point interconnect coupled to the interconnect switch.

14. The apparatus as claimed in claim 13, characterized in that, The communication mode is a full reduction mode.

15. The apparatus as claimed in claim 13, characterized in that, The worker nodes in the first group are grouped according to topological locality and configured to perform full reduction synchronization of data among the worker nodes.

16. The apparatus as claimed in claim 15, characterized in that, The data associated with the first thread group includes parameter data.

17. The apparatus as claimed in claim 16, characterized in that, The first thread group is used to send updated parameter data to the parameter server via the point-to-point interconnect and via the interconnect switch.

18. The apparatus as claimed in claim 17, characterized in that, The parameter server is used to synchronize the updated parameter data with the second group of worker nodes, which are grouped according to topological locality.

19. The apparatus as claimed in claim 18, characterized in that, The device further includes a second graphics processor among the plurality of graphics processors, the second graphics processor being coupled to the interconnect switch via a second point-to-point interconnect, the second graphics processor being configured as a worker node in the first group of worker nodes.

20. A method for establishing persistent communication sessions for distributed machine learning across multiple computing nodes, the method comprising: The identifier of the receiving node, to which a persistent network communication session will be established, which is established during the distributed training of the neural network; Resolve one or more network addresses of the node and persistently store one or more resolved network addresses; Receive instructions for a set of network operations; resource allocation for that set of network operations will be persistent. Allocate resources for communicating with the node and mark the resources as persistent; The requested network operation is performed using the node, while maintaining the resource allocation associated with the operation identified as persistent; as well as After receiving an indication that the persistent session has ended, the persistently allocated resources are deallocated.

21. The method as described in claim 20, characterized in that, Additional land includes: Receive requests at the communication framework to perform operations associated with persistent distributed training sessions; Determine whether the operation is indicated as a persistent operation; Access the resources previously allocated for the persistent operation; and If the operation is indicated to be non-persistent, a new resource allocation is performed for the operation.

22. A data processing system comprising means for performing the method of any one of claims 20-21.

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