Semiconductor device and method for forming a semiconductor device

Abstract

The present application relates to semiconductor devices and methods for forming semiconductor devices. The present invention discloses a semiconductor device, and embodiments of the semiconductor device may include a die having a first side and a second side; a contact pad coupled to the first side of the die; and a metal layer coupled to the second side of the die. The thickness of the die may not exceed four times the thickness of the metal layer.

Description

Technical Field

[0001] Aspects of this document relate generally to semiconductor devices and semiconductor wafers and device processing methods. Background Art

[0002] Semiconductor manufacturing processes may involve many steps. In some processes, a wafer receives one or more layers, such as a conductive layer. The conductive layer may be used to provide electrical contact areas for individual semiconductor devices cut from the wafer. The conductive layer is typically formed using sputtering, evaporation, or electroplating operations. Summary of the invention

[0003] Embodiments of a semiconductor device may include a die having a first side and a second side; a contact pad coupled to the first side of the die; and a metal layer coupled to the second side of the die. The thickness of the die may not exceed four times the thickness of the metal layer.

[0004] Implementations of the semiconductor device may include one, all, or any of the following:

[0005] The thickness of the die may be less than 30 micrometers (μm).

[0006] The thickness of the die may be substantially the same as the thickness of the metal layer.

[0007] The device may include a molding compound directly coupled to the metal layer.

[0008] The device may include a molding compound coupled directly over the metal layer.

[0009] Embodiments of a semiconductor device may include a die having a first side and a second side; a contact pad coupled to the first side of the die; a metal layer coupled to the second side of the die; and a mold compound directly coupled to the metal layer. The die may have a thickness of less than 30 μm.

[0010] Implementations of the semiconductor device may include one, all, or any of the following:

[0011] The thickness of the die may be substantially the same as the thickness of the metal layer.

[0012] The molding compound may be coupled directly over the metal layer.

[0013] An embodiment of a method for forming a semiconductor die may include forming a plurality of contact pads coupled to a first side of a wafer; forming a groove in a second side of the wafer opposite to the first side by back grinding the wafer; forming a metal layer within the groove; patterning the metal layer within the groove; and cutting the wafer into a plurality of semiconductor devices.

[0014] Implementations of methods for forming a semiconductor device may include one, all, or any of the following:

[0015] The method may include coupling a molding compound to the metal layer within the recess.

[0016] The metal layer may be exposed through the mold compound.

[0017] The molding compound may be coupled directly over the metal layer.

[0018] The method may include back grinding a portion of the wafer until the portion of the wafer is coplanar with a plane formed by a portion of the molding compound.

[0019] The method may include thinning the wafer by forming a groove, wherein a portion of the wafer is thinned to less than 30 μm.

[0020] The method may include coating the recess with a seed layer.

[0021] The method may include forming a plurality of bumps over the metal layer.

[0022] The method may include coupling a metal layer, a molding compound, and one of a plurality of bumps to a backside protection layer, and then dicing the wafer.

[0023] An embodiment of a method for forming a semiconductor die may include forming a plurality of contact pads coupled to a first side of a wafer; forming a groove in a second side of the wafer opposite to the first side by back grinding the second side of the wafer; forming a metal layer within the groove; forming a plurality of openings within the metal layer; forming a molding compound into the openings of the metal layer; and cutting the wafer into a plurality of semiconductor devices.

[0024] Implementations of methods for forming a semiconductor device may include one, all, or any of the following:

[0025] The method may also include forming a metal layer between the contact pads and the first side of the wafer.

[0026] The thickness of the metal layer may be substantially the same as the thickness of the wafer.

[0027] The thickness of the metal layer may be substantially three times the thickness of the wafer.

[0028] The method may include coupling a second metal layer over the metal layer.

[0029] The molding compound may encapsulate the metal layer.

[0030] The foregoing and other aspects, features and advantages will be apparent to those skilled in the art from the detailed description and accompanying drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Various embodiments will be described below in conjunction with the accompanying drawings, wherein like reference numerals represent like elements, and:

[0032] Figure 1 is a cross-sectional side view of a first embodiment of a semiconductor device;

[0033] Figure 2 is a cross-sectional side view of a second embodiment of a semiconductor device;

[0034] Figure 3 is a cross-sectional side view of a third embodiment of a semiconductor device;

[0035] Figure 4 is a cross-sectional side view of a fourth embodiment of a semiconductor device;

[0036] Figure 5 is a cross-sectional side view of a fifth embodiment of a semiconductor device;

[0037] Figure 6 is a cross-sectional side view of a sixth embodiment of a semiconductor device;

[0038] Figure 7 is a cross-sectional side view of a seventh embodiment of a semiconductor device;

[0039] Figure 8 is a graph showing on-resistance of various embodiments of semiconductor devices;

[0040] Fig. 9 is a cross-sectional side view of the wafer;

[0041] Fig.10 having a groove formed therein Fig. 9 a cross-sectional side view of a wafer;

[0042] Fig.11 yes Fig.10 a cross-sectional side view of a wafer of wherein a mask is formed in a recess;

[0043] Fig.12 yes Fig.10 a cross-sectional side view of a wafer of FIG. 1 , wherein a metal layer is formed in a groove;

[0044] Fig.13 yes Fig.12 a cross-sectional side view of a wafer of claim 1 wherein a molding compound is formed over the metal layer;

[0045] Fig.14 yes Fig.13 a cross-sectional side view of a wafer with a portion of a ring of the wafer removed;

[0046] Fig.15 is rotated with the belt applied to the molding compound Fig.14 a cross-sectional side view of a wafer;

[0047] Fig.16 It is cut Fig.15 a cross-sectional side view of a wafer;

[0048] Fig.17 yes Fig.13 a cross-sectional side view of a wafer with tape applied to a molding compound;

[0049] Fig.18 It is cut Fig.17 a cross-sectional side view of a wafer;

[0050] Fig.19 yes Fig.12 a cross-sectional side view of a wafer with a molding compound filling the recess;

[0051] Fig. 20 yes Fig.10 a cross-sectional side view of a wafer of , wherein a non-patterned metal layer is formed in the groove;

[0052] Fig.21 yes Fig.12 a cross-sectional side view of a wafer with a portion of a ring of the wafer removed;

[0053] Fig. 22 yes Fig.21 a cross-sectional side view of a wafer of FIG. 1 , wherein bumps are formed over a metal layer;

[0054] Fig.23 yes Fig.21 a cross-sectional side view of a wafer of wherein a molding compound is formed between openings in the metal layer;

[0055] Fig.24 yes Fig. 22 a cross-sectional side view of a wafer of wherein a molding compound is formed between openings in the metal layer;

[0056] Figure 25A-25B shows a process for dicing a wafer having a BSP layer applied thereto; and

[0057] Figure 26A-26B A process for dicing a wafer without a BSP layer applied thereto is shown. DETAILED DESCRIPTION

[0058] The present disclosure, its aspects, and implementations are not limited to the specific components, assembly processes, or method elements disclosed herein. Many other components, assembly processes, and / or method elements known in the art that are consistent with the intended semiconductor device will obviously be used with the specific embodiments of the present disclosure. Thus, for example, although the present invention discloses specific embodiments, such embodiments and implementation components may include any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, etc. known in the art for such semiconductor devices and implementation components and methods that are consistent with the intended operation and method.

[0059] Specific embodiments of semiconductor devices and implementing components and methods may be similar or identical to the semiconductor devices and implementing components and methods disclosed in the following patents: U.S. Patent No. 9,905,522, entitled “Semiconductor Copper Metallization Structure and Related Methods” to Yusheng Lin, Application Serial No. 15,254,640 filed on September 1, 2016 and published on February 27, 2018 (the '522 patent), and Semiconductor Backmetal (BM) and OverPad Metallization (OPM) Structures and Related No. 9,640,497, filed on June 30, 2016, and published on May 2, 2017, each of which is hereby incorporated by reference in its entirety.

[0060] In various embodiments, the semiconductor devices disclosed herein may be power semiconductor devices, such as, by way of non-limiting example, metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs). In other embodiments, the device may be other types of power semiconductor devices, or may be a semiconductor device that is not a power semiconductor device. See Figure 1, showing a cross-sectional side view of a first embodiment of a semiconductor device. The semiconductor device 2 includes a die 4 having a first side 6 and a second side 8. The die 4 may include silicon, and in various embodiments, may include an epitaxial portion 10. It should be understood that where the present disclosure relates to a silicon die, the silicon die may be any type of silicon die, including, by way of non-limiting example, an epitaxial silicon die, silicon on insulator, polysilicon, any combination thereof, or any other silicon-containing die material. Additionally, it should be further understood that in various embodiments, dies other than silicon-containing dies may be used, such as, by way of non-limiting example, gallium arsenide or metal-containing dies. Figure 1 In the illustrated embodiment, the semiconductor device may be a trench MOSFET device, as indicated by patterned portion 24 in epitaxial portion 10 of die 4, showing the location of the trench, however, other embodiments may not include a trench MOSFET structure, but may include a different semiconductor device that may or may not be a power semiconductor device. In various embodiments, the thickness of die 4 may be about 25 micrometers (μm), about 40 μm, about 75 μm, greater than about 75 μm, between about 25 μm and about 75 μm, less than about 30 μm, and less than about 25 μm.

[0061] In various embodiments, semiconductor device 2 may include a conductive layer 12 coupled to first side 6 of die 4. The conductive layer may be a metal or a metal alloy, and in such embodiments, by way of non-limiting example, may include aluminum, copper, gold, silver, titanium, nickel, any other metal, and any combination thereof. In various embodiments, the length and width of conductive layer 12 may be the same as die 4, however, in other embodiments, such as Figure 1 As shown, the length or width of the conductive layer may be smaller than the length or width of the die 4 .

[0062] In various embodiments, semiconductor device 2 may include contact pads 14 coupled to the conductive layer. Contact pads 14 may be any type of metal or metal alloy disclosed herein. In a particular embodiment, contact pads may be SnAg or NiAu. Contact pads 14 may have the same length and width as conductive layer 12, however, in other embodiments, such as Figure 1 As shown, the length or width of the contact pad may be less than the length or width of the conductive layer 12. In various embodiments, the semiconductor device 2 may not include the contact pad 14 in addition to the conductive layer 12, but may use the conductive layer as the contact pad. Similarly, in a particular embodiment, the semiconductor device 2 may not include the conductive layer 12, but may include the contact pad 14 directly coupled to the first side 6 of the die 4.

[0063] In various embodiments, the intermediate pad may be coupled between the conductive layer 12 and the contact pad 14. The intermediate pad may be a metal deposited using electroplating, and in particular embodiments, may be electroplated copper. In particular embodiments, the intermediate pad may include a metal alloy, and by way of non-limiting example, may include Ni, Au, Pd, Cu, or any combination thereof. In various embodiments, the intermediate pad may have different widths, wherein a first portion of the intermediate pad directly coupled to the conductive layer 12 has a smaller cross-sectional width than a second portion of the intermediate pad directly coupled to the contact pad 14. In other embodiments, the cross-sectional width of the first portion of the intermediate pad may be the same as the second portion of the intermediate pad.

[0064] In various embodiments, such as Figure 1 As shown, the semiconductor device may include a passivation material 72 coupled over the die 4. The surface 74 of the passivation material may be coplanar with the plane formed by the exposed surface of the contact pad 14. In embodiments including an intermediate pad, the passivation layer may only cover a portion of the intermediate pad so that the entire contact pad 14 is not directly coupled to the passivation layer. In a particular embodiment, the passivation material may at least partially encapsulate the conductive layer 12. By way of non-limiting example, the passivation material may be SiN, SiO 2 , or any other type of passivating material.

[0065] Still see Figure 1 , the semiconductor device 2 includes a metal layer / back metal layer 16 coupled to the second side 8 of the tube core 4. In various embodiments, by way of non-limiting example, the metal layer may include copper, gold, silver, aluminum, titanium, nickel, any other metal, and any combination thereof. In a particular embodiment, the metal layer 16 may be the same or similar to the back metal layer disclosed in the '522 patent and the '497 patent, both of which have been previously incorporated herein by reference. In various embodiments, the metal layer 16 may include a single type of metal or metal alloy, while in other embodiments, the metal layer may include multiple metal layers of the same or different metals and / or metal alloys. In various embodiments, the thickness of the metal layer 16 may be about 10μm, about 25μm, about 40μm, less than about 10μm, between about 10-40μm, and greater than about 40μm, including thicknesses as great as about 200μm. Compared to the tube core 4, in various embodiments, the thickness of the tube core may not exceed about four times the thickness of the metal layer 16. In more specific embodiments, the thickness of die 4 may be about three times the thickness of metal layer 16, about two and a half times the thickness of the metal layer, about two times the thickness of the metal layer, or about the same thickness as metal layer 16. In other embodiments, the thickness of die 4 may be greater than about four times the thickness of metal layer 16, or less than the thickness of metal layer 16.

[0066] In various embodiments, the semiconductor device 2 may include a seed layer 18 between the second side 8 of the die 4 and the metal layer 16. The seed layer 18 may be configured to facilitate bonding between the metal layer 16 and the die 4 and / or provide a location for electrodeposition to begin during an electroplating operation. The seed layer 18 may include a metal or a metal alloy, and in particular embodiments, may include TiCu or TiWCu. In other embodiments, the seed layer 18 may include any metal previously disclosed herein.

[0067] In various embodiments, semiconductor device 2 may include a mold compound / resin / protective coating (hereinafter referred to as "mold compound" 20) coupled to metal layer 16. Although the term "mold compound" is used herein to describe the material above the metal layer, it should be understood that the term, as used herein, includes many types of resins, epoxies, and other kinds of protective coatings. In particular embodiments, mold compound 20 may be directly coupled to metal layer 16, and in even more particular embodiments, the mold compound may be directly coupled above the metal layer. Figure 1 As shown, the mold compound 20 can encapsulate the metal layer 16. In other embodiments, as shown and discussed later herein, the metal layer 16 can be exposed through the mold compound 20. The sidewalls 22 of the mold compound 20 can be stepped, however, in other embodiments, the sidewalls 22 may not include steps.

[0068] Figure 1 The semiconductor device of the present invention, along with other semiconductor devices disclosed herein, may be coupled to or paired with other semiconductor devices, which may be semiconductor devices of the same type or different types. In various embodiments, the semiconductor devices may be paired and / or electrically / thermally coupled together via metal layer 16. By way of non-limiting example, the devices may also be paired together using wire bonding, conductive traces, or any other coupling means.

[0069] See also Figure 2 , a cross-sectional view of a second embodiment of a semiconductor device is shown. The semiconductor device 26 is similar to Figure 1 The semiconductor device 2 is different in that the molding compound 28 is Figure 1 The molding compound 20 is thicker. However, in various embodiments, the molding compound may be thicker than Figure 1 The thickness of the mold compound shown is thinner. Additionally, in various embodiments, the sidewalls 30 of the mold compound 28 are not stepped.

[0070] See also Figure 3 , shows a cross-sectional side view of a third embodiment of a semiconductor device. The semiconductor device 32 is similar to Figure 1The semiconductor device 2 is similar to the semiconductor device 2, except that the length and width of the metal layer 34 are the same as the length and width of the tube core 4. By being the same as the length and width of the tube core, the metal layer is exposed on the sidewalls of the semiconductor device. The semiconductor device 32 may also include a molding compound 36 coupled to the metal layer 34. Figure 3 As shown, the mold compound may be directly coupled to the metal layer without being directly coupled to any sidewalls 38 of the metal layer 34. In various embodiments, Figure 3 The semiconductor device can be paired with any number of other semiconductor devices. Figure 3 In such embodiments, the devices may be positioned side-by-side such that metal layer 16 directly contacts a metal layer of another semiconductor device, thereby allowing the semiconductor devices to be electrically paired through the metal layer on the back side of the semiconductor devices.

[0071] In other embodiments, the semiconductor device may have a conductive layer coupled over the metal layer 34 instead of the mold compound 36. The conductive layer may be any type of conductive layer disclosed herein. Such an embodiment is similar to the embodiment of the present invention. Figure 5 The embodiment shown differs in that the sidewalls of the conductive layer and the metal layer may be coextensive with the sidewalls of the die.

[0072] See also Figure 4 , shows a cross-sectional side view of a fourth embodiment of a semiconductor device. The semiconductor device 40 may be similar to Figure 1 The semiconductor device of the present invention is different in that there is no molding compound coupled to the metal layer 42. In such an embodiment, the perimeter of the metal layer can be coextensive with the side of the tube core 44, such as Figure 3 As shown in the metal layer, or the periphery of the metal layer 42 can be set from the side of the tube core, such as Figure 4 shown.

[0073] See also Figure 5 , a cross-sectional view of a fifth embodiment of a semiconductor device is shown. The semiconductor device 46 may be similar to Figure 4 The semiconductor device of the present invention is different in that the conductive layer 48 is formed above the metal layer 50. In various embodiments, the layer can be thermally conductive and / or electrically conductive. In various embodiments, the conductive layer can be a second metal layer and can include any metal or metal alloy disclosed herein, including Ni, SnAg, and NiAu by way of non-limiting example. In a specific embodiment, the conductive layer 48 can be a bump or a pad. The conductive layer, bump, or pad may or may not be coextensive with the side 52 of the metal layer 50.

[0074] See also Figure 6 , a cross-sectional view of a sixth embodiment of a semiconductor device is shown. The semiconductor device 54 may be similar to Figure 4The semiconductor device of the present invention is shown in FIG. 1 , except that the mold compound 56 is directly coupled to the sidewalls 58 of the metal layer 60. Because the mold compound 56 is only coupled to the sidewalls of the metal layer 60, the surface of the metal layer parallel to the plane formed by the largest surface of the die is exposed through the mold layer 56.

[0075] See also Figure 7 , a cross-sectional view of a seventh embodiment of a semiconductor device is shown. The semiconductor device 62 may be similar to Figure 5 The semiconductor device of FIG. 1 is different in that the mold compound 64 is directly coupled to the sidewalls of both the metal layer 66 and the conductive layer 68 coupled above the metal layer. Figure 7 In the embodiment shown, the mold compound is not over the conductive layer 68, so the conductive layer is exposed through the mold compound 64. The conductive layer can be Figure 5 The conductive layers are the same or similar.

[0076] Throughout the present disclosure, the term "above" is used with respect to various layers and elements. The term is not meant to express an upward or downward position in the drawings, but is intended to express a relative external position. For example, the term "above" is used with respect to various layers and elements. Figure 7 In the upper (above) and lower (below) directions of die 70, layers placed above die 70 will be "above" the die, and layers placed below metal layer 66 will similarly be "above" the metal layer.

[0077] See also Figure 8 , a graph showing the on-resistance of various embodiments of semiconductor devices is shown. The Y-axis of the graph shows the on-resistance in milliohms (mΩ). The X-axis of the graph shows the thickness of the silicon die in microns. The resistance of the die with different thicknesses of the back metal is shown by four lines in the graph. As shown in the graph, as the thickness of the silicon layer decreases, the on-resistance decreases, and as the thickness of the back metal increases, the on-resistance also decreases. The first star represents a first semiconductor device having a silicon die with a thickness of 125 μm and a back metal layer with a thickness of 6 μm. It has an on-resistance of 2.6 mΩ. The second star represents a second semiconductor device having a silicon die with a thickness of 75 μm and a back metal layer with a thickness of 15 μm. The on-resistance of the second semiconductor device is 1.9 mΩ. The third star represents a third semiconductor device having a silicon die with a thickness of 25 μm and a back metal layer with a thickness of 15 μm. The third semiconductor device has an on-resistance of 1.6 mΩ. As shown in the graph, as the thickness of the silicon layer decreases, the on-resistance decreases, and as the thickness of the back metal increases, the on-resistance also decreases. Such low on-resistance may be beneficial for semiconductor devices used in various applications, including fast charging systems. In addition, by significantly reducing the thickness of the die, the overall size of the semiconductor package can be reduced.

[0078] See also Figure 9-Figure 24, showing the use for forming Figure 1-Figure 7 See the various methods of various semiconductor devices shown in . Fig. 9 , showing a cross-sectional view of a wafer. In various embodiments, a method of forming a semiconductor device includes providing a wafer 76 having a first side 78 and a second side 80. In various embodiments, the wafer 76 can be silicon. It should be understood that where the present disclosure refers to a silicon layer, the silicon layer can be any type of silicon layer, including, by way of non-limiting example, an epitaxial silicon layer, silicon on insulator, polysilicon, any combination thereof, or any other silicon-containing substrate material. Fig. 9 As shown, wafer 76 may include epitaxial silicon portion 82. Additionally, it should also be understood that in various embodiments, substrates other than silicon-containing substrates may be used, such as, by way of non-limiting example, gallium arsenide or metal-containing substrates. In various embodiments, the method may include partially / completely forming a plurality of semiconductor devices within wafer 76. In particular embodiments, a plurality of power semiconductor devices may be partially / completely formed within epitaxial silicon portion 82, including, by way of non-limiting example, MOSFETs, IGBTs, or any other power semiconductor devices. Fig. 9 In the illustrated embodiment, a plurality of trench MOSFETs 84 are partially formed within the epitaxial silicon portion 82. The portion of the power semiconductor device formed within the wafer 76 may include wiring / routing to allow the semiconductor device to be connected to other package components and / or circuits when in use. In such embodiments, the wiring may be aluminum or any other conductive material disclosed herein.

[0079] In various embodiments, a method for forming a semiconductor device may include forming a conductive layer 86 over a first side 78 of a wafer 76. In various embodiments, and as Fig. 9 As shown, the conductive layer may be patterned, however, in other embodiments, the conductive layer may not be patterned. The conductive layer may be a metal or a metal alloy, and in such embodiments, by way of non-limiting example, may include aluminum, copper, gold, silver, titanium, nickel, any other metal, and any combination thereof, including those disclosed herein.

[0080] In various embodiments, a method for forming a semiconductor device may include forming a plurality of contact pads 88 coupled to a first side 78 of a wafer 76. Fig. 9As shown, the conductive layer 86 can separate the contact pads 88 from the wafer 76. In other embodiments, the method may include forming the contact pads directly to the wafer and omitting the conductive layer from the process of forming the semiconductor device. In various embodiments, the plurality of contact pads 88 can form a solder top metal (STM) and can be made of any metal or metal alloy. In a specific embodiment, the plurality of contact pads can be NiAu. In such embodiments, the NiAu contact pads can be formed onto the conductive layer 86 or the wafer 76 by chemical plating. The plurality of contact pads 88 can be considered to be on the source side of the wafer 76.

[0081] Still see Fig. 9 , a method of forming a semiconductor device may include applying a passivation layer 90 to the wafer 76, the conductive layer 86, and / or the plurality of contact pads 88. The passivation layer 90 may be any type of passivation layer previously disclosed herein. The passivation layer 90 may at least partially encapsulate the conductive layer 86. Additionally, the plurality of contact pads 88 may be exposed through the passivation layer 90. In a particular embodiment, the passivation layer 90 may initially cover the plurality of contact pads 88, and the plurality of contact pads 88 may be exposed through the passivation layer by back grinding or chemical mechanical polishing (CMP) of the passivation layer. Additionally, as Fig. 9 As shown, a surface 92 of the passivation layer 90 may be coplanar with a plane formed by exposed portions of the plurality of contact pads 88. By way of non-limiting example, the passivation layer 90 and the plurality of contact pads 88 may be planarized using a CMP technique.

[0082] In other embodiments, the method for forming a semiconductor package may include forming an intermediate layer between the conductive layer 86 and the contact pad 88. The intermediate layer may be an electroplated metal layer, and in a specific embodiment, may be electroplated copper. The intermediate layer may include an alloy, including Ni, Au, Pd, Cu, and any combination thereof, by way of non-limiting example. In other embodiments, the intermediate layer may be sputtered onto the conductive layer 86. In various embodiments, the method for forming the intermediate layer may include forming a plurality of layers within the intermediate layer. In such embodiments, one of the plurality of layers may be a seed layer, which may include Ti or Cu. In a specific embodiment, the method for forming a semiconductor package may include patterning the intermediate layer into a plurality of intermediate pads. In the case where the method for forming the intermediate layer includes forming a plurality of layers within the intermediate layer, each layer within the intermediate layer may have a different pattern, which forms an intermediate pad with a stepped sidewall. During the process of forming the intermediate layer, the seed layer may be etched after the material forming the pad 88 is formed. As an example, the intermediate layer may be patterned to form a plurality of intermediate pads having a first portion directly coupled to the conductive layer having a cross-sectional width smaller than a second portion of the plurality of intermediate pads directly coupled to the contact pad 88. In embodiments where the intermediate pads are formed, the passivation layer may fully or partially cover the sidewalls of the intermediate pads.

[0083] See also Fig.10 , showing a device having a groove formed therein Fig. 9 . In various embodiments, a method of forming a semiconductor device includes forming a groove 94 in the second side 80 of the wafer 76. By forming the groove 94, the wafer 76 can be thinned. In various embodiments, the groove 94 can be formed by back grinding the second side 80 of the wafer 76. In such embodiments, a back grinding tape 100 can be coupled to the contact pad. In a specific embodiment, the groove 94 can be formed by back grinding using a process sold by DISCO, Tokyo, Japan under the trade name TAIKO. Back grinding leaves a ring 96 (TAIKO ring) of unremoved material, which helps prevent the wafer from curling, warping or otherwise bending during processing, while removing most of the thickness and material of the second side 80 or the back side of the wafer 76. In other embodiments of the method of forming a semiconductor device, the TAIKO process may not be used, but some other back grinding or other material removal techniques may be used, such as removing material by wet etching. In various embodiments, the thickness of thinned portion 98 of wafer 76 may be thinned to about 25 μm, about 40 μm, about 75 μm, greater than about 75 μm, between about 25 μm and about 75 μm, less than about 30 μm, and less than about 25 μm.

[0084] See also Fig.11 , showing Fig.10 A cross-sectional side view of a wafer of FIG. 1 , wherein a mask is formed in a recess. The mask can be formed using a variety of processes, including, by way of non-limiting example, photolithography, film attachment, and other methods of forming a pattern in the recess. The method can also include forming a patterned photoresist layer 104 within the recess 94. In various embodiments, the method of forming a semiconductor device also includes coating the recess 94 with a seed layer 102 before or after forming the mask. The seed layer 102 can be a metal or a metal alloy. In a specific embodiment, the seed layer can be TiCu or TiWCu. In various embodiments, the interior of the recess can be coated with the seed layer 102 by sputtering. See FIG. Fig.12 , showing Fig.1094, wherein a metal layer is formed in the groove. In various embodiments, the method of forming a semiconductor device may include forming a metal layer 106 or a back metal in the groove 94. The metal layer 106 may include copper, aluminum, gold, silver, nickel, titanium, any other metal, and any combination thereof. In embodiments where the seed layer 102 is coupled to the wafer 76 in the groove 94, the metal layer 106 may be coupled to the wafer 76 via the seed layer 102. In some embodiments, the metal layer may be applied by copper plating or other metal plating processes. In other embodiments, the metal layer may be applied using a sputtering or evaporation process.

[0085] In various embodiments, metal layer 106 may include multiple layers of the same or different metals, while in other embodiments, the metal layer may include only a single layer of metal. In various embodiments, the thickness of metal layer 106 may be about 10 μm, about 25 μm, about 40 μm, less than about 10 μm, between about 10-40 μm, and greater than about 40 μm, including thicknesses as great as about 200 μm. Compared to thinned portion 98 of wafer 76, in various embodiments, the thickness of the thinned portion of the wafer is no more than about four times the thickness of metal layer 106. In more specific embodiments, the thickness of thinned portion 98 of wafer 76 may be substantially three times the thickness of metal layer 106, two and a half times the thickness of the metal layer, twice the thickness of the metal layer, or substantially the same as the thickness of metal layer 106. In other embodiments, the thickness of thinned portion 98 of wafer 76 may be greater than about four times the thickness of metal layer 106, or less than the thickness of metal layer 106.

[0086] In a specific embodiment, and as Fig.12 As shown, the method may include patterning or forming openings 108 in the metal layer 106 . Fig.11 The photoresist layer 104 may be used to form the pattern of the openings 108 or metal layer 106. After the metal layer 106 is formed within the recesses 94, the photoresist layer 104 and portions of the seed layer 102 may be stripped. In various embodiments, the metal layer 106 may not include scribe lines, which may reduce debris from the wafer 76 (and therefore, the diced dies) when the wafer is to be diced.

[0087] See also Fig.13 , showing Fig.12 94 , wherein the mold compound is formed over the metal layer. The method of forming a semiconductor device may include coupling the mold compound 112 to the metal layer 106 within the recess 94. The mold compound 112 may be applied to prevent oxidation of the metal layer 106 and to protect the metal layer from physical damage. In various embodiments, the mold compound 112 may be coupled directly over the metal layer 106, such as Fig.13108. In embodiments where the metal layer 106 is patterned, the mold compound 112 may also be within the opening 108 within the metal layer 106. In various embodiments, the mold compound 112 may have a substantially constant thickness so that the opening 108 is not completely filled with the mold compound 112. By way of non-limiting example, the mold compound 112 may be applied to the metal layer 106 using a liquid dispensing technique, a transfer molding technique, a printer molding technique, a compression molding technique, or a lamination technique. In various embodiments, by way of non-limiting example, the mold compound 112 may be an epoxy mold compound, an acrylic mold compound, or any other type of mold compound or protective covering.

[0088] See also Fig.14 , showing Fig.13 96 . A cross-sectional side view of a wafer of FIG. 76 in which a portion of a ring of the wafer is removed. In various embodiments, a method for forming a semiconductor device may include removing a portion of ring 96. In a particular embodiment, the portion of ring 96 may be removed by back grinding ring 96. In other embodiments, the ring may be at least partially removed using other removal techniques or methods, such as sawing the ring away cyclically around the edge of the wafer. In various embodiments, enough of ring 96 is removed so that a surface 114 of ring 96 or wafer 76 is coplanar with a surface 116 of mold compound 112. In other embodiments, portions of the ring may be partially removed, but not to the extent that surface 114 of ring 96 is planarized with surface 116 of mold compound 112. In various embodiments, the method may include removing back grinding tape 90 from the source side of wafer 76 and applying new back grinding / dicing tape 118 to the contact pads, such as Fig.14 shown.

[0089] See also Fig.15 , showing the belt rotating with the molding compound applied to it Fig.14 A method for forming a semiconductor device may include applying a tape to the back side of wafer 76, or to mold compound 112. In various embodiments, and as Fig.15 As shown, wafer 76 may be removed from back grinding / dicing tape 118 as shown. Fig.14 As shown, the wafer may be rotated with the backside of the wafer and / or mold compound 112 reapplied to the back grinding tape 118 (or initially applied to the sawing tape for dicing), as shown. Fig.15 shown.

[0090] See also Fig.16 , showing the cutting Fig.15The method for forming semiconductor devices includes cutting the wafer 76 into a plurality of semiconductor devices 120. By way of non-limiting example, the wafer 76 may be cut by blade cutting, laser cutting, water jet cutting, etching, or any other cutting method. Fig.16 As shown, each of the semiconductor devices 120 is Figure 1 The semiconductor components 2 shown are identical.

[0091] See also Figure 17-Figure 18 , showing the formation Figure 1 For details, see Fig.17 , showing Fig.13 Cross-sectional side view of a wafer with tape applied to the molding compound. Fig.17 The method may include applying tape 122 to mold compound 112 and to ring 96 of wafer 76 instead of back grinding ring 96, as shown. Fig.14 Then, as indicated by cut 124, ring 96 may be removed from the metal layer by cutting through passivation layer 90, wafer 76, and mold compound 112. Fig.18 , showing the cut Fig.17 The method may include dicing the wafer 76 into a plurality of semiconductor devices 126. The wafer may be diced using any dicing method disclosed herein. Fig.18 The plurality of semiconductor devices 126 shown may be Figure 1 The semiconductor components 2 shown are identical.

[0092] See also Fig.19 , showing Fig.12 Cross-sectional side view of a wafer with molding compound filling the recesses. Fig.19 An alternative method for forming a semiconductor device is shown. Fig.19 The method shown may include completely filling the recess 94 with the mold compound 128, rather than forming the mold compound 112 to have a uniform thickness over the entire length of the protective coating covering the metal layer 106, as shown in FIG. Fig.13 The mold compound 128 may be applied to the recess using any of the techniques disclosed herein and may be any type of mold compound or other protective coating disclosed herein. Fig.19 As shown, Fig.13 In contrast, the outer surface 130 of the mold compound 128 has a smooth surface that does not follow the contours of the patterned metal layer 106, and thus the mold compound 128 may have a different thickness. In other words, the mold compound 128 may completely fill the opening 108 within the metal layer 106. The mold compound 128 may increase chip strength and may be particularly useful in embodiments where the thickness of the thinned portion 98 of the wafer 76 is less than about 30 μm.

[0093] In other embodiments, rather than having mold compound 128 completely fill recess 94, the mold compound may only partially fill the recess. In such embodiments, outer surface 130 of mold compound 128 may still have a smooth surface that does not follow the contours of patterned metal layer 106, however, outer surface 130 may not be coplanar with the ends of ring 96.

[0094] Still see Fig.19 In various embodiments, the method for forming the semiconductor device may include back grinding the ring 96, the mold compound 128, or both the ring and the mold compound. The wafer 76 may then be cut into a plurality of semiconductor devices using any of the cutting methods previously disclosed herein. The plurality of cut semiconductor devices may be cut into a plurality of semiconductor devices. Figure 2 Because the mold compound 128 completely fills the opening 108 in the metal layer 106, the cut semiconductor device can have a mold compound 28 that has a sidewall 30 that is not stepped, such as Figure 2 shown.

[0095] See also Fig. 20 , showing Fig.10 A cross-sectional side view of a wafer in which an unpatterned metal layer is formed within the recesses. Fig. 20 An alternative method for forming a semiconductor device is shown. The method may include forming a solid metal layer 132 coupled to the wafer 76, rather than forming a patterned metal layer 106, such as Figure 11-Figure 12 As shown. In various embodiments, the seed layer 102 may be between the metal layer 132 and the wafer 76. The method may include coating the metal layer 132 with a protective coating, which may be a mold compound 134. The mold compound 134 may partially fill the groove 94, while in other embodiments, it may completely fill the groove 94. In various embodiments, the method for forming the semiconductor device may include back grinding the ring 96, the mold compound 134, or both the ring and the mold compound. The wafer 76 may then be cut into a plurality of semiconductor devices using any of the cutting methods previously disclosed herein. The plurality of cut semiconductor devices may be cut with Figure 3 By not patterning the metal layer 132, the semiconductor device 32 shown in FIG. Figure 11-Figure 12 This approach can potentially save costs compared to the approach shown.

[0096] In other embodiments, the method for forming a semiconductor device may include forming a conductive layer onto the metal layer 132 instead of coating the metal layer 132 with the mold compound 134. The conductive layer may be any type of conductive layer disclosed herein, including Ni, NiAu, SnAg. In various embodiments, the method may include plating the conductive layer onto the metal layer, while in other embodiments, the conductive layer is applied to the metal layer by sputtering, evaporation, or other deposition techniques. The method for forming a semiconductor device may include back grinding ring 96. The wafer 76 may then be cut into a plurality of semiconductor devices using any of the cutting methods previously disclosed herein. The plurality of cut semiconductor devices may be similar to Figure 3 The semiconductor device 32 is shown in FIG. 3 , except that instead of a molding compound over the metal layer, the semiconductor device has a conductive layer over the metal layer.

[0097] See also Fig.21 , showing Fig.12 A cross-sectional side view of a wafer with a portion of the ring of the wafer removed. Fig.21 An alternative method for forming a semiconductor device is shown. The method may include not covering the metal layer 106 with any type of molding compound or protective covering, and instead forming a molding compound over the metal layer 106, such as Fig.13 and Fig.19 In various embodiments, the method for forming a semiconductor device may include a back grinding ring 96. The wafer 76 may then be cut into a plurality of semiconductor devices using any of the cutting methods previously disclosed herein. The plurality of cut semiconductor devices may be cut into a plurality of semiconductor devices. Figure 4 The semiconductor device 40 shown in FIG.

[0098] See also Fig. 22 , showing Fig.21 A cross-sectional side view of a wafer with bumps formed over a metal layer. Fig. 22 An alternative method for forming a semiconductor device is shown. The method may include forming a plurality of bumps / pads 136 over the metal layer 106, rather than leaving the metal layer 106 uncovered, such as Fig.21 As shown. In various embodiments, the plurality of bumps 136 can be considered as a second metal layer above the metal layer 106. The plurality of bumps 136 can be any type of material disclosed herein. In various embodiments, the method for forming the semiconductor device can include back grinding ring 96. The wafer 76 can then be cut into a plurality of semiconductor devices using any of the cutting methods previously disclosed herein. The plurality of cut semiconductor devices can be cut with Figure 5 The semiconductor device 46 shown in FIG.

[0099] See also Fig.23 , showing Fig.21A cross-sectional side view of a wafer with molding compound formed between openings in the metal layer. Fig.23 An alternative method for forming a semiconductor device is shown. Fig.21 In contrast, Fig.23 The method shown includes coupling a mold compound 138 within the opening 108 of the metal layer 106 while exposing the metal layer through the mold compound 138. An outer surface of the mold compound 138 can be coplanar or substantially coplanar with an outer surface of the metal layer 106. In various embodiments, the mold compound 138 can initially cover the metal layer 106, such as Fig.19 138, but may then be back ground to expose metal layer 106 through mold compound 138. In various embodiments, the method for forming semiconductor devices may include back grinding ring 96, mold compound 138, or both the ring and the mold compound. Wafer 76 may then be cut into a plurality of semiconductor devices using any of the cutting methods previously disclosed herein. The plurality of cut semiconductor devices may be cut with Figure 6 The semiconductor device 54 shown in FIG.

[0100] See also Fig.24 , showing Fig. 22 A cross-sectional side view of a wafer with molding compound formed between openings in the metal layer. Fig.24 An alternative method for forming a semiconductor device is shown. Fig. 22 In contrast, Fig.24 The method shown includes coupling a mold compound 140 within the opening 108 of the metal layer 106 while exposing the plurality of bumps 136, or the second metal layer, through the mold compound 140. An outer surface of the mold compound 140 may be coplanar with an outer surface of the plurality of bumps 136. In various embodiments, the mold compound 140 may initially cover the plurality of bumps 136, but may then be back ground to expose the plurality of bumps through the mold compound 140. In various embodiments, the method for forming a semiconductor device may include back grinding the ring 96, the mold compound 140, or both the ring and the mold compound. The wafer 76 may then be cut into a plurality of semiconductor devices using any of the cutting methods previously disclosed herein. The plurality of cut semiconductor devices may be cut together with the semiconductor device. Figure 7 The semiconductor device 62 shown in FIG.

[0101] See also Figure 25A-25B , showing a process for cutting a substrate having a back side protection (BSP) layer applied thereto. Figure 25A-25B The methods shown can be incorporated into any method embodiments previously disclosed herein. Fig.25AAs shown, wafer 142 may be coupled to metal layer 144. In various embodiments, the metal layer may be coupled to BSP layer 146. In various embodiments, the BSP layer may be a tape including epoxy resin and may include glass filler. In a particular embodiment, the BSP layer may be manufactured by LINTEC Corporation, Tokyo, Japan under the trade name Wafer backside coating tape is sold as BSP. The BSP layer may be coupled to tape 148 that is used to hold the wafer during dicing of the wafer.

[0102] Fig.25B Wafer 142, metal layer 144, and BSP layer 146 are shown after being cut to form semiconductor device 150. Fig.25B As shown, the sidewalls 152 where the wafer, metal layers, and BSP are cut form a clean cut, meaning that different layers do not extend into adjacent layers, including the strips 148. In contrast, and see Figure 26A-26B , showing a process for cutting a substrate having no BSP layer applied thereto. Fig.26A Wafer 154 is shown coupled to a metal layer 156 which is directly coupled to a tape 158 for holding the wafer during dicing. Fig.26B As shown, it shows the semiconductor device 160 cut into Fig.26A 162, a material burr 162 generated by cutting metal layer 156 may extend into tape 158. In various embodiments, cutting a metal layer directly coupled to a non-BSP tape may generate a burr similar to burr 162, which may prevent semiconductor devices 160 from being removed from tape 158 during a die pick operation.

[0103] In various embodiments of the semiconductor devices disclosed herein, the thickness of the die may be less than 30 microns.

[0104] In other embodiments, the die is substantially as thick as the thickness of the metal layer.

[0105] In various implementations, the mold compound may be coupled directly to the metal layers of the device.

[0106] In various implementations, the mold compound may be coupled directly over the metal layer.

[0107] In various embodiments of a method of forming a semiconductor device like those disclosed herein, the method may include forming a conductive layer between the contact pad and the first side of the wafer.

[0108] In various method embodiments, the thickness of the metal layer is substantially the same as the thickness of the wafer.

[0109] In various method embodiments, the thickness of the metal layer is substantially three times the thickness of the wafer.

[0110] In various embodiments of the method, the mold compound may encapsulate the metal layer.

[0111] In various method embodiments, the method further includes coating the recess with a seed layer.

[0112] In various method embodiments, the method includes forming a plurality of bumps over a metal layer.

[0113] In various method implementations, the method may include coupling a metal layer, a mold compound, or a plurality of bumps to the backside protection layer and then dicing the wafer.

[0114] Where specific embodiments of semiconductor devices and implementing components, sub-components, methods and sub-methods are mentioned in the above description, it should be readily apparent that various modifications may be made without departing from the essence thereof, and that these embodiments, implementing components, sub-components, methods and sub-methods may be applied to other semiconductor devices.

Claims

1. A semiconductor device, comprising: a die comprising a first side and a second side; a contact pad coupled to the first side of the die; a metal layer coupled to the second side of the die; and a molding compound directly coupled to the metal layer; wherein an outer sidewall of the molding compound includes a step facing away from the metal layer; wherein the thickness of the tube core is less than 30 microns; wherein the contact pads are exposed through a passivation layer coupled over the die; wherein the tube die is a sawn tube die; wherein the molding compound covers and contacts an outermost sidewall of the metal layer; wherein an outer sidewall of the tube core is coplanar with an outermost sidewall of the molding compound; and The periphery of the entire metal layer is smaller than the periphery of the tube core and is located within the periphery of the tube core.

2. A semiconductor device comprising: a die comprising a first side and a second side; a contact pad coupled to the first side of the die; a metal layer coupled to the second side of the die; and a molding compound directly coupled to and over an entire first surface of the metal layer, the entire first surface of the metal layer being opposite a second surface of the metal layer facing the second side of the die; wherein an outer sidewall of the molding compound includes a step; wherein the die is cut from a wafer; wherein the molding compound covers and contacts an outermost sidewall of the metal layer; wherein an outer sidewall of the tube core is coplanar with an outermost sidewall of the molding compound; and The periphery of the entire metal layer is smaller than the periphery of the tube core and is located within the periphery of the tube core.

3. A method for forming a semiconductor device, comprising: forming a plurality of contact pads coupled to the first side of the wafer; forming a groove in a second side of the wafer by back grinding the wafer, the second side being opposite to the first side of the wafer; forming a metal layer in the groove; patterning the metal layer in the groove; coupling a molding compound to the metal layer within the recess; removing a portion of the wafer until the portion of the wafer is coplanar with a plane formed by a portion of the molding compound; as well as The wafer is cut into a plurality of semiconductor devices. The method of claim 3 , wherein the metal layer is exposed through the mold compound. The method of claim 3 , wherein the mold compound is coupled directly over the metal layer. 6 . The method of claim 3 , further comprising thinning the wafer by forming the groove, wherein a portion of the wafer is thinned to less than 30 microns.

7. A method for forming a semiconductor device, comprising: forming a plurality of contact pads coupled to the first side of the wafer; forming a groove in a second side of the wafer by back grinding the second side of the wafer, the second side being opposite to the first side; forming a metal layer in the groove; forming a plurality of openings in the metal layer; forming a molding compound into the plurality of openings of the metal layer; removing a portion of the wafer until the portion of the wafer is coplanar with a plane formed by a portion of the molding compound; as well as The wafer is cut into a plurality of semiconductor devices. The method of claim 7 , further comprising coupling a second metal layer over the metal layer.

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