Non-volatile memory device with switchable read mode and reading method thereof

Abstract

Embodiments of the present disclosure relate to a non-volatile memory device with a switchable read mode and a method for reading the same. A non-volatile memory device that can switch between different read modes is described herein. In particular, the memory device includes a plurality of memory cells and can alternately implement differential type reading and single-ended type reading. A method for reading a memory device is further described herein.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102018000003796, filed on March 20, 2018, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a non-volatile memory device that can switch between different read modes; in addition, the present disclosure relates to a method for reading the memory device. Background Art

[0004] Phase change memory (PCM) is a new generation of non-volatile memory in which, in order to store information, the properties of materials with the property of switching between phases of different electrical characteristics are exploited. These materials can switch between a disordered / amorphous phase and an ordered, crystalline or polycrystalline phase; the different phases are characterized by different resistivity values ​​and are therefore associated with different values ​​of the stored data. For example, elements of Group VI of the periodic table, such as tellurium (Te), selenium (Se) or antimony (Sb), known as "chalcogenides" or "chalcogenides", can be used to manufacture phase change memory elements. In particular, alloys consisting of germanium (Ge), antimony (Sb) and tellurium (Te), known as GST (with the chemical composition Ge2Sb2Te5), are currently widely used in such memory cells.

[0005] The phase change in the memory element can be obtained by locally increasing the temperature of the cell of chalcogenide material via a resistive electrode (often referred to as a "heater") arranged in contact with the chalcogenide material region.

[0006] The access (or selection) devices (eg bipolar or MOS transistors) are connected to the heaters so that a programming current (also called a write current) can be selectively passed through them. This current generates the temperature required for the phase change through the Joule effect.

[0007] In particular, when the chalcogenide material is in an amorphous state and therefore has a high resistivity (the so-called RESET state), it is necessary to apply a current / voltage pulse (or an appropriate number of current / voltage pulses) with a certain duration and amplitude so that the chalcogenide material can be slowly cooled. After this treatment, the chalcogenide material changes state and switches from a high resistivity state to a low resistivity state (the so-called SET state). Conversely, when the chalcogenide material is in the SET state, it is necessary to apply a current / voltage pulse with an appropriate duration and a large amplitude so as to return the chalcogenide material to the high resistivity amorphous RESET state.

[0008] During reading, the state of the chalcogenide material is detected by applying a voltage low enough not to cause its thermal heating, and then reading the value of the current flowing in the memory cell via a sense amplifier. Assuming that the current is proportional to the conductivity of the chalcogenide material, it is possible to determine which state the material is in, and therefore the data stored in the memory cell.

[0009] An example of a PCM device in which the selector element is formed by a bipolar transistor of the PNP type is described in Italian patent application No. 102017000108905 filed on September 28, 2017 in the name of the present applicant, and in which Figure 1 The PCM device (designated by 1) is illustrated in FIG.

[0010] In particular, the PCM device 1 comprises a memory array 2 formed of a plurality of memory cells 3 arranged in rows (or word lines WL) and columns (or bit lines BL). Purely by way of example, Figure 1 Three word lines designated by WL and three bit lines designated by BL are illustrated in , which enable nine memory cells 3 to be addressed.

[0011] Each memory cell 3 is formed of a storage element 4a and a selector element 4b, which are connected in series between a corresponding bit line BL and a reference potential terminal (eg, ground, abbreviated as GND).

[0012] The memory element 4a comprises an element made of a phase-change material (for example a chalcogenide such as GST) and is therefore capable of storing data in the form of resistance levels associated with the different phases assumed by the material itself.

[0013] The selector element 4b is formed by a bipolar junction transistor (BJT) of the PNP type, whose emitter terminal is connected to the first terminal of the storage element 4a, and the base terminal is connected to the corresponding word line WL; the collector terminal of the bipolar transistor is connected to the ground. In this regard, one word line WL is connected to all base terminals of the bipolar transistors 4b aligned along the same row; similarly, one bit line BL is connected to all second terminals of the storage elements 4a aligned along the same column.

[0014] In practice, given a memory cell 3, the second terminal of the storage element 4a and the base terminal of the bipolar transistor 4b form a bit line terminal and a word line terminal of the memory cell 3, respectively.

[0015] The PCM device 1 further comprises a column decoder 8 and a row decoder 10, which enable the selection of the memory cells 3 based on an address signal (specified as a whole by AS) received at the input. The address signal AS may be generated by a control logic CL, which also drives the column decoder 8 and the row decoder 10, so as to enable reading and writing (also referred to as programming) of the memory cells 3 addressed by the address signal AS. The control logic CL also provides control signals to the column decoder 8 and the row decoder 10, so as to control the above-mentioned read / write operations.

[0016] The column decoder 8 and the row decoder 10 enable biasing of the word line WL and the bit line BL addressed each time, thereby selecting the memory cell 3 connected thereto; in this way, the memory cell 3 is enabled to be read and written.

[0017] In more detail, the row decoder 10 is designed to select a corresponding word line WL based on the address signal AS. The other word lines WL are deselected. For this purpose, the row decoder 10 comprises a decoder stage 4 and a plurality of driver circuits 6.

[0018] The decoder stage 4 receives the address signal AS and controls the driver circuits 6 according to the address signal AS. Therefore, each driver circuit 6 has an input connected to the decoder stage 4. Each driver circuit 6 also has an output connected to the corresponding word line WL.

[0019] Each drive circuit 6 biases the base terminal of the bipolar transistor 4b connected to the corresponding word line WL and thereby controls it so as to select / deselect the word line WL according to the address signal AS.

[0020] As for the column decoder 8, it selects one or more bit lines BL according to the address signal AS. In practice, the column decoder 8 cooperates with the row decoder 10 so that during the step of reading or programming any selected memory cell 3, a reading current or a programming current respectively flows through the storage element 4a of the memory cell 3.

[0021] In particular, the column decoder 8 is configured to internally implement two different paths toward the bit lines BL each time the memory array 2 is selected: a read path that electrically connects each selected bit line BL to the read stage 17 during a read step; and a program path that electrically connects each selected bit line BL to the write stage 18 during a programming step.

[0022] To this end, the column decoder 8 comprises, for each reading and programming path, appropriate selection elements (in particular controlled transistors) connected in cascade mode and configured to implement an address decoding (generally of the hierarchical type) for selecting the memory cells 3 .

[0023] like Figure 2 As schematically illustrated in FIG. 1 , the memory array 2 is typically arranged in a plurality of sectors S, each sector S comprising a plurality of memory cells 3. Each sector S comprises a plurality of respective word lines WL and respective local bit lines (again designated by BL and distinguished from those of other sectors), which are connected to the memory cells 3 of the memory array 2 present in the same sector S. In addition, for each set formed by a number k (e.g., four) of local bit lines BL, a corresponding master bit line MBL is provided. When selected at a higher hierarchical level, the master bit line MBL enables subsequent selection of one or more of the respective local bit lines BL and the corresponding memory cells 3 at a lower hierarchical level. Typically, the use of the adjective "local" when referring to a bit line or a word line emphasizes that it belongs to a sector.

[0024] The master bitlines MBL traverse a certain number of sectors S and can be selected in groups in a hierarchical decoding level (even higher than the decoding level associated with the selection of the master bitlines MBL).

[0025] Therefore, the column decoder 8 comprises: for each sector S at least one corresponding first stage decoder circuit (in Figure 2 11 in the table), which enables the local bit lines BL to be connected to the corresponding main bit lines MBL during programming operations and during read operations; and for each set of sectors S (in Figure 2 In the example of FIG. 1 , a corresponding second stage decoder circuit (designated by 114) is formed of two sectors, which enables selection of the main bit line MBL during programming operations and during reading operations.

[0026] Generally, a decoder circuit for PCM with a BJT selector is provided with a P-channel CMOS transistor.

[0027] As has been said, for simplicity, in the following, "first stage decoder circuit" and "second stage decoder circuit" are meant to refer to the relevant read circuit. Figure 3 A scheme of the type illustrated in , in which a first stage decoder circuit is designated by 11 and a second stage decoder circuit is designated by 114.

[0028] Reference again Figure 3 , which shows how the control logic CL sends the main column decoding signal YN to the second stage decoder circuit 114 On this basis, the second stage decoder circuit 114 activates the selected master bit line (herein MBL) by activating the corresponding master selection switch (described below). 4 and 5. In this regard, the reading stage 17 includes a plurality of sense amplifiers, although only the sense amplifier 46 is referred to hereinafter.

[0029] As mentioned earlier, Figure 3 It is further shown that given each sector S, each main bit line MBL how it is associated with (i.e., it can be electrically coupled to) a corresponding set of local bit lines (here denoted by BL<i,j> In addition, given a sector S, the corresponding first stage decoder circuit 11 is able to address the local bit lines BL coupled to the<i,j> This is due to the presence of local selection switches, which are decoded by the corresponding local column decoding signal YO generated by the control logic CL.<i,j> drive.

[0030] The PCM device 1 implements a differential read scheme. In other words, the memory array 2 is operably divided into pairs of memory cells 3, which are written so that when a cell in the pair is in the SET / RESET state, the other cell is in the RESET / SET state. In addition, the reading of the memory array 2 is performed in pairs. In particular, the read stage 17 is configured to compare the read currents circulating in the corresponding pairs of memory cells 3. The cells in the pair (also referred to as complementary cells) are arranged in the same row (word line). Likewise, the write stage 18 is configured to provide appropriate programming currents to the corresponding pairs of memory cells 3 so as to program the memory cells 3 of each pair to opposite states.

[0031] In more detail, when the memory cell 3 is selected, the base terminal of its bipolar transistor 4b is set to approximately zero voltage. In contrast, when the memory cell 3 is not selected, the base terminal of its bipolar transistor 4b is set to a positive voltage. In addition, in the case of programming the RESET state, there is a voltage drop of typically between 1.1V and 2.1V on the storage element 4a; in the case of programming the SET state, there is a voltage drop of typically between 1.1V and 1.7V on the storage element 4a; again, in the case of performing a read operation, there is a voltage drop of approximately 0.4V on the storage element 4a. In general, the voltage present on the second terminal of the storage element 4a and therefore the voltage that needs to be applied to the corresponding bit line BL depends on the characteristic parameters of the bipolar transistor 4b.

[0032] As indicated in the portion of the first sector S' Figure 4 As shown in more detail in FIG. 1 , the memory array 2 includes a plurality of first memory cells 3′ ( Figure 4 Only one of them is shown) and a plurality of second memory units 3" ( Figure 4 The second memory cell 3" corresponds to the first memory cell 3' in terms of manufacturing characteristics and number, and stores logic data complementary to the logic data stored in the corresponding first memory cell 3'. In particular, the first and second memory cells 3', 3" are identical to each other. In addition, each memory cell is coupled to a corresponding bit line capacitor 4c, which represents the parasitic capacitance of the corresponding local bit line (respectively denoted by BL L <j>(in the case of the first memory cell 3') and BL R <j>(In the case of the second memory cell 3″), and the corresponding bit line capacitor 4c is connected in parallel with the corresponding storage element 4a and the corresponding selection element 4b in series. In addition, the pair formed by the first memory cell 3′ and the corresponding second memory cell 3″ is read in differential mode.

[0033] In more detail, Figure 4 Only one pair of complementary cells is shown, and thus only one first memory cell 3' and only one second memory cell 3" as before are shown, which are electrically coupled to the corresponding local word line WL in addition to being electrically coupled to the respective local bit line.

[0034] In use, the column decoder 8 receives at input a first local column decoded signal YO L <j>(generated by control logic CL) to select the corresponding local bit line BL L <j>, where j is an integer that can be in the range between 1 and k (as mentioned above, where k is the number of local bit lines that can be coupled to the corresponding master bit line) in order to access the corresponding memory cell 3'. In addition, the column decoder 8 receives the second local column decoding signal YO R <j>(generated by control logic CL) to select the corresponding local bit line BL R <j>, in order to access the corresponding memory cell 3".

[0035] In more detail, the column decoder 8 is configured to arrange all corresponding k local bit lines BL by closing L <i,j> The common node A and the selected bit line BL L <j>The local select switch 13a between the two switches enables the selected bit line BL L <j>and a portion of the current path between the first input 17a of the read stage 17 and arranged on all corresponding k local bit lines BL R <i,j> The common node B and the selected bit line BL R <j>The local selection switch 13b between the two bits enables the selected bit line BL R <j>and part of the current path between the second input 17 b of the reading stage 17 .

[0036] In particular, the local column decoded signal YO L <j>、YOU R <j>The local selection switches 13a and 13b are driven respectively. In addition, the corresponding local selection switch 13a corresponds to each local bit line BL L <j>, and the corresponding local selection switch 13b corresponds to each local bit line BL R <j>.

[0037] In the following, for simplicity of description, reference will always be made to Figure 4 1 and 2, and the corresponding local bit lines. In addition, the signal controlling the local selection switch 13a and the local selection switch 13b respectively coupled to the first and second memory cells 3', 3" will be referred to as the local column decoding signal Y0. L ,YO R .

[0038] The first main bit line (in Figure 4 MBL L ) extends between node A and ground, thereby forming a main bit line parasitic capacitor 9', which has a capacitance C between 30fF and 120fF, for example. MBL By inserting a corresponding main selection switch 12a, node A is coupled to the first input 17a of the reading stage 17. Likewise, by inserting a corresponding pre-charging switch 14a, node A is coupled to the charging line 19.

[0039] As described more fully below, during an operation to read the first memory cell 3', the precharge switch 14a is controlled to precharge the main line parasitic capacitor 9' at the voltage value BL_CHARGE of the charge line 19 (e.g., selected between 1.5V and 1.8V). L It is supplied to the column decoder 8 by the control logic CL so as to control the main selection switch 12a.

[0040] The second main bit line MBL R extends between node B and ground, thereby forming a main bit line parasitic capacitor 9'' having a capacitance substantially equal to that of C MBL In this regard, the first and second main bit lines MBL L 、MBL R The first and second master bit lines MBL may have the same size and may be arranged symmetrically with respect to the read stage 17. More specifically, the first and second master bit lines MBL L 、MBL R They are arranged parallel to each other and aligned in a direction perpendicular to them.

[0041] By inserting a corresponding main select switch 12b, node B is coupled to the second input 17b of the read stage 17. Likewise, by inserting a corresponding precharge switch 14b, node B is coupled to the charge line 19. As described more fully below, during an operation of reading the second memory cell 3″, the precharge switch 14b is driven to precharge the main bit line capacitor 9″ at the voltage value of the charge line 19. In addition, the main column decode signal YN R It is supplied to the column decoder 8 by the control logic CL so as to control the main selection switch 12b.

[0042] In the following, for the sake of brevity, we refer to Figure 4 The signal YN of the main selection switches 12a and 12b shown in FIG. L And YN R will be referred to as the main column decode signal YN L , YN R .

[0043] Therefore, the column decoder 8 includes two different read decoder circuits (particularly, a first read decoder block 8a and a second read decoder block 8b), which are designed to respectively implement: (i) a current path between the first memory cell 3' and the first input 17a of the read stage 17, and (ii) a current path between the second memory cell 3" and the second input 17b of the read stage 17. Therefore, the current paths generated thereby are different from each other and separated from each other. In addition, the first read decoder block 8a and the second read decoder block 8b have a mirror structure.

[0044] The PCM device 1 further comprises a charge pump 39 ( Figure 3 ), which is connected to the power supply line 19 and coupled to the second stage decoder circuit 114. In the idle state of the PCM device 1, the main bit line MBL A positive voltage, for example, between 1.5 V and 1.8 V, is provided by the charge pump 39 .

[0045] Reference again Figure 4 The selection switches 12a, 12b, 13a, and 13b are implemented by MOS transistors, and their gate terminals receive the column decoding signal YN L , YN R ,YO L ,YO R , i.e. a logic signal having a voltage value between 0 V and at least the voltage value of the charging line 19 (the voltage swing of the above signal may even be higher than the voltage swing of the charging line 19).

[0046] The charging line 19 may be electrically connected to the first and second inputs 17a, 17b of the reading stage 17 via respective voltage clamp switches 20a, 20b which may be controlled by a voltage clamp signal YMPS_CLAMP generated by the control logic CL.

[0047] The sense amplifier 46 includes a first input 46a, which is electrically coupled to the first input 17a of the reading stage 17 via a first coupling capacitor 22a and a first coupling switch 24a connected in series, the first coupling capacitor 22a having two conductive terminals, and the first coupling switch 24a also having two conductive terminals. In particular, one terminal of the first coupling capacitor 22a forms the first input 46a of the sense amplifier 46, while one terminal of the first coupling switch 24a forms the first input 17a of the reading stage 17. In addition, the other terminal of the first coupling capacitor 22a is connected to the other terminal of the first coupling switch 24a at a common node 25a.

[0048] The sense amplifier 46 includes a second input 46b, which is electrically coupled to the second input 17b of the reading stage 17 via a second coupling capacitor 22b and a second coupling switch 24b connected in series, the second coupling capacitor 22b having two conductive terminals, and the second coupling switch 24b also having two conductive terminals. In particular, one terminal of the second coupling capacitor 22b forms the second input 46b of the sense amplifier 46, while one terminal of the second coupling switch 24b forms the second input 17b of the reading stage 17. In addition, the other terminal of the second coupling capacitor 22b is connected to the other terminal of the second coupling switch 24b at the common node 25b.

[0049] The sense amplifier 46 further includes a first inverter 26 having an input terminal 26a and an output terminal 26b, and a first balancing switch 28 connected between the input terminal 26a and the output terminal 26b of the first inverter 26. A first compensation capacitor 30 is connected between the output terminal 26b of the first inverter 26 and a second input 46b of the sense amplifier 46. The input terminal 26a of the first inverter 26 is connected to the first input 46a of the sense amplifier 46.

[0050] The sense amplifier 46 further includes a second inverter 32 having an input terminal 32a and an output terminal 32b, and a second balancing switch 34 connected between the input terminal 32a and the output terminal 32b of the second inverter 32. The second compensation capacitor 36 is connected between the output terminal 32b of the first inverter 32 and the first input 46a of the sense amplifier 46. The input terminal 32a of the second inverter 32 is connected to the second input 46b of the sense amplifier 46.

[0051] The read stage 17 further comprises a read switch 38 connected between the nodes 25a, 25b.

[0052] Figure 5 Relative to Figure 4 The reading stage 17 is shown in more detail. In this respect, Figure 5 In the example, the first and second inputs 17a, 17b of the read stage 17 are also provided by YMPS and specified.

[0053] In more detail, the reading stage 17 comprises a control switch 40 for controlling the first inverter 26 and a control switch 42 for controlling the second inverter 32. The control switches 40, 42 are PMOS type transistors and are driven by a control signal EnableSA provided by the control logic CL.

[0054] In a manner known per se, the first inverter 26 is formed by a PMOS transistor 26 ′ and an NMOS transistor 26 ″. Likewise, the second inverter 32 is formed by a PMOS transistor 32 ′ and an NMOS transistor 32 ″.

[0055] In particular, the control switch 40 of the first inverter 26 has a voltage connected to the supply voltage V DD (eg, between 0V and 1V) and a second conductive terminal connected to the first conductive terminal of the PMOS transistor 26'. In addition, the control switch 42 of the second inverter 32 has a first conductive terminal connected to the supply voltage V DD and a first conduction terminal connected to a first conduction terminal of the PMOS transistor 32'.

[0056] The gate terminal of the PMOS transistor 26' and the gate terminal of the NMOS transistor 26" are connected together and form an input terminal 26a. The second conductive terminal of the PMOS transistor 26' and the first conductive terminal of the NMOS transistor 26" are connected together and form an output terminal 26b. The second conductive terminal of the NMOS transistor 26" is connected to ground.

[0057] The gate terminal of the PMOS transistor 32' and the gate terminal of the NMOS transistor 32" are connected together and form an input terminal 32a. The second conductive terminal of the PMOS transistor 32' and the first conductive terminal of the NMOS transistor 32" are connected together and form an output terminal 32b. The second conductive terminal of the NMOS transistor 32" is connected to ground.

[0058] The reading stage 17 also comprises further initialization switches 44, 45 formed by NMOS transistors (in Figure 5 ), the initialization switches 44, 45 are driven by the signal EnableSA and are arranged respectively between ground and the first and second input nodes 46a, 46b of the sense amplifier 46. In use, the initialization switches 44, 45 enable the potentials of the first and second inputs 46a, 46b of the sense amplifier 46 to be initialized to the value of the ground potential at the beginning of a read cycle. In this way, at the beginning of each read cycle, the coupling capacitors 22a, 22b are biased at a voltage corresponding to the potential of the charge line 19, while the compensation capacitors 30, 36 are biased at 0V. In fact, during the idle state of the sense amplifier 46, the balancing switches 28, 34 remain closed, enabling the compensation capacitors 30, 36 to be fully discharged, thereby preventing the sense amplifier 46 from behaving differently depending on the history of previous read cycles.

[0059] The output terminal 26b of the first inverter 26 and the output terminal 32b of the second inverter 32 are connected to the corresponding input terminals of the voltage comparator 50, which is designed to compare the voltages at the output terminals 26b, 32b of the first and second inverters 26, 32 and generate an output signal DataSense. For example, if the voltage of the output terminal 26b of the first inverter 26 is lower than the voltage of the output terminal 32b of the second inverter 32, the output signal DataSense has a logic value of "0"; otherwise, it has a logic value of "1".

[0060] Figure 6A-6H The time diagram of the control signals of the switches of the PCM device 1 is shown using a common time scale; in this respect the following applies:

[0061] When the voltage clamp logic signal YMPS_CLAMP( Fig. 6A ) has a logic value of "0", the voltage clamp switches 20a, 20b are closed; otherwise, they are open;

[0062] When the local column decoding signal YO L ,YO R ( Figure 6B ) has a logic value of "0", the local selection switches 13a, 13b are closed; otherwise, they are open;

[0063] When the main column decoding signal YN L , YN R ( Figure 6C ) has a logic value of "0", the main selection switches 12a, 12b are closed; otherwise, they are open;

[0064] The pre-charge switches 14a and 14b are respectively controlled by logic signals / YN L and logic signal / YN R (Easier, also by / YN L and / YN R They are generated by the control logic CL to respectively represent the corresponding main column decoding signal YN L 、IN R In addition, when the logic signal / YN L 、 / IN R When the logic value is "0", the pre-charge switches 14a, 14b are closed; otherwise, they are open;

[0065] The selector elements 4b of the first and second memory cells 3', 3" are activated by a word line signal S applied to the word line WL. WL ( Fig.6D ) drive; in particular, when the word line signal S WL With a logic value of "0", the selector elements 4b are turned on; otherwise, they are turned off;

[0066] As mentioned above, the signal EnableSA( Fig. 6E ) drives the control switches 40, 42 and the initialization switches 44, 45; in particular, when the signal EnableSA has a logic value of "0", i) the control switches 40, 42 are closed, and ii) the initialization switches 44, 45 are opened; otherwise, i) the control switches 40, 42 are opened, and ii) the initialization switches 44, 45 are closed;

[0067] The balance switches 28 and 34 are driven by the balance signal EQ ( Fig. 6F ); In particular, when the balance signal EQ has a logic value of "1", the balance switches 28, 34 are closed; otherwise, they are disconnected;

[0068] The first and second coupling switches 24a, 24b are connected by the coupling signal HIZ ( Figure 6G ) driven, the coupling signal HIZ is generated by the control logic CL, and when it presents a logic value "0", the first and second coupling switches 24a, 24b are closed; otherwise, they are open; and

[0069] The read switch 38 is controlled by a read signal NHIZ ( Figure 6H ) drive; in particular, when the read signal NHIZ has a logic value "1", the read switch 38 is opened; otherwise the read switch 38 is closed.

[0070] Having said all this, the differential reading of the logical data stored in the pair formed by the first and second memory cells 3 ′, 3 ″ is performed as described below.

[0071] In a first step of the method, the control signals of the PCM device 1 are in an initial configuration.

[0072] In detail, at the initial time t0, the signal YMPS_CLAMP has a logic value of "0", and the local column decoding signal YO L ,YO R With logic value "1", the main column decoding signal YN L , YN R With a logic value of "1", the word line signal S WL has a logic value “1”, the signal EnableSA has a logic value “1”, the balance signal EQ has a logic value “1”, the coupling signal HIZ has a logic value “0”, and the read signal NHIZ has a logic value “1”.

[0073] In the initial configuration, and therefore at the initial time t0 mentioned above, because / YN L =0 and / YN R =0, the main bit line capacitors 9', 9" (similarly, all main bit lines of the PCM device 1) are charged at the voltage value BL_CHARGE of the charging line 19. In addition, the coupling capacitors 22a, 22b are connected to the first and second inputs 17a, 17b of the reading stage 17 via the first and second coupling switches 24a, 24b, respectively. Therefore, the coupling capacitors 22a, 22b are also charged at the voltage value of the charging line 19. At the same time, the local word line WL is biased at a voltage value (for example, between 1.5V and 1.8V) so that the selector elements 4b of the memory cells 3', 3" are in the OFF state; this voltage value can be provided to the local word line WL by a charge pump (not shown).

[0074] The differential read operation starts at time t1 after the initial time t0.

[0075] At time t1, the local column decoded signal YO L ,YO R and the main column decoding signal YN L , YN R The logic state of the signal t0 changes from a logic value of “1” to a logic value of “0”, while the signal EnableSA changes from a logic value of “1” to a logic value of “0”. The other control signals maintain their previous logic states (those at time t0).

[0076] Thus, at time t1, the sense amplifier 46 is enabled (EnableSA=0) and the balancing switches 28, 34 are still closed (EQ=1). Without the first and second compensation capacitors 30, 36, the first inverter 26 will set the potential on the second input 46b of the sense amplifier 46 to be equal to the trip point (usually close to the supply voltage V DD The second inverter 32 will set the potential on the first input 46a of the sense amplifier 46 to be equal to the trip point plus the offset voltage (usually different from the offset voltage set on the second input 46b of the sense amplifier 46) to address the technology process expansion that causes the mismatch between the inverters 26 and 32.

[0077] In fact, immediately before time t1, the first and second compensation capacitors 30, 36 are discharged. Immediately after time t1, the first input 46a of the sense amplifier 46 has a voltage (V trip26 ), and the second input 46b of the sense amplifier 46 has a voltage (V trip32 ), so the first and second coupling capacitors 22a, 22b are subjected to a voltage equal to BL_CHARGE-V trip26 and BL_CHARGE-V trip32 voltage.

[0078] In practice, the presence of the first and second compensation capacitors 30, 36 enables the storage of two offset voltages. Thus, in the subsequent steps of the reading method, when the balancing switches 28, 34 will be disconnected, the inverters 26, 32 will still be in their amplification region and arranged electrically in series. Thus, the resulting latch structure will be in a metastable equilibrium state and will remain in this state until an event occurs that is capable of disturbing this state. In the absence of the compensation capacitors 30, 36, the mismatch between the inverters 26, 32 will result in unforeseen switching of the latch structure when the balancing switches 28, 34 are disconnected.

[0079] In addition, at time t1, the local bit line BL L <j>and the corresponding local bit line BL R <j>are connected to the main bit lines MBL L 、MBL R (YO L <j>=0, YOU R <j>=0,IN L =0,IN R =0), main bit line MBL L 、MBL R Disconnected from the charging line 19 by the corresponding pre-charging switches 14a, 14b ( / YN L =1, / IN R =1), but still powered by the charge line 19 through the corresponding voltage clamp switches 20a, 20b (YMPS_CLAMP=0). In this way, the main bit line parasitic capacitors are connected in parallel and are charged at the voltage BL_CHARGE. The total value of the capacitance (of the order of several hundred picofarads) is such that the capacitors form a kind of filter for the voltage BL_CHARGE. Therefore, when the decoding path enabling the precharging of the bit line parasitic capacitor 4c is activated, the voltage drop on the charge line 19 will be negligible (in the range of 10 millivolts) due to the amount of charge transferred. In other words, even if the voltage BL_CHARGE is generated by a charge pump, it can be considered that the voltage BL_CHARGE is constant. In addition, to a first approximation, the precharging time of the bit line parasitic capacitor 4c depends exactly on the resistance associated with the local selection switches 13a and 13b and is therefore of the order of nanoseconds. In this step, there is no static power consumption, since no current flows through the memory cell 3 as long as the row has not yet been selected.

[0080] On the local bit line BL L <j>、BL R <j>After charging, the subsequent steps of the reading method are performed at time t2 after time t1. The time interval between time t1 and time t2 is generated by an analog delay, the size of which is adjusted to ensure charging of the local bit line, and the time interval is within the range of 1 ns.

[0081] At time t2, the voltage clamp signal YMPS_CLAMP changes logic state from logic value "0" to logic value "1". Therefore, the voltage clamp switches 20a, 20b are opened to enable a possible change in voltage on the first and second inputs 17a, 17b of the read stage 17 after time t2.

[0082] Next, at time t3 after time t2, the word line signal S WL The logic state changes from a logic value "1" to a logic value "0". Therefore, the selector element 4b is turned on, allowing current to pass.

[0083] In practice, the voltage clamp signal YMPS_CLAMP is WL The time interval between time t2 and time t3 is of the order of hundreds of picoseconds, and ensures that the word line signal S WL Switching of the voltage clamp signal YMPS_CLAMP occurs previously.

[0084] When the selector 4b is turned on, the first and second memory cells 3', 3" are disconnected from the charging line 19, thereby preventing the charge pump 39 connected to the charging line 19 from consuming direct current. In addition, at time t3, the bit line capacitor 4c and the main bit line capacitor 9', 9" begin to discharge via the path of current passing through the corresponding memory cells.

[0085] The value of the current passing through the first and second memory cells 3', 3" depends on the state of the corresponding storage element 4a. In particular, if the storage element 4a is in the RESET state, the current passing through the memory cell is, for example, between less than 100nA and 5μA; conversely, if the storage element 4a is in the SET state, the current passing through the memory cell is, for example, between 10μA and 30μA. Therefore, the capacitors 4c, 9' on the left-hand side and the capacitors 4c, 9" on the right-hand side of the memory array 2 are discharged at different rates, so that the voltages at the inputs 17a, 17b of the read stage 17 (equal to the voltages of the corresponding common nodes 25a, 25b) will be different during the discharge process.

[0086] At time t4 (after time t3 at a time interval Δt (e.g. between 4 ns and 6 ns)), there is a voltage difference ΔV between the inputs 17a, 17b of the reading stage 17 and, therefore, different voltages at the common nodes 25a, 25b (i.e. at the terminals of the coupling capacitors 22a, 22b connected to the respective terminals of the coupling switches 24a, 24b). This voltage difference ΔV is, for example, higher than 30 mV when the difference between the currents through the first and second memory cells 3', 3" during the time interval Δt is 2 μA on average.

[0087] At time t4, the bit line capacitor 4c and the main bit line capacitors 9', 9" are only partially discharged.

[0088] At time t4, the first and second coupling switches 24a, 24b are opened because the signal HIZ switches to "0". As a result, the common nodes 25a, 25b of the read stage 17 are disconnected from the respective inputs 17a, 17b of the read stage 17, and the voltage between the common nodes 25a, 25b no longer changes (it is "frozen" at the last voltage value it had during the time interval Δt). In addition, the voltages of the bit line capacitor 4c and the main bit line capacitors 9', 9" approach asymptotes.

[0089] At time t5 after time t4, the first and second balancing switches 28, 34 are opened (because the balancing signal EQ is switched to "0"), and the read switch 38 is closed (because the read signal NHIZ is switched to "1").

[0090] As previously described, the opening of the balancing switches 28, 34 places the sense amplifier 46 in a metastable equilibrium condition. In addition, the closing of the read switch 38 (at time t5, as described above, or as also described later) places the coupling capacitors 22a, 22b in series so as to cancel the common-mode voltage between the coupling capacitors 22a, 22b (due to the pre-charging of the main line capacitors 9', 9"). In practice, immediately before time t5, the potential difference between the input terminal 26a and the output terminal 26b of the first inverter 26 is zero, and similarly, the potential difference between the input terminal 32a and the output terminal 32b of the second inverter 32 is also zero. Immediately after time t5, the potential difference between the input terminal 26a and the output terminal 26b of the first inverter 26 (and similarly the potential difference between the input terminal 32a and the output terminal 32b of the second inverter 32) is equal to the potential difference between the common nodes 25a, 25b, regardless of the offset of the first and second inverters 26, 32.

[0091] Thus, even if the step of precharging the main bit line capacitors 9′, 9″ has been performed at a high voltage (up to a value between, for example, 1.5 V and 1.8 V), the use of coupling capacitors 22 a, 22 b enables the sense amplifier 46, which is powered at a lower voltage (e.g., below 1 V), to detect the voltage difference between the common nodes 25 a, 25 b, thereby limiting the power consumption.

[0092] Due to the previous difference between the discharge currents of the memory cells 3', 3", the difference in potential existing across the two coupling capacitors 22a, 22b disturbs the metastable equilibrium condition of the sense amplifier 46 and causes the sense amplifier 46 to switch according to the sign of the above-mentioned difference in potential so that the output terminals 26b, 32b of the inverters 26, 32 present complementary logical values. In other words, according to the state of the storage element 4a of the first and second memory cells 3', 3", the output terminals 26b, 32b of the inverters 26, 32 present complementary logical values. For example, the logical values ​​corresponding to the voltages on the output terminals 26b, 32b of the inverters 26, 32 follow the rules listed in the following table.

[0093] Memory unit 3' Memory unit 3" Output terminal 26b Output terminal 32b SET RESET "0” "1” RESET SET "1” "0”

[0094] In other words, after time t4, the latch structure evolves towards the first equilibrium condition or the second equilibrium condition, depending on the state of the storage element 4a of the first and second memory cell 3', 3".

[0095] When a good separation of the voltages of the output terminals 26b, 32b of the inverters 26, 32 has been achieved (e.g. greater than 100 mV), the comparator 50 may be enabled to update the value of the output signal DataSense according to the logic data stored in the first and second memory cells 3', 3". Thus, the comparator 50 may be enabled before an equilibrium condition is reached.

[0096] Next, the control signals can be brought back to their initial conditions at time t0 described previously, and the read cycle is thus completed. WL During the period of changing to the logic state "1", the discharge of the bit line capacitor 4c and the discharge of the main bit line capacitors 9', 9" are interrupted. Summary of the invention

[0097] The previously described reading method enables differential reading to be performed in an efficient manner in case of highly balanced conditions of capacitive loads, since it is based on a comparison between the discharge rates of the capacitors. However, the Applicant has noticed that, at least in certain cases, a need is felt to be able to switch between different reading modes of a memory array.

[0098] It is therefore an object of the present disclosure to provide a phase change memory device that will at least partially meet the encountered needs.

[0099] According to the present disclosure, a phase change memory device and a reading method are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0100] For a better understanding of the present disclosure, preferred embodiments thereof will now be described purely by way of non-limiting examples with reference to the accompanying drawings, in which:

[0101] Figure 1 shows a block diagram of a PCM device;

[0102] Figure 2 and Figure 3 Shown in Figure 1 A block diagram of a portion of a PCM device illustrated in FIG.

[0103] Figure 4 Shown in Figure 1 A circuit diagram of a portion of a PCM device illustrated in FIG.

[0104] Figure 5 Shown in Figure 4 A circuit diagram of a sub-portion of a portion of a PCM device illustrated in FIG.

[0105] Figure 6A-6H Shown in Figure 1 A timing diagram of a signal generated in the PCM device shown in FIG.

[0106] Figure 7 shows a block diagram of the present PCM device;

[0107] Figure 8A-8B , Fig. 9 and Fig.10 Shown in Figure 7 A circuit diagram of a portion of a PCM device illustrated in FIG.

[0108] Figure 11A-11C Shown in Figure 7 A circuit diagram of a portion of a PCM device illustrated in FIG.

[0109] Fig.12 , Fig.14 , Fig.16 , Fig.17 , Fig.19 and Fig.21 shows the Figure 7 A timing diagram of a signal generated in the PCM device shown in FIG.

[0110] Fig.13A and Fig. 13B shows an indication during the above read mode in Figure 7 A table of signals generated in the PCM device illustrated in FIG.

[0111] Fig.15 , Fig.18 , Fig. 20 and Fig. 22 The Fig.16 , Fig.17 , Fig.19 and Fig.21 The read mode mentioned in Figure 7 A circuit diagram of a portion of a PCM device illustrated in FIG. 1 ; and

[0112] Fig.23 is a block diagram of possible electronic devices that may include the present apparatus. DETAILED DESCRIPTION

[0113] As described below, the Applicant has noticed how the previously described reading stage can be modified so that it is possible to alternatively implement reading of memory cells of the differential type (also referred to as "normal" reading mode) or reading of memory cells of the so-called single-ended type (also referred to as "verify" reading mode). In this respect, in the following, a PCM device 100 is described (limited to the differences with the PCM device 1). Furthermore, unless otherwise stated, components already present in the PCM device 1 are designated by the same reference numerals.

[0114] As in Figure 7 As illustrated in FIG, in addition to the first sector S', the memory array 2 also includes a second sector S", which is symmetrically arranged relative to the intermediate stage 317 (described below). The first and second sectors S', S" may be identical to each other.

[0115] In detail, the middle stage 317 includes an upper reading stage 117 and a lower reading stage 217 .

[0116] In more detail, Fig. 8A The upper reading stage 117 is illustrated in FIG. 1 and the description will now be limited to the differences with respect to the reading stage 17. Unless otherwise specified, the components of the upper reading stage 117 that are already present in the reading stage 17 are designated by the same reference numerals increased by one hundred. In addition, voltage clamp switches (here designated by 120 a and 120 b) and charging lines (here designated by 119) are provided in FIG. Fig. 8A As can also be seen in FIG. 1 , the charge line is set at a voltage BL_CHARGE_TOP (equal to the aforementioned voltage BL_CHARGE) and is hereinafter referred to as the upper charge line 119. Fig. 8A In the example, the first and second inputs 117a, 117b of the upper read stage 117 are also provided by YMPS_TOP and It is further contemplated that, with respect to the circuit details regarding the coupling between the upper read stage 117 (particularly, the first and second inputs 117a, 117b) and the first sector S' (particularly, the first and second memory cells 3', 3", hereinafter referred to as the first and second upper memory cells 3', 3", respectively), the same as has been described with reference to Figure 4 and read the contents described in level 17. Fig. 9 The coupling between the upper read stage 117 and the first sector S′ is illustrated in , wherein the upper read stage 117 is illustrated in a simplified manner.

[0117] It has been said that the upper reading stage 117 comprises the first additional control switch 101 and the second additional control switch 102 .

[0118] The first additional control switch 101 is arranged between the first input 146a of the sense amplifier 146 and the second compensation capacitor 136. The second additional control switch 102 is arranged between the first compensation capacitor 130 and the second input 146b of the sense amplifier 146.

[0119] More specifically, if the terminal of the second compensation capacitor 136 opposite to the terminal of the capacitor connected to the output terminal 132b of the second inverter 132 is represented by a node NL1, the first additional control switch 101 is arranged between the first input 146a of the sense amplifier 146 and the node NL1. In addition, if the terminal of the first compensation capacitor 130 opposite to the terminal of the capacitor connected to the output terminal 126b of the first inverter 126 is represented by a node NR1, the second additional control switch 102 is arranged between the node NR1 and the second input 146b of the sense amplifier 146.

[0120] For ease of understanding Fig. 8A The contents of the diagram will refer to Figure 8B The relationship between the contents described is Fig. 8A Nodes NL2 and NL3 (coincident with the first input 146a of the sense amplifier 146 and the common node 125b, respectively) and nodes NR2 and NR3 (coincident with the second input 146b of the sense amplifier 146 and the common node 125a, respectively) are further illustrated in FIG.

[0121] Having said that, the following will happen:

[0122] The voltage clamp switches 120a, 120b are driven by the upper voltage clamp signal YMPS_CLAMP_TOP generated by the control logic CL so that they are closed when the latter signal is equal to "0", otherwise they are open;

[0123] The first and second coupling switches 124a, 124b are driven by the first upper coupling signal HIZ_TOP_L and the second upper coupling signal HIZ_TOP_R generated by the control logic CL, respectively, so that they are opened when the corresponding control signal has a logic value of "0", and closed otherwise;

[0124] The read switch 138 is driven by the upper read signal NHIZ_TOP generated by the control logic CL so that it is opened when the read signal NHIZ_TOP has a logic value of "0", and is closed otherwise;

[0125] The control switch 140 and the initialization switch 144 are driven by the signal EnableSA_TOP1 generated by the control logic CL, so that they are opened and closed respectively when the signal EnableSA_TOP1 has a logic value of "1", and are closed and opened respectively otherwise;

[0126] The control switch 142 and the initialization switch 145 are driven by the signal EnableSA_TOP2 generated by the control logic CL so that they are opened and closed respectively when the signal EnableSA_TOP2 has a logic value of "1", otherwise they are closed and opened respectively;

[0127] The first and second additional control switches 101, 102 are controlled by a signal SENSEMODE generated by the control logic CL. <1> drive so that they are in the SENSEMODE signal <1> Closed when equal to "1", otherwise open;

[0128] The balance switches 128, 134 are driven by the balance signal EQ so that they are closed when the balance signal EQ has a logic value of "1", and are open otherwise; and

[0129] The selector elements 4b of the first and second upper memory cells 3', 3" are driven by a word line signal WL_TOP, which is applied to the corresponding word line WL.

[0130] Reference again Fig. 8A , the signals present at the output terminals 126b and 132b of the first and second inverters 126, 132 are represented by VC1_TOP and VC2_TOP, respectively.

[0131] exist Figure 8B 1 and the description will now be limited to the differences with respect to the upper read stage 117. In addition, unless otherwise specified, components of the lower read stage 217 that are already present in the upper read stage 117 are designated by the same reference numerals increased by one hundred, such as in the case of nodes NL1, NL2, NL3, NR1, NR2, NR3, which are now designated by the addition of a prime. In addition, additional voltage clamp switches (designated 220a and 220b) are provided in the Figure 8B As can also be seen in FIG. 1 , an additional voltage clamp switch is coupled to an additional charging line, which is set at a voltage BL_CHARGE_BOT (equal to the aforementioned voltage BL_CHARGE_TOP) and is referred to hereinafter as the lower charging line 219. Figure 8B The first and second inputs 217a, 217b of the lower read stage 217 are also provided by YMPS_BOT and In addition, the coupling between the lower read stage 217 and the second sector S" is the same as the coupling existing between the upper read stage 117 and the first sector S', as also explained below. In this regard, it is contemplated that the second sector S" includes a first lower memory cell 3"' and a second lower memory cell 3"" arranged symmetrically with respect to the first and second upper memory cells 3', 3", respectively. In addition, the first and second lower memory cells 3"', 3"" are coupled to corresponding local bit lines (in the case of the first lower memory cell 3"', by BL L <j>' indicates that, and in the case of the second lower memory cell 3"" by BL R <j>'), the corresponding local bit lines can in turn be coupled to the corresponding main bit lines (respectively represented by MBL L ' and MBL R '), and the corresponding main bit line parasitic capacitors of the corresponding local bit lines are represented by 9"' and 9"", respectively, in the same manner as Figure 4 Reference memory cells 3', 3", local bit lines BL L <j>and BL R <j>and the main bit line MBL L and MBL R Same as shown.

[0132] As has been said, in the lower read level 217 the following occurs:

[0133] The voltage clamp switches 220a, 220b are driven by the lower voltage clamp signal YMPS_CLAMP_BOT generated by the control logic CL so that they are closed when the latter signal is equal to "0", otherwise they are open;

[0134] The first and second coupling switches 224a, 224b are driven by the first down-coupling signal HIZ_BOT_L and the second down-coupling signal HIZ_BOT_R generated by the control logic CL, respectively, so that they are opened when the corresponding control signal has a logic value of "0", and closed otherwise;

[0135] The read switch 238 is driven by the lower read signal NHIZ_BOT generated by the control logic CL so that it is opened when the lower read signal NHIZ_BOT has a logic value of "0", and is closed otherwise;

[0136] The control switch 240 and the initialization switch 244 are driven by the signal EnableSA_BOT1 generated by the control logic CL, so that they are opened and closed respectively when the signal EnableSA_BOT1 has a logic value of "1", and are closed and opened respectively otherwise;

[0137] The control switch 242 and the initialization switch 245 are driven by the signal EnableSA_BOT2 generated by the control logic CL so that they are opened and closed respectively when the signal EnableSA_BOT2 has a logic value of "1", and are closed and opened respectively otherwise;

[0138] The first and second additional control switches 201, 202 are both controlled by the signal SENSEMODE <1> drive so that they are in the SENSEMODE signal <1> Closed when equal to "1", otherwise open;

[0139] The balance switches 228, 234 are driven by the balance signal EQ so that they are closed when the balance signal EQ has a logic value of "1", and are open otherwise; and

[0140] The selector elements 4b of the first and second lower memory cells 3"', 3"" are driven by a word line signal WL_BOT applied to a word line (designated by WL) to which the first and second lower memory cells 3"', 3"" are coupled.

[0141] Reference again Figure 8B , the signals present at the output terminals 226b and 232b of the first and second inverters 226, 232 are represented by VC1_BOT and VC2_BOT, respectively.

[0142] As in Figure 8B As again illustrated in , the PCM device 100 comprises six additional switches, which are arranged between the upper read stage 117 and the lower read stage 217 and are designated by SW1_R, SW2_R, SW3_R and SW1_L, SW2_L, SW3_L.

[0143] In detail, the additional switch SW1_R is arranged between the nodes NR1 and NR2' and is controlled by the signal SENSEMODE generated by the control logic CL. <2> to drive it so that it signals SENSEMODE <2> Closed when equal to "1", otherwise open.

[0144] The additional switch SW2_R is arranged between the nodes NR2 and NR1′ and is switched by the signal SENSEMODE generated by the control logic CL. <0> to drive it so that it signals SENSEMODE <0> Closed when equal to "1", otherwise open.

[0145] The additional switch SW3_R is arranged between the nodes NR3 and NL3 ′ and is driven by the signal NHIZ_TOPL_BOTR generated by the control logic CL so that it is closed when the signal NHIZ_TOPL_BOTR is equal to “1” and is open otherwise.

[0146] The additional switch SW1_L is arranged between the nodes NL1 and NL2' and is controlled by the signal SENSEMODE <0> drive to enable it to signal SENSEMODE <0> Closed when equal to "1", otherwise open.

[0147] The additional switch SW2_L is arranged between the nodes NL2 and NL1' and is controlled by the signal SENSEMODE <2> drive to enable it to signal SENSEMODE <2> Closed when equal to "1", otherwise open.

[0148] The additional switch SW3_L is arranged between the nodes NL3 and NR3 ′ and is driven by the signal NHIZ_TOPR_BOTL generated by the control logic CL so that it is closed when the signal NHIZ_TOPR_BOTL is equal to “1” and is open otherwise.

[0149] exist Fig.10 The coupling between the lower read stage 217 and the second sector S″ is illustrated in , where the lower read stage 217 is illustrated in a simplified manner (limited to details that help provide an understanding of the coupling with the second sector S″).

[0150] In particular, the sense amplifier 246 is coupled to the first and second lower memory cells 3'", 3".

[0151] Reference again Fig.10 The main selection switch, the local selection switch and the pre-charge switch are represented by 12a'-12b', 13a'-13b' and 14a'-14b' respectively, and the signals controlling these switches are represented by YN L '-IN R '(hereinafter referred to as YN L '-YN R '), YO L <j>'-YO R <j>'(hereinafter referred to as YO L '-YO R ') and / YN L '- / IN R '. In addition, the nodes corresponding to nodes A and B are designated by A' and B'.

[0152] like Fig.11A As shown in FIG. 1 , the PCM device 100 further includes a first reference generator 402 configured to generate a reference current and a first upper mode switch 404 and a second upper mode switch 406. The first reference generator 402 is controlled by a signal VERIFY_TOP so that it is turned on when the signal VERIFY_TOP is equal to "1", otherwise it is turned off.

[0153] The first upper mode switch 404 is arranged between the node YMPS_TOP and the first terminal of the first reference generator 402, and the second terminal of the first reference generator 402 is connected to the ground. The second upper mode switch 406 is arranged at the node and a first terminal of the first reference generator 402. The first and second upper mode switches 404, 406 are respectively controlled by the signal VERIFY_TOPL and the signal VERIFY_TOPR generated by the control logic CL, so that they are opened when the corresponding signal is equal to "0", and closed otherwise.

[0154] As in Fig. 11B As shown in FIG. 1 , the PCM device 100 further includes a second reference generator 502, and a first down-mode switch 504 and a second down-mode switch 506. The second reference generator 502 is configured so that it also generates a reference current. The second reference generator 502 is controlled by the signal VERIFY_BOT so that it is turned on when the signal VERIFY_BOT is equal to "1", otherwise it is turned off.

[0155] The first lower mode switch 504 is arranged between the node YMPS_BOT and the first terminal of the second reference generator 502, and the second terminal of the second reference generator 502 is connected to the ground. The second lower mode switch 506 is arranged at the node and a first terminal of the second reference generator 502. The first and second down mode switches 504, 506 are respectively controlled by the signal VERIFY_BOTL and the signal VERIFY_BOTR generated by the control logic CL so that they are opened when the corresponding signal is equal to "0", and closed otherwise.

[0156] As in Fig. 11C , the PCM device 100 further comprises a multiplexing stage 600 which receives at input signals VC1_TOP and VC2_TOP, which are present at output terminals 126b and 132b, respectively, of first and second inverters 126, 132 of sense amplifier 146 of upper read stage 117. In addition, the multiplexing stage 600 receives at input signals VC1_BOT and VC2_BOT, which are present at output terminals 226b and 232b, respectively, of first and second inverters 226, 232 of sense amplifier 246 of lower read stage 217. As described below, the multiplexing stage 600 generates the signals VC1 and VC2.

[0157] The PCM device 100 further includes a comparison stage 602 that generates a signal DataSense (as described below) based on the signals VC1 and VC2, the signal DataSense indicating the result of the reading. For example, the timing of the comparison stage 600 is performed based on the signal EnableComp.

[0158] As already said, in the first operating mode, the control logic CL issues a command for differential mode reading, alternatively on part of the upper reading stage 117 or on part of the lower reading stage 217. In other words, a pair of cells alternatively formed by the first and second upper memory cells 3', 3" or a pair of cells formed by the first and second lower memory cells 3'", 3"" is read in differential mode.

[0159] For example, in the case of reading the first and second upper memory cells 3', 3" (in Fig.13A and Fig. 13B The control logic CL operates so that (as in Fig.12 ):

[0160] The upper voltage clamp signal YMPS_CLAMP_TOP follows the Fig. 6A The same mode as the voltage clamp signal YMPS_CLAMP shown in FIG.

[0161] Local column decoding signal YO L ,YO R With Figure 6B The local column decoded signal YO shown in FIG. L ,YO R Same pattern;

[0162] Main column decoding signal YN L , YN R With Figure 6C The main column decoding signal YN shown in the figure L , YN R The same mode, determine the corresponding logic signal / YN L and / YN R mode;

[0163] The word line signal WL_TOP follows the Fig.6D The word line signal S shown in FIG. WL The same mode, while the word line signal WL_BOT remains equal to "1" so as to deselect the word line WL' coupled to the first and second lower memory cells 3"', 3"";

[0164] Signals EnableSA_TOP1 and EnableSA_TOP2 follow the same Fig. 6E The same pattern as the signal EnableSA shown in the figure;

[0165] Balanced signal EQ continues to have the same Fig. 6F The same mode as the balanced signal EQ shown in the figure;

[0166] The upper coupling signals HIZ_TOP_L and HIZ_TOP_R follow the same Figure 6G The coupled signal HIZ shown in the figure has the same pattern;

[0167] The upper read signal NHIZ_TOP follows the Figure 6H The same pattern as the read signal NHIZ shown in FIG. ; and

[0168] The signal EnableComp switches from “0” to “1” at time t6 in order to enable the comparison stage 602 , which thus updates the value of the signal DataSense.

[0169] Next, at time t7, the upper voltage clamp signal YMPS_CLAMP_TOP returns to "0". At the subsequent time t8, the local column decoding signal Y0 L ,YO R , Main column decoding signal YN L , YN R , signals EnableSA_TOP1 and EnableSA_TOP2, signal EnableComp, and upper coupling signals HIZ_TOP_L and HIZ_TOP_R also return to have the values ​​they had at time t0. In contrast, for the word line signal WL_TOP, it returns to have a value of "1" between time t6 and time t7. In addition, the upper read signal NHIZ_TOP returns to be equal to "1" at time t9.

[0170] Reference again Fig.12 , the signal VERIFY_BOT and the signal VERIFY_TOP remain equal to “0” for the entire time interval t0-t9 in order to keep the first and second reference generators 402, 502 turned off.

[0171] In the above situation, if Fig.13A As shown in the combined diagram in FIG. 6 , the control logic CL drives the multiplexing stage 600 so as to force the signals VC1 , VC2 present at the output of the multiplexing stage 600 to be equal to the signals VC1_TOP and VC2_TOP, respectively.

[0172] Furthermore, for the entire time interval t0-t9, the control logic CL operates such that:

[0173] SignalSENSEMODE <1> is equal to "1" so that the first and second additional control switches 101, 102 of the upper reading stage 117 are closed;

[0174] SignalSENSEMODE <0> and SENSEMODE <2> = "0" to disconnect the additional switches SW1_R, SW2_R and SW1_L, SW2_L; and

[0175] The signals NHIZ_TOPL_BOTR and NHIZ_TOPR_BOTL are equal to “0” so that the additional switches SW3_R and SW3_L are turned off.

[0176] In practice, the upper read stage 117 and the lower read stage 217 are decoupled, and the multiplexing stage 600 connects the upper read stage 117 to the comparison stage 602. In turn, the upper read stage 117 operates like the read stage 17.

[0177] Referring again to the signals generated by the control logic CL, Fig. 13B A table is presented, the first row of which corresponds precisely to the differential reading of the first and second upper memory cells 3', 3". In addition, the table schematically presents the values ​​taken by the signal indicated therein in the interval t0-t9; where the wording "signal" is present, this means that the signal to which it refers is not constant and follows a corresponding pattern. In this respect, Fig. 13B It is shown how, in the case of differential reading of the first and second upper memory cells 3', 3", the signals EnableSA_BOT1 and EnableSA_BOT2 are equal to "1", and thus the control switches 240, 242 are opened, while the initialization switches 244, 245 are closed. In addition, the signals VERIFY_TOPL, VERIFY_TOPR, VERIFY_BOTL and VERIFY_BOT are equal to "0". In addition, the lower read signal NHIZ_BOT is equal to "0", while the first and second lower coupling signals HIZ_BOT_L, HIZ_BOT_R are equal to "1" so that the first and second coupling switches 224a, 224b are closed, while the read switch 238 is open.

[0178] In a similar manner as described with reference to the differential reading of the first and second upper memory cells 3', 3", the control logic CL may issue a command for differentially reading the first and second lower memory cells 3'", 3"". Fig.13A and Fig. 13B (the case represented by BOT-BOT in the example).

[0179] In detail, the control logic CL operates so that the signals VC1, VC2 present at the output of the multiplexing stage 600 are equal to the signals VC1_BOT and VC2_BOT, respectively, as in Fig.13A In addition, as shown in Fig. 13B As shown in FIG, the control logic CL operates so that:

[0180] SignalSENSEMODE <1> is equal to "1" so that the first and second additional control switches 201, 202 of the lower reading stage 217 are closed;

[0181] SignalSENSEMODE <0> and SENSEMODE <2> = "0" to disconnect the additional switches SW1_R, SW2_R and SW1_L, SW2_L;

[0182] The signals NHIZ_TOPL_BOTR and NHIZ_TOPR_BOTL are equal to "0" so that the additional switches SW3_R and SW3_L are turned off;

[0183] Signals EnableSA_TOP1 and EnableSA_TOP2 are equal to "1", and thus control switches 140 and 142 to be open, while initialization switches 144 and 145 to be closed;

[0184] The signals VERIFY_TOPL, VERIFY_TOPR, VERIFY_BOTL, and VERIFY_BOT are equal to "0"; and

[0185] The upper read signal NHIZ_TOP is equal to “0”, and the first and second upper coupling signals HIZ_TOP_L, HIZ_TOP_R are equal to “1”, so that the first and second coupling switches 124a, 124b are closed, and the read switch 138 is opened.

[0186] In addition, the control logic CL operates so that, as in Fig.14 In the picture:

[0187] The lower voltage clamp signal YMPS_CLAMP_BOT follows the Fig. 6A The same mode as the voltage clamp signal YMPS_CLAMP shown in FIG.

[0188] Local column decoding signal YO L ', YO R 'Have and in Figure 6B The same pattern as the local column decoded signal shown in FIG.

[0189] Main column decoding signal YN L ', YN R 'Have and in Figure 6C The main column decoding signal is the same as the pattern shown in the figure, and the corresponding logic signal / YN is determined at the same time L ' and / YN R 'mode;

[0190] The word line signal WL_BOT follows the Fig.6D The word line signal S shown in FIG. WL the same mode, while the word line signal WL_TOP remains equal to "1" so as to deselect the word line WL coupled to the first and second upper memory cells 3', 3";

[0191] Signals EnableSA_BOT1 and EnableSA_BOT2 follow the same Fig. 6E The same pattern as the signal EnableSA shown in the figure;

[0192] Balanced signal EQ continues to have the same Fig. 6F The same mode as the balanced signal EQ shown in the figure;

[0193] The lower coupling signals HIZ_BOT_L and HIZ_BOT_R follow the same Figure 6G The coupled signal HIZ shown in the figure has the same pattern;

[0194] The next read signal NHIZ_BOT follows the same Figure 6H The same pattern as the read signal NHIZ shown in FIG.

[0195] For the entire time interval t0-t9, the signals VERIFY_BOT and VERIFY_TOP remain equal to "0" in order to keep the first and second reference generators 402, 502 off; and

[0196] Signal EnableComp follows the reference Fig.12 Same pattern as described.

[0197] In practice, the upper read stage 117 and the lower read stage 217 are decoupled, and the multiplexing stage 600 connects the lower read stage 217 to the comparison stage 602. In turn, the lower read stage 217 operates like the read stage 17.

[0198] In another operation mode, the control logic CL issues a command for single-ended reading of the first upper memory cell 3' (at Fig.13A and Fig. 13B In this case, the control logic CL operates so that (as in Fig.13A ) the signals VC1, VC2 present at the output of the multiplexing stage 600 are equal to the signals VC1_TOP and VC2_BOT, respectively. Fig. 13B As shown in FIG, the control logic CL operates so that:

[0199] SignalSENSEMODE <0> = "0" to disconnect the additional switches SW2_R and SW1_L;

[0200] SignalSENSEMODE <1> = "0" to disconnect the first and second additional control switches 101, 102 of the upper read stage 117 and the first and second additional control switches 201, 202 of the lower read stage 217;

[0201] SignalSENSEMODE <2> = "1" to close the additional switches SW1_R and SW2_L;

[0202] The signal EnableSA_TOP2 is equal to "1" to open and close the control switch 142 and the initialization switch 145 respectively;

[0203] The signal EnableSA_BOT1 is equal to "1" to open and close the control switch 240 and the initialization switch 244 respectively;

[0204] The signals VERIFY_TOPL, VERIFY_TOPR, and VERIFY_BOTL are equal to "0", and the signal VERIFY_BOTR is equal to "1", so that (as in Fig.15 The second reference generator 502 is connected to the node

[0205] The signal VERIFY_TOP is equal to "0" to shut down the first reference generator 402;

[0206] The upper read signal NHIZ_TOP and the second upper coupling signal HIZ_TOP_R are equal to "0" to disconnect the read switch 138 and the second coupling switch 124b;

[0207] The lower read signal NHIZ_BOT and the first lower coupling signal HIZ_BOT_L are equal to "0" to disconnect the read switch 238 and the first coupling switch 224a; and

[0208] The signal NHIZ_TOPR_BOTL is equal to “0” so that the additional switch SW3_L is turned off.

[0209] In addition, the control logic CL operates so that, as in Fig. 13B and Fig.16 In the picture:

[0210] The upper voltage clamp signal YMPS_CLAMP_TOP and the lower voltage clamp signal YMPS_CLAMP_BOT follow the same Fig. 6A The voltage clamp signals YMPS_CLAMP shown in FIG. 1 and FIG. 2 have the same pattern, except for the fact that they switch to “1” at time t3 instead of at time t2;

[0211] Local column decoding signal YO L ,YO R ,YO L ', YO R 'Present and in Figure 6B The same pattern as the local column decoded signal shown in FIG.

[0212] Main column decoding signal YN L , YN R , YN L ', YN R 'Have and in Figure 6C The same pattern as the main column decoded signal shown in the figure;

[0213] The word line signal WL_TOP follows the Fig.6D The word line signal S shown in FIG. WL The same pattern, except for the fact that it switches to "0" at instant t2 instead of at instant t3; instead, the word line signal WL_BOT remains equal to "1";

[0214] Signals EnableSA_TOP1 and EnableSA_BOT2 follow the same Fig. 6E The same pattern as the signal EnableSA shown in the figure;

[0215] Balanced signal EQ continues to have the same Fig. 6F The same pattern as the balanced signal shown in the figure;

[0216] The first upper coupling signal HIZ_TOP_L and the second lower coupling signal HIZ_BOT_R follow the same Figure 6G The coupled signal HIZ shown in the figure has the same pattern;

[0217] The signal NHIZ_TOPL_BOTR follows the Figure 6H The same pattern as the read signal NHIZ shown in FIG.

[0218] Signal EnableComp follows the reference Fig.12 The same pattern as described; and

[0219] Signal VERIFY_BOT has a value equal to “0” at time t0 and switches to “1” at time t2, maintaining this value until time t7; in this way, second reference generator 502 remains switched on during the time interval t2-t7.

[0220] In practice, such as Fig.15 As can be seen in FIG. 1 , the first inverter 126 and the first compensation capacitor 130 of the sense amplifier 146 of the upper read stage 117 and the second inverter 232 and the second compensation capacitor 236 of the sense amplifier 246 of the lower read stage 217 form a latch structure (hereinafter also referred to as a first aggregate latch structure) of the same type as the latch structure described with reference to the read stage 17, which is maintained in a metastable equilibrium state until an event occurs that can disturb this state. The inputs of the above-mentioned first aggregate latch structure are represented by the first input 146a of the sense amplifier 146 of the upper read stage 117 and the second input 246b of the sense amplifier 246 of the lower read stage 217.

[0221] In addition, the first upper memory cell 3' is coupled to the local bit line BL L <j>and the corresponding master bit line MBL L The coupling of the second lower memory cell 3"" to the local bit line BL is performed in the same manner and at the same timing as the coupling to the first input 117a of the upper read stage 117. R <j>' and the corresponding main bit line MBL R ', and coupled to the second input 217b of the lower read stage 217.

[0222] In more detail, after the word line WL of the first sector S' has been selected while the word line WL' of the second sector S" remains deselected, the upper voltage clamp signal YMPS_CLAMP_TOP and the lower voltage clamp signal YMPS_CLAMP_BOT are switched to "1". In this regard, the fact that the word line WL is pre-selected with respect to the switching of the upper voltage clamp signal YMPS_CLAMP_TOP requires a certain power loss, but enables the implementation to be simplified because the use of the signal S that activates the cell current can be avoided in this case. WL The read reference (ie, signal VERIFY_BOT) is turned on synchronously.

[0223] In the case where all this has been said, between the instant t3 and the instant t4, the discharge of the bit line capacitor 4c corresponding to the first upper memory cell 3' and the discharge of the main bit line capacitor 9' occurs through the first upper memory cell 3', with a consequent change in the voltage of the first input 117a of the upper reading stage 117. As a result, the voltage present at the common node 125a changes in a manner similar to that which has been described previously, for example with reference to the case indicated as TOP-TOP. In particular, the voltage at the common node 125a changes until the instant t4 when the common node 125a is decoupled from the first input 117a of the upper reading stage 117. The extent of the discharge depends on the data stored in the first upper memory cell 3'.

[0224] In addition, during the time interval between time t3 and time t4, discharging of the bit line capacitor 4c corresponding to the second lower memory cell 3″″ and discharging of the main bit line capacitor 9″″ also occur. In particular, since the word line WL is deselected, the discharging is performed through the second reference generator 502 and therefore at a rate that depends on the reference current.

[0225] In practice, during the time interval between time t3 and time t4, the voltage of the second input 217b of the lower read stage 217 changes, which changes according to the reference current and has nothing to do with the data stored in the second lower memory cell 3″″. In addition, the capacitance seen by the second input 217b of the lower read stage 217 is substantially equal to the capacitance seen by the first input 117a of the upper read stage 117.

[0226] A change in the voltage at the second input 217b of the lower read stage 217 causes an equal change in the voltage present at the common node 225b in a manner similar to that previously described with reference to the case denoted as BOT-BOT, for example. In particular, when the common node 225b is decoupled from the second input 217b of the lower read stage 217, the voltage at the common node 225b changes until time t4.

[0227] Thus, at time t4, there is a voltage difference between the first input 117a of the upper read stage 117 and the second input 217b of the lower read stage 217, and therefore between the inputs of the first aggregate latch structure described above. The voltage difference depends on the difference between the reference current and the current flowing in the first upper memory cell 3', the latter current varying according to the data stored in the first upper memory cell 3'.

[0228] After time t4, the first coupling switch 124a decouples the common node 125a from the first input 117a of the upper read stage 117, and the second coupling switch 224b decouples the common node 225b from the second input 217b of the lower read stage 217. Therefore, the voltage between the common nodes 125a and 225b remains fixed at the value it had at time t4.

[0229] Subsequently, at time t5, the balancing switches 128 and 234 are opened, and the additional switch SW3_R is closed. Therefore, the voltage across the first coupling capacitor 122a of the upper read stage 117 and the second coupling capacitor 222b of the lower read stage 217 (whose voltages are respectively determined by Fig.15 V TOP_LEFT and V BOT_RIGHT The potential difference present at the output of the comparison stage 602 (indicates) is due to the difference between the discharge current of the first upper memory cell 3' and the reference current. This potential difference disturbs the metastable equilibrium condition of the first aggregate latch structure and causes the first aggregate latch structure to switch according to the sign of the above-mentioned potential difference. This switching causes the voltages VC1_TOP and VC2_BOT present at the output terminals of the first inverter 126 of the sense amplifier 146 of the upper read stage 117 and the second inverter 232 of the sense amplifier 246 of the lower read stage 217, respectively, to take complementary logical values, which depend on the difference between the discharge current of the first upper memory cell 3' and the reference current. As previously mentioned, since the signals VC1, VC2 present at the output of the multiplexing stage 600 are equal to the signals VC1_TOP and VC2_BOT, respectively, it is found that the signal DataSense at the output of the comparison stage 602 represents the comparison between the discharge current of the first upper memory cell 3' and the reference current, and therefore represents the data stored in the first upper memory cell 3. In other words, the signal DataSense represents the signal of the single-ended reading of the first upper memory cell 3'. In particular, the read mode can be used to determine the state of the addressed cell, i.e., to verify whether the current of the addressed cell is higher or lower than a certain reference current. In other words, the read mode can be used in all SET and RESET algorithms whose purpose is to verify whether the SET or RESET operation has been able to cause a change in the cell state.

[0230] Referring again to the TOPL-BOPR case, it can be noted how the first aggregate latch structure, coupling switches 124a, 224b and additional switch SW3_R operate in the same manner as described, for example, with respect to the latch structure formed by the sense amplifier 146 of the upper read stage 117, balancing switches 124a, 124b and read switch 138 in the case referred to as TOP-TOP.

[0231] In a manner similar to that described with reference to case TOPL-BOTR, the control logic CL may issue a command for single-ended reading of the second upper memory cell 3" and any one of the first and second lower memory cells 3"', 3"".

[0232] For example, the case of single-ended reading of the second lower memory cell 3"" will now be described with reference only to the differences relative to the case TOPL-BOTR ( Fig.13A , Fig. 13B is referred to as BOTR-TOPL).

[0233] In detail, as from Fig.13A and Fig. 13B and from Fig.17 Clearly, the following occurs:

[0234] The signal VERIFY_TOPL is equal to "1" so that the first reference generator 402 is connected to the node YMPS_TOP, ie, to the first input 117a of the upper read stage 117;

[0235] The signal VERIFY_BOTR is equal to "0" to enable the first reference generator 402 to operate from the node Disconnect;

[0236] The signal VERIFY_BOT is equal to "0" to turn off the first reference generator 402;

[0237] The signal VERIFY_TOP follows the Fig.16 The same pattern as the signal VERIFY_TOP shown in FIG. 1 ; and

[0238] The signals WL_TOP and WL_BOT have relative Fig.16 The mode illustrated in FIG. 1 is reversed so that the word line WL remains deselected.

[0239] In fact, as in Fig.18 As shown in FIG. , the first aggregate latch structure is relatively Fig.15 However, between the instants t3 and t4 a discharge of the bit line capacitor 4c corresponding to the second lower memory cell 3"" and of the main bit line capacitor 9"" occurs through the second lower memory cell 3"" with a consequent change in the voltage of the second input 217b of the lower read stage 217. In contrast, the first upper memory cell 3' is discharged by the reference current generated by the first reference generator 402.

[0240] In a manner similar to that already described with reference to the case TOPL-BOTR, the control logic CL may further issue a command for single-ended reading of the second upper memory cell 3″ ( Fig.13A , Fig. 13B denoted as TOPR-BOTL in the example above), as described below.

[0241] In detail, the signals VC1, VC2 present at the output of the multiplexing stage 600 are equal to the signals VC1_BOT and VC2_TOP, respectively. In addition, the control logic CL operates so that:

[0242] SignalSENSEMODE <0> = "1" to close the additional switches SW2_R and SW1_L;

[0243] SignalSENSEMODE <1> = "0" to disconnect the first and second additional control switches 101, 102 of the upper read stage 117 and the first and second additional control switches 201, 202 of the lower read stage 217;

[0244] SignalSENSEMODE <2> = "0" to disconnect the additional switches SW1_R and SW2_L;

[0245] The signal EnableSA_TOP1 is equal to "1" to open and close the control switch 140 and the initialization switch 144 respectively;

[0246] The signal EnableSA_BOT2 is equal to "1" to open and close the control switch 242 and the initialization switch 245 respectively;

[0247] The signals VERIFY_TOPL, VERIFY_TOPR, and VERIFY_BOTR are equal to "0", and the signal VERIFY_BOTL is equal to "1" so that the second reference generator 502 is connected to the node YMPS_BOT;

[0248] The signal VERIFY_TOP is equal to "0" to shut down the first reference generator 402;

[0249] The upper read signal NHIZ_TOP and the first upper coupling signal HIZ_TOP_L are equal to "0" to disconnect the read switch 138 and the first coupling switch 124a;

[0250] The lower read signal NHIZ_BOT and the second lower coupling signal HIZ_BOT_R are equal to "0" to disconnect the read switch 238 and the second coupling switch 224b; and

[0251] The signal NHIZ_TOPL_BOTR is equal to “0” so that the additional switch SW3_R is turned off.

[0252] In addition, the control logic CL is as follows Fig. 13B and Fig.19 Operate as shown in the figure:

[0253] The upper voltage clamp signal YMPS_CLAMP_TOP and the lower voltage clamp signal YMPS_CLAMP_BOT follow the same Fig. 6A The voltage clamp signals YMPS_CLAMP shown in FIG. 1 and FIG. 2 have the same pattern, except for the fact that they switch to “1” at time t3 instead of at time t2;

[0254] Local column decoding signal YO L ,YO R ,YO L ', YO R 'Have and in Figure 6B The same pattern as the local column decoded signal shown in FIG.

[0255] Main column decoding signal YN L , YN R , YN L ', YN R 'Have and in Figure 6C The same pattern as the main column decoded signal shown in the figure;

[0256] The word line signal WL_TOP follows the Fig.6D The word line signal S shown in FIG. WL The same pattern, except for the fact that it switches to "0" at instant t2 instead of at instant t3; instead, the word line signal WL_BOT remains equal to "1";

[0257] Signals EnableSA_TOP2 and EnableSA_BOT1 follow the same Fig. 6E The same pattern as the signal EnableSA shown in the figure;

[0258] Balanced signal EQ continues to have the same Fig. 6F The same pattern as the balanced signal shown in the figure;

[0259] The second top coupling signal HIZ_TOP_R and the first bottom coupling signal HIZ_BOT_L follow the same Figure 6G The coupled signal HIZ shown in the figure has the same pattern;

[0260] The signal NHIZ_TOPR_BOTL follows the Figure 6H The same pattern as the read signal NHIZ shown in FIG.

[0261] Signal EnableComp follows the reference Fig.12 The same pattern as described; and

[0262] Signal VERIFY_BOT has a value equal to “0” at time t0 and switches to “1” at time t2, maintaining this value until time t7; in this way, second reference generator 502 remains switched on during the time interval t2-t7.

[0263] In practice, Fig. 20 As can be seen, the second inverter 132 and the second compensation capacitor 136 of the read amplifier 146 of the upper read stage 117 and the first inverter 226 and the first compensation capacitor 230 of the read amplifier 246 of the lower read stage 217 form a second aggregate latch structure, whose operation is similar to that of the first aggregate latch structure, except for the differences outlined below.

[0264] The inputs of the second aggregate latch structure are represented by the second input 146 b of the sense amplifier 146 of the upper read stage 117 and the first input 246 a of the sense amplifier 246 of the lower read stage 217 .

[0265] In addition, the first lower memory cell 3'' is coupled to the local bit line BL L <j>' and the corresponding main bit line MBL L ' and coupled to the first input 217a of the lower read stage 217 in the same manner and with the same timing, the second upper memory cell 3" is coupled to the local bit line BL R <j>and the corresponding master bit line MBL R , and coupled to the second input 117b of the upper read stage 117. Therefore, the capacitance seen by the first input 217a of the lower read stage 217 is substantially equal to the capacitance seen by the second input 117b of the upper read stage 117.

[0266] Thus, at time t4, a voltage difference occurs between the second input 117b of the upper read stage 117 and the first input 217a of the lower read stage 217, and thus between the inputs of the second aggregate latch structure. This voltage difference depends on the difference between the reference current and the current flowing in the second upper memory cell 3", the latter current varying according to the data stored in the second upper memory cell 3". The second coupling capacitor 222a across the upper read stage 117 and the first coupling capacitor 222a of the lower read stage 217 (whose voltages are respectively determined by Fig. 20 V TOP_RIGHT and V BOT_LEFT The potential difference present at the comparison stage 602 is due to the difference between the current passing through the second upper memory cell 3" and the reference current. This potential difference disturbs the metastable equilibrium condition of the second aggregate latch structure and causes the second aggregate latch structure to switch according to the sign of the above-mentioned potential difference. This switching causes the voltages VC2_TOP and VC1_BOT present at the output terminals of the second inverter 132 of the sense amplifier 146 of the upper read stage 117 and the first inverter 226 of the sense amplifier 246 of the lower read stage 217, respectively, to take complementary logic values, which depend on the difference between the current flowing in the second upper memory cell 3" and the reference current. As previously described, since the signals VC1, VC2 present at the output of the multiplexing stage 600 are equal to the signals VC1_BOT and VC2_TOP, respectively, it is found that the signal DataSense at the output of the comparison stage 602 represents the comparison between the current passing through the second upper memory cell 3" and the reference current. In other words, the signal DataSense represents the signal of the single-ended read of the second upper memory cell 3".

[0267] Referring again to the case TOPR-BOTL, it can be noted how the second aggregate latch structure, the coupling switches 124b, 224a and the additional switch SW3_L operate in the same manner as described, for example, with reference to the latch structure formed by the read amplifier 146 of the upper read stage 117, the balancing switches 124a, 124b and the read switch 138 in the case referred to as TOP-TOP.

[0268] In a similar manner to that already described with reference to the case TOPR-BOTL, the control logic CL may issue a command for single-ended reading of the first lower memory cell 3'' ( Fig.13A , Fig. 13B The case referred to as BOTL-TOPR in the literature) will now be described with reference only to the differences relative to the case TOPR-BOTL.

[0269] In detail, as from Fig.13A , Fig. 13B and Fig.21 Clearly indicated, the following apply:

[0270] The signal VERIFY_TOPR is equal to "1" so that the first reference generator 402 is connected to the node As in Fig. 22 As shown in the figure;

[0271] The signal VERIFY_BOTL is equal to "0" to disconnect the second reference generator 502 from the node YMPS_BOT;

[0272] The signal VERIFY_BOT is equal to "0" to turn off the second reference generator 502;

[0273] The signal VERIFY_TOP follows the Fig.19 The same pattern as the signal VERIFY_BOT shown in FIG. 1 ; and

[0274] The signals WL_TOP and WL_BOT have relative Fig.19 A pattern that is the inverse of the pattern shown in the figure.

[0275] The PCM device 100 is suitable for a wide range of applications. For example, Fig.23 A portion of an electronic device 1070 is illustrated, which may be, for example: a PDA (personal digital assistant); a portable or fixed computer (possibly with wireless data transmission capability); a telephone; a digital audio player; a camera or camcorder; or other equipment capable of processing, storing, transmitting and receiving information.

[0276] In detail, the electronic device 1070 includes: a controller 1071 (for example, provided with a microprocessor, DSP or microcontroller), an input / output device 1072 for inputting and displaying data (for example, provided with a keyboard and a display), a PCM device (here designated by 1040) provided with an array 2 of the phase change type memory cells 3 described above, a wireless interface 1074 (for example, an antenna) for transmitting and receiving data through a wireless radio frequency communication network, and a RAM 1075. All components of the electronic device 1070 are coupled through a bus 1076. A battery 1077 can be used as a power source in the electronic device 1070, and the electronic device 1070 can be further provided with a camera or a video camera or a camcorder 1078. In addition, the controller 1071 can control the PCM device 1040, for example, by cooperating with the control logic CL.

[0277] From the foregoing description it is clear that the advantages provided by the present memory device are apparent.

[0278] In detail, the present memory device enables switching between different read modes, in particular between a differential read mode and a single-ended read mode, thereby maintaining capacitance balance.

[0279] Finally, it is clear that modifications and variations may be made to the system described and illustrated herein without departing from the scope of the present disclosure.

[0280] For example, the timing may be different from that already described.

[0281] The selector may also be of a different type than that described. For example, the selector may be formed by MOS transistors.

[0282] It is also possible that the voltage clamp switch does not exist; in this case, the local column decoding signal YO and the main column decoding signal YN switch at different times.< / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. A memory device, comprising: A first sector and a second sector of a memory cell array, wherein each of the first sector and the second sector is associated with a corresponding selector and a corresponding phase change element, the corresponding phase change element being configured to have a first resistance value or a second resistance value associated with corresponding logic data, wherein the first sector comprises: first and second upper memory cells, each coupled to an upper word line and to a first and second upper local bit line, respectively; and A first upper main bit line and a second upper main bit line are coupled to the first upper local bit line and the second upper local bit line, respectively; and The second sector includes: a first lower memory cell and a second lower memory cell, each lower memory cell being coupled to a lower word line and to a first lower local bit line and a second lower local bit line, respectively; and a first lower master bit line and a second lower master bit line, respectively coupled to the first lower local bit line and the second lower local bit line; The memory device further includes a controller and a read circuit, the read circuit being arranged between the first sector and the second sector, the read circuit including an upper read stage and a lower read stage, the upper read stage including a first upper input node and a second upper input node, the lower read stage including a first lower input node and a second lower input node; an upper circuit device configured to be controlled so as to charge the first upper input node and the second upper input node and to couple the first upper input node and the second upper input node to the first upper memory cell and the second upper memory cell respectively through the first upper local bit line and the first upper main bit line and through the second upper local bit line and the second upper main bit line, respectively; a lower circuit device configured to be controlled so as to charge the first lower input node and the second lower input node and to couple the first lower input node and the second lower input node to the first lower memory cell and the second lower memory cell respectively through the first lower local bit line and the first lower main bit line and through the second lower local bit line and the second lower main bit line, respectively; and A reference generator is configured to generate a reference current and is driven by the controller so as to be coupled to the first upper input node or the second upper input node or to the first lower input node or the second lower input node.

2. The memory device of claim 1 , wherein the upper read stage comprises: an upper sense amplifier, comprising a first input, a second input, a first upper branch, and a second upper branch, wherein the first upper branch is arranged between the first input and a first upper internal node of the upper sense amplifier, and the first upper branch comprises a first upper inverter and a first upper compensation capacitor coupled together, the second upper branch is arranged between the second input and the second upper internal node of the upper sense amplifier, and the second upper branch comprises a second upper inverter and a second upper compensation capacitor coupled together, the upper sense amplifier further comprising a first upper routing switch and a second upper routing switch, the first upper routing switch being arranged between the second upper internal node and the first input of the upper sense amplifier, and the second upper routing switch being arranged between the first upper internal node and the second input of the upper sense amplifier; a first upper coupling capacitor coupled to the first input of the upper sense amplifier and a first upper intermediate node; a second upper coupling capacitor coupled to the second input of the upper sense amplifier and a second upper intermediate node; as well as a first upper coupling switch and a second upper coupling switch, respectively configured to be controlled so as to couple the first upper intermediate node and the second upper intermediate node to the first upper input node and the second upper input node, respectively; and an upper read switch configured to be controlled to couple the first upper intermediate node and the second upper intermediate node together.

3. The memory device of claim 2, wherein the lower read stage comprises: a lower sense amplifier, comprising a corresponding first input, a corresponding second input, a first lower branch, and a second lower branch, wherein the first lower branch is arranged between the first input and a first lower internal node of the lower sense amplifier, and the first lower branch comprises a first lower inverter and a first lower compensation capacitor coupled together, the second lower branch is arranged between the second input and the second lower internal node of the lower sense amplifier, and the second lower branch comprises a second lower inverter and a second lower compensation capacitor coupled together, the lower sense amplifier further comprising a first lower routing switch and a second lower routing switch, the first lower routing switch being arranged between the second lower internal node and the first input of the lower sense amplifier, and the second lower routing switch being arranged between the first lower internal node and the second input of the lower sense amplifier; a first lower coupling capacitor coupled to the first input of the lower sense amplifier and a first lower intermediate node; a second lower coupling capacitor coupled to the second input of the lower sense amplifier and a second lower intermediate node; as well as a first lower coupling switch and a second lower coupling switch, respectively configured to be controlled so as to couple the first lower intermediate node and the second lower intermediate node to the first lower input node and the second lower input node, respectively; and a lower read switch configured to be controlled to couple the first lower intermediate node and the second lower intermediate node together.

4. The memory device according to claim 3, further comprising: a first additional switch arranged between the first upper internal node and the second input of the lower sense amplifier; a second additional switch arranged between the second upper internal node and the first input of the lower sense amplifier; a third additional switch arranged between the first lower internal node and the second input of the upper sense amplifier; a fourth additional switch arranged between the second lower internal node and the first input of the upper sense amplifier; and a fifth additional switch disposed between the first upper intermediate node and the second lower intermediate node, wherein the controller is configured to operate in a first operation mode to drive the first additional switch, the second additional switch, the third additional switch, and the fourth additional switch to decouple the upper sense amplifier from the lower sense amplifier, and wherein the controller performs a first set of operations or a second set of operations, the first set of operations comprising: driving the first upper routing switch and the second upper routing switch to couple the first upper branch and the second upper branch and form a first loop circuit; selecting the upper word line and driving the upper circuit device so as to discharge the first upper input node and the second upper input node by currents flowing in the first upper memory cell and the second upper memory cell, respectively, and depending on resistance values ​​of the corresponding phase change elements; and driving the first upper coupling switch and the second upper coupling switch to discharge the first upper coupling capacitor and the second upper coupling capacitor according to the discharge of the first upper input node and the second upper input node, respectively; and then driving the upper read switch to couple the first upper intermediate node and the second upper intermediate node together, and according to the charge difference between the first upper coupling capacitor and the second upper coupling capacitor, the first loop circuit evolves into a corresponding first balanced state or a second balanced state; And wherein the second set of operations comprises: driving the first lower routing switch and the second lower routing switch to couple the first lower branch and the second lower branch and form a second loop circuit; selecting the lower word line and driving the lower circuit device so as to discharge the first lower input node and the second lower input node by currents flowing in the first lower memory cell and the second lower memory cell, respectively, and depending on the resistance values ​​of the corresponding phase change elements; and driving the first lower coupling switch and the second lower coupling switch to discharge the first lower coupling capacitor and the second lower coupling capacitor respectively according to the discharge of the first lower input node and the second lower input node; and then driving the lower read switch to couple the first lower intermediate node and the second lower intermediate node together, and according to the charge difference between the first lower coupling capacitor and the second lower coupling capacitor, the second loop circuit evolves into a corresponding first balanced state or a second balanced state; and wherein the controller is further configured to operate at least in a second operating mode to drive the first upper routing switch and the second upper routing switch to decouple the first upper branch and the second upper branch, and to drive the first lower routing switch and the second lower routing switch to decouple the first lower branch and the second lower branch, and to perform a third set of operations, the third set of operations comprising: driving the first additional switch and the fourth additional switch to couple the first upper branch and the second lower branch and form a third loop circuit; selecting the upper word line and driving the upper circuit device to discharge the first upper input node by a current flowing in the first upper memory cell and depending on the resistance value of the corresponding phase change element; driving the lower circuit device to couple the second lower input node to the second lower local bit line and the second lower main bit line; deselecting the lower word line; coupling the reference generator to the second lower input node and discharging the second lower input node through the reference current; and The first upper coupling switch and the second lower coupling switch are driven to discharge the first upper coupling capacitor and the second lower coupling capacitor according to the discharge of the first upper input node and the second lower input node, respectively; and the fifth additional switch is then driven to couple the first upper intermediate node and the second lower intermediate node together, and according to the charge difference between the first upper coupling capacitor and the second lower coupling capacitor, the third loop circuit evolves into a corresponding first balanced state or a second balanced state.

5. The memory device of claim 4 , further comprising a sixth additional switch disposed between the second upper intermediate node and the first lower intermediate node, and wherein the controller is further configured to operate in a third operation mode to drive the first upper routing switch and the second upper routing switch to decouple the first upper branch and the second upper branch, and to drive the first lower routing switch and the second lower routing switch to decouple the first lower branch and the second lower branch, and to drive the second additional switch and the third additional switch to couple the second upper branch and the first lower branch and form a fourth loop circuit, and to perform a fourth set of operations, the fourth set of operations comprising: selecting the upper word line and driving the upper circuit device to discharge the second upper input node by a current flowing in the second upper memory cell and depending on the resistance value of the corresponding phase change element; driving the lower circuit device to couple the first lower input node to the first lower local bit line and the first lower main bit line; deselecting the lower word line; coupling the reference generator to the first lower input node and discharging the first lower input node through the reference current; as well as driving the second upper coupling switch and the first lower coupling switch to discharge the second upper coupling capacitor and the first lower coupling capacitor according to the discharge of the second upper input node and the first lower input node, respectively; And then driving the sixth additional switch to couple the second upper intermediate node and the first lower intermediate node together, and according to the charge difference between the second upper coupling capacitor and the first lower coupling capacitor, the fourth loop circuit evolves into the corresponding first balanced state or the second balanced state.

6. The memory device of claim 5, wherein when the controller operates in the second operation mode, the controller is configured to selectively perform the third set of operations or a fifth set of operations, the fifth set of operations comprising: selecting the lower word line and driving the lower circuit device so as to discharge the second lower input node by a current flowing in the second lower memory cell and depending on the resistance value of the corresponding phase change element; driving the upper circuit device to couple the first upper input node to the first upper local bit line and the first upper main bit line; deselecting the upper word line; coupling the reference generator to the first upper input node and discharging the first upper input node through the reference current; as well as driving the first upper coupling switch and the second lower coupling switch to discharge the first upper coupling capacitor and the second lower coupling capacitor according to the discharge of the first upper input node and the second lower input node, respectively; And then driving the fifth additional switch to couple the first upper intermediate node and the second lower intermediate node together, and according to the charge difference between the first upper coupling capacitor and the second lower coupling capacitor, the third loop circuit evolves into the corresponding first balanced state or second balanced state.

7. The memory device of claim 6, wherein when the controller operates in the third operation mode, the controller is configured to selectively perform the fourth set of operations or a sixth set of operations, the sixth set of operations comprising: selecting the lower word line and driving the lower circuit device so as to discharge the first lower input node by a current flowing in the first lower memory cell and depending on the resistance value of the corresponding phase change element; driving the upper circuit device to couple the second upper input node to the second upper local bit line and the second upper main bit line; deselecting the upper word line; coupling the reference generator to the second upper input node and discharging the second upper input node through the reference current; as well as driving the second upper coupling switch and the first lower coupling switch to discharge the second upper coupling capacitor and the first lower coupling capacitor according to the discharge of the second upper input node and the first lower input node, respectively; And then driving the sixth additional switch to couple the second upper intermediate node and the first lower intermediate node together, and according to the charge difference between the second upper coupling capacitor and the first lower coupling capacitor, the fourth loop circuit evolves into the corresponding first balanced state or the second balanced state.

8. The memory device of claim 7 , further comprising a first power line and a second power line, the first power line and the second power line being configured to be set at a supply voltage and coupled to the upper circuit device and the lower circuit device, respectively, and wherein the first upper local bit line and the second upper local bit line form a first upper parasitic capacitor and a second upper parasitic capacitor, respectively, and the first upper main bit line and the second upper main bit line form a third upper parasitic capacitor and a fourth upper parasitic capacitor, respectively, and wherein the first lower local bit line and the second lower local bit line form a first lower parasitic capacitor and a second lower parasitic capacitor, respectively, and the first lower main bit line and the second lower main bit line form a third lower parasitic capacitor and a fourth lower parasitic capacitor, respectively, and wherein the upper circuit device is configured to be controlled by the controller so as to: charging the first upper parasitic capacitor and the third upper parasitic capacitor at the supply voltage, coupling the first upper input node to the first upper parasitic capacitor and the third upper parasitic capacitor, and discharging the first upper parasitic capacitor and the third upper parasitic capacitor through the first upper memory cell when the upper word line is selected; as well as charging the second upper parasitic capacitor and the fourth upper parasitic capacitor at the supply voltage, coupling the second upper input node to the second upper parasitic capacitor and the fourth upper parasitic capacitor, and discharging the second upper parasitic capacitor and the fourth upper parasitic capacitor through the second upper memory cell when the upper word line is selected; and wherein the lower circuit device is configured to be controlled by the controller so as to: charging the first lower parasitic capacitor and the third lower parasitic capacitor at the supply voltage, coupling the first lower input node to the first lower parasitic capacitor and the third lower parasitic capacitor, and discharging the first lower parasitic capacitor and the third lower parasitic capacitor through the first lower memory cell when the lower word line is selected; as well as The second lower parasitic capacitor and the fourth lower parasitic capacitor are charged at the supply voltage, the second lower input node is coupled to the second lower parasitic capacitor and the fourth lower parasitic capacitor, and the second lower parasitic capacitor and the fourth lower parasitic capacitor are discharged through the second lower memory cell when the upper word line is selected.

9. The memory device of claim 8, wherein the upper circuit means comprises: a first upper local switch disposed between the first upper local bit line and the first upper main bit line; a first upper precharge switch, arranged between the first upper main bit line and the first power line; a first upper main selection switch arranged between the first upper main bit line and the first upper input node; a second upper local switch disposed between the second upper local bit line and the second upper main bit line; a second upper precharge switch, arranged between the second upper main bit line and the first power line; a second upper main selection switch arranged between the second upper main bit line and the second upper input node; a first upper voltage clamp switch disposed between the first power line and the first upper input node; as well as a second upper voltage clamp switch disposed between the first power line and the second upper input node; And wherein the lower circuit device comprises: a first lower local switch disposed between the first lower local bit line and the first lower main bit line; a first lower precharge switch arranged between the first lower main bit line and the second power line; a first lower main selection switch disposed between the first lower main bit line and the first lower input node; a second lower local switch disposed between the second lower local bit line and the second lower main bit line; a second lower precharge switch, arranged between the second lower main bit line and the second power line; a second lower main selection switch disposed between the second lower main bit line and the second lower input node; a first lower voltage clamp switch disposed between the second power line and the first lower input node; and a second lower voltage clamp switch disposed between the second power line and the second lower input node; and wherein the first set of operations performed by the controller comprises: At a corresponding first moment, closing the first upper pre-charging switch and the second upper pre-charging switch, and charging the third upper parasitic capacitor and the fourth upper parasitic capacitor at the supply voltage; At a corresponding second time after the corresponding first time, opening the first upper precharge switch and the second upper precharge switch, closing the first upper main selection switch and the second upper main selection switch so as to couple the first upper main bit line and the second upper main bit line to the first upper input node and the second upper input node, respectively, and further closing the first upper local switch and the second upper local switch, and charging the first upper parasitic capacitor and the second upper parasitic capacitor using voltages of the third upper parasitic capacitor and the fourth upper parasitic capacitor, respectively; and Keeping the first upper voltage clamp switch and the second upper voltage clamp switch closed until a corresponding third moment after the corresponding second moment; selecting the upper word line at a corresponding fourth time after the corresponding third time; and disconnecting the first upper coupling switch and the second upper coupling switch at a fifth moment corresponding to the fourth moment; and wherein the second set of operations performed by the controller comprises: At a corresponding first moment, closing the first lower pre-charging switch and the second lower pre-charging switch, and charging the third lower parasitic capacitor and the fourth lower parasitic capacitor at the supply voltage; At a corresponding second time after the corresponding first time, opening the first lower precharge switch and the second lower precharge switch, closing the first lower main selection switch and the second lower main selection switch so as to couple the first lower main bit line and the second lower main bit line to the first lower input node and the second lower input node, respectively, and further closing the first lower local switch and the second lower local switch, and charging the first lower parasitic capacitor and the second lower parasitic capacitor using voltages of the third lower parasitic capacitor and the fourth lower parasitic capacitor, respectively; Keeping the first lower voltage clamp switch and the second lower voltage clamp switch closed until a corresponding third moment after the corresponding second moment; selecting the lower word line at a corresponding fourth moment after the corresponding third moment; disconnecting the first down-coupling switch and the second down-coupling switch at a fifth time corresponding to the fourth time; And wherein each of the third set of operations and the fifth set of operations performed by the controller comprises: At a corresponding first moment, closing the first upper pre-charging switch and the second lower pre-charging switch, and charging the third upper parasitic capacitor and the fourth lower parasitic capacitor at the supply voltage; At a corresponding second time after the corresponding first time, opening the first upper precharge switch and the second lower precharge switch, closing the first upper main selection switch and the second lower main selection switch so as to couple the first upper main bit line and the second lower main bit line to the first upper input node and the second lower input node, respectively, and further closing the first upper local switch and the second lower local switch, and charging the first upper parasitic capacitor and the second lower parasitic capacitor using voltages of the third upper parasitic capacitor and the fourth lower parasitic capacitor, respectively; and Keeping the first upper voltage clamp switch and the second lower voltage clamp switch closed until a corresponding third time after the corresponding second time; At a corresponding fourth time before the corresponding third time, selecting the upper word line in the case of the third set of operations, or selecting the lower word line in the case of the fifth set of operations; and At a fifth moment corresponding to the third moment, disconnecting the first upper coupling switch and the second lower coupling switch; And wherein each of the fourth set of operations and the sixth set of operations performed by the controller comprises: At a corresponding first moment, closing the second upper pre-charging switch and the first lower pre-charging switch, and charging the fourth upper parasitic capacitor and the third lower parasitic capacitor at the supply voltage; At a corresponding second time after the corresponding first time, opening the second upper precharge switch and the first lower precharge switch, closing the second upper main selection switch and the first lower main selection switch so as to couple the second upper main bit line and the first lower main bit line to the second upper input node and the first lower input node, respectively, and further closing the second upper local switch and the first lower local switch, and charging the second upper parasitic capacitor and the first lower parasitic capacitor using voltages of the fourth upper parasitic capacitor and the third lower parasitic capacitor, respectively; Keeping the second upper voltage clamp switch and the first lower voltage clamp switch closed until a corresponding third time after the corresponding second time; At a corresponding fourth time before the corresponding third time, selecting the upper word line in the case of the fourth set of operations, or selecting the lower word line in the case of the sixth set of operations; and At a fifth moment corresponding to the third moment, the second upper coupling switch and the first lower coupling switch are turned off. 10 . The memory device of claim 1 , wherein the first lower memory cell and the second lower memory cell are symmetrically arranged with respect to the first upper memory cell and the second upper memory cell, respectively.

11. The memory device of claim 1, wherein the first sector and the second sector are identical to each other.

12. The memory device of claim 3, further comprising an output stage configured to select a pair of charges from charges present on output terminals of the first and second upper inverters and the first and second lower inverters.

13. An electronic device comprising: The memory device according to claim 1; Controller; as well as A bus is configured to electrically couple the controller and the memory device.

14. A method for reading a memory device, the memory device comprising a first sector and a second sector of a memory cell array, each of the first sector and the second sector comprising a corresponding selector and a phase change element, the phase change element being configured to have a first resistance value or a second resistance value associated with corresponding logic data; the first sector comprising: a first upper memory cell and a second upper memory cell coupled to the upper word line and to the first upper local bit line and the second upper local bit line, respectively; as well as a first upper main bit line and a second upper main bit line, respectively coupled to the first upper local bit line and the second upper local bit line; The second sector includes: A first lower memory cell and a second lower memory cell coupled to the lower word line and to the first lower local bit line and the second lower local bit line, respectively; and a first lower master bit line and a second lower master bit line, respectively coupled to the first lower local bit line and the second lower local bit line; The memory device further includes a read circuit arranged between the first sector and the second sector, and the read circuit includes an upper read stage and a lower read stage, the upper read stage includes a first upper input node and a second upper input node, the lower read stage includes a first lower input node and a second lower input node, the memory device further includes: an upper circuit device configured to be controlled so as to charge the first upper input node and the second upper input node and to couple the first upper input node and the second upper input node to the first upper memory cell and the second upper memory cell respectively through the first upper local bit line and the first upper main bit line and through the second upper local bit line and the second upper main bit line, respectively; a lower circuit device configured to be controlled so as to charge the first lower input node and the second lower input node and to couple the first lower input node and the second lower input node to the first lower memory cell and the second lower memory cell respectively through the first lower local bit line and the first lower main bit line and through the second lower local bit line and the second lower main bit line, respectively; and a reference generator configured to generate a reference current and driven by a controller so as to be coupled to the first upper input node or the second upper input node or to the first lower input node or the second lower input node; The upper reading stage comprises: an upper sense amplifier, comprising a first input, a second input, a first upper branch, and a second upper branch, wherein the first upper branch is arranged between the first input and a first upper internal node of the upper sense amplifier, and the first upper branch comprises a first upper inverter and a first upper compensation capacitor coupled together, the second upper branch is arranged between the second input and the second upper internal node of the upper sense amplifier, and the second upper branch comprises a second upper inverter and a second upper compensation capacitor coupled together, the upper sense amplifier further comprising a first upper routing switch and a second upper routing switch, the first upper routing switch being arranged between the second upper internal node and the first input of the upper sense amplifier, and the second upper routing switch being arranged between the first upper internal node and the second input of the upper sense amplifier; a first upper coupling capacitor coupled to the first input of the upper sense amplifier and a first upper intermediate node; a second upper coupling capacitor coupled to the second input and the second upper intermediate node of the upper sense amplifier; and a first upper coupling switch and a second upper coupling switch, respectively configured to be controlled so as to couple the first upper intermediate node and the second upper intermediate node to the first upper input node and the second upper input node, respectively; and an upper read switch, configured to be controlled so as to couple the first upper intermediate node and the second upper intermediate node together; The lower reading stage comprises: a lower sense amplifier, comprising a corresponding first input, a corresponding second input, a first lower branch, and a second lower branch, wherein the first lower branch is arranged between the first input and a first lower internal node of the lower sense amplifier, and the first lower branch comprises a first lower inverter and a first lower compensation capacitor coupled together, the second lower branch is arranged between the second input and the second lower internal node of the lower sense amplifier, and the second lower branch comprises a second lower inverter and a second lower compensation capacitor coupled together, the lower sense amplifier further comprising a first lower routing switch and a second lower routing switch, the first lower routing switch being arranged between the second lower internal node and the first input of the lower sense amplifier, and the second lower routing switch being arranged between the first lower internal node and the second input of the lower sense amplifier; a first lower coupling capacitor coupled to the first input of the lower sense amplifier and a first lower intermediate node; a second lower coupling capacitor coupled to the second input and a second lower intermediate node of the lower sense amplifier; and a first lower coupling switch and a second lower coupling switch, each configured to be controlled so as to couple the first lower intermediate node and the second lower intermediate node to the first lower input node and the second lower input node, respectively; and a lower read switch, configured to be controlled so as to couple the first lower intermediate node and the second lower intermediate node together; The memory device further comprises: a first additional switch arranged between the first upper internal node and the second input of the lower sense amplifier; a second additional switch arranged between the second upper internal node and the first input of the lower sense amplifier; a third additional switch arranged between the first lower internal node and the second input of the upper sense amplifier; a fourth additional switch arranged between the second lower internal node and the first input of the upper sense amplifier; and a fifth additional switch, arranged between the first upper intermediate node and the second lower intermediate node; The method for reading includes performing a first set of operations, the first set of operations including driving the first additional switch, the second additional switch, the third additional switch, and the fourth additional switch to decouple the upper sense amplifier and the lower sense amplifier, and performing a first group of operations or a second group of operations, the first group of operations including: driving the first upper routing switch and the second upper routing switch to couple the first upper branch and the second upper branch and form a first loop circuit; selecting the upper word line and driving the upper circuit device so as to discharge the first upper input node and the second upper input node by currents flowing in the first upper memory cell and the second upper memory cell, respectively, and depending on resistance values ​​of the corresponding phase change elements; and driving the first upper coupling switch and the second upper coupling switch to discharge the first upper coupling capacitor and the second upper coupling capacitor according to the discharge of the first upper input node and the second upper input node, respectively; and then driving the upper read switch to couple the first upper intermediate node and the second upper intermediate node together, and according to the charge difference between the first upper coupling capacitor and the second upper coupling capacitor, the first loop circuit evolves into a corresponding first balanced state or a second balanced state; And wherein the second set of operations comprises: driving the first lower routing switch and the second lower routing switch to couple the first lower branch and the second lower branch and form a second loop circuit; selecting the lower word line and driving the lower circuit device so as to discharge the first lower input node and the second lower input node by currents flowing in the first lower memory cell and the second lower memory cell, respectively, and depending on the resistance values ​​of the corresponding phase change elements, and driving the first lower coupling switch and the second lower coupling switch to discharge the first lower coupling capacitor and the second lower coupling capacitor respectively according to the discharge of the first lower input node and the second lower input node; and then driving the lower read switch to couple the first lower intermediate node and the second lower intermediate node together, and according to the charge difference between the first lower coupling capacitor and the second lower coupling capacitor, the second loop circuit evolves into a corresponding first balanced state or a second balanced state; The method for reading also includes performing at least one second set of operations, the at least one second set of operations including: driving the first upper routing switch and the second upper routing switch to decouple the first upper branch and the second upper branch, driving the first lower routing switch and the second lower routing switch to decouple the first lower branch and the second lower branch, and performing a third set of operations, the third set of operations including: driving the first additional switch and the fourth additional switch to couple the first upper branch and the second lower branch and form a third loop circuit; selecting the upper word line and driving the upper circuit device to discharge the first upper input node by a current flowing in the first upper memory cell and depending on the resistance value of the corresponding phase change element; driving the lower circuit device to couple the second lower input node to the second lower local bit line and the second lower main bit line; deselecting the lower word line; coupling the reference generator to the second lower input node and discharging the second lower input node through the reference current; and The first upper coupling switch and the second lower coupling switch are driven to discharge the first upper coupling capacitor and the second lower coupling capacitor according to the discharge of the first upper input node and the second lower input node, respectively; and the fifth additional switch is then driven to couple the first upper intermediate node and the second lower intermediate node together, and according to the charge difference between the first upper coupling capacitor and the second lower coupling capacitor, the third loop circuit evolves into a corresponding first balanced state or a second balanced state.

15. The method for reading a memory device according to claim 14, wherein the memory device further comprises a sixth additional switch, the sixth additional switch being arranged between the second upper intermediate node and the first lower intermediate node, the method for reading further comprising performing a third set of operations, the third set of operations comprising: The first upper routing switch and the second upper routing switch are driven to decouple the first upper branch and the second upper branch, the first lower routing switch and the second lower routing switch are driven to decouple the first lower branch and the second lower branch, and the second additional switch and the third additional switch are driven to couple the second upper branch and the first lower branch and form a fourth loop circuit, the third set of operations further comprising performing a fourth group of operations, the fourth group of operations comprising: selecting the upper word line and driving the upper circuit device to discharge the second upper input node by a current flowing in the second upper memory cell and depending on the resistance value of the corresponding phase change element; driving the lower circuit device to couple the first lower input node to the first lower local bit line and the first lower main bit line; deselecting the lower word line; coupling the reference generator to the first lower input node and discharging the first lower input node through the reference current; and The second upper coupling switch and the first lower coupling switch are driven to discharge the second upper coupling capacitor and the first lower coupling capacitor according to the discharge of the second upper input node and the first lower input node, respectively; and the sixth additional switch is then driven to couple the second upper intermediate node and the first lower intermediate node together, and according to the charge difference between the second upper coupling capacitor and the first lower coupling capacitor, the fourth loop circuit evolves into the corresponding first balanced state or the second balanced state.

16. The method for reading a memory device according to claim 15, wherein the second set of operations comprises selectively performing the third set of operations or a fifth set of operations, the fifth set of operations comprising: selecting the lower word line and driving the lower circuit device so as to discharge the second lower input node by a current flowing in the second lower memory cell and depending on the resistance value of the corresponding phase change element; driving the upper circuit device to couple the first upper input node to the first upper local bit line and the first upper main bit line; deselecting the upper word line; coupling the reference generator to the first upper input node and discharging the first upper input node through the reference current; as well as driving the first upper coupling switch and the second lower coupling switch to discharge the first upper coupling capacitor and the second lower coupling capacitor according to the discharge of the first upper input node and the second lower input node, respectively; And then driving the fifth additional switch to couple the first upper intermediate node and the second lower intermediate node together, and according to the charge difference between the first upper coupling capacitor and the second lower coupling capacitor, the third loop circuit evolves into the corresponding first balanced state or second balanced state.

17. The method for reading a memory device according to claim 16, wherein the third set of operations comprises selectively performing the fourth set of operations or a sixth set of operations, the sixth set of operations comprising: selecting the lower word line and driving the lower circuit device so as to discharge the first lower input node by a current flowing in the first lower memory cell and depending on the resistance value of the corresponding phase change element; driving the upper circuit device to couple the second upper input node to the second upper local bit line and the second upper main bit line; deselecting the upper word line; coupling the reference generator to the second upper input node and discharging the second upper input node through the reference current; as well as driving the second upper coupling switch and the first lower coupling switch to discharge the second upper coupling capacitor and the first lower coupling capacitor according to the discharge of the second upper input node and the first lower input node, respectively; And then driving the sixth additional switch to couple the second upper intermediate node and the first lower intermediate node together, and according to the charge difference between the second upper coupling capacitor and the first lower coupling capacitor, the fourth loop circuit evolves into the corresponding first balanced state or the second balanced state.

18. The method for reading a memory device according to claim 17, wherein the memory device further comprises a first power line and a second power line, the first power line and the second power line being configured to be set at a supply voltage and coupled to the upper circuit device and the lower circuit device, respectively, and wherein the first upper local bit line and the second upper local bit line form a first upper parasitic capacitor and a second upper parasitic capacitor, respectively, and the first upper main bit line and the second upper main bit line form a third upper parasitic capacitor and a fourth upper parasitic capacitor, respectively, and wherein the first lower local bit line and the second lower local bit line form a first lower parasitic capacitor and a second lower parasitic capacitor, respectively, and the first lower main bit line and the second lower main bit line form a third lower parasitic capacitor and a fourth lower parasitic capacitor, respectively, the method for reading further comprising driving the upper circuit device so as to: charging the first upper parasitic capacitor and the third upper parasitic capacitor at the supply voltage, coupling the first upper input node to the first upper parasitic capacitor and the third upper parasitic capacitor, and discharging the first upper parasitic capacitor and the third upper parasitic capacitor through the first upper memory cell when the upper word line is selected; as well as charging the second upper parasitic capacitor and the fourth upper parasitic capacitor at the supply voltage, coupling the second upper input node to the second upper parasitic capacitor and the fourth upper parasitic capacitor, and discharging the second upper parasitic capacitor and the fourth upper parasitic capacitor through the second upper memory cell when the upper word line is selected; The method for reading also includes driving the lower circuit device so as to: charging the first lower parasitic capacitor and the third lower parasitic capacitor at the supply voltage, coupling the first lower input node to the first lower parasitic capacitor and the third lower parasitic capacitor, and discharging the first lower parasitic capacitor and the third lower parasitic capacitor through the first lower memory cell when the lower word line is selected; as well as The second lower parasitic capacitor and the fourth lower parasitic capacitor are charged at the supply voltage, the second lower input node is coupled to the second lower parasitic capacitor and the fourth lower parasitic capacitor, and the second lower parasitic capacitor and the fourth lower parasitic capacitor are discharged through the second lower memory cell when the upper word line is selected.

Images