Switching power supplies that achieve power level expansion by using controllers in parallel

Abstract

The present invention provides a switching power supply that achieves power level expansion by using controllers in parallel, including: at least one integrated power controller, the integrated power controller working in slave control mode is connected in parallel with the integrated power controller working in master control mode. The switching power supply provided by the present invention achieves power level expansion by connecting integrated power controllers in parallel, which can meet applications with higher power levels, allowing users to design according to specific needs, which is flexible and convenient; a chip, that is, an integrated power controller, can achieve switching power supplies with multiple output powers, which not only saves the development costs of chip manufacturers and subsequent product management costs, but also provides users with the autonomy to design according to specific needs, meets users' needs for the diversity of switching power output power, and improves user experience; the performance of the power supply is better.

Description

Technical Field

[0001] The present invention belongs to the technical field of switching power supplies of single-chip integrated power MOS tubes, and in particular relates to a switching power supply that realizes power level expansion by using a controller in parallel. Background Art

[0002] In recent years, with the multi-faceted development of integrated circuit technology, more and more BCD processes have integrated MOS and LDMOS tubes of various withstand voltage levels, and controllers and power LDMOS tubes can be integrated on the same wafer. Figure 1 As shown in the figure, it is a principle block diagram that we often see, which integrates the control circuit and power MOS tube required for the power supply into the same chip. Since the power tube is integrated inside the chip, it is also convenient to integrate the current sampling inside the chip, and many beneficial effects will be obtained at the same time. Figure 1 Rsense in the figure is the sampling resistor, which often uses the parasitic resistance of the source wiring of the LDMOS tube. Since no special series connection is required to generate additional losses, it is often called built-in lossless current sampling. In this way, the sampling resistor is very small, with an order of magnitude of tens of milliohms or even several milliohms. The voltage drop caused by the current passing through the power tube on this sampling resistor is also very small, with a maximum value often within 100mV. However, such a small voltage does not have the prominent signal-to-noise ratio problem like external current sampling, because the current sampling is built into the chip, the sampling loop is small, and a relatively large part of the common-mode signal can be eliminated by reasonably arranging the wiring. It can be seen that with the improvement of semiconductor technology and the integration of power MOS tubes and lossless current sampling into the chip, not only excellent characteristics are obtained, but also the peripheral circuits of the chip are simplified, so this highly integrated power controller is becoming more and more popular.

[0003] However, the higher the integration of the control chip, the less room there is for users to design according to the specific needs of the switching power supply, so it is impossible to optimize the performance indicators of power supplies of various specifications. If a variety of highly integrated control chips are designed to meet the diversity of switching power supply needs, it will be very costly for chip manufacturers and not conducive to product management. Therefore, high integration is a double-edged sword. Among the diversity of power supply needs, the most prominent performance is the different output power levels of the power supply. It is not possible to separate the power controller and power tube like the solution of non-integrated power tubes. Customers can achieve switching power supplies of different power levels by selecting power tubes of different sizes. The power controller is still the same and there is no need to distinguish the power levels. If there is a highly integrated power chip that can achieve an output power of 30W, it can be used to achieve a switching power supply with an output power of 10W. Naturally, it can be achieved, but the first problem is the cost. The LDMOS tube integrated inside the controller is a planar structure, and the on-resistance is much larger than that of the vertical structure VDMOS. Therefore, the cost of using a 30W highly integrated chip to make a power supply with an output power of 10W or less is too high, and at the same time, it cannot achieve the best performance in some indicators, such as no-load power consumption. Summary of the invention

[0004] In view of the fact that it is difficult for the existing single-chip integrated power MOS tube power control chip to realize switching power supplies of various power levels with one chip while ensuring reasonable cost, and it is not easy to meet the user's demand for the diversity of switching power output power, the present invention proposes a switching power supply that realizes power level expansion by using controllers in parallel, and the power level expansion can be achieved by connecting one or more integrated power controllers in parallel.

[0005] In order to have a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended to be a general review, nor is it intended to identify key / important components or to delineate the scope of protection of these embodiments. Its only purpose is to present some concepts in a simple form as a preface to the detailed description that follows.

[0006] The present invention adopts the following technical solution:

[0007] In some optional embodiments, there is provided a switching power supply for implementing power level expansion by using controllers in parallel, comprising: at least one integrated power controller, the integrated power controller operating in a slave control mode being connected in parallel with the integrated power controller operating in a master control mode;

[0008] The integrated power supply controller comprises: a mode selection circuit;

[0009] When the mode selection input signal port of the mode selection circuit receives the internal driving signal, the internal driving timing receiving port of the mode selection circuit receives the internal driving timing signal from the internal chip of the mode selection circuit, and turns on or off the power MOS tube according to the internal driving timing signal;

[0010] When the mode selection input signal port of the mode selection circuit receives an external drive signal, the external drive timing transceiver port of the mode selection circuit receives the external drive timing signal output by the monolithic integrated power supply controller working in the master control mode, and turns on or off the power MOS tube according to the external drive timing signal.

[0011] In some optional embodiments, the monolithic integrated power supply controller also includes: a power supply function circuit and a driving circuit; the internal driving timing sending port of the power supply function circuit is connected to the internal driving timing receiving port of the mode selection circuit, the driving control signal sending port of the mode selection circuit is connected to the driving control signal receiving port of the driving circuit, and the driving output port of the driving circuit is connected to the gate of the power MOS tube; the internal driving timing signal is generated by the power supply function circuit, and the internal driving timing signal turns on or off the power MOS tube through the driving circuit.

[0012] In some optional embodiments, the mode selection circuit includes: a NAND gate NAND1, a NAND gate NAND2, a NAND gate NAND3, a NOT gate NOT and a selection switch;

[0013] One of the input ports of the NAND gate NAND1 is connected to the first port of the selection switch and serves as the internal driving timing receiving port of the mode selection circuit, and the other input port of the NAND gate NAND1 is connected to the control port of the selection switch and the input port of the NOT gate NOT and serves as the mode selection input signal port of the mode selection circuit;

[0014] One of the input ports of the NAND gate NAND2 is connected to the output port of the NOT gate NOT, and the other input port of the NAND gate NAND2 is connected to the second port of the selection switch and serves as an external driving timing receiving and transmitting port of the mode selection circuit;

[0015] The two input ports of the NAND gate NAND3 are respectively connected to the output ports of the NAND gate NAND2 and the NAND gate NAND1, and the output port of the NAND gate NAND3 serves as a driving control signal sending port of the mode selection circuit.

[0016] In some optional embodiments, the integrated power supply controller includes: a MODE pin, a DORS pin and a DRN pin; the MODE pin is connected to the mode selection input signal port of the mode selection circuit and the enable input port of the power function circuit to receive the mode selection signal from outside the integrated power supply controller; the DORS pin is connected to the external drive timing transceiver port of the mode selection circuit to receive or send the external drive timing signal; the DRN pin is connected to the drain of the power MOS tube to output voltage.

[0017] In some optional embodiments, the DORS pin of the integrated power controller operating in slave mode is connected to the DORS pin of the integrated power controller operating in master mode, and the DRN pin of the integrated power controller operating in slave mode is connected to the DRN pin of the integrated power controller operating in master mode.

[0018] The beneficial effects brought about by the present invention are as follows: the switching power supply provided by the present invention realizes the expansion of power level through the parallel connection of integrated power supply controllers, which can meet the application of larger power level, so that users can design according to specific needs, which is flexible and convenient; a chip, that is, an integrated power supply controller can realize switching power supplies with multiple output powers, which not only saves the development costs and subsequent product management costs of chip manufacturers, but also provides users with the autonomy to design according to specific needs, meets the user's demand for the diversity of switching power supply output power, and improves user experience; the performance of the power supply is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the prior art for integrating the power MOS tube and the control circuit on the same chip;

[0020] Figure 2 An application diagram of a single-stage use of the switching power supply of the present invention;

[0021] Figure 3 A logic circuit diagram of a mode selection circuit of the present invention;

[0022] Figure 4 This is an application diagram of the integrated power supply controllers of the switching power supplies of the present invention being used in parallel. DETAILED DESCRIPTION

[0023] The following description and accompanying drawings fully demonstrate specific embodiments of the present invention so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible variations only. Unless clearly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments.

[0024] like Figures 2 to 4 As shown, in some illustrative embodiments, a switching power supply is provided for achieving power level expansion by using controllers in parallel, including: at least one integrated power supply controller 1, which can be used in parallel.

[0025] The monolithic integrated power controller 1 includes: a power MOS tube NMO, a power function circuit, a drive circuit and a mode selection circuit. The integrated power controller 1 integrates the power function circuit, the power MOS tube NMO and the drive circuit into the same chip.

[0026] The power supply function circuit refers to the circuit set of output voltage sampling, current sampling, protection function, etc. required to achieve the purpose of stable output voltage of the switching power supply. It ultimately generates a duty cycle driving timing signal, which turns on or off the power MOS tube NMO through the driving circuit. Figure 1 As shown, the error amplifier EA, comparator, frequency control, current sampler and RS trigger in the controller can form a basic power supply function circuit, wherein the frequency control is usually a frequency-controllable oscillator.

[0027] The power function circuit includes: an enable input port 101 and an internal drive timing sending port 102.

[0028] The driving circuit includes: a driving control signal receiving port 103 and a driving output port 104 . Figure 1 The controller generates a control signal with a certain duty cycle at the output port Q of the RS trigger. The control signal does not have the ability to drive the power tube to turn on and off, so it needs to pass through the drive circuit to amplify the driving ability before the power tube can be turned on and off. The simplest drive circuit can be composed of a group of non-gates connected in series with step-by-step amplification of the driving ability. Of course, in order to improve the reliability of the power supply, various protection functions are often added to the power supply chip to improve the control process of the power supply. The drive circuit also has functions such as limiting the maximum driving voltage to protect the power tube. These are achievable by those skilled in the art, and this embodiment will not be repeated for a specific power supply implementation method.

[0029] The mode selection circuit includes: a mode selection input signal port 105 , an internal drive timing receiving port 106 , a drive control signal sending port 107 , and an external drive timing receiving and sending port 108 .

[0030] The integrated power controller 1 includes: a MODE pin, a DORS pin and a DRN pin. The MODE pin is the mode selection pin of the integrated power controller 1, and the DORS pin is the external drive timing receiving and transmitting pin of the integrated power controller 1. The integrated power controller 1 can be placed in the master control mode or the slave control mode through the MODE pin.

[0031] The enable input port 101 is connected to the mode selection input signal port 105, and is also connected to the MODE pin of the integrated power controller; the internal drive timing sending port 102 is connected to the internal drive timing receiving port 106; the drive control signal receiving port 103 is connected to the drive control signal sending port 107; the drive output port 104 is connected to the gate of the power MOS tube NMO; the drain of the power MOS tube NMO is connected to the DRN pin of the integrated power controller 1; the external drive timing transceiver port 108 is connected to the DORS pin of the integrated power controller 1.

[0032] When the integrated power controller 1 is in the master control mode, the DORS pin works in the mode of sending the driving timing signal, and the controller can be called the master controller. The master controller sends the same driving timing signal as the internal driving timing signal from the DORS pin, and the power MOS tube NMO of the master controller is turned on or off according to the internal driving timing signal. When the integrated power controller 1 is in the slave control mode, the DORS pin works in the mode of receiving the external driving control signal, and the controller can be called the slave controller. The slave controller receives the driving timing signal from the external driving timing transceiver pin, and turns on or off the power MOS tube NMO according to the received external driving timing signal.

[0033] Master controller and slave controller are names for the same integrated power controller in different operating modes.

[0034] A main controller is used in a switching power supply to achieve maximum output power up to a standard power level.

[0035] A master controller is used in parallel with one or more slave controllers. The maximum power level that can be achieved is the sum of the number of master controllers and slave controllers.

[0036] The method of parallel use is as follows:

[0037] The power MOS tube NMO in the integrated power controller 1 working in the master control mode is switched according to the internal driving timing provided by its own power function circuit, that is, the internal driving timing receiving port 106 of the mode selection circuit receives the internal driving timing signal from the inside of its own chip, and turns on or off the power MOS tube NMO according to the internal driving timing signal, and also outputs the same driving timing signal from the DORS pin.

[0038] The power MOS tube NMO in the integrated power controller 1 working in the slave mode is not switched according to its own internal drive timing, but is switched according to the drive timing signal provided by the master controller, that is, the external drive timing transceiver port 108 of the mode selection circuit receives the external drive timing signal output from the monolithic integrated power controller working in the master mode, and turns on or off the power MOS tube according to the external drive timing signal. As long as the DORS pin of the integrated power controller working in the master mode and the DORS pin of the integrated power controller working in the slave mode are connected together, the drive timing signal can be transmitted. The DRN pin of the integrated power controller working in the slave mode is connected to the DRN pin of the integrated power controller working in the master mode to complete the parallel connection.

[0039] The mode selection circuit includes: a NAND gate NAND1, a NAND gate NAND2, a NAND gate NAND3, a NOT gate NOT and a selection switch 2.

[0040] One of the input ports of the NAND gate NAND1 is connected to the first port of the selection switch and serves as the internal drive timing receiving port 106 of the mode selection circuit. The other input port of the NAND gate NAND1 is connected to the control port of the selection switch and the input port of the NOT gate NOT and serves as the mode selection input signal port 105 of the mode selection circuit.

[0041] One input port of the NAND gate NAND2 is connected to the output port of the NOT gate NOT, and the other input port of the NAND gate NAND2 is connected to the second port of the selection switch 2 and serves as the external driving timing transceiver port 108 of the mode selection circuit.

[0042] Two input ports of the NAND gate NAND3 are connected to the output ports of the NAND gate NAND2 and the NAND gate NAND1 respectively, and the output port of the NAND gate NAND3 serves as a driving control signal sending port 107 of the mode selection circuit.

[0043] The internal drive signal received by the mode selection input signal port of the mode selection circuit can be a high level, and the external drive signal received can be a low level. Of course, the internal drive signal can also be defined as a low level and the external drive signal can be defined as a high level. The following explains the working principle of the mode selection circuit with the internal drive signal being a high level and the external drive signal being a low level.

[0044] The working principle of the mode selection circuit is as follows:

[0045] When the mode selection input signal port 105 is at a high level, no matter whether the external drive timing transceiver port 108 is at a high level or a low level logic, the output of the NAND gate NAND2 is at a high level; the signal of the internal drive timing receiving port 106 is output from the drive control signal sending port 107 after two negation operations by the NAND gates NAND1 and NAND3. It can be seen that when the mode selection input signal port 105 is at a high level, the logic signal from the drive control signal sending port 107 is the same as that of the internal drive timing receiving port 106, that is, the power MOS tube NMO is driven according to the internal drive timing. At the same time, under the high level of the mode selection input signal port 105, the selection switch is closed, then the external drive timing transceiver port 108 is connected to the internal drive timing signal, and the internal drive timing signal is sent from the external drive timing transceiver port 108, and the external drive timing transceiver port 108 is also the port for sending the internal drive timing outward.

[0046] When the mode selection input signal port 105 is at a low level, no matter whether the internal drive timing receiving port 106 is at a high level or a low level logic, the output of the NAND gate NAND1 is at a high level; the signal of the external drive timing transceiver port 108 is output from the drive control signal sending port 107 after two negation operations by the NAND gates NAND2 and NAND3. It can be seen that when the mode selection input signal port 105 is at a low level, the logic signal of the drive control signal sending port 107 is the same as that of the external drive timing transceiver port 108, that is, the power MOS tube NMO is driven according to the external drive timing, and this external drive timing is received from the external drive timing transceiver port 108, because the selection switch is disconnected under the low level of the mode selection input signal port 105, cutting off the connection relationship between the external drive timing transceiver port 108 and the internal drive timing signal, so that the external drive timing transceiver port 108 is in a working state of receiving the external drive timing.

[0047] The integrated power controller works as follows:

[0048] If the MODE pin inputs a high level, the integrated power controller operates in the master control mode. In the master control mode, the power function circuit operates normally. According to the working principle of the mode selection circuit, the signal of the drive control signal sending port 107 is the same as the internal drive timing receiving port 106, so the drive circuit drives the power MOS tube NMO according to the internal drive timing provided by the power function circuit; at the same time, the internal drive timing signal of the integrated power controller in the master control mode is sent from the external drive timing receiving port 108.

[0049] If the MODE pin inputs a low level, the integrated power controller is in the slave control mode. In the slave control mode, the power function circuit can be turned off to save power consumption, and it no longer outputs the internal drive control signal. The mode selection circuit selects the signal from the DORS pin as the output drive timing of the mode selection circuit. According to the working principle of the mode selection circuit, the signal of the drive control signal sending port 107 is the same as the signal of the external drive timing transceiver port 108, so the drive circuit drives the power MOS tube NMO according to the external drive timing signal from the external drive timing transceiver port 108.

[0050] Figure 2 The figure shows the application of a single-stage integrated power controller. At this time, a positive voltage is applied to the MODE pin, and it is in the master mode, which can realize complete switching power supply control and achieve the purpose of stabilizing the power supply output voltage. According to the principle of the master mode, the internal drive timing signal is sent at the DORS pin of the integrated power controller, but it is a single-stage application and does not serve as an external drive timing signal from the controller.

[0051] Figure 4 The schematic diagram of the integrated power controller of the present invention being used in parallel to expand the power level. The integrated power controller working in the master control mode has its MODE pin connected to a positive voltage, so that its internal power function circuit works normally, stabilizes the power output voltage, and provides a driving timing signal from the DORS pin of the master controller.

[0052] The MODE pin of the integrated power controller working in the slave mode is grounded, and the DORS pin of the integrated power controller working in the master mode is connected to the DORS pin of the integrated power controller working in the slave mode. The DORS pin of the integrated power controller working in the slave mode receives the driving timing signal from the master controller, so the slave controller is driven according to the driving timing signal provided by the master controller. The DRN pin of the integrated power controller working in the slave mode is connected to the DRN pin of the integrated power controller working in the master mode, so that the power tubes of the two controllers are driven according to the timing of the master controller. The parallel connection of the power tubes reduces the parallel resistance of the power tubes by half, so the actual current passing through the transformer is twice that of the master controller, and the power level is doubled.

[0053] According to the above principle, it is easy to deduce that as long as multiple slave controllers are connected in parallel, applications with higher power levels can be met, so users can design according to specific needs, which is flexible and convenient. Since the power tubes of each integrated power controller are separated on different chips and packages, rather than the total area of ​​several power tubes integrated on the silicon substrate of the same chip, a large amount of charge will be injected into the silicon substrate, causing abnormal operation of the control circuit on the same substrate.

[0054] The integrated power supply controller provided by the present invention realizes the expansion of power levels. One chip can realize switching power supplies with multiple output powers, which not only saves the development costs and subsequent product management costs of chip manufacturers, but also provides users with the autonomy to design according to specific needs, and the power supply performance is better. To design a chip with higher power, the chip cannot use the commonly used package. Customized packaging involves cooperation in the industrial chain, with a long development cycle and high costs. Large-area power tubes are concentrated inside the chip, which will inject a large amount of switching noise, which is more likely to affect the normal operation of the functional circuit. The controller provided by the present invention greatly reduces this problem through package isolation.

[0055] Those skilled in the art will also appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the embodiments herein can all be implemented as electronic hardware, computer software, or a combination thereof. In order to clearly illustrate the interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above around their functions. Whether such functions are implemented as hardware or software depends on specific applications and the design constraints imposed on the entire system. A skilled person can implement the described functions in an alternative manner for each specific application, but such implementation decisions should not be interpreted as departing from the scope of protection of the present disclosure.

Claims

1. A switching power supply that achieves power level expansion by using controllers in parallel, characterized in that: include: At least one integrated power controller, the integrated power controller operating in the slave control mode is connected in parallel with the integrated power controller operating in the master control mode; The integrated power supply controller comprises: a mode selection circuit; When the mode selection input signal port of the mode selection circuit receives a high level, the internal drive timing receiving port of the mode selection circuit receives the internal drive timing signal from the internal chip of the mode selection circuit, and turns on or off the power MOS tube according to the internal drive timing signal; When the mode selection input signal port of the mode selection circuit receives a low level, the external drive timing transceiver port of the mode selection circuit receives an external drive timing signal output from the integrated power supply controller working in the master control mode, and turns on or off the power MOS tube according to the external drive timing signal; The mode selection circuit includes: a NAND gate NAND1, a NAND gate NAND2, a NAND gate NAND3, a NOT gate NOT and a selection switch; One of the input ports of the NAND gate NAND1 is connected to the first port of the selection switch and serves as the internal driving timing receiving port of the mode selection circuit, and the other input port of the NAND gate NAND1 is respectively connected to the control port of the selection switch and the input port of the NOT gate NOT and serves as the mode selection input signal port of the mode selection circuit; One of the input ports of the NAND gate NAND2 is connected to the output port of the NOT gate NOT, and the other input port of the NAND gate NAND2 is connected to the second port of the selection switch and serves as an external driving timing receiving and transmitting port of the mode selection circuit; One input port of the NAND gate NAND3 is connected to the output port of the NAND gate NAND2, another input port of the NAND gate NAND3 is connected to the output port of the NAND gate NAND1, and the output port of the NAND gate NAND3 serves as a driving control signal sending port of the mode selection circuit.

2. The switching power supply for realizing power level expansion by using controllers in parallel according to claim 1, characterized in that: The integrated power supply controller also includes: a power supply function circuit and a drive circuit; an internal drive timing sending port of the power supply function circuit is connected to an internal drive timing receiving port of the mode selection circuit, a drive control signal sending port of the mode selection circuit is connected to a drive control signal receiving port of the drive circuit, and a drive output port of the drive circuit is connected to a gate of the power MOS tube; the internal drive timing signal is generated by the power supply function circuit, and the internal drive timing signal turns on or off the power MOS tube through the drive circuit.

3. The switching power supply for realizing power level expansion by using controllers in parallel according to claim 2, characterized in that: The integrated power controller includes: a MODE pin, a DORS pin and a DRN pin; the MODE pin is connected to the mode selection input signal port of the mode selection circuit and the enable input port of the power function circuit to receive the mode selection signal from outside the integrated power controller; the DORS pin is connected to the external drive timing transceiver port of the mode selection circuit to receive or send the external drive timing signal; the DRN pin is connected to the drain of the power MOS tube to output voltage.

4. The switching power supply for realizing power level expansion by using controllers in parallel according to claim 3, characterized in that: The DORS pin of the integrated power controller working in the slave mode is connected to the DORS pin of the integrated power controller working in the master mode, and the DRN pin of the integrated power controller working in the slave mode is connected to the DRN pin of the integrated power controller working in the master mode.

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