Semiconductor device, semiconductor package, semiconductor module and semiconductor circuit device

Abstract

The present invention provides a semiconductor device, a semiconductor package, a semiconductor module and a semiconductor circuit device capable of appropriately detecting temperature. The semiconductor device comprises a semiconductor substrate provided with a transistor portion and a diode portion, and the semiconductor device comprises: a temperature detection portion provided above the upper surface of the semiconductor substrate and having a long side in a predetermined long side direction; an upper surface electrode provided above the upper surface of the semiconductor substrate; and one or more external wirings, which include a connection portion connected to the upper surface electrode, and electrically connect the upper surface electrode to an external circuit of the semiconductor device, wherein the temperature detection portion is arranged in a manner that extends over one or more transistor portions and one or more diode portions in the long side direction, and when viewed from above, at least one connection portion of the external wiring is arranged around the temperature detection portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a semiconductor package, a semiconductor module and a semiconductor circuit device. Background Art

[0002] Conventionally, there is known a structure in which a semiconductor chip in which a transistor such as an insulated gate bipolar transistor (IGBT) and a diode such as a freewheeling diode FWD are provided on the same semiconductor substrate has a temperature detection element for detecting the chip temperature (for example, see Patent Document 1). In addition, there is known a water-cooled semiconductor module including a transistor such as an IGBT (for example, Patent Document 2).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2008-235405

[0004] Patent Document 2: Japanese Patent Application Publication No. 2017-183530 Summary of the invention

[0005] Technical issues

[0006] In the semiconductor devices described above, improvements in product performance are expected. For example, it is desired that the temperature detection element can detect the chip temperature more appropriately.

[0007] Technical Solution

[0008] In order to solve the above-mentioned problems, in one embodiment of the present invention, a semiconductor device having a semiconductor substrate is provided. The semiconductor device may include a transistor portion provided on the semiconductor substrate. The semiconductor device may include a diode portion provided on the semiconductor substrate and alternately arranged with the transistor portion in an arrangement direction parallel to the upper surface of the semiconductor substrate. The semiconductor device may include a temperature detection portion provided above the upper surface of the semiconductor substrate and having a long side in a predetermined long side direction. The semiconductor device may include an upper surface electrode provided above the upper surface of the semiconductor substrate. The semiconductor device may include one or more external wirings including a connection portion connected to the upper surface electrode, electrically connecting the upper surface electrode to an external circuit of the semiconductor device. The temperature detection portion may be arranged in a manner that extends over one or more transistor portions and one or more diode portions in the long side direction. When viewed from above, the connection portion of at least one external wiring may be arranged around the temperature detection portion.

[0009] At least one connection portion of the external wiring may be arranged above the one or more transistor portions and above the one or more diode portions.

[0010] When the length of the temperature detection portion in the longitudinal direction is defined as the detection portion length, the distance between the connection portion of at least one external wiring and the temperature detection portion in a plan view may be less than or equal to the detection portion length.

[0011] The diode units may be arranged at a predetermined arrangement period in the arrangement direction. In a plan view, a distance between a connection portion of at least one external wiring and the temperature detection unit may be less than or equal to 5 times the arrangement period.

[0012] The external wiring may be a wire. A plurality of external wirings may be connected to the upper surface electrode. For at least two external wirings, when viewed from above, the distance between the connection portion and the temperature detection portion may be less than 5 times the periodicity of the arrangement. The temperature detection portion may be configured in a manner such that it is sandwiched between any two connection portions whose distance is less than 5 times the periodicity of the arrangement when viewed from above.

[0013] When the long side length of the connection portion of the external wiring in plan view is defined as the connection portion length, the distance between the connection portion of at least one external wiring in plan view and the temperature detection portion may be less than the connection portion length.

[0014] A plurality of external wirings are connected to the upper surface electrode, and the connection portions of the external wirings can be arranged at a predetermined wiring interval in a direction perpendicular to the long side direction. The distance between the connection portion of at least one external wiring and the temperature detection unit when viewed from above can be less than the wiring interval.

[0015] In a plan view, at least one connection portion of the external wiring may be provided so as to face the temperature detection portion in a direction perpendicular to the longitudinal direction.

[0016] In a plan view, the two connection portions may be arranged around the temperature detection portion and in a direction parallel to the longitudinal direction of the temperature detection portion. The two connection portions may be arranged to face a portion of the longitudinal direction of the temperature detection portion.

[0017] The plurality of connection portions may be arranged around the temperature detection unit in a plan view. The temperature detection unit may be arranged inside a rectangular region circumscribing the plurality of connection portions in a plan view.

[0018] In a plan view, the connection portions of the plurality of external wirings may be arranged more around the temperature detection portion than in areas other than the area around the temperature detection portion.

[0019] The external wiring may be a lead frame.

[0020] The connection portion of the external wiring may include two first portions arranged in a direction perpendicular to the longitudinal direction of the temperature detection portion with the temperature detection portion sandwiched therebetween. The connection portion of the external wiring may include a second portion connecting the two first portions.

[0021] The semiconductor device may include a temperature detection wiring provided above the upper surface of the semiconductor substrate and connected to the temperature detection unit. In a plan view, the second portion of the connection portion may be arranged on the opposite side of the temperature detection wiring with respect to the temperature detection unit.

[0022] The semiconductor device may include a gate pad disposed above the upper surface of the semiconductor substrate and connected to the gate electrode of the transistor portion. The semiconductor device may include a temperature detection wiring disposed above the upper surface of the semiconductor substrate and connected to the temperature detection portion. When viewed from above, the gate pad may be arranged on the opposite side of the temperature detection wiring with respect to the temperature detection portion.

[0023] The semiconductor device may include a cathode pad and an anode pad provided above the upper surface of the semiconductor substrate and connected to the temperature detection wiring. The cathode pad and the anode pad may be arranged on the opposite side of the gate pad with respect to the temperature detection unit.

[0024] In a second aspect of the present invention, there is provided a semiconductor package including the semiconductor device according to the first aspect and an external circuit.

[0025] A semiconductor package may include two semiconductor devices. Each semiconductor device may have a gate pad disposed above the upper surface of a semiconductor substrate and connected to a gate electrode of a transistor portion. Each semiconductor device may have a temperature detection wiring disposed above the upper surface of a semiconductor substrate and connected to a temperature detection portion. Each semiconductor device may have a cathode pad and an anode pad disposed above the upper surface of a semiconductor substrate and connected to the temperature detection wiring. The gate pad may be disposed on the opposite side of the temperature detection wiring when viewed from above, with the temperature detection portion as a reference. The cathode pad and the anode pad may be disposed on the opposite side of the gate pad, with the temperature detection portion as a reference. In each semiconductor device, when the end edge closest to the gate pad among the end edges when viewing the semiconductor substrate from above is set as the gate pad end edge, the two semiconductor devices may be disposed in a manner such that the gate pad end edges are opposed to each other.

[0026] In a second aspect of the present invention, a semiconductor module is provided. The semiconductor module includes a housing having a control terminal and two semiconductor devices arranged inside the housing and connected in parallel. The two semiconductor devices each include a detection unit. The housing includes a cooling unit for allowing a refrigerant to flow in a predetermined flow direction. The detection unit of the semiconductor device arranged on one side of the flow direction is connected to the control terminal, and the detection unit of the semiconductor device arranged on the other side of the flow direction is not connected to the control terminal.

[0027] The detection unit may be a temperature detection unit. The detection unit may be a sensing semiconductor element unit that detects current.

[0028] The housing may have a refrigerant inlet for introducing the refrigerant and a refrigerant outlet for discharging the refrigerant. The side close to the refrigerant outlet is one side of the flow path direction, and the side close to the refrigerant inlet is the other side of the flow path direction.

[0029] The semiconductor device disposed on one side in the flow path direction may have a detection pad connected to the detection unit, while the semiconductor device disposed on the other side in the flow path direction may not have a detection pad on the surface of the semiconductor device.

[0030] Each of the two semiconductor devices may include an emitter electrode. The detection portion of the semiconductor device disposed on the other side in the flow path direction may be covered by the emitter electrode of the semiconductor device.

[0031] A plurality of wiring patterns on which two semiconductor devices are arranged may be provided. The plurality of control terminals may be arranged in parallel on one side in the flow path direction.

[0032] The two semiconductor devices may include a transistor portion and a gate pad connected to a gate electrode of the transistor portion. The two semiconductor devices may be arranged in parallel in the flow path direction. A gate terminal may be provided between the two semiconductor devices in the flow path direction. The gate pads of the two transistor portions may be connected to the gate terminals, respectively.

[0033] The gate pad of one semiconductor device and the gate pad of another semiconductor device may be arranged to face each other.

[0034] The active portion areas of the two semiconductor devices may be the same.

[0035] In a third aspect of the present invention, a semiconductor module is provided. The semiconductor module includes: a plurality of wiring patterns; a semiconductor device disposed on the wiring patterns and having a plated surface; and a lead frame having one end bonded to the surface of the semiconductor device and the other end bonded to the wiring pattern. The lead frame may include a bridge portion protruding to a side away from the surface of the semiconductor device, an opening portion provided in the bridge portion, and a mold portion disposed above and below the bridge portion.

[0036] The bridge portion may be provided between the one end and the other end. A plurality of opening portions may be provided.

[0037] The semiconductor device may include a temperature detection portion above the upper surface of the semiconductor substrate, and the lead frame may be bonded to the surface of the semiconductor device via the temperature detection portion.

[0038] In a fourth aspect of the present invention, a semiconductor device is provided. The semiconductor device may include: a main semiconductor element portion, which is provided on a semiconductor substrate and includes a transistor portion and a diode portion; a sensing semiconductor element portion, which includes another transistor portion, which is provided on the semiconductor substrate and is different from the transistor portion, and another diode portion, which is different from the diode portion and is arranged on the inner side of the other transistor portion; a current detection circuit, which detects a forward current and a reverse current of the sensing semiconductor element portion; and a gate drive circuit, which outputs a signal according to the value of the reverse current.

[0039] It should be noted that the above summary of the invention does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups may also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 Schematic diagram showing the structure of the upper surface of the semiconductor device 100 according to one embodiment of the present invention.

[0041] Figure 2 Yes Figure 1 An enlarged view of the vicinity of area A in FIG.

[0042] Figure 3 Yes means Figure 2 FIG. 1 is an example of a BB cross section.

[0043] Figure 4 FIG. 1 is a diagram showing another example of the top surface structure of the semiconductor device 100 .

[0044] Figure 5 1 is a diagram showing an example of the relationship between the temperature detection unit 110 and the connection portion 132 .

[0045] Figure 6 1 is a diagram showing another example of the relationship between the temperature detection unit 110 and the connection portion 132 .

[0046] Figure 7 1 is a diagram showing another example of the relationship between the temperature detection unit 110 and the connection portion 132 .

[0047] Figure 8 1 is a diagram showing a configuration example of the temperature detection unit 110 on the XY plane.

[0048] Fig. 9 is a schematic diagram showing another structure of the upper surface of the semiconductor device 100 .

[0049] Fig.10 It is a diagram showing the arrangement of the first portion 136 or the second portion 138 of a comparative example.

[0050] Fig.11is a schematic diagram showing another structure of the upper surface of the semiconductor device 100 .

[0051] Fig.12 FIG. 2 is a diagram showing an example of a semiconductor package 200 according to an embodiment of the present invention.

[0052] Fig.13 This is a diagram showing an example of the upper surface of a semiconductor module 400 according to an embodiment of the present invention.

[0053] Fig.14 Yes means Fig.13 FIG. 1 is a diagram of an example of an E-E' section.

[0054] Fig.15 This is a schematic circuit diagram showing the connection relationship between the upper arm and the lower arm of the semiconductor module including one embodiment of the present invention.

[0055] Fig.16 This is a diagram showing an example of the upper surface of the semiconductor module 300 according to the embodiment of the present invention.

[0056] Fig.17 This is a diagram showing an example of the back surface of a semiconductor module 300 according to an embodiment of the present invention.

[0057] Fig.18 Yes means Fig.16 as well as Fig.17 FIG. 1 is a diagram of an example of a CC' cross section.

[0058] Fig.19 Yes means Fig.16 as well as Fig.17 FIG. 1 is a diagram of an example of a D-D' section.

[0059] Fig. 20 FIG. 1 is a diagram showing another example of the structure of the upper surface of the semiconductor device 100 according to the embodiment of the present invention.

[0060] Fig.21 1 is a schematic circuit diagram of a semiconductor circuit device 500 according to an embodiment of the present invention.

[0061] Fig. 22 yes Fig. 20 An enlarged view of the vicinity of the sensing semiconductor element portion 124 in FIG.

[0062] Fig.23 yes Fig. 20 Another enlarged view of the vicinity of the sensing semiconductor element portion 124 in FIG.

[0063] Fig.24 Yes means Fig.21FIG. 1 is a diagram showing the relationship between the voltage Vce and the current Ic of the semiconductor device 100 .

[0064] Fig.25 Yes means Fig.21 FIG. 1 is a graph of current sensing characteristics of the semiconductor device 100 shown.

[0065] Fig.26 Yes means Fig.16 The illustrated semiconductor module 300 is a view of the vicinity of the circuit substrate 162 disposed on the most negative side in the Y-axis direction.

[0066] Fig. 27 It is expressed according to the position on the X-axis. Fig.26 A graph showing the temperature of the refrigerant in the semiconductor module 300 is shown.

[0067] Explanation of symbols

[0068] 10…semiconductor substrate, 11…well region, 12…emitter region, 14…base region, 15…contact region, 16…accumulation region, 18…drift region, 20…buffer region, 21…upper surface, 22…collector region, 23…lower surface, 24…collector electrode, 25…connecting portion, 29…straight portion, 30…dummy portion, 31…front end portion, 32…dummy insulating film, 34…dummy conductive portion, 38…interlayer insulating film, 39…straight portion, 40…gate trench portion, 41…front end portion, 42…gate insulating film, 44…gate conductive portion, 48…gate flow channel, 49…contact hole, 50…gate flow channel, 51…gate flow channel, 52…emitter electrode, 53…solder layer, 54… contact hole, 56…contact hole, 60…mesa portion, 63…side wall, 70…transistor portion, 71…transistor portion, 80…diode portion, 81…diode portion, 82…anode region, 84…through hole, 86…main terminal, 88…housing, 90…edge terminal structure portion, 92…guard ring, 93…recessed portion, 94…bottom surface, 95…cooling fin, 96…relay terminal, 97…refrigerant inlet, 98…refrigerant outlet, 99…control terminal, 100…semiconductor device, 108…detection portion, 110…temperature detection portion, 112…temperature detection wiring, 114…cooling portion, 115…dummy gate pad, 116…gate pad, 117… Gate pad end, 118… cathode pad, 119… anode pad, 120… active portion, 122… sensing emitter pad, 124… sensing semiconductor element portion, 125… main semiconductor element portion, 126… detection pad, 130… external wiring, 131… wiring, 132… connection portion, 133… connection portion, 134… lead frame, 136… first portion, 137… wiring, 138… second portion, 139… wiring, 140… outer peripheral end, 141… region, 142… foot portion, 144… bridge portion, 146… region, 147… straight line, 148… protective film, 149… interface, 152… N-type region, 153… wiring , 154…P-type region, 155, 157…metal layer, 162…circuit substrate, 164…wiring pattern (gate terminal), 166…wiring pattern, 168…wiring pattern, 169…wiring pattern, 170…wiring pattern, 172…control circuit, 178…lead frame, 180…first contact portion, 182…second contact portion, 184…bridge portion, 186…leg portion, 188…leg portion, 190…opening portion, 192…molding portion, 198…lead portion, 200…semiconductor package, 210…temperature detection circuit, 220…current detection circuit, 300…semiconductor module, 400…semiconductor module, 500…semiconductor circuit device DETAILED DESCRIPTION

[0069] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0070] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the mounting direction on a substrate when mounting a semiconductor device.

[0071] In this specification, technical contents are sometimes described using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the upper surface of a semiconductor substrate is defined as an XY plane, and a depth direction perpendicular to the upper surface of the semiconductor substrate is defined as a Z axis.

[0072] In each embodiment, an example is shown in which the first conductivity type is set to N type and the second conductivity type is set to P type, but it is also possible to set the first conductivity type to P type and the second conductivity type to N type. In this case, the conductivity types of the substrate, layer, region, etc. of each embodiment are respectively opposite in polarity. In addition, in this specification, the case described as P+ type (or N+ type) means that the doping concentration is higher than that of P type (or N type), and the case described as P- type (or N- type) means that the doping concentration is lower than that of P type (or N type).

[0073] In this specification, the doping concentration refers to the concentration of the donor or acceptor impurities. In this specification, the difference between the concentrations of the donor and the acceptor is sometimes referred to as the doping concentration. In addition, sometimes the peak value of the doping concentration distribution in the doping region is referred to as the doping concentration in the doping region.

[0074] Figure 1 1 is a diagram showing the structure of the upper surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate.

[0075] In this specification, the end of the outer periphery of the semiconductor substrate 10 when viewed from above is referred to as the outer periphery end 140. When viewed from above, it means the case of observing in parallel with the Z axis from the upper surface side of the semiconductor substrate 10. In addition, the direction parallel to one end side of the outer periphery end 140 of the semiconductor substrate 10 when viewed from above is referred to as the X-axis direction, and the direction perpendicular to the end side is referred to as the Y-axis direction.

[0076] The semiconductor device 100 includes an active portion 120 and an edge termination structure portion 90. The active portion 120 is a region where current flows along the depth direction inside the semiconductor substrate 10 from the upper surface to the lower surface, or from the lower surface to the upper surface. For example, the active region is a region where the main current flows between the upper surface and the lower surface of the semiconductor substrate 10 when the transistor element included in the semiconductor device 100 is controlled to be in the on state, or when the transistor element is switched from the on state to the off state. The active portion 120 may refer to a region surrounded by the gate flow channel 50 described later.

[0077] The active portion 120 includes a transistor portion 70 and a diode portion 80. In this specification, the transistor portion 70 and the diode portion 80 are sometimes referred to as element portions or element regions, respectively. In this example, the transistor portion 70 and the diode portion 80 are alternately provided in the active portion 120 along the X-axis direction.

[0078] A plurality of pads ( Figure 1 In the example of FIG. 1 , the gate pad 116, the cathode pad 118, the anode pad 119, and the sensing emitter pad 122 are connected to the emitter electrode arranged above the upper surface of the semiconductor substrate 10. The gate pad 116 is connected to the gate electrode of the transistor unit 70. The cathode pad 118 and the anode pad 119 are connected to the temperature detection unit 110 described later. It should be noted that the number and type of pads provided on the semiconductor substrate 10 are not limited to Figure 1 Example shown.

[0079] Each pad is formed of a metal material such as aluminum. The plurality of pads in this example are arranged along any end side of the upper surface of the semiconductor substrate 10 in a predetermined arrangement direction (eg, X-axis direction or Y-axis direction).

[0080] The semiconductor device 100 includes a gate flow channel 50 for transmitting a gate voltage to the transistor portion 70. As an example, the gate flow channel 50 is provided above the upper surface of the semiconductor substrate 10 and is insulated from the upper surface of the semiconductor substrate 10 by an interlayer insulating film.

[0081] When viewed from above, the gate flow channel 50 is arranged in a manner passing through the end edge of the semiconductor substrate 10 and between each pad. The gate flow channel 50 of this example passes between each pad of the gate pad 116, the cathode pad 118, the anode pad 119 and the sense emitter pad 122 and the end edge closest to these pads and is arranged parallel to the end edge. The gate flow channel 50 is connected to the gate pad 116. In addition, the gate flow channel 50 is arranged in a manner surrounding the active part 120 between the other end edge of the semiconductor substrate 10 and the active part 120. In other words, the gate flow channel 50 of this example is arranged in a ring shape along each end edge of the semiconductor substrate 10. The gate flow channel 50 can be a metal wiring such as aluminum, or a semiconductor wiring such as polysilicon doped with impurities, or a metal wiring and a semiconductor wiring can be arranged overlappingly with an insulating film. A contact hole for connecting the metal wiring and the semiconductor wiring is provided in the insulating film. The gate flow channel 50 of this example is a metal wiring.

[0082] The transistor section 70 includes a transistor such as an IGBT. The diode section 80 includes a diode such as a FWD. The diode section 80 is arranged with a predetermined arrangement period P1 in an arrangement direction parallel to the upper surface of the semiconductor substrate 10 (in this example, the X-axis direction), and is arranged alternately with the transistor section 70 in the X-axis direction.

[0083] In each diode portion 80 , an N+ type anode region is provided in a region in contact with the lower surface of the semiconductor substrate 10 . Figure 1 The diode portion 80 indicated by the solid line is a region where the anode region is provided on the lower surface of the semiconductor substrate 10. In the semiconductor device 100 of this example, the region other than the anode region in contact with the lower surface of the semiconductor substrate is a P+ type collector region.

[0084] The diode portion 80 is a region formed by projecting the anode region in the Z-axis direction. The transistor portion 70 is a region in which a collector region is formed on the lower surface of the semiconductor substrate 10 and a unit structure including an N+ type emitter region is periodically formed on the upper surface of the semiconductor substrate 10. The region obtained by extending the region in the active portion 120 in the Y-axis direction by projecting the anode region in the Z-axis direction can also be used as the diode portion 80. The region other than the diode portion 80 in the active portion 120 can be used as the transistor portion 70. The boundary between the diode portion 80 and the transistor portion 70 in the X-axis direction is the boundary between the anode region and the collector region.

[0085] The edge terminal structure 90 is provided between the gate flow channel 50 and the outer peripheral end 140 of the semiconductor substrate 10 on the upper surface of the semiconductor substrate 10. The edge terminal structure 90 can be arranged in a ring shape on the upper surface of the semiconductor substrate 10 so as to surround the gate flow channel 50. The edge terminal structure 90 of this example is arranged along the outer peripheral end 140 of the semiconductor substrate 10. The edge terminal structure 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge terminal structure 90 has, for example, a guard ring, a field plate, a surface electric field reduction (resurf), and a structure combining these.

[0086] The semiconductor device 100 includes a temperature detection portion 110 and a temperature detection wiring 112. The temperature detection portion 110 is disposed above the active portion 120. When viewed from the upper surface of the semiconductor substrate 10, the temperature detection portion 110 may be disposed at the center of the active portion 120. The temperature detection portion 110 has a long side in a predetermined long side direction. The long side direction in this example is the X-axis direction, but the long side direction may be different from the X-axis direction.

[0087] The temperature detection unit 110 is arranged in the long-side direction over one or more transistor units 70 and one or more diode units 80. In other words, a part of the temperature detection unit 110 is arranged above the transistor unit 70, and another part of the temperature detection unit 110 is arranged above the diode unit 80. The temperature detection unit 110 may be a PN type temperature sensing diode formed of single crystal silicon or polycrystalline silicon.

[0088] The temperature detection wiring 112 is provided above the active portion 120. The temperature detection wiring 112 may be a semiconductor wiring such as polysilicon to which impurities are added. The temperature detection wiring 112 is connected to the temperature detection portion 110. The temperature detection wiring 112 extends to the end of the active portion 120 on the upper surface of the semiconductor substrate 10, and is connected to the cathode pad 118 and the anode pad 119. By measuring the electrical characteristics of the temperature detection portion 110 via the cathode pad 118 and the anode pad 119, the temperature of the temperature detection portion 110 can be detected.

[0089] By configuring the temperature detection unit 110 to cover one or more transistor units 70 and one or more diode units 80, it is possible to detect the temperature corresponding to the heat generated by both the transistor unit 70 and the diode unit 80. Therefore, it is possible to accurately detect the temperature in either the state where the transistor unit 70 is operating or the state where the diode unit 80 is operating.

[0090] The length of the long side direction of the temperature detection portion 110, i.e., the detection portion length L1, is greater than the larger width of the diode portion 80 in the X-axis direction and the width of the transistor portion 70 in the X-axis direction. The detection portion length L1 of the temperature detection portion 110 may be greater than the arrangement period P1 of the diode portion 80 (i.e., the sum of the width of the diode portion 80 and the width of the transistor portion 70). The detection portion length L1 of the temperature detection portion 110 may be less than 3 times or less than 2 times the arrangement period P1.

[0091] The semiconductor device 100 includes an upper surface electrode provided above the upper surface of the semiconductor substrate 10. Figure 1 The semiconductor device 100 includes one or more external wirings 130 that electrically connect the upper surface electrode to an external circuit of the semiconductor device 100. As an example, the external wiring 130 is a wire formed of a conductive material such as a metal, but the external wiring 130 may not be a wire. The external wiring 130 has a connection portion 132 connected to the upper surface electrode. The connection portion 132 refers to an area where the external wiring 130 contacts the upper surface electrode.

[0092] In a plan view, at least one connection portion 132 of the external wiring 130 is disposed around the temperature detection unit 110. The connection portion 132 being disposed around the temperature detection unit 110 means that the connection portion 132 satisfies at least one of the following conditions in a plan view.

[0093] (1) The distance D1 between the connection portion 132 and the temperature detection unit 110 is equal to or less than 5 times the arrangement period P1.

[0094] (2) The distance D1 between the connection portion 132 and the temperature detection unit 110 is equal to or less than the detection unit length L1.

[0095] (3) The distance D1 between the connection portion 132 and the temperature detection unit 110 is equal to or less than the length of the connection portion 132 in the longitudinal direction, that is, the connection portion length L2.

[0096] (4) The distance D1 between the connection portion 132 and the temperature detection unit 110 is equal to the wiring interval L3 (see Figure 4 )the following.

[0097] The connection portion 132 disposed around the temperature detection unit 110 may satisfy two or more of the above conditions (1) to (4), three or more of the above conditions, or all of the above conditions. In addition, other numerical ranges described in this specification may be used as numerical ranges for each condition.

[0098] exist Figure 1In the example, a distance D1 between the connection portion 132 of at least one external wiring 130 and the temperature detection unit 110 is less than or equal to 5 times the arrangement period P1 in a plan view. Figure 1 In the example of FIG. 1 , only the connection portion 132 that satisfies this condition is shown. In this specification, the connection portion of the external wiring 130 other than the connection portion 132 is referred to as the connection portion 133 (for example, see Figure 4 In other words, the connection portion disposed around (in other words, near) the temperature detection unit 110 is referred to as the connection portion 132 , and the connection portion not disposed around (in other words, near) is referred to as the connection portion 133 .

[0099] By arranging the connection portion 132 near the temperature detection portion 110, the temperature detection portion 110 can also detect the temperature corresponding to the heat generated in the connection portion 132. Therefore, the temperature of the semiconductor device 100 can be detected with better accuracy. The distance D1 between the connection portion 132 and the temperature detection portion 110 in condition (1) can be less than 3 times the arrangement period P1, or less than 2 times. The distance D1 can be more than 1 times the arrangement period P1.

[0100] The distance D1 between the connection portion 132 and the temperature detection unit 110 may be the shortest distance between the ends of the connection portion 132 and the ends of the temperature detection unit 110 in a plan view.

[0101] In addition, a plurality of connection portions 132 may be provided on the upper surface of the semiconductor substrate 10. Figure 1 In the example of FIG. 1 , connection parts 132 - 1 , 132 - 2 , 132 - 3 , and 132 - 4 are provided.

[0102] At least a portion of the plurality of connection portions 132 may be disposed opposite to the temperature detection unit 110 in the Y-axis direction. Thus, the long side of the temperature detection unit 110 is easily subjected to heat from the connection portion 132, and the temperature corresponding to the heat generated in the connection portion 132 can be appropriately detected.

[0103] It should be noted that being arranged opposite to each other in the Y-axis direction means that at least a portion of the region overlaps in the X-axis direction. The connection portion 132 that is opposite to the temperature detection unit 110 in the Y-axis direction may also be arranged on both the positive side and the negative side of the Y-axis direction relative to the temperature detection unit 110. Figure 1In the example, the connection portion 132-1 and the connection portion 132-3 (or the connection portion 132-2 and the connection portion 132-4) are configured to be divided into the positive side in the Y-axis direction and the negative side in the Y-axis direction relative to the temperature detection unit 110. Thus, the temperature gradient of the temperature detection unit 110 in the Y-axis direction can be reduced, and the temperature can be detected with good accuracy.

[0104] As shown in condition (2), the distance D1 between at least one connection portion 132 and the temperature detection portion 110 may be less than the detection portion length L1. As shown in condition (3), the distance D1 between at least one connection portion 132 and the temperature detection portion 110 may also be less than the length in the long side direction of the connection portion 132, that is, the connection portion length L2. By arranging at least one connection portion 132 near the temperature detection portion 110 in a manner that satisfies at least one of these conditions, the temperature detection portion 110 can more appropriately detect the temperature.

[0105] In addition, at least one connection portion 132 may be disposed above one or more transistor portions 70 and one or more diode portions 80. Thus, it is possible to suppress uneven heat generation of the connection portion 132 due to the operating state of the semiconductor device 100.

[0106] In the following Figure 4 In the embodiment, the plurality of connection portions 132 and 133 are arranged at a predetermined wiring interval L3 in the Y-axis direction perpendicular to the long side direction (X-axis direction) of the connection portion, but when viewed from above, the plurality of connection portions can be arranged more around the temperature detection portion 110 than in the area other than the area around the temperature detection portion 110. For example, when compared under the same area, when viewed from above, the plurality of connection portions can be arranged more densely than in other cases when the distance D1 from the temperature detection portion 110 can be within a range of 5 times or less of the arrangement period P1 (i.e., the range that satisfies condition (1)). As the amount of connection portions arranged in each area, the number of connection portions can be used, or the area when the upper surface is observed can be used. In addition, when only comparing the range in which the distance D1 from the temperature detection portion 110 is 5 times or less of the arrangement period P1 when viewed from above and other ranges, the number or area of ​​the connection portions can be arranged more when the distance D1 is within a range of 5 times or less of the arrangement period P1. In addition, it can be configured so that the closer to the temperature detection portion 110, the higher the density of the plurality of connection portions. As the range around the temperature detection unit 110, a range that satisfies any one or more of the above conditions (1) to (4) can be used.

[0107] Figure 2 Yes Figure 1The semiconductor device 100 of this example includes a guard ring 92, a gate groove portion 40, a dummy portion 30, a P+ type well region 11, an N+ type emitter region 12, a P- type base region 14, and a P+ type contact region 15, which are arranged inside the semiconductor substrate 10 and exposed on the upper surface of the semiconductor substrate 10. In this specification, the gate groove portion 40 or the dummy portion 30 is sometimes simply referred to as a groove portion. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate channel 50 arranged above the upper surface of the semiconductor substrate 10. The emitter electrode 52 is an example of an upper surface electrode. The emitter electrode 52 and the gate channel 50 are arranged to be separated from each other.

[0108] The edge termination structure 90 is arranged outside the gate flow channel 50 (positive side in the Y-axis direction). As described above, the edge termination structure 90 may have one or more guard rings 92. The guard ring 92 is a P-type region formed inside the semiconductor substrate 10. The guard ring 92 is arranged in a ring shape around the active portion 120 outside the gate flow channel 50.

[0109] An interlayer insulating film is formed between the emitter electrode 52 and the gate runner 50 and the upper surface of the semiconductor substrate 10. Figure 2 In the interlayer insulating film of this example, contact holes 56, 49, and 54 are formed so as to penetrate the interlayer insulating film.

[0110] The emitter electrode 52 passes through the contact hole 54 to contact the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10. In addition, the emitter electrode 52 passes through the contact hole 56 to connect to the dummy conductive portion in the dummy portion 30. Between the emitter electrode 52 and the dummy conductive portion, a connecting portion 25 formed of a conductive material such as polysilicon doped with impurities may be provided. An insulating film such as an oxide film is formed between the connecting portion 25 and the upper surface of the semiconductor substrate 10.

[0111] The gate flow channel 50 passes through the contact hole 49 and contacts the gate flow channel 51. Figure 1 In the embodiment, the gate flow channel 51 is omitted. The gate flow channel 51 is connected to the gate trench portion 40. In other examples, the gate flow channel 50 and the gate trench portion 40 may be connected without the gate flow channel 51.

[0112] The gate channel 51 is formed of polysilicon doped with impurities or the like. The gate channel 51 is connected to the gate conductive portion in the gate groove portion 40 on the upper surface of the semiconductor substrate 10. The gate conductive portion is an example of a gate electrode in the transistor portion 70. The gate channel 51 is not connected to the dummy conductive portion in the dummy portion 30. The gate channel 51 of this example is formed from below the contact hole 49 to the front end portion 41 of the gate groove portion 40.

[0113] An insulating film such as an oxide film is formed between the gate flow channel 51 and the upper surface of the semiconductor substrate 10. The gate conductive portion is exposed from the upper surface of the semiconductor substrate 10 at the front end portion 41 of the gate groove portion 40. A contact hole connecting the gate conductive portion and the gate flow channel 51 is provided in the insulating film located above the gate conductive portion. Figure 2 In the embodiment, the emitter electrode 52 and the gate channel 51 overlap at a position in a plan view, but the emitter electrode 52 and the gate channel 51 are electrically insulated from each other via an insulating film (not shown).

[0114] The emitter electrode 52 and the gate runner 50 are formed of a material containing a metal. For example, at least a portion of each electrode is formed of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium, a titanium compound, etc. under the region formed of aluminum, etc., and may have a plug formed of tungsten, etc. in the contact hole.

[0115] One or more gate trench portions 40 and one or more dummy portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. In the transistor portion 70 of this example, one or more gate trench portions 40 and one or more dummy portions 30 are alternately formed along the arrangement direction.

[0116] The gate trench portion 40 of this example may include two straight portions 39 extending in a straight line along the long side direction (the Y-axis direction in this example) perpendicular to the arrangement direction and a front end portion 41 connecting the two straight portions 39. Preferably, at least a portion of the front end portion 41 is formed in a curved shape on the upper surface of the semiconductor substrate 10. By connecting the ends of the straight shape along the long side direction of the two straight portions 39 of the gate trench portion 40 to the front end portion 41, the electric field concentration at the ends of the straight portions 39 can be alleviated.

[0117] At least one dummy portion 30 is disposed between each straight portion 39 of the gate trench portion 40. These dummy portions 30 may have a straight portion 29 and a front end portion 31 similar to the gate trench portion 40. In other examples, the dummy portion 30 may have a straight portion 29 but not a front end portion 31. Figure 2 In the illustrated example, in the transistor portion 70 , the two straight line portions 29 of the dummy portion 30 are arranged between the two straight line portions 39 of the gate trench portion 40 .

[0118] In the diode portion 80 , a plurality of dummy portions 30 are arranged along the X-axis direction on the upper surface of the semiconductor substrate 10 . The shape of the dummy portions 30 in the diode portion 80 in the XY plane may be the same as that of the dummy portions 30 provided in the transistor portion 70 .

[0119] The front end 31 and the straight portion 29 of the dummy portion 30 have the same shape as the front end 41 and the straight portion 39 of the gate trench portion 40. The dummy portion 30 provided in the diode portion 80 and the straight dummy portion 30 provided in the transistor portion 70 may have the same length in the Y-axis direction.

[0120] The emitter electrode 52 is formed above the gate trench portion 40, the dummy portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 is provided in the XY plane, separated from the end portion of the contact hole 54 in the longitudinal direction on the side where the gate flow channel 50 is provided. The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy portion 30. A portion of the gate trench portion 40 and the dummy portion 30 on the gate flow channel 50 side is formed in the well region 11. The bottom of the front end portion 41 of the gate trench portion 40 and the bottom of the front end portion 31 of the dummy portion 30 in the Z-axis direction may be covered by the well region 11.

[0121] The transistor section 70 and the diode section 80 are each provided with one or more mesa portions 60 sandwiched between the trench portions. The mesa portion 60 is a region of the semiconductor substrate 10 sandwiched between the trench portions, which is located on the upper surface side of the deepest bottom of the trench portion.

[0122] The base region 14 is formed in the mesa portion 60 sandwiched between the trench portions. The base region 14 is of the second conductivity type (P-type) having a lower doping concentration than the well region 11 .

[0123] A contact region 15 of a second conductivity type having a higher doping concentration than the base region 14 is formed on the upper surface of the base region 14 of the mesa portion 60. The contact region 15 in this example is of P+ type. In the upper surface of the semiconductor substrate 10, the well region 11 can be formed separately from the contact region 15 disposed at the end in the Y-axis direction in the direction of the gate flow channel 50. In the upper surface of the semiconductor substrate 10, the base region 14 is exposed between the well region 11 and the contact region 15.

[0124] In the transistor portion 70, an emitter region 12 of a first conductivity type having a higher doping concentration than the drift region formed inside the semiconductor substrate 10 is selectively formed on the upper surface of the mesa portion 60-1. The emitter region 12 in this example is of N+ type. The portion of the base region 14 adjacent to the emitter region 12 in the depth direction (-Z-axis direction) of the semiconductor substrate 10 that is in contact with the gate groove portion 40 functions as a channel portion. If a conduction voltage is applied to the gate groove portion 40, a channel serving as an electron inversion layer is formed in the portion of the base region 14 disposed between the emitter region 12 and the drift region that is adjacent to the gate groove portion 40 in the Z-axis direction. By forming a channel in the base region 14, carriers flow between the emitter region 12 and the drift region.

[0125] In this example, base regions 14-e are arranged at both ends in the Y-axis direction of each mesa portion 60. In this example, on the upper surface of each mesa portion 60, a region adjacent to the base region 14-e on the center side of the mesa portion 60 is a contact region 15. In addition, a region in contact with the base region 14-e on the opposite side from the contact region 15 is a well region 11.

[0126] In the mesa portion 60-1 of the transistor portion 70 of this example, contact regions 15 and emitter regions 12 are alternately arranged along the Y-axis direction in the region sandwiched between the base regions 14-e at both ends in the Y-axis direction. The contact regions 15 and the emitter regions 12 are formed from one adjacent trench portion to the other.

[0127] In one or more mesa portions 60-2 of the mesa portion 60 of the transistor portion 70, a contact region 15 having a larger area than the contact region 15 of the mesa portion 60-1 is provided, and the mesa portion 60-2 is provided at the boundary between the transistor portion 70 and the diode portion 80. The emitter region 12 may not be provided in the mesa portion 60-2. In the mesa portion 60-2 of this example, the contact region 15 is provided in the entire region sandwiched by the base region 14-e.

[0128] In each mesa portion 60-1 of the transistor portion 70 of this example, the contact hole 54 is formed above each region of the contact region 15 and the emitter region 12. The contact hole 54 of the mesa portion 60-2 is formed above the contact region 15. In each mesa portion 60, the contact hole 54 is not formed in the region corresponding to the base region 14-e and the well region 11. The contact holes 54 of each mesa portion 60 of the transistor portion 70 may have the same length in the Y-axis direction.

[0129] In the diode portion 80, an N+ type anode region 82 is formed in a region in contact with the lower surface of the semiconductor substrate 10. Figure 2 In FIG. 8 , a region where the anode region 82 is formed is indicated by a dotted line. A P+ type collector region may be formed in a region in contact with the lower surface of the semiconductor substrate 10 where the anode region 82 is not formed.

[0130] The transistor portion 70 may be a region in which a mesa portion 60 having a contact region 15 and an emitter region 12 is provided in a region overlapping with the collector region in the Z-axis direction, and a groove portion adjacent to the mesa portion 60. However, the contact region 15 may be provided in place of the emitter region 12 in the mesa portion 60-2 at the boundary with the diode portion 80.

[0131] The base region 14 is arranged on the upper surface of the mesa portion 60-3 of the diode portion 80. However, a contact region 15 may be provided in a region adjacent to the base region 14-e. Above the contact region 15, the contact hole 54 terminates.

[0132] Figure 3 Yes means Figure 2FIG. 2 is a diagram showing an example of a BB cross section of FIG. BB cross section is an XZ plane including the diode portion 80 and the transistor portion 70 and passing through the emitter region 12 .

[0133] The semiconductor device 100 of this example includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross section. The interlayer insulating film 38 is formed by covering at least a portion of the upper surface of the semiconductor substrate 10. Through holes such as contact holes 54 are formed in the interlayer insulating film 38. The upper surface of the semiconductor substrate 10 is exposed through the contact holes 54. The interlayer insulating film 38 may be a silicate glass such as PSG or BPSG, or may be an oxide film or a nitride film.

[0134] The emitter electrode 52 is formed on the upper surface of the semiconductor substrate 10 and the interlayer insulating film 38 in the transistor section 70 and the diode section 80. The emitter electrode 52 is also formed inside the contact hole 54 and contacts the upper surface 21 of the semiconductor substrate 10 exposed through the contact hole 54.

[0135] As described above, the connection portion 132 is connected to the upper surface of the emitting electrode 52. In addition to the metal layer containing aluminum, the emitting electrode 52 may also include a plating layer or a solder layer provided on the metal layer. The connection portion 132 may be in contact with the metal layer, the plating layer, or the solder layer.

[0136] The collector electrode 24 is formed on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a conductive material such as a metal. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction (Z-axis direction). The direction from the collector electrode 24 toward the emitter electrode 52 is referred to as the positive direction of the Z-axis direction.

[0137] A P-type base region 14 is formed on the upper surface side of the semiconductor substrate 10 in the diode portion 80 and the transistor portion 70. An N-type drift region 18 is arranged below the base region 14 in the interior of the semiconductor substrate 10. Each trench portion is provided so as to penetrate the base region 14 from the upper surface of the semiconductor substrate 10 and reach the drift region 18.

[0138] In this cross section, an N+ type emitter region 12, a P- type base region 14, and an N+ type accumulation region 16 are sequentially arranged in each mesa portion 60-1 of the transistor portion 70 from the upper surface side of the semiconductor substrate 10. The accumulation region 16 has a higher concentration of donor accumulation than the drift region 18. The drift region 18 is provided below the accumulation region 16. The accumulation region 16 can be provided to cover the entire lower surface of the base region 14 in each mesa portion 60. In other words, the accumulation region 16 can be sandwiched between the groove portions in the X-axis direction. By providing an accumulation region 16 having a higher concentration than the drift region 18 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect, Injection-Enhancement effect) can be improved, and the on-voltage in the transistor portion 70 can be reduced.

[0139] In the XZ cross section passing through the contact region 15 of the transistor portion 70, the contact region 15 is provided in each mesa portion 60-1 of the transistor portion 70 instead of the emitter region 12. In addition, the contact region 15 is provided in the mesa portion 60-2 instead of the emitter region 12. The contact region 15 can function as a latch-up suppressing layer for suppressing latch-up.

[0140] In this cross section, a P-type base region 14 and an N+ type accumulation region 16 are sequentially arranged in each mesa portion 60-3 of the diode portion 80 from the upper surface side of the semiconductor substrate 10. A drift region 18 is provided below the accumulation region 16. The diode portion 80 may not be provided with the accumulation region 16.

[0141] A P+ type collector region 22 is provided in a region of the transistor portion 70 adjacent to the lower surface 23 of the semiconductor substrate 10. An N+ type anode region 82 is provided in a region of the diode portion 80 adjacent to the lower surface 23 of the semiconductor substrate 10.

[0142] In the semiconductor substrate 10 of this example, an N+ type buffer region 20 is provided between the drift region 18 and the collector region 22 and between the drift region 18 and the anode region 82. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 can function as a field stop layer that prevents the depletion layer diffused from the lower surface side of the base region 14 from reaching the P+ type collector region 22 and the N+ type anode region 82.

[0143] One or more gate groove portions 40 and one or more dummy portions 30 are formed on the upper surface 21 side of the semiconductor substrate 10. Each groove portion penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 to reach the drift region 18. In a region where at least one of the emitter region 12, the contact region 15 and the accumulation region 16 is provided, each groove portion also penetrates these regions to reach the drift region 18. The groove portion penetrating the doped region is not limited to being manufactured in the order of forming the doped region first and then forming the groove portion. It also includes the manufacturing in the order of forming the doped region between the groove portions after the groove portions are formed, and the groove portion penetrating the doped region.

[0144] The gate trench portion 40 has a gate trench formed on the upper surface side of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed in a manner covering the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is an example of a gate electrode. The gate conductive portion 44 is formed inside the gate trench at a position closer to the inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0145] The gate conductive portion 44 includes a region that is at least opposite to the adjacent base region 14 in the depth direction via the gate insulating film 42. The gate trench portion 40 in the cross section is covered by the interlayer insulating film 38 on the upper surface of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel consisting of an electron inversion layer is formed in the surface layer of the interface in the base region 14 that is in contact with the gate trench.

[0146] The dummy portion 30 may have the same structure as the gate groove portion 40 in this cross section. The dummy portion 30 has a dummy groove formed on the upper surface 21 side of the semiconductor substrate 10, a dummy insulating film 32 and a dummy conductive portion 34. The dummy insulating film 32 is formed in a manner covering the inner wall of the dummy groove. The dummy conductive portion 34 is formed inside the dummy groove and is formed at a position closer to the inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. The dummy portion 30 in this cross section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. It should be noted that the bottoms of the dummy portion 30 and the gate trench portion 40 may be in a curved shape (curved shape in cross section) that is convex toward the bottom.

[0147] Figure 41 is a diagram showing another example of the upper surface structure of the semiconductor device 100. The semiconductor device 100 of this example is provided with a plurality of connection parts 132 and 133 above the upper surface of the semiconductor substrate 10. The external wiring in this example is a wire. Each connection part is provided at a predetermined wiring interval L3 in the Y-axis direction perpendicular to the long side direction of the connection part. The wiring interval L3 refers to the distance in the Y-axis direction from the center of the connection part in the XY plane. The wiring interval L3 is constant in the entire upper surface of the semiconductor substrate 10.

[0148] In this example, when viewed from above, the distance D1 between at least one connection portion 132 and the temperature detection portion 110 is less than the wiring interval L3 (condition (4)). The distance D1 may be less than half of the wiring interval L3. In addition, the temperature detection portion 110 may be arranged at the center of the region sandwiched by the two connection portions 132 in the Y-axis direction. With such an arrangement, the temperature detection portion 110 can detect the temperature more appropriately.

[0149] It should be noted that the connection parts may be arranged at predetermined intervals in the X-axis direction. The plurality of connection parts arranged in the X-axis direction may be connection parts of the same external wiring 130. In other words, one external wiring 130 may be connected to the upper surface electrode at a plurality of locations in the X-axis direction.

[0150] Figure 5 1 is a diagram showing an example of the relationship between the temperature detection unit 110 and the connection portion 132. As described above, the temperature detection unit 110 and the connection portion 132 may be arranged to face each other in the Y-axis direction. Figure 5 As shown by the dotted line in FIG. 1 , at least one connecting portion 132 may be disposed at least partially in the extended region after the temperature detection portion 110 is extended along the Y-axis direction. Figure 5 As shown, the connection portion 132 may be disposed so as to be opposed to the entire temperature detection unit 110 in the X-axis direction.

[0151] like Figure 5 As shown, the connection portion length L2 of the connection portion 132 may be greater than the detection portion length L1. Thus, even if the relative position of the connection portion 132 and the temperature detection portion 110 in the X-axis direction deviates, the heat generated in the connection portion 132 can be detected with good accuracy. It should be noted that the connection portion length L2 may be the same as the detection portion length L1, or may be less than the detection portion length L1. In addition, it is preferred that the temperature detection portion 110 is sandwiched by two connection portions 132 in the Y-axis direction. Thus, even if the relative position of the temperature detection portion 110 and the connection portion 132 in the Y-axis direction deviates, the heat generated in the connection portion 132 can be detected with good accuracy.

[0152] Figure 61 is a diagram showing another example of the relationship between the temperature detection unit 110 and the connection portion 132. The connection portion 132 of this example is arranged to be opposed to a portion of the temperature detection unit 110 in the X-axis direction. It should be noted that a plurality of connection portions 132 that partially oppose the temperature detection unit 110 may be provided in the X-axis direction. Figure 6 In the example, two connection portions 132 partially facing the temperature detection unit 110 are arranged in parallel in the X-axis direction. In addition, based on the temperature detection unit 110, one or more connection portions 132 partially facing the temperature detection unit 110 may be arranged on both the positive side in the Y-axis direction and the negative side in the Y-axis direction. Figure 6 In the example of FIG. 1 , two connection portions 132 are arranged on both the positive side in the Y-axis direction and the negative side in the Y-axis direction of the temperature detection unit 110. With such an arrangement, even if the heat generation in the connection portions 132 is biased, the heat generated from the plurality of connection portions 132 reaches the temperature detection unit 110, so that the influence of the bias can be reduced.

[0153] In addition, on the XY plane, a rectangular area circumscribed with the plurality of connection portions 132 is defined as an area 141. The area 141 has sides in the X-axis direction and the Y-axis direction. The temperature detection unit 110 may be provided inside the area 141. The temperature detection unit 110 may be arranged in the center of the area 141. With such an arrangement, the heat generated in the connection portion 132 can be detected more appropriately.

[0154] Figure 7 1 is a diagram showing another example of the relationship between the temperature detection unit 110 and the connection portion 132 . Figure 1 to Figure 6 In the example, the connection portion 132 has a long side in the X-axis direction, but the connection portion 132 in this example has a long side in the Y-axis direction. In addition, at least one connection portion 132 having a long side in the Y-axis direction can be configured in a manner opposite to the temperature detection unit 110 in the X-axis direction. In addition, the connection portion 132 opposite to the temperature detection unit 110 in the Y-axis direction may have a long side in the X-axis direction, and the connection portion 132 opposite to the temperature detection unit 110 in the X-axis direction may have a long side in the Y-axis direction. With such a structure, the connection portion 132 can be configured in a manner to surround the temperature detection unit 110.

[0155] Figure 8 1 is a diagram showing a structural example of the temperature detection unit 110 in the XY plane. The temperature detection unit 110 of this example has a structure in which one or more PN junctions in the P-type region 154 and the N-type region 152 are arranged in the long side direction (in this example, the X-axis direction). Each PN junction is electrically connected in series through the wiring 153.

[0156] The detection portion length L1 of the temperature detection portion 110 may be the distance between both ends of the PN junction in the long-side direction. This distance may include the wiring 153 that connects the PN junction in series.

[0157] Fig. 9 1 is a schematic diagram showing other structures on the upper surface of the semiconductor device 100. In this example, the external wiring is a lead frame 134. The lead frame 134 includes a plate-shaped conductive component parallel to the XY plane. The lead frame 134 of this example has a first portion 136 and a second portion 138 in contact with the semiconductor device 100, a leg portion 142 extending from the second portion 138 in a direction away from the semiconductor substrate 10 (in this example, the Z-axis direction), and a bridge portion 144 extending from the leg portion 142 toward other circuit elements.

[0158] In this example, the first portion 136 is formed integrally with the second portion 138. The first portion 136 and the second portion 138 correspond to the connection portion 132 with the semiconductor substrate 10.

[0159] The distance D1 between the first portion 136 and the second portion 138 and the temperature detection unit 110 satisfies the same condition as the distance D1 between the connection portion 132 and the temperature detection unit 110. For example, the distance D1 is less than 5 times the arrangement period P1. It should be noted that the distance D1 between the first portion 136 and the second portion 138 and the temperature detection unit 110 is the distance between the end of the first portion 136 and the second portion 138 closest to the temperature detection unit 110 and the temperature detection unit 110.

[0160] In this example, the two first portions 136 are arranged across the temperature detection portion 110 in a direction (in this example, the Y-axis direction) perpendicular to the long side direction (in this example, the X-axis direction) of the temperature detection portion 110. The temperature detection portion 110 may be arranged in the center of the region between the two first portions 136 in the Y-axis direction.

[0161] The width of each first portion 136 in the X-axis direction may be greater than the width of the temperature detection unit 110 in the X-axis direction. A portion of the first portion 136 may be disposed to face a portion of the temperature detection wiring 112 in the Y-axis direction.

[0162] The second portion 138 connects the two first portions 136. The second portion 138 of this example is arranged on the opposite side of the temperature detection wiring 112 in a plan view with respect to the temperature detection portion 110. As an example, when the upper surface of the semiconductor substrate 10 is divided into two regions 146-1 and 146-2 by a straight line 147 passing through the center of the temperature detection portion 110 and parallel to the Y axis, the temperature detection wiring 112 and the second portion 138 are arranged in different regions 146. Fig. 9In the example of FIG. 1 , the second portion 138 is disposed in the region 146 - 2 , and the temperature detection wiring 112 is disposed in the region 146 - 1 . The second portion 138 and the temperature detection wiring 112 may be disposed across the temperature detection unit 110 in the X-axis direction.

[0163] With such a structure, the first portion 136 or the second portion 138 can be disposed to surround the temperature detection unit 110 while the first portion 136 and the second portion 138 can be disposed to avoid the temperature detection unit 110 and the temperature detection wiring 112 .

[0164] It should be noted that the length L4 of the portion of the first portion 136 disposed in the region 146-2 in the X-axis direction may be smaller than the length L5 of the portion disposed in the region 146-1 in the X-axis direction. In other words, the first portion 136 is extended longitudinally toward both sides of the temperature detection wiring 11 in the X-axis direction with the straight line 147 as a reference. Thus, the temperature detection unit 110 can be surrounded by more first portions 136.

[0165] Fig.10 1 is a diagram showing the arrangement of the first portion 136 or the second portion 138 in a comparative example. In the comparative example, at least one of the first portion 136 and the second portion 138 is arranged to overlap with at least one of the temperature detection unit 110 and the temperature detection wiring 112 . Fig.10 136 or the second portion 138 is shown as an example in which the first portion 136 or the second portion 138 is overlapped with the temperature detection unit 110. Figures 1 to 9 For the semiconductor device 100 described in the above, the structure other than the configuration of the first portion 136 or the second portion 138 may have Fig.10 The structure shown.

[0166] A metal layer 155 and a metal layer 157 are provided on the P-type region 154 and the N-type region 152 of the temperature detection unit 110. The metal layer 155 and the metal layer 157 may be, for example, Figure 8 The wiring 153 shown is functional. The temperature detection unit 110, the metal layer 155, and the metal layer 157 are covered with a protective film 148 such as polyimide.

[0167] The emitter electrode 52 is provided above the semiconductor substrate 10. A portion of the emitter electrode 52 may be covered by the protective film 148. A solder layer 53 is provided on the emitter electrode 52 and the protective film 148. The solder layer 53 functions as a portion of the upper surface electrode. The first portion 136 or the second portion 138 in this example is connected to the upper surface of the solder layer 53.

[0168] Compared with the combination of the solder layer 53 and the emitter electrode 52 or the solder layer 53 and the first portion 136 (or the second portion 138), the solder layer 53 and the protective film 148 have low adhesion at the interface 149. If the first portion 136 or the like is arranged above the temperature detection unit 110 or the like, stress is easily applied to the interface 149 due to the difference in linear expansion coefficients among the first portion 136, the solder layer 53, the protective film 148, and the semiconductor substrate 10. Therefore, there is a case where the protective film 148 and the solder layer 53 are peeled off at the interface 149.

[0169] In contrast, according to Fig. 9 In the semiconductor device 100 shown, the first portion 136 and the second portion 138 are arranged so as not to overlap with the temperature detection unit 110 and the temperature detection wiring 112. Therefore, it is possible to suppress the protective film 148 and the solder layer 53 from being peeled off.

[0170] Fig.11 Schematic diagram showing other structures on the upper surface of the semiconductor device 100. Fig.11 The external wiring and connection parts are omitted, but the structure of the external wiring and connection parts is the same as Figures 1 to 9 However, each pad and each connection portion are arranged so as not to overlap.

[0171] In this example, the gate pad 116 is arranged on the opposite side of the temperature detection wiring 112 when viewed from above, with reference to the temperature detection portion 110. As an example, when the upper surface of the semiconductor substrate 10 is divided into two regions 146-1 and 146-2 by a straight line 147 passing through the center of the temperature detection portion 110 and parallel to the Y axis, the temperature detection wiring 112 and the gate pad 116 are arranged in different regions 146.

[0172] Fig.11 In the example of , the gate pad 116 is arranged in the region 146-2, and the temperature detection wiring 112 is arranged in the region 146-1. The gate pad 116 and the temperature detection wiring 112 can be arranged in the X-axis direction across the temperature detection unit 110. In other words, the gate pad 116 can be arranged on a straight line formed by extending the temperature detection wiring 112 in the X-axis direction.

[0173] In addition, the sensing emitter pad 122 can be arranged on the opposite side of the gate pad 116 with respect to the temperature detection unit 110. The sensing emitter pad 122 of this example is arranged in the region 146-1. In addition, the cathode pad 118 and the anode pad 119 can also be arranged on the opposite side of the gate pad 116. In other words, the cathode pad 118 and the anode pad 119 are arranged on the same side as the temperature detection wiring 112. Thus, the temperature detection wiring 112 and the cathode pad 118 and the anode pad 119 can be easily connected.

[0174] Semiconductor device 100 may include gate flow channel 48 provided from gate pad 116 toward temperature detection unit 110 in the XY plane. Gate flow channel 48 may have the same structure as gate flow channel 51. In other words, gate flow channel 48 may be a semiconductor wiring such as polysilicon doped with impurities.

[0175] The gate flow channel 48 may branch in two directions, namely, the positive side in the Y-axis direction and the negative side in the Y-axis direction, at a position opposite to the end of the temperature detection unit 110. Two gate flow channels 48 may be provided parallel to the X-axis direction along the temperature detection unit 110 and the temperature detection wiring 112. The gate flow channel 48 bypasses each pad in the XY plane and is connected to the gate flow channel 51.

[0176] By disposing the gate flow channel 48 above the active portion 120, a gate voltage with little delay and attenuation can be applied even to a region separated from the gate flow channel 50 and the gate flow channel 51. In addition, according to the pad arrangement of this example, since the gate flow channel 48 is provided along the temperature detection wiring 112 and the like, the area loss of the active portion 120 caused by providing the gate flow channel 48 and the area loss of the active portion 120 caused by providing the temperature detection wiring 112 can be minimized.

[0177] Fig.12 1 is a diagram showing an example of a semiconductor package 200 according to an embodiment of the present invention. The semiconductor package 200 includes one or more semiconductor devices 100 and an external circuit. The semiconductor package 200 of this example has a circuit substrate 162 provided with wiring patterns (164, 166, 168, 170) as an external circuit. The wiring pattern may be a thin film formed of a conductive material such as copper. The wiring patterns and the semiconductor device 100 and the wiring pattern are connected by external wiring 130. A lead frame 134 may be used to replace part or all of the external wiring 130.

[0178] The semiconductor device 100 of this example may have Fig.11 The pad configuration shown. Each semiconductor device 100 can be connected to the wiring pattern 170 by solder or the like. In the semiconductor device 100 of this example, the collector electrode 24 is connected to the wiring pattern 170. In each wiring pattern 170, a plurality of semiconductor devices 100 can be connected in parallel. In addition, semiconductor devices 100 provided in different wiring patterns 170 can be connected in series. In other words, in semiconductor devices 100 provided in different wiring patterns 170, the emitter electrode 52 of one can be electrically connected to the collector electrode 24 of the other. In addition, the wiring pattern 168 is connected to the emitter electrodes 52 of a plurality of semiconductor devices 100 provided in the same wiring pattern 170. The wiring pattern 168 can be connected to the outside via the wiring pattern 166.

[0179] In this example, the end side closest to the gate pad 116 among the end sides of the semiconductor device 100 in a plan view is defined as the gate pad end side 117. Two semiconductor devices 100 arranged on the same wiring pattern 170 may be arranged so that the gate pad end sides 117 face each other.

[0180] A wiring pattern 164 is provided between the two gate pad ends 117. The gate pads 116 of the two semiconductor devices 100 are connected to the common wiring pattern 164. The wiring pattern 164 is arranged between the two gate pad ends 117. With such an arrangement, a common gate voltage can be applied to the two semiconductor devices 100 by simple wiring. In addition, since a common wiring pattern 164 can be provided for the two semiconductor devices 100, the devices can be miniaturized.

[0181] In addition, for one of the semiconductor devices 100 (semiconductor devices 100-1 and 100-3 in this example) arranged on the same wiring pattern 170, the sense emitter pad 122, the cathode pad 118, and the anode pad 119 are connected to the wiring pattern 166. The wiring pattern 166 is a pad connected to an external device. In the semiconductor device 100 of this example, since the gate pad 116 and the other pads are arranged on the opposite side, the sense emitter pad 122, the cathode pad 118, and the anode pad 119 can be arranged near the wiring pattern 166.

[0182] In the other semiconductor devices 100 (semiconductor devices 100-2 and 100-4 in this example) arranged on the same wiring pattern 170, cathode pad 118 and anode pad 119 may not be connected to wiring pattern 166. In this example, the temperature of this semiconductor device 100 is not detected.

[0183] Fig.13 FIG. 4 is a diagram showing an example of the upper surface of a semiconductor module 400 according to an embodiment of the present invention. It should be noted that in the semiconductor module 400, the arrangement of the anode pad 119 and the cathode pad 118 is similar to that of FIG. Fig.12 The configurations of the anode pad 119 and the cathode pad 118 are opposite, but Fig.12 The anode pad 119 and Fig.13 The anode pad 119 has the same function as Fig.12 The cathode pad 118 and Fig.13The cathode pad 118 in the embodiment has the same function and is therefore labeled with the same symbol. In addition, the wiring pattern of the upper arm is referred to as wiring pattern 170-1, and the wiring pattern of the lower arm is referred to as wiring pattern 170-2. The wiring pattern serving as the gate terminal is referred to as wiring pattern 164, and the wiring pattern serving as a relay terminal with the control terminal described later is referred to as wiring pattern 166.

[0184] The semiconductor module 400 of this example includes a lead frame 178. As described above, the semiconductor device 100 is a plated chip whose surface is plated, and is arranged on predetermined wiring patterns 170-1 and 170-2. One end of the lead frame 178 is bonded to the plated chip, and the other end is bonded to the wiring patterns 168 and 170-2 as an external circuit. The lead frame 178 of this example has a first contact portion 180 in contact with the semiconductor device 100, a second contact portion 182 in contact with the wiring patterns 168 and 170-2, a bridge portion 184 bridging the first contact portion 180 and the second contact portion 182 above the circuit substrate 162, a leg portion 186 connecting the first contact portion 180 and the bridge portion 184, and a leg portion 188 connecting the second contact portion 182 and the bridge portion 184. The first contact portion 180, the second contact portion 182, and the bridge portion 184 can be composed of a plate-shaped conductive member parallel to the XY plane. The bridge portion 184 may be a convex portion that protrudes toward a side away from the surface of the semiconductor device 100 .

[0185] The semiconductor module 400 of this example has a molded portion 192 (see Fig.14 ). The mold portion 192 is made of a gel-like resin or the like.

[0186] The bridge portion 184 is provided with an opening 190 for injecting the resin of the mold portion 192 below the bridge portion 184. In the bridge portion 184 of this example, a plurality of openings 190 are provided inside and near the center thereof. Thus, the gel-like resin constituting the mold portion 192 can be reliably moved along the vertical direction of the lead frame 178. It should be noted that the wiring pattern 170-1, the wiring pattern 170-2, and the wiring pattern 168 may be provided with a lead portion 198 electrically connected to the main terminal outside the semiconductor module 400.

[0187] Fig.14 Yes means Fig.13 FIG. 1 is a diagram showing an example of an EE' cross section in FIG. The EE' cross section is a YZ plane passing through the opening 190 provided in the lead frame 178. Fig.14As shown, one end of the lead frame 178 is connected to the semiconductor device 100-1 provided above the wiring pattern 170-1. In addition, the other end of the lead frame 178 is connected to the wiring pattern 170-2. The first contact portion 180 is arranged above the semiconductor device 100-1. The second contact portion 182 is arranged above the wiring pattern 170-2. The semiconductor devices 100-1, 100-2, 100-3, and 100-4 of this example are so-called plated chips whose surfaces are plated. The bridge portion 184 is connected to the first contact portion 180 through the leg portion 186, and is connected to the second contact portion 182 through the leg portion 188. As described above, since the opening portion 190 is provided in the bridge portion 184, the space divided by the leg portion 186, the leg portion 188, and the bridge portion 184 is also filled with the gel-like resin of the mold portion 192. The mold portion 192 may also be composed of other materials such as epoxy resin. It should be noted that, in order to improve the close contact with the molded portion 192 , the opening portion 190 may be provided in any one or more of the first contact portion 180 , the second contact portion 182 , the leg portion 186 , or the leg portion 188 .

[0188] It should be noted that the semiconductor devices 100-1, 100-2, 100-3, and 100-4 of this example may be Fig. 9 The semiconductor device 100 having the temperature detection unit 110 shown in FIG. 1 may be a semiconductor device 100 having the temperature detection unit 110 shown in FIG. Fig. 9 The lead frame 134 shown does not overlap with the temperature detection portion 110. That is, the lead frame 178 can be bonded to the surface of the semiconductor device 100 in a manner sandwiching the temperature detection portion 110. The lead frame 178 has a first portion 136 and a second portion 138 formed integrally, and the first portion 136 or the second portion 138 can be arranged to surround the temperature detection portion 110.

[0189] Fig.15 FIG. 1 is a schematic circuit diagram showing the connection relationship between the upper arm and the lower arm of a semiconductor module according to an embodiment of the present invention. Fig.15 As shown, semiconductor devices 100-1 and 100-2 are connected in parallel to form an upper arm. Semiconductor devices 100-3 and 100-4 are connected in parallel to form a lower arm. In this example, one arm is composed of two semiconductor devices 100. The upper arm including semiconductor devices 100-1 and 100-2 is connected in series with the lower arm including semiconductor devices 100-3 and 100-4. Fig.13 As shown, the semiconductor device 100-1 and the semiconductor device 100-3 are arranged on the negative side of the X-axis of the semiconductor module 400. Fig.13 As shown, the semiconductor device 100 - 2 and the semiconductor device 100 - 4 are arranged on the positive side of the X axis of the semiconductor module 400 .

[0190] A control circuit 172-1 is connected to the semiconductor device 100-1 and the semiconductor device 100-2. The control circuit 172-1 supplies gate voltage to the semiconductor device 100-1 and the semiconductor device 100-2. In addition, another control circuit 172-2 is connected to the semiconductor device 100-3 and the semiconductor device 100-4. The control circuit 172-2 may have the same function as the control circuit 172-1.

[0191] The sensing emitter terminal (SE) is connected to the sensing emitter pad 122. The emission terminal (E) is connected to the emission electrode 52. The control circuit 172-1 and the control circuit 172-2 detect the current flowing between the sensing emitter terminal (SE) and the emission terminal (E) via the sensing resistor Rse, respectively. In addition, the control circuits 172-1 and 172-2 may have a temperature detection circuit that detects the temperature based on the voltage change of the temperature sensing diode of the temperature detection unit 110 connected to the anode pad 119 and the cathode pad 118.

[0192] Fig.16 FIG. 1 is a diagram showing an example of the upper surface of a semiconductor module 300 according to an embodiment of the present invention. Fig.16 As shown, the semiconductor module 300 of this example has a shell 88. The shell 88 has main terminals 86 such as U, V, W, P, and N, and control terminals 99 such as G (gate), Se (sense emitter), A (anode), and K (cathode). A circuit substrate 162 having a wiring pattern 170 is mounted above the bottom surface 94 of the shell 88. The circuit substrate 162 is formed, for example, by joining a copper circuit board to an alumina ceramic substrate. The semiconductor module 300 of this example is used, for example, to drive a three-phase motor, and is a so-called 6-in-1 type having 6 arms. In the shell 88, three circuit substrates 162 are mounted in parallel in the Y-axis direction. Each circuit substrate 162 includes an upper and lower arm that constitutes an output to each main terminal 86 of U, V, and W. In addition, as shown in FIG. Fig.15 As shown, each arm has two semiconductor devices 100 connected in parallel.

[0193] The shell 88 has a relay terminal 96 for connecting to the wiring pattern 166. The wiring pattern 166 and the relay terminal 96 are connected by the wiring 131. It should be noted that the sensing emitter pad 122, the cathode pad 118 and the anode pad 119 can also be connected to the wiring pattern 166 by the same wiring 131. In addition, the shell 88 has a control terminal 99. Each relay terminal 96 is connected to each control terminal 99 by a wiring 139. Unlike the wiring 131, the wiring 139 is not a wire, etc., but can be a metal wiring buried in the shell 88. In this example, the control terminal 99 is arranged on the negative side of the X-axis of the circuit substrate 162, and is not arranged on the positive side of the X-axis. Such a configuration is due to the fact that the detection unit 108 (refer to Fig. 20 ) is not connected to the control terminal 99. This makes it possible to improve assemblability with the control circuits 172-1 and 172-2 such as the gate drive circuit connected to the control terminal 99, and to simplify the layout configuration.

[0194] The number of control terminals 99 may be the same as the number of relay terminals 96 and wiring patterns 166. In this example, five wiring patterns 166 and five relay terminals 96 are provided corresponding to the semiconductor devices 100-1 and 100-2, and five wiring patterns 166 and five relay terminals 96 are provided corresponding to the semiconductor devices 100-3 and 100-4.

[0195] A cooling unit for circulating a refrigerant in a predetermined flow direction is arranged below the housing 88. The cooling unit is arranged below the bottom surface 94 and is arranged Fig.16 In addition, the housing 88 may have a through hole 84 for fixing the semiconductor module 300 to an external device.

[0196] Fig.17 This is a diagram showing an example of the back surface of a semiconductor module 300 according to an embodiment of the present invention. Fig.17 It is viewed from the opposite side of the Z axis direction, that is, the negative side of the Z axis. Fig.16 The top view of the diagram. Fig.17 As shown, the housing 88 has a cooling portion 114. The cooling portion 114 has a side wall 63. A space surrounded by the side wall 63 is provided in the cooling portion 114. A refrigerant flows in the space. A plurality of cooling fins 95 arranged along the X-axis direction may be provided in the space of the cooling portion 114.

[0197] The housing 88 has a refrigerant inlet 97 for introducing the refrigerant into the cooling portion 114 and a refrigerant outlet 98 for outlet the refrigerant from the cooling portion 114. Therefore, the side close to the refrigerant outlet 98 is the downstream side, and the other side close to the refrigerant inlet 97 is the upstream side. In this example, the semiconductor module 300 has one refrigerant inlet 97 and one refrigerant outlet 98, but may have a plurality of refrigerant inlet 97 and refrigerant outlet 98, respectively.

[0198] The refrigerant inlet 97 and the refrigerant outlet 98 may be provided on two sides facing each other in the X-axis direction or the Y-axis direction. In this example, the refrigerant inlet 97 is on the positive side of the X-axis, and the refrigerant outlet 98 is on the negative side of the X-axis.

[0199] Fig.18 Yes means Fig.16 as well as Fig.17 FIG. 1 is a diagram showing an example of a CC' cross section. The CC' cross section is an XZ plane passing through the semiconductor device 100-1 and the semiconductor device 100-2. Fig.18 As shown, the housing 88 is provided with a recess 93 for mounting a circuit substrate 162 having a wiring pattern 170. That is, the circuit substrate 162 is disposed on the bottom surface 94 of the recess 93. The circuit substrate 162 may have the semiconductor device 100-1 and the semiconductor device 100-2 thereon. The depth of the recess 93 may be deeper than the thickness of the semiconductor devices 100-1, 100-2 and the circuit substrate 162. It should be noted that, for convenience, Fig.18 as well as Fig.19 The mold portion 192 covering the semiconductor devices 100 - 1 and 100 - 2 is omitted from illustration.

[0200] The housing 88 has a cooling portion 114 below the bottom surface 94. The housing 88 has a refrigerant inlet 97 and a refrigerant outlet 98. Since the CC' cross section does not pass through the refrigerant inlet 97 and the refrigerant outlet 98, Fig.18 The positions of the coolant inlet 97 and the coolant outlet 98 in the XZ plane are indicated by dotted lines. The coolant flows from the positive side to the negative side of the X axis in the cooling unit 114. The two parallel semiconductor devices 100-1 and 100-2 can be arranged parallel to the direction in which the coolant flows.

[0201] Fig.19 Yes means Fig.16 as well as Fig.17FIG. 1 is a diagram showing an example of a D-D' cross section. The D-D' cross section is a YZ plane passing through the semiconductor device 100-2 and the semiconductor device 100-4. In this example, three circuit substrates 162 are arranged on the bottom surface 94 of the recess 93 in the Y-axis direction. A plurality of cooling fins 95 can be provided in the cooling portion 114. The cooling fins 95 can be provided in the space inside the cooling portion 114 from the lower end to the upper end in the Z-axis direction of the space.

[0202] When the cooling fins 95 are provided in the cooling unit 114, the refrigerant flows along the X-axis direction between adjacent cooling fins 95. Therefore, the flow direction of the refrigerant may be the extending direction (X-axis direction) of the cooling fins 95. When the cooling unit 114 is not provided with cooling fins 95, the flow direction of the refrigerant may be the direction connecting the refrigerant inlet 97 and the refrigerant outlet 98.

[0203] Fig. 20 FIG. 1 is a diagram showing another example of the structure of the upper surface of the semiconductor device 100 according to one embodiment of the present invention. The semiconductor modules 300 and 400 include the semiconductor device 100. Fig. 20 1 and 2 show an example of the upper surface of the semiconductor device 100-1 and the semiconductor device 100-2. The semiconductor device 100-1 is provided on one side of the flow path of the refrigerant (the refrigerant outlet 98 side) in the semiconductor module 300 or 400. In addition, the semiconductor device 100-2 is provided on the other side of the flow path of the refrigerant (the refrigerant inlet 97 side) in the semiconductor module 300 or 400.

[0204] The semiconductor device 100-1 includes an active portion 120 and an edge termination structure portion 90. A main semiconductor element portion 125 and a sensing semiconductor element portion 124 are formed in the active portion 120. A transistor portion 70 and a diode portion 80 are provided in the main semiconductor element portion 125. In this example, the transistor portion 70 and the diode portion 80 are provided in a manner extending along the X-axis direction. In addition, in this example, the transistor portion 70 and the diode portion 80 are alternately provided in the Y-axis direction.

[0205] In the semiconductor device 100-1, a gate pad 116, a dummy gate pad 115, and a plurality of detection pads 126 are provided above the upper surface 21 of the semiconductor substrate 10. As an example, the detection pad 126 is an anode pad 119, a cathode pad 118, and a sensing emitter pad 122. In the semiconductor device 100-1, the detection pad 126 is provided on one side of the end sides opposite to each other in the X-axis direction (the negative side of the X-axis), and the gate pad 116 and the dummy gate pad 115 are provided on the other side of the end side (the positive side of the X-axis). It should be noted that the number and types of pads provided on the semiconductor substrate 10 are not limited to Fig. 20 Example shown.

[0206] In the semiconductor device 100-1, a sensing semiconductor element portion 124 is provided above the upper surface 21 of the semiconductor substrate 10. In this example, the sensing semiconductor element portion 124 is provided on one side of the end sides opposite to each other in the X-axis direction (the negative side of the X-axis). The sensing semiconductor element portion 124 is connected to the sensing emitter pad 122, and the sensing emitter pad 122 is connected to the sensing emitter terminal (SE).

[0207] Cathode pad 118 and anode pad 119 are respectively connected to the anode and cathode of the temperature sensing diode of temperature detection unit 110. Gate pad 116 is connected to the gate electrode of transistor unit 70. Dummy gate pad 115 is a pad for selecting a dummy trench.

[0208] The semiconductor device 100-1 includes a gate flow channel 50 for supplying a gate voltage to the transistor portion 70. As an example, the gate flow channel 50 is provided above the upper surface 21 of the semiconductor substrate 10 and is insulated from the upper surface 21 by the interlayer insulating film 38.

[0209] When viewed from above, the gate flow channel 50 is arranged in a manner passing through the end edge of the semiconductor substrate 10 and between each pad. The gate flow channel 50 of this example is arranged in a manner passing between each pad of the gate pad 116, the cathode pad 118, the anode pad 119, and the sense emitter pad 122 and the end edge closest to these pads and parallel to the end edge. The gate flow channel 50 is connected to the gate pad 116. In addition, the gate flow channel 50 is arranged between the other end edges of the semiconductor substrate 10 and the active portion 120 in a manner surrounding the active portion 120. In other words, the gate flow channel 50 of this example is arranged in a ring shape along each end edge of the semiconductor substrate 10.

[0210] The gate flow path 48 bypasses each pad on the XY plane and is connected to the gate flow path 50. The gate flow path 48 may be provided above the active portion 120. The gate flow path 48 may be provided along the temperature detection portion 110 and the temperature detection wiring 112 in parallel with the X-axis direction.

[0211] The edge terminal structure portion 90 is provided on the upper surface of the semiconductor substrate 10 between the gate flow channel 50 and the outer peripheral end 140 of the semiconductor substrate 10. The edge terminal structure portion 90 may be arranged in an annular shape on the upper surface of the semiconductor substrate 10 so as to surround the gate flow channel 50. The edge terminal structure portion 90 of this example is arranged along the outer peripheral end 140 of the semiconductor substrate 10.

[0212] Semiconductor device 100-1 includes detection unit 108. As an example, detection unit 108 is temperature detection unit 110 or sensing semiconductor element unit 124. Semiconductor device 100-1 includes detection pad 126 connected to detection unit 108. On the other hand, semiconductor device 100-2 includes detection unit 108 but does not include detection pad 126.

[0213] The temperature detection unit 110 is disposed above the active unit 120. When viewed from the upper surface of the semiconductor substrate 10, the temperature detection unit 110 may be disposed in the center of the active unit 120. The temperature detection unit 110 has a long side in a predetermined long side direction. The long side direction in this example is the X-axis direction, but the long side direction may be different from the X-axis direction. The temperature detection unit 110 may be configured to cover one or more transistor units 70 and one or more diode units 80.

[0214] The temperature detection wiring 112 is provided above the active portion 120. The temperature detection wiring 112 is connected to the temperature detection portion 110. The temperature detection wiring 112 extends to the end of the active portion 120 on the upper surface 21 of the semiconductor substrate 10, and is connected to the cathode pad 118 and the anode pad 119. By measuring the electrical characteristics of the temperature detection portion 110 via the cathode pad 118 and the anode pad 119, the temperature of the temperature detection portion 110 can be detected.

[0215] The temperature detection wiring 112 of this example is formed of aluminum (Al). The temperature detection wiring 112 can be formed by sputtering aluminum (Al). That is, the wiring connecting the temperature detection wiring 112 and the cathode pad 118 and the wiring connecting the temperature detection wiring 112 and the anode pad 119 can be formed by sputtering aluminum (Al) and then etching the sputtered aluminum (Al). It should be noted that the temperature detection wiring 112 can be formed of polysilicon.

[0216] The semiconductor device 100-2 has a structure obtained by inverting the semiconductor device 100-1 in the X-axis direction. The active portion 120 of the semiconductor device 100-1 and the semiconductor device 100-2 has the same area. Therefore, when the semiconductor device 100-1 and the semiconductor device 100-2 operate, substantially the same current flows through the semiconductor device 100-1 and the semiconductor device 100-2.

[0217] In semiconductor device 100-1, cathode pad 118, anode pad 119, sense emitter pad 122, and sense semiconductor element portion 124 are arranged on one side of the end sides facing each other in the X-axis direction (X-axis negative side), and gate pad 116 is arranged on the other side of the end side (X-axis positive side). In semiconductor device 100-2, sense pad 126 is not provided, and gate pad 116 is arranged on one side of the end side (X-axis negative side).

[0218] In the semiconductor device 100-2, the temperature detection unit 110 and the sensing semiconductor element unit 124 as the detection unit 108 can be built-in. That is, the semiconductor devices 100-1 and 100-2 can be the same chip. However, in the semiconductor device 100-2, in particular, when the sensing emitter pad 122 connected to the sensing semiconductor element unit 124 is set as the detection pad 126 and the sensing emitter pad 122 is released, the gate potential of the sensing semiconductor element unit 124 becomes unstable, which may damage the operation of the element. Such a problem can be eliminated by connecting the sensing emitter pad 122 as the detection pad 126 to the emitter potential, but additional wiring is required, which may go against the purpose of miniaturization of the product. Therefore, in this example, the temperature detection unit 110 and the sensing semiconductor element unit 124 can be invalidated in a way that they cannot be taken out. Specifically, for example, when the detection pad 126 is not set and the emitter electrode 52 is covered on the semiconductor substrate 10, these detection units 108 can be covered. The detection portion 108 covered by the emitter electrode 52 may be covered with a protective film such as polyimide, or may be covered with a protective film such as polyimide instead of being covered by the emitter electrode 52 .

[0219] In the semiconductor modules 300 and 400 , the semiconductor device 100 - 3 has the same configuration as the semiconductor device 100 - 1 of this example. Also, the semiconductor device 100 - 4 has the same configuration as the semiconductor device 100 - 4 of this example.

[0220] Fig.21 FIG. 5 is a schematic circuit diagram of a semiconductor circuit device 500 according to an embodiment of the present invention.

[0221] Fig.21 As shown in FIG. 1 , the semiconductor circuit device 500 of this example includes a semiconductor device 100. The semiconductor device 100 includes a main semiconductor element portion 125 and a sensing semiconductor element portion 124 (see FIG. 1 ) provided on a semiconductor substrate 10. Fig. 22 as well as Fig.23 The main semiconductor element portion 125 includes a transistor portion 70 and a diode portion 80. The sensing semiconductor element portion 124 includes a transistor portion 71 different from the transistor portion 70 and a diode portion 81 different from the diode portion 80 and arranged inside the transistor portion 71.

[0222] In addition, the semiconductor circuit device 500 includes a control circuit 172, which includes a current detection circuit 220 for detecting the forward current and the reverse current of the sensing semiconductor element portion 124, a temperature detection circuit 210 for detecting the temperature of the semiconductor device 100, and a gate drive circuit 230 for outputting a signal according to the value of the reverse current. Here, the above description is applicable to both the semiconductor device 100 and the control circuit 172 of this example.

[0223] In the semiconductor device 100, the gate terminal (G) corresponds to the gate pad 116. The anode terminal (A) corresponds to the anode pad 119 and is connected to the temperature detection circuit 210 provided outside the semiconductor device 100. The cathode terminal (K) corresponds to the cathode pad 118 and is grounded outside the semiconductor device 100. The sense emitter terminal (SE) corresponds to the sense emitter pad 122, and the current detection circuit 220 and the sense resistor Rse provided outside the semiconductor device 100 are connected in parallel on the downstream side of the sense emitter pad 122. The temperature detection circuit 210 detects the temperature based on the voltage change of the temperature sensing diode of the temperature detection unit 110. For example, the temperature sensing diode has a negative temperature characteristic in which the resistance decreases as the temperature increases. The current detection circuit 220 converts the voltage drop of the sense resistor Rse into a current and detects the current flowing in the main semiconductor element unit 125 based on the area ratio of the main semiconductor element unit 125 and the sense semiconductor element unit 124. The gate drive circuit 230 drives the gate of the semiconductor device 100. The gate driving circuit 230 can receive a signal indicating abnormal heating from the temperature detection circuit 210 or a signal indicating overcurrent from the current detection circuit 220 to perform a protective action such as blocking the gate.

[0224] Fig. 22 yes Fig. 20 FIG. 1 is an enlarged view of the vicinity of the sensing semiconductor element portion 124. Fig.21 As shown in , one feature of this example is that the sensing semiconductor element portion 124 is composed of a so-called reverse conducting IGBT having a transistor portion 71 and a diode portion 81. In a plan view, the sensing semiconductor element portion 124 is surrounded by a second conductivity type (P type) well region 11 having a higher impurity concentration than the base region 14 and a depth deeper than the trench portion. Here, in this example, the diode portion 81 is surrounded by the transistor portion 71, so that the diode portion 81 is arranged at a position further inside than the transistor portion 71.

[0225] The diode portion 81 may be a region formed by projecting the region where the anode region 82 is provided on the lower surface 23 onto the upper surface 21. In this example, since the diode portion 81 is surrounded by the transistor portion 71, it is possible to prevent carriers from flowing from the well region 11 to the anode region 82 of the diode portion 81. In addition, the area ratio of the transistor portion 71 to the diode portion 81 in the sensing semiconductor element portion 124 may be as large as: Fig. 20 In the semiconductor device 100 shown, the area ratios of the transistor portion 70 and the diode portion 80 are equal.

[0226] Fig.23 yes Fig. 20 Another enlarged view of the vicinity of the sensing semiconductor element portion 124 in FIG. Fig. 22 The difference of the sensing semiconductor element portion 124 shown is that a diode portion 81 is sandwiched between two transistor portions 71. The diode portion 80 may be a region formed by projecting a region on the lower surface 23 where the anode region 82 is provided onto the upper surface 21.

[0227] In the sensing semiconductor element portion 124, in a plan view, a collector region 22 may be provided on the lower surface 23 in a region other than the transistor portion 71 and the diode portion 81. In this example, since the anode region 82 is separated from the well region 11 and the diode portion 81 is disposed at a position further inside than the transistor portion 71, it is possible to prevent carriers from flowing from the well region 11 into the anode region 82 of the diode portion 81. It should be noted that the area ratio of the transistor portion 71 to the diode portion 81 in the sensing semiconductor element portion 124 may be as large as 1 / 2. Fig. 20 In the semiconductor device 100 shown, the area ratios of the transistor portion 70 and the diode portion 80 are equal.

[0228] Fig.24 Yes means Fig.21 FIG. 1 is a diagram showing the relationship between the voltage Vce and the current Ic of the semiconductor device 100. Fig.24 As shown in FIG. 1 , when the voltage Vce increases from zero to the positive direction, the transistor units 70 and 71 start to operate, so the current Ic increases in the positive direction as the voltage Vce increases. When the voltage Vce increases from zero to the negative direction, the diode units 80 and 81 start to operate, so the current Ic increases in the negative direction as the voltage Vce increases.

[0229] Fig.25 Yes means Fig.21 FIG. 1 is a graph showing the current sensing characteristics of the semiconductor device 100. Fig.25 In FIG. 1 , the operation in the case where a gate voltage Vg of 15 (V) is applied and the case where a gate voltage Vg of 15 (V) is not applied (the case where Vg = 0 (V)) are shown as an example. Fig.25As shown, the semiconductor device 100 of this example increases the sense current Is in the positive direction as the sense voltage Vse increases in the positive direction. In addition, the semiconductor device 100 of this example is composed of a reverse conducting IGBT to form the sense semiconductor element portion 124, and thus the current Is increases in the negative direction as the voltage Vse increases in the negative direction. In addition, even when the voltage Vg is zero, the current Is increases in the negative direction as the voltage Vse increases in the negative direction. When the voltage Vg is zero, even when the voltage Vg is 15V, the negative direction of the current Ic increases sharply as the voltage Vse increases in the negative direction. It should be noted that the present invention is not limited to this example, and the sense semiconductor element portion 124 may not have the diode portion 81 but may be composed of only the transistor portion 71.

[0230] Fig.26 Yes means Fig.16 The illustrated semiconductor module 300 is a view of the vicinity of the circuit substrate 162 disposed on the most negative side in the Y-axis direction. Fig.26 The flow direction of the refrigerant flowing through the cooling unit 114 is also shown.

[0231] The active parts 120 of the semiconductor devices 100-1 and 100-2 arranged in the wiring pattern 170-1 are the same in area. Therefore, when the semiconductor devices 100-1 and 100-2 are operating, approximately the same current flows through the semiconductor devices 100-1 and 100-2, and approximately the same heat is generated. In order to suppress the heat generation to below the allowable temperature, the refrigerant is circulated from the refrigerant inlet 97 of the cooling part 114 to the refrigerant outlet 98 for cooling. Here, as described above, the refrigerant flows from the refrigerant inlet 97 to the refrigerant outlet 98, thereby being heated by the heat generated by the semiconductor devices 100-2 and 100-4 arranged on the other side (positive side of the X axis) of the predetermined flow path direction, and the semiconductor devices 100-1 and 100-3 arranged on one side (negative side of the X axis) of the predetermined flow path direction are cooled by the refrigerant having a higher temperature than the refrigerant inlet 97. Here, the other side is the upstream side, and the one side is the downstream side. Therefore, since the semiconductor devices 100 mounted on the semiconductor modules 300 and 400 are used within the permitted conditions (within the permitted temperature and the permitted current), it is sufficient to monitor only the detection unit 108 of the semiconductor device 100 disposed on the downstream side. Fig. 27 The details are explained below.

[0232] Fig. 27 It is expressed according to the position on the X-axis. Fig.26 FIG. 3 is a graph showing the temperature of the refrigerant in the semiconductor module 300. Fig. 27As shown, the temperature of the refrigerant in the refrigerant inlet 97 is set as temperature T1. The temperature of the refrigerant in the semiconductor device 100-2 arranged on the upstream side of the refrigerant is set as temperature T2. The temperature of the refrigerant in the semiconductor device 100-1 arranged on the downstream side of the refrigerant is set as temperature T3. The temperature of the refrigerant in the refrigerant outlet 98 is set as temperature T4.

[0233] From the refrigerant inlet 97 (see Fig.17 ) The refrigerant introduced by the semiconductor device 100-2 and the semiconductor device 100-4 cools down the semiconductor device 100-2 and the semiconductor device 100-4, so the temperature rises due to the cooling. Therefore, the temperature T2 is greater than the temperature T1. The refrigerant that has cooled down the semiconductor device 100-2 and the semiconductor device 100-4 subsequently cools down the semiconductor device 100-1 and the semiconductor device 100-3, so the temperature further rises due to the cooling. Therefore, the temperature T3 is greater than the temperature T2. Since there is no semiconductor device 100 in the refrigerant outlet 98, the temperature of the refrigerant that has cooled down the semiconductor device 100-1 and the semiconductor device 100-3 does not rise. Therefore, the temperature T4 is less than the temperature T3. Therefore, by monitoring the temperature T3 of the semiconductor device 100-1 and the semiconductor device 100-3, it is possible to determine whether each semiconductor device 100 is in an overheated state. The temperature T2 of the semiconductor device 100-2 and the semiconductor device 100-4 may not be monitored.

[0234] Fig.26 In the example, since the semiconductor device 100-1 and the semiconductor device 100-3 arranged on one side of the flow path direction of the refrigerant (the negative side of the X axis) are monitored to be in an overheated state, the detection pad 126 (the anode pad 119, the cathode pad 118, and the sensing emitter pad 122) is connected to the wiring pattern 166. The wiring pattern 166 is connected to the relay terminal 96 provided in the housing 88 of the semiconductor module 300, and the relay terminal 96 is connected to the control terminal 99. Thus, the overheated state of the semiconductor device 100 can be monitored from the outside of the semiconductor module 300.

[0235] Since the semiconductor device 100-2 and the semiconductor device 100-4 arranged on the other side (X-axis positive side) of the flow path direction of the refrigerant are not monitored to see if they are in an overheated state, the detection unit 108 of the semiconductor device 100-2 and the semiconductor device 100-4 can be invalidated. Specifically, the detection pad 126 may not be provided. In addition, since the detection pad 126 is not provided in the semiconductor device 100-2 and the semiconductor device 100-4, the wiring pattern 166, the relay terminal 96, and the control terminal 99 may not be provided.

[0236] In this example, the external wiring 130-1 connects the semiconductor devices 100-1 and 100-2 to the wiring pattern 170-2. The wiring pattern 170-2 is connected to the wiring pattern 169-1 disposed between the semiconductor devices 100-1 and 100-2, and the wiring pattern 169-1 is connected to one wiring pattern 166. The one wiring pattern 166 is connected to one relay terminal 96. In addition, the external wiring 130-2 connects the semiconductor devices 100-3 and 100-4 to the wiring pattern 168. The wiring pattern 168 is connected to the wiring pattern 169-2 disposed between the semiconductor devices 100-3 and 100-4, and the wiring pattern 169-2 is connected to another wiring pattern 166. The other wiring pattern 166 is connected to another relay terminal 96. In this example, the wiring pattern 169 is disposed between the two semiconductor devices 100 and functions as a relay terminal, thereby enabling the wiring pattern 166 to be disposed on the other side (X-axis positive side) of the coolant flow direction.

[0237] Since the semiconductor module 300 of this example does not have the detection pads 126 of the semiconductor devices 100-2 and 100-4, the corresponding wiring patterns 166, relay terminals 96, and control terminals 99 are not provided. Therefore, the number of control terminals 99 taken out of the semiconductor module 300 can be reduced, and the size can be reduced.

[0238] In the semiconductor module 300 of this example, both the temperature detection unit 110 and the sensing semiconductor element unit 124 are provided on the downstream side of the semiconductor device 100 of one arm arranged on the upstream and downstream sides of the refrigerant, but only one of them may be provided.

[0239] In this example, two semiconductor devices 100 are connected in parallel in one arm, but three or more semiconductor devices 100 may be connected in parallel. The more semiconductor devices 100 are arranged in one arm, the greater the miniaturization effect can be achieved by arranging the control terminal 99 on one side of the flow path direction of the refrigerant instead of on the other side. It should be noted that the predetermined flow path direction may be the side where the detection unit 108 is invalidated in advance as the upstream side, and the side where the signal from the detection unit 108 is taken out as the downstream side.

[0240] like Fig.26As shown, the wiring pattern 164 as the gate terminal of the semiconductor module 300 can be arranged between the semiconductor device 100-1 and the semiconductor device 100-2 in the flow direction of the refrigerant. The gate pad 116 of the semiconductor device 100-1 and the gate pad 116 of the semiconductor device 100-2 can be connected to the wiring pattern 164 as the gate terminal. By arranging the wiring pattern 164 as the gate terminal between the semiconductor device 100-1 and the semiconductor device 100-2 in the flow direction of the refrigerant, the semiconductor device 100-1 and the semiconductor device 100-2 can share the gate terminal. As a result, the number of gate terminals of the semiconductor module 300 can be reduced, and the miniaturization can be achieved.

[0241] The wiring pattern 164 as the gate terminal is connected to one wiring pattern 166 via the wiring 137. In addition, the one wiring pattern 166 is connected to one relay terminal 96 provided in the housing 88. The relay terminal 96 is connected to the control terminal 99 via the wiring 139. That is, the gate voltage is applied to the two semiconductor devices 100 via the control terminal 99, the wiring 139, the one relay terminal 96, the wiring 131, the one wiring pattern 166, the wiring 137, and the gate terminal 164.

[0242] Wiring 131, wiring 137, and wiring 139 may be metal wirings such as aluminum, copper, and / or gold. Wiring 137 may be thicker than wiring 131 and wiring 139. Since wiring 137 is longer than wiring 131 and wiring 139, heating caused by current in wiring 137, wiring 131, and wiring 139 is more likely to be greater, and wiring 137 is more likely to be disconnected. Therefore, by making wiring 137 thicker than wiring 131 and wiring 139, disconnection of wiring 137 can be suppressed.

[0243] like Fig.26 As shown, the semiconductor device 100-1 and the semiconductor device 100-2 can be arranged in such a manner that the gate pad 116 of one semiconductor device 100-2 and the gate pad 116 of the other semiconductor device 100-1 are opposed to each other in the flow direction of the refrigerant. That is, in the flow direction of the refrigerant, a wiring pattern 164 as a gate terminal can be arranged between the gate pad edge 117 of the semiconductor device 100-1 and the gate pad edge 117 of the semiconductor device 100-2. By arranging two semiconductor devices 100 in this way, the wiring between the gate pads 116 of the two semiconductor devices 100 and the wiring pattern 164 as the gate terminal can be shortened. In addition, since the gate terminal is shared with respect to the two semiconductor devices 100, the semiconductor module 300 can be miniaturized.

[0244] It should be noted that in the above-mentioned embodiment, the wiring 131 connected to the control terminal 99 is led out in the vertical direction (X-axis direction), but it is not limited to this example, and other configurations are also possible. For example, the wiring 131 can be led out in the left-right direction (Y-axis direction) from the semiconductor device 100. In addition, the control terminals 99 may not be arranged in a row in the Y-axis direction.

[0245] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the methods obtained by various changes or improvements are also included in the technical scope of the present invention.

[0246] It should be noted that the execution order of each process, such as actions, sequences, processes, and steps, in the apparatus, system, program, and method shown in the claims, specifications, and drawings should be implemented in any order, as long as it is not specifically stated as "earlier," "before," etc., and the output of the previous process is used in the subsequent process. Even if the action flow in the patent claims, specifications, and drawings is described using "first," "next," etc. for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: The semiconductor device includes a semiconductor substrate and: A transistor portion, which is disposed on the semiconductor substrate; a diode portion provided on the semiconductor substrate and arranged alternately with the transistor portion in an arrangement direction parallel to the upper surface of the semiconductor substrate; a temperature detection portion disposed above the upper surface of the semiconductor substrate and having a long side in a predetermined long side direction; an upper surface electrode disposed above the upper surface of the semiconductor substrate; as well as one or more external wirings including a connection portion connected to the upper surface electrode, the one or more external wirings electrically connecting the upper surface electrode to an external circuit of the semiconductor device, The one or more external wirings and the corresponding connection portions are arranged so as not to overlap with the temperature detection portion. The density of the connection portion increases within a predetermined distance range from the temperature detection portion, and the predetermined distance range is less than 5 times the arrangement period of the diode portion. The temperature detection unit is arranged so as to extend over one or more transistor units and one or more diode units in the longitudinal direction. The connection portion of at least one of the external wirings is arranged around the temperature detection unit in a plan view.

2. The semiconductor device according to claim 1, wherein: The connection portion of the at least one external wiring is arranged above one or more transistor portions and above one or more diode portions.

3. The semiconductor device according to claim 1, wherein: When the length of the temperature detection section in the longitudinal direction is defined as a detection section length, a distance between the connection portion of the at least one external wiring and the temperature detection section in a plan view is equal to or less than the detection section length.

4. The semiconductor device according to claim 2, wherein: When the length of the temperature detection section in the longitudinal direction is defined as a detection section length, a distance between the connection portion of the at least one external wiring and the temperature detection section in a plan view is equal to or less than the detection section length.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The diode units are arranged in the arrangement direction at the predetermined arrangement period.

6. The semiconductor device according to claim 5, wherein: The external wiring is a wire, A plurality of the external wirings are connected to the upper surface electrodes, The temperature detection portion is arranged so as to be sandwiched between any two of the connection portions within the predetermined distance range when viewed from above.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that The external wiring is a wire, When the long side length of the connection portion of the external wiring in a plan view is defined as a connection portion length, the distance between the connection portion of the at least one external wiring and the temperature detection portion in a plan view is less than or equal to the connection portion length.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that The external wiring is a wire, A plurality of the external wirings are connected to the upper surface electrodes, The connection portions of the respective external wirings are arranged at predetermined wiring intervals in a direction perpendicular to the long side direction, A distance between the connection portion of the at least one external wiring and the temperature detection unit in a plan view is equal to or smaller than the wiring interval.

9. The semiconductor device according to any one of claims 1 to 4, characterized in that The external wiring is a wire, The connection portion of at least one of the external wirings is provided so as to face the temperature detection portion in a direction perpendicular to the longitudinal direction in a plan view.

10. The semiconductor device according to claim 9, wherein: In a plan view, the two connection portions are arranged around the temperature detection portion and arranged along a direction parallel to the long side direction of the temperature detection portion. The two connection portions are arranged so as to face a portion of the temperature detection portion in the longitudinal direction, respectively.

11. The semiconductor device according to claim 9, wherein: In a plan view, the plurality of connection portions are arranged around the temperature detection portion. The temperature detection unit is arranged inside a rectangular region circumscribing the plurality of connection portions in a plan view.

12. The semiconductor device according to claim 10, wherein: In a plan view, the plurality of connection portions are arranged around the temperature detection portion. The temperature detection unit is arranged inside a rectangular region circumscribing the plurality of connection portions in a plan view.

13. The semiconductor device according to any one of claims 1 to 4, characterized in that The external wiring is a wire, In a plan view, the connection portions of the plurality of external wirings are arranged more around the temperature detection portion than in a region other than around the temperature detection portion.

14. The semiconductor device according to any one of claims 1 to 4, characterized in that The external wiring is a lead frame.

15. The semiconductor device according to claim 14, wherein: The connection portion of the external wiring has: two first portions arranged to sandwich the temperature detection portion in a direction perpendicular to the long side direction of the temperature detection portion; and The second part connects the two first parts.

16. The semiconductor device according to claim 15, wherein: The semiconductor device includes a temperature detection wiring provided above the upper surface of the semiconductor substrate and connected to the temperature detection unit. The second portion of the connection portion is disposed on the opposite side to the temperature detection wiring with respect to the temperature detection unit in a plan view.

17. The semiconductor device according to any one of claims 1 to 4, characterized in that have: a gate pad disposed above the upper surface of the semiconductor substrate and connected to the gate electrode of the transistor portion; a temperature detection wiring, which is provided above the upper surface of the semiconductor substrate and connected to the temperature detection unit, The gate pad is arranged on the opposite side of the temperature detection wiring with respect to the temperature detection portion in a plan view.

18. The semiconductor device according to claim 17, wherein: The semiconductor device includes a cathode pad and an anode pad which are provided above the upper surface of the semiconductor substrate and connected to the temperature detection wiring. The cathode pad and the anode pad are arranged on the opposite side of the gate pad with respect to the temperature detection unit.

19. A semiconductor package, characterized in that: have: The semiconductor device according to any one of claims 1 to 18; and The external circuit.

20. The semiconductor package according to claim 19, wherein The semiconductor package comprises two semiconductor devices. Each of the semiconductor devices comprises: a gate pad disposed above the upper surface of the semiconductor substrate and connected to the gate electrode of the transistor portion; a temperature detection wiring, which is disposed above the upper surface of the semiconductor substrate and connected to the temperature detection portion; as well as A cathode pad and an anode pad are disposed above the upper surface of the semiconductor substrate and connected to the temperature detection wiring. The gate pad is arranged on the opposite side of the temperature detection wiring in a plan view with respect to the temperature detection portion. The cathode pad and the anode pad are arranged on the opposite side of the gate pad with respect to the temperature detection unit. In each of the semiconductor devices, when the end side closest to the gate pad among the end sides when the semiconductor substrate is viewed from above is defined as a gate pad end side, the two semiconductor devices are arranged such that the gate pad end sides face each other.

21. A semiconductor module, characterized in that: have: a housing having control terminals; and The two semiconductor devices according to any one of claims 1 to 18 are arranged inside the housing and connected in parallel, The two semiconductor devices each have a detection unit. The housing has a cooling portion through which the refrigerant flows in a predetermined flow direction. The detection unit of the semiconductor device disposed on one side of the flow path direction is connected to the control terminal. The detection unit of the semiconductor device disposed on the other side in the flow path direction is not connected to the control terminal.

22. The semiconductor module according to claim 21, characterized in that The detection section is a temperature detection section or a sensing semiconductor element section that detects current.

23. The semiconductor module according to claim 21, characterized in that The housing has a refrigerant inlet for introducing the refrigerant and a refrigerant outlet for discharging the refrigerant. The side close to the refrigerant outlet is one side in the flow path direction, and the side close to the refrigerant inlet is the other side in the flow path direction.

24. The semiconductor module according to claim 22, characterized in that The housing has a refrigerant inlet for introducing the refrigerant and a refrigerant outlet for discharging the refrigerant. The side close to the refrigerant outlet is one side in the flow path direction, and the side close to the refrigerant inlet is the other side in the flow path direction.

25. The semiconductor module according to any one of claims 21 to 24, characterized in that: The semiconductor device disposed on one side of the flow path direction has a detection pad connected to the detection unit. The semiconductor device disposed on the other side in the flow path direction has no detection pad on the surface of the semiconductor device.

26. The semiconductor module according to any one of claims 21 to 24, characterized in that: The two semiconductor devices each have an emitter electrode, The detection portion of the semiconductor device disposed on the other side in the flow path direction is covered by the emitter electrode of the semiconductor device.

27. The semiconductor module according to any one of claims 21 to 24, characterized in that: The semiconductor module further includes a plurality of wiring patterns in which the two semiconductor devices are arranged. The plurality of control terminals are arranged in parallel on one side in the flow path direction.

28. The semiconductor module according to any one of claims 21 to 24, characterized in that: The two semiconductor devices have: a transistor portion; and a gate pad connected to a gate electrode of the transistor portion, The two semiconductor devices are arranged in parallel in the flow path direction, A gate terminal is provided between the two semiconductor devices in the flow path direction, The gate pads of the two transistor units are respectively connected to the gate terminals.

29. The semiconductor module according to claim 28, characterized in that The gate pad of one of the semiconductor devices and the gate pad of the other semiconductor device are arranged to face each other in the flow path direction.

30. The semiconductor module according to any one of claims 21 to 24, characterized in that: The active portions of the two semiconductor devices have the same area.

31. A semiconductor module, characterized in that: have: multiple wiring patterns; A semiconductor device, which is the semiconductor device according to any one of claims 1 to 18, arranged on the wiring pattern and having a surface plated; as well as a lead frame having one end bonded to the surface of the semiconductor device and the other end bonded to the wiring pattern, The lead frame includes a bridge portion protruding toward a side separated from a surface of the semiconductor device, an opening portion provided in the bridge portion, and a mold portion arranged above and below the bridge portion.

32. The semiconductor module according to claim 31, characterized in that The bridge portion is disposed between the one end and the other end, A plurality of the openings are provided.

33. The semiconductor module according to claim 31 or 32, characterized in that The semiconductor device includes a temperature detection unit above an upper surface of a semiconductor substrate. The lead frame is bonded to the surface of the semiconductor device via the temperature detection portion.

34. A semiconductor circuit device, characterized in that: have: A semiconductor device, which is the semiconductor device according to any one of claims 1 to 18; and Control circuit, The semiconductor device comprises: a main semiconductor element portion, which is provided on the semiconductor substrate and includes a transistor portion and a diode portion; and a sensing semiconductor element portion including another transistor portion provided on the semiconductor substrate and different from the transistor portion, and another diode portion different from the diode portion and arranged on the inner side of the other transistor portion, The control circuit comprises: a current detection circuit for detecting a forward current and a reverse current of the sensing semiconductor element portion; as well as A gate driving circuit outputs a signal according to the value of the reverse current.

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