Method and system for using camera device for deep channel and convolutional neural network images and formats

Abstract

Methods and systems for using a camera device for deep channel and convolutional neural network (CNN) images and formats are disclosed. In one example, image values ​​are captured by a color sensor array in an image capture device or camera. The image values ​​provide color channel data. The image values ​​captured by the color sensor array are input to a CNN having at least one CNN layer. The CNN provides CNN channel data for each layer. The color channel data and the CNN channel data are used to form a deep channel image stored in a memory. In another example, the image values ​​are captured by a sensor array. The image values ​​captured by the sensor array are input to a CNN having a first CNN layer. The image values ​​captured by the color sensor array are used to generate an output at the first CNN layer. The output of the first CNN layer is stored as a feature map of the captured image.

Description

Technical Field

[0001] Embodiments of the present invention are in the field of data processing, including image processing, graphics processing, and machine learning. More specifically, embodiments of the present invention relate to methods and systems for using camera devices for deep channel and convolutional neural network (CNN) images and formats. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently, some graphics processors have become programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques such as pipelining to attempt to process as much graphics data as possible in parallel throughout different parts of the graphics pipeline. Parallel graphics processors with a single instruction, multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as frequently as possible to improve processing efficiency. A general overview of the software and hardware for a SIMT architecture can be found in Shane Cook, CUDA Programming, Chapter 3, pages 37-51 (2013).

[0004] Machine learning has been successful in solving a variety of tasks. The calculations that occur when training and using machine learning algorithms (e.g., neural networks) are naturally suitable for efficient parallel implementation. Therefore, parallel processors such as general-purpose graphics processing units (GPGPUs) have played an important role in the actual implementation of deep neural networks. Parallel graphics processors with single instruction, multi-thread (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, parallel thread groups try to execute program instructions together synchronously as frequently as possible to improve processing efficiency. The efficiency provided by parallel machine learning algorithm implementations allows the use of high-capacity networks and enables those networks to be trained on larger data sets.

[0005] One type of neural network is a convolutional neural network (CNN), which can perform deep machine learning. The nodes in the input layer of a CNN are organized into a set of "filters" that can act as feature detectors. The output of each set of filters is propagated to the nodes in the successive layers of the network. Therefore, CNN is useful in computer vision and image recognition applications because of its feature detection capabilities. However, for image detection and processing applications, CNN processing can be processing and computationally intensive at each layer. In addition, image capture devices such as digital cameras are not easily integrated with deep machine learning capabilities on captured images. Therefore, what is needed is an image capture device integrated with a CNN that can provide deep machine learning feature detection capabilities during the image capture process and can reduce CNN calculations at the layer level. Summary of the invention

[0006] According to one aspect of the present invention, there is provided an image processing method, comprising: capturing image values ​​through a color sensor array, the image values ​​providing color channel data; inputting the image values ​​captured through the color sensor array into a convolutional neural network (CNN) having at least one CNN layer, the CNN providing CNN channel data for each layer; wherein the color channel data and the CNN channel data are used to form a depth channel image; and storing the depth channel image in a memory.

[0007] According to another aspect of the present invention, there is provided an image processing system, comprising: a sensor array for capturing image values, the image values ​​providing color channel data; a field programmable gate array (FPGA) programmed with a convolutional neural network (CNN) having at least one CNN layer, wherein the FPGA is used to: input the image values ​​captured by the color sensor array into the CNN convolutional neural network (CNN) having at least one CNN layer, and use the CNN to process the captured image values, and provide CNN channel data for each layer; and a memory for storing the color channel data and the CNN channel data, wherein the color channel data and the CNN channel data form a depth channel image.

[0008] According to yet another aspect of the present invention, there is provided an image processing system, comprising: a unit for capturing image values ​​through a color sensor array, the image values ​​providing color channel data; a unit for inputting the image values ​​captured through the color sensor array into a convolutional neural network (CNN) having at least one CNN layer, the CNN providing CNN channel data for each layer; wherein the color channel data and the CNN channel data are used to form a depth channel image; and

[0009] Means for storing said depth channel image in a memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings illustrate examples, and are therefore exemplary embodiments, and are not to be considered limiting in scope.

[0011] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the exemplary embodiments described herein.

[0012] Figures 2A-2D A parallel processor assembly according to an exemplary embodiment is shown.

[0013] Figure 3A-3B is a block diagram of a graphics multiprocessor according to an exemplary embodiment.

[0014] Figures 4A-4F An exemplary architecture is shown in which multiple graphics processing units (GPUs) are communicatively coupled to multiple multi-core processors.

[0015] Figure 5 A graphics processing pipeline is shown according to an exemplary embodiment.

[0016] Figure 6 A machine learning software stack according to an exemplary embodiment is shown.

[0017] Figure 7 A highly parallel general purpose graphics processing unit is shown in accordance with an exemplary embodiment.

[0018] Figure 8 A multi-GPU computing system is shown in accordance with an exemplary embodiment.

[0019] Figures 9A-9B The layers of an exemplary deep neural network are shown.

[0020] Fig.10 An exemplary recurrent neural network is shown.

[0021] Fig.11 An exemplary embodiment of the training and deployment of a deep neural network is shown.

[0022] Fig.12 is an exemplary block diagram illustrating distributed learning.

[0023] Fig.13 An exemplary inference system-on-chip (SOC) suitable for performing inference using a trained model is shown.

[0024] Fig.14 is an exemplary block diagram of an image capture system using a convolutional neural network (CNN) to store depth channel images.

[0025] Fig.15A flowchart showing exemplary operations for generating a depth channel image using a CNN.

[0026] Fig.16 An example diagram showing the portion where RGB and CNN channel data are stored as a depth channel image.

[0027] Fig.17 An exemplary system for storing feature maps using the first layer of a CNN for a camera device is shown.

[0028] Fig.18 A flowchart illustrating exemplary operations for storing feature maps using a first layer of a CNN for a camera device.

[0029] Fig.19 A block diagram of a processing system is shown according to an exemplary embodiment.

[0030] Fig. 20 An exemplary block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor is shown.

[0031] Fig.21 An exemplary block diagram of a graphics processor is shown.

[0032] Fig. 22 A block diagram of a graphics processing engine of a graphics processor according to an exemplary embodiment is shown.

[0033] Fig.23 A block diagram of another exemplary embodiment of a graphics processor is shown.

[0034] Fig.24 Thread execution logic is shown including an array of processing elements employed in an exemplary embodiment of a graphics processing engine (GPE).

[0035] Fig.25 A block diagram of a graphics processor instruction format is shown according to an exemplary embodiment.

[0036] Fig.26 A block diagram of an exemplary embodiment of a graphics processor is shown.

[0037] Fig.27A A block diagram of a graphics processor command format is shown according to an exemplary embodiment.

[0038] Fig.27B A block diagram of a graphics processor command sequence is shown according to an exemplary embodiment.

[0039] Fig.28 An exemplary graphics software architecture for a data processing system in accordance with an exemplary embodiment is shown.

[0040] Fig.29 A block diagram of an IP core development system that may be used to fabricate an integrated circuit (IC) to perform operations according to an exemplary embodiment is shown.

[0041] Fig.30 A block diagram of an exemplary system-on-chip IC that may be fabricated using one or more IP cores according to an exemplary embodiment is shown.

[0042] Fig.31 A block diagram of an exemplary graphics processor on a system-on-chip IC that may be fabricated using one or more IP cores according to an exemplary embodiment is shown.

[0043] Fig.32 A block diagram of an exemplary add-on graphics processor for a system-on-chip IC that may be fabricated using one or more IP cores according to an exemplary embodiment is shown. DETAILED DESCRIPTION

[0044] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the main processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0045] In some embodiments, the image capture device is a standalone device. However, the image capture device may be part or a subcomponent of another computing device that requires image capture capabilities, such as a portable or handheld computing device with a digital camera for capturing images.

[0046] In the following description, many specific details are set forth to provide a more thorough understanding. However, it will be apparent that the embodiments described herein can be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of the exemplary embodiments.

[0047] Computing System Overview

[0048] Figure 11 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the exemplary embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104 communicating via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component or may be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that may enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 may enable a display controller to provide output to one or more display devices 110A, which may be included in one or more processors 102. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0049] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a computationally focused parallel or vector processing system that includes a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 110B.

[0050] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 may be used to provide an interface mechanism to enable connection between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119 that may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 120. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0051] Computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 107. Figure 1 The communication paths for the various components in the system may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or any other bus or point-to-point communication interface and / or protocol, such as the NV-Link high-speed interconnect or an interconnect protocol known in the art.

[0052] In one embodiment, one or more parallel processors 112 include circuits optimized for graphics and video processing (including, for example, video output circuits), and constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 include circuits optimized for general-purpose processing while retaining the underlying computing architecture, which is described in more detail herein. In yet another embodiment, the components of the computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, memory hub 105, processor 102, and I / O hub 107 can be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0053] It should be appreciated that the computing system 100 shown herein is illustrative, and variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112, may be modified as desired. For example, in some embodiments, the system memory 104 is directly connected to the processor 102 instead of through a bridge, and other devices communicate with the system memory 104 via the memory hub 105 and the processor 102. In other alternative topologies, the parallel processors 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102, rather than being connected to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. Some embodiments may include two or more groups of processors 102 attached via multiple sockets, which may be coupled to two or more instances of the parallel processor 112.

[0054] Some of the specific components shown herein are optional and may not be included in all embodiments of computing system 100. For example, any number of add-in cards or peripherals may be supported, or some components may be eliminated. In addition, some architectures may be specific to the Figure 1 Components that are similar are shown using different terminology. For example, memory hub 105 may be referred to as a north bridge in some architectures, while I / O hub 107 may be referred to as a south bridge.

[0055] Figure 2A 2 shows a parallel processor 200 according to an exemplary embodiment. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). The parallel processor 200 shown is a processor according to an exemplary embodiment. Figure 1 Variations of the one or more parallel processors 112 shown.

[0056] In one embodiment, parallel processor 200 includes parallel processing unit 202. Parallel processing unit includes I / O unit 204, which enables communication with other devices, including other instances of parallel processing unit 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 is connected to other devices via the use of a hub or switch interface (e.g., memory hub 105). The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within parallel processing unit 202, I / O unit 204 is connected to host interface 206 and memory crossbar 216, wherein host interface 206 receives commands directed to perform processing operations, and memory crossbar 216 receives commands directed to perform memory operations.

[0057] When the host interface 206 receives the command buffer via the I / O unit 204, the host interface 206 can direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210, which is configured to distribute commands or other work items to the processing cluster array 212. In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is properly configured and in a valid state before tasks are distributed to the processing clusters of the processing cluster array 212. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity to achieve fast preemption and context switching of threads executed on the processing array 212. In one embodiment, the host software can prove the workload for scheduling on the processing array 212 via one of a plurality of graphics processing doorbells. The workload can then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0058] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B to cluster 214N). Each cluster 214A-214N in the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or work distribution algorithms to assign work to the clusters 214A-214N of the processing cluster array 212, which may vary depending on the workload generated for each type of program or calculation. Scheduling may be handled dynamically by the scheduler 210, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 212. In one embodiment, different clusters 214A-214N of the processing cluster array 212 may be assigned to process different types of programs or to perform different types of calculations.

[0059] Processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations (including physics operations), and performing data transformations.

[0060] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute shader programs associated with graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored to on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0061] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable graphics processing operations to be distributed to multiple clusters 214A-214N of processing cluster array 212. In some embodiments, portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N can be stored in a buffer to allow the intermediate data to be sent between clusters 214A-214N for further processing.

[0062] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, and state parameters and commands defining how the data is to be processed (e.g., what program to execute). The scheduler 210 may be configured to obtain an index corresponding to a task, or may receive an index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.) is initiated.

[0063] Each of the one or more instances of the parallel processing unit 202 can be coupled to a parallel processor memory 222. The parallel processor memory 222 can be accessed via a memory crossbar switch 216, which can receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar switch 216 can access the parallel processor memory 222 via a memory interface 218. The memory interface 218 can include a plurality of partition units (e.g., partition unit 220A, partition unit 220B to partition unit 220N), each of which can be coupled to a portion of the parallel processor memory 222 (e.g., a memory unit). In one embodiment, the number of partition units 220A-220N is configured to be equal to the number of memory units, such that a first partition unit 220A has a corresponding first memory unit 224A, a second partition unit 220B has a corresponding memory unit 224B, and an Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0064] In various embodiments, the memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A-224N may vary and may be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps may be stored across the memory units 224A-224N to allow the partition units 220A-220N to write portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In an embodiment, local instances of the parallel processor memory 222 may be excluded to facilitate the unified memory design of the system memory in conjunction with the local cache memory.

[0065] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process data to be written to any memory unit 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to transmit the output of each cluster 214A-214N to any partition unit 220A-220N or to another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with a memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has a connection to the memory interface 218 to communicate with the I / O unit 204, and a connection to a local instance of the parallel processor memory 222 to enable the processing units within different processing clusters 214A-214N to communicate with the system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 may use virtual channels to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N.

[0066] Although a single instance of parallel processing unit 202 is shown in parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single add-on card, or multiple add-on cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, and in one embodiment, some instances of parallel processing unit 202 may include floating point units with higher precision relative to other instances. Systems comprising one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in various configurations and form factors, including but not limited to desktop, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0067] Figure 2B is a block diagram of a partition unit 220 according to an exemplary embodiment. In one embodiment, the partition unit 220 is Figure 2A220N. As shown, partition unit 220 includes L2 cache 221, frame buffer interface 225, and ROP 226 (raster operation unit). L2 cache 221 is a read / write cache that is configured to perform load and store operations received from memory crossbar switch 216 and ROP 226. Read misses and urgent writeback requests are output to frame buffer interface 225 via L2 cache 221 for processing. Updates can also be sent to the frame buffer via frame buffer interface 225 for processing. In one embodiment, frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory, such as Figure 2A Memory units 224A-224N (eg, within parallel processor memory 222).

[0068] In graphics applications, ROP 226 is a processing unit that performs raster operations (e.g., stencil, z-test, blending, etc.). ROP 226 then outputs processed graphics data that is stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic can be lossless compression logic that utilizes one or more of a plurality of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0069] In some embodiments, ROP 226 is included in each processing cluster (e.g., Figure 2A 214A-214N) rather than within partition unit 220. In such an embodiment, read and write requests for pixel data are sent through memory crossbar switch 216 rather than pixel fragment data. The processed graphics data may be displayed on a display device, such as Figure 1 One of the one or more display devices 110A and 110B is routed for further processing by the processor 102, or is routed for Figure 2A One of the processing entities within parallel processor 200 further processes.

[0070] Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit according to an exemplary embodiment. In one embodiment, a processing cluster is Figure 2AAn instance of one of the processing clusters 214A-214N. Processing cluster 214 can be configured to execute multiple threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a specific input data set. In some embodiments, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, a common instruction unit is used, and a single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of usually synchronized threads, and the common instruction unit is configured to issue instructions to a group of processing engines in each processing cluster in the processing cluster. Unlike the SIMD execution mechanism (wherein all processing engines usually execute the same instructions), SIMT execution allows different threads to more easily follow different execution paths through a given thread program. It will be appreciated by those skilled in the art that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0071] The operation of the processing cluster 214 may be controlled via a pipeline manager 232, which distributes processing tasks to SIMT parallel processors. The pipeline manager 232 Figure 2A The scheduler 210 receives instructions and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures may be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 may be included in the processing cluster 214. The graphics multiprocessor 234 may process data, and the data crossbar 240 may be used to distribute the processed data to one of a plurality of possible destinations, including other shader units. The pipeline manager 232 may facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via the data crossbar 240.

[0072] Each graphics multiprocessor 234 within a processing cluster 214 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner in which a new instruction may be issued before a previous instruction is completed. The function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0073] The instructions sent to the processing cluster 214 constitute threads. A group of threads executed across the group of parallel processing engines is a thread group. The thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 234. The thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 234. When the thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle that the thread group is being processed. The thread group may also include more threads than the number of processing engines within the graphics multiprocessor 234. When the thread group includes more threads than the number of processing engines within the graphics multiprocessor 234, processing may be performed on consecutive clock cycles. In one embodiment, multiple thread groups may be executed concurrently on the graphics multiprocessor 234.

[0074] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 may abandon the internal cache and use the cache memory (e.g., L1 cache 248) within the processing cluster 214. Each graphics multiprocessor 234 also has a partition unit (e.g., Figure 2A 20N) that are shared among all processing clusters 214 and can be used to transfer data between threads. Graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data that can be stored in L1 cache 248.

[0075] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses into physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2 . The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses and optional cache line indexes for slices (more on slices below). The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. Processing physical addresses to distribute surface data access locality to allow efficient request interleaving between partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0076] In graphics and computing applications, the processing clusters 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from an L1 cache within the graphics multiprocessor 234 and fetched from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to a ROP unit, which may be located with a partition unit as described herein (e.g., partition units 220A-220N of FIG. 2 ). The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translations.

[0077] It should be appreciated that the core architecture described herein is illustrative, and variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within processing cluster 214. Furthermore, while only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0078] Figure 2D A graphics multiprocessor 234 is shown according to an exemplary embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0079] In one embodiment, the instruction cache 252 receives an instruction stream to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch the instructions into thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. The instruction can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0080] Register file 258 provides a set of registers for the functional units of graphics multiprocessor 234. Register file 258 provides temporary storage for operands for data paths of functional units (e.g., GPGPU core 262, load / store unit 266) connected to graphics multiprocessor 234. In one embodiment, register file 258 is divided between each of the functional units so that each functional unit is assigned a dedicated portion of register file 258. In one embodiment, register file 258 is divided between different warps executing by graphics multiprocessor 234.

[0081] Each GPGPU core 262 may include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 234. Depending on the embodiment, the GPGPU core 262 may be similar in architecture or may be different in architecture. For example, and in one embodiment, the first part of the GPGPU core 262 includes a single-precision FPU and an integer ALU, and the second part of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or implement variable-precision floating-point arithmetic. The graphics multiprocessor 234 may additionally include one or more fixed-function or special-function units to perform specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more GPGPU cores in the GPGPU core may also include fixed or special-function logic.

[0082] In one embodiment, GPGPU core 262 includes SIMD logic that can execute single instruction to multiple groups of data. In one embodiment, GPGPU core 262 can physically execute SIMD4, SIMD8 and SIMD16 instructions and logically execute SIMD1, SIMD2 and SIMD32 instructions. SIMD instructions for GPGPU core can be generated by shader compiler at compile time, or automatically generated when executing a program written and compiled for single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for SIMT execution model can be executed via a single SIMD instruction. For example, and in one embodiment, eight SIMT threads performing the same or similar operation can be executed in parallel via a single SIMD8 logic unit.

[0083] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so that the latency of data transfer between the GPGPU core 262 and the register file 258 is very low. The shared memory 270 can be used to implement communication between threads executed on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used as, for example, a data cache to cache texture data transferred between the functional units and the texture unit 236. The shared memory 270 can also be used as a cache managed by the program. In addition to the automatically cached data stored in the cache memory 272, threads executed on the GPGPU core 262 can also programmatically store data in the shared memory.

[0084] Figure 3A-3B Additional graphics multiprocessors are shown according to an exemplary embodiment. The graphics multiprocessors 325, 350 shown are Figure 2C-2D The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0085] Figure 3A A graphics multiprocessor 325 is shown according to an additional exemplary embodiment. The graphics multiprocessor 325 includes a processor with respect to Figure 2C-2DThe graphics multiprocessor 325 may include multiple additional instances of the execution resource unit of the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture units 344A-344B. The graphics multiprocessor 325 also includes multiple groups of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple groups of load / store units 340A-340B. In one embodiment, the execution resource unit has a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346.

[0086] Various components may communicate via interconnect structure 327. In one embodiment, interconnect structure 327 includes one or more crossbar switches to enable communication between various components of graphics multiprocessor 325. In one embodiment, interconnect structure 327 is a separate high-speed network fabric layer on which each component of graphics multiprocessor 325 is stacked. Components of graphics multiprocessor 325 communicate with remote components via interconnect structure 327. For example, GPGPU cores 336A-336B, 337A-337B, and 338A-338B may each communicate with shared memory 346 via interconnect structure 327. Interconnect structure 327 may arbitrate communications within graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0087] Figure 3B A graphics multiprocessor 350 according to an additional exemplary embodiment is shown. The graphics processor includes multiple sets of execution resources 356A-356D, wherein each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load storage units, such as Figure 2D and Figure 3A Execution resources 356A-356D may collaborate with texture units 360A-360D for texture operations while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A-356D may share instruction cache 354 and shared memory 362, as well as multiple instances of texture and / or data caches 358A-358B. The various components may communicate with each other via Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352 .

[0088] Those skilled in the art will understand that Figure 1 , 2AThe architectures described in -2D and 3A-3B are illustrative and not limiting of the scope of the present embodiments, which are exemplary. Therefore, without departing from the scope of the embodiments described herein, the techniques described herein may be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (e.g., parallel processing unit 202 of FIG. 2 ), and one or more graphics processors or special processing units.

[0089] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the main processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal (i.e., package or chip internal) processor bus / interconnect. Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a command / instruction sequence contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0090] Technologies for GPU to host processor interconnect

[0091] Figure 4A An exemplary architecture is shown in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 429, 440, 442, and 443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, depending on the implementation, high-speed links 429, 440, 442, and 443 support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the invention are not limited to any particular communication protocol or throughput.

[0092] Additionally, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444 and 449, which may be implemented using the same or different protocols / links as used for high-speed links 429, 440, 442, and 443. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A All communications between the various system components shown may be accomplished using the same protocols / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0093] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453. Memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM) and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portions of the memory may be volatile memory, while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0094] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific memories 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among all of the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0095] Figure 4BAdditional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to an exemplary embodiment are shown. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0096] The processor 407 shown includes a plurality of cores 460A-460D, each of which has a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The core may include various other components for executing instructions and processing data, which are not shown to avoid obscuring the basic principles of the present invention (such as other components such as fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.). Caches 462A-462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by multiple groups of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each of which has its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441, which may include the processor memories 401-402.

[0097] Via inter-core communications on the coherence bus 464, coherence is maintained for data and instructions stored in the various caches 462A-462D, 456, and the system memory 441. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 464 in response to a detected read or write to a particular cache line. In one embodiment, a cache snooping protocol is implemented on the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well known to those skilled in the art and will not be described in detail here to avoid obscuring the underlying principles of the present invention.

[0098] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the consistency bus 464 to allow the graphics acceleration module 446 to participate in the cache consistency protocol as a peer of the core. Specifically, the interface 435 provides a connection to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0099] In one embodiment, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431-432, N, or the graphics processing engines 431-432, N may be individual GPUs integrated on a common package, line card, or chip.

[0100] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation) and a memory access protocol for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one embodiment, the cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. In one embodiment, the data stored in the cache 438 and the graphics memory 433-434, N is kept consistent with the core caches 462A-462D, 456 and the system memory 441. As described above, this may be accomplished via proxy circuitry 425 that participates in cache coherence mechanisms on behalf of cache 438 and memories 433-434, N (e.g., sending updates to cache 438 associated with modifications / accesses of cache lines on processor caches 462A-462D, 456 and receiving updates from cache 438).

[0101] A set of registers 445 stores context data for threads executed by the graphics processing engines 431-432, N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 may perform save and restore operations to save and restore contexts for various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, context management circuitry 448 may store current register values ​​to a specified area in memory (e.g., identified by a context pointer). Then, upon returning to context, context management circuitry 448 may restore the register values. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0102] In one embodiment, the virtual / effective address from the graphics processing engine 431 is converted to an actual / physical address in the system memory 441 by the MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executed on the processor 407, or can be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented, in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). Resources can be subdivided into "slices", which are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0103] Thus, the accelerator integrated circuit acts as a bridge to the system for the graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management of the graphics processing engine.

[0104] Because the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, N so that they appear to be independent units to the system.

[0105] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0106] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that the data stored in graphics memory 433-434, M is the data most frequently used by graphics processing engines 431-432, N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by a core (and preferably not graphics processing engines 431-432, N) within the core's cache 462A-462D, 456 and system memory 441.

[0107] Figure 4C Another exemplary embodiment is shown in which an accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via interface 437 and interface 435 (again, which can utilize any form of bus or interface protocol) through a high-speed link 440. The accelerator integrated circuit 436 can perform operations related to Figure 4B The same operation is described, but with potentially higher throughput given its proximity to the coherency bus 464 and caches 462A-462D, 426.

[0108] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0109] In one embodiment of a dedicated process model, the graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to the graphics engines 431-432, N to provide virtualization within a VM / partition.

[0110] In a dedicated process programming model, graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize graphics processing engines 431-432, N to allow access by each operating system. For a single partition system without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each process or application.

[0111] For the shared programming model, the graphics acceleration module 446 or individual graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, the process element is stored in the system memory 441 and can be addressed using the effective address to real address conversion techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, N (i.e., calling the system software to add the process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0112] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 441 stores process elements 483. In one embodiment, the process element 483 is stored in response to a GPU call 481 from an application 480 executed on the processor 407. The process element 483 contains the process state of the corresponding application 480. The work descriptor (WD) 484 contained in the process element 483 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application address space 482.

[0113] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N may be shared by all or some of the processes in the system. Embodiments of the present invention include infrastructure for establishing process state and sending WD 484 to graphics acceleration module 446 to launch jobs in a virtualized environment.

[0114] In one embodiment, a dedicated process programming model is implementation specific. In this model, a single process owns the graphics acceleration module 446 or individual graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, when the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition and the operating system initializes the accelerator integrated circuit 436 for the owning process.

[0115] In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an indication of the work to be completed by one of the graphics processing engines of the graphics acceleration module 446. The data from the WD 484 can be stored in the register 445 and used by the MMU 439, the interrupt management circuit 447 and / or the context management circuit 448, as shown. For example, one embodiment of the MMU 439 includes a segment / page walk circuitry for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can handle the interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engine 431-432, N is converted to an actual address by the MMU 439.

[0116] In one embodiment, for each graphics processing engine 431-432, N and / or graphics acceleration module 446, the same set of registers 445 is duplicated and can be initialized by a hypervisor or operating system. Each of these duplicate registers can be included in an accelerator integrated slice 490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0117] Table 1 - Registers initialized by the hypervisor

[0118] 1 Chip Control Register 2 Real Address (RA) dispatched process area pointer 3 Permission Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt Vector Table Entry Limits 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0119] Exemplary registers that may be initialized by the operating system are shown in Table 2.

[0120] Table 2 - Registers initialized by the operating system

[0121] 1 Process and thread identities 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) stores the segment table pointer 5 Permission Mask 6 Job Descriptor

[0122] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information needed by the graphics processing engine 431-432, N to perform its work, or it may be a pointer to a memory location of a command queue where the application has set up work to be done.

[0123] Figure 4E Additional details of an exemplary embodiment of a sharing model are shown. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes the graphics acceleration module engine to an operating system 495.

[0124] The shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics-oriented sharing.

[0125] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization through the hypervisor 496, the graphics acceleration module 446 may be subject to the following requirements: 1) The application's job request must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 guarantees that the application's job request is completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 446 provides the ability to preempt job processing. 3) When operating in a directed shared programming model, the graphics acceleration module 446 must be guaranteed fairness between processes.

[0126] In one embodiment, for the shared model, the application 480 is required to make an operating system 495 system call with a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the following forms: a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure used to describe the work to be completed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the user authority mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current permission mask override register (AMOR) value before placing the AMR into the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the application's address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if no state needs to be saved between jobs or when a job is preempted. The context save / restore area may be pinned system memory.

[0127] Upon receiving the system call, the operating system 495 may verify that the application 480 has been registered and given permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 with the information shown in Table 3.

[0128] Table 3 - OS to Hypervisor Call Parameters

[0129] 1 Work Descriptor (WD) 2 The value of the permission mask register (AMR) (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Processor ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0130] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has been registered and given permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into a linked list of process elements for the corresponding type of graphics acceleration module 446. The process element may include the information shown in Table 4.

[0131] Table 4 - Process element information

[0132]

[0133]

[0134] In one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 490 registers 445 .

[0135] like Figure 4F As shown, an exemplary embodiment of the present invention employs a unified memory that is addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this embodiment, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. Thus, the entire virtual / effective memory space (sometimes referred to as the effective address space) is distributed across each of processor memories 401-402 and GPU memories 420-423 to allow any processor or GPU to access any physical memory with a virtual address mapped to that memory.

[0136] In one embodiment, bias / coherency management circuits 494A-494E within one or more of MMUs 439A-439E ensure cache coherency between caches of the host processor (e.g., 405) and GPUs 410-413 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Figure 4F Multiple instances of bias / consistency management circuits 494A- 494E are shown in , but the bias / consistency circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436 .

[0137] One embodiment allows GPU-attached memory 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering from the typical performance drawbacks associated with full system cache coherence. The ability to access GPU-attached memory 420-423 as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows the host processor 405 software to set operands and access calculation results without the overhead of traditional I / O DMA data copying. This traditional copying involves driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherence overhead may be critical to the execution time of the offloaded calculation. For example, in the case of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 410-413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU calculation all play a role in determining the effectiveness of GPU offloading.

[0138] In one embodiment, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table may be used, which may be a page granular structure comprising 1 or 2 bits per GPU attached memory page (i.e., controlled at the granularity of a memory page). With or without a bias cache in the GPU 410-413 (e.g., for caching frequently / recently used entries of the bias table), the bias table may be implemented in a stolen memory range of one or more GPU attached memories 420-423. Alternatively, the entire bias table may be maintained within the GPU.

[0139] In one embodiment, the bias table entry associated with each access to the GPU attached memory 420-423 is accessed before the actual access to the GPU memory, resulting in the following operations. First, local requests from GPUs 410-413 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPUs whose pages are found in the host bias are forwarded to the processor 405 (e.g., via a high-speed link as described above). In one embodiment, requests from processor 405 to find the requested page in the host processor bias complete the request like a regular memory read. Alternatively, requests for GPU bias pages can be forwarded to GPUs 410-413. The GPU can then convert the page to the host processor bias if it is not currently using the page.

[0140] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, by a purely hardware-based mechanism.

[0141] One mechanism for changing the bias state employs an API call (e.g., OpenCL) which in turn calls the GPU's device driver, which in turn sends a message to the GPU (or queues a command descriptor) to direct the GPU to change the bias state, and for some transitions, performs a cache flush operation in the host. The cache flush operation is required for a transition from a host processor 405 bias to a GPU bias, but not for the reverse transition.

[0142] In one embodiment, cache coherency is maintained by temporarily presenting GPU biased pages that are not cacheable by the host processor 405. To access these pages, the processor 405 may request access from the GPU 410, which may or may not immediately grant access, depending on the implementation. Therefore, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that the GPU biased pages are pages that are needed by the GPU and not the host processor 405, and vice versa.

[0143] Graphics processing pipeline

[0144] Figure 5 500 is shown according to an exemplary embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein, such as Figure 2A In one embodiment, the parallel processor 200 is Figure 1 Variations of the parallel processor 112 of FIG. Various parallel processing systems can be implemented via parallel processing units (e.g., Figure 2A The graphics processing pipeline 500 may be implemented using one or more instances of a parallel processing unit 202 of the graphics processing unit. For example, a shader unit (e.g., Figure 2C-2D The graphics multiprocessor 234 of the embodiment of the present invention may be configured to perform the functions of one or more of the following: the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be implemented by processing clusters and corresponding partitioning units (e.g., Figure 2Aother processing engines within the partition units 220A-220N) to execute (for example, Figure 2A The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., such as a CPU) via a memory interface 528. Figure 2A The parallel processor memory 222 in the memory interface 528 may be Figure 2A An example of a memory interface 218 .

[0145] In one embodiment, data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. Data assembler 502 then outputs vertex data including vertex attributes to vertex processing unit 504. Vertex processing unit 504 is a programmable execution unit that executes vertex shader programs to light and transform vertex data specified by vertex shader programs. Vertex processing unit 504 reads data stored in cache, local or system memory for processing vertex data, and can be programmed to transform vertex data from object-based coordinate representation to world space coordinate space or standardized device coordinate space.

[0146] The first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc., which are supported by various graphics processing application programming interfaces (APIs).

[0147] The tessellation control processing unit 508 treats the input vertices as control points of a geometry patch. The control points are transformed from an input representation from the patch (e.g., a basis for the patch) to a representation suitable for use in surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometry patch. The tessellation factors are applied to individual edges and quantize the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the patch edges and tessellate the patch into a plurality of geometric primitives, such as line, triangle, or quadrilateral primitives, which are sent to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0148] The second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to tessellate graphics primitives into one or more new graphics primitives and calculate parameters for rasterizing the new graphics primitives.

[0149] In some embodiments, the geometry processing unit 516 can add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or the system memory for processing the geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0150] The rasterizer 522 can perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit that is configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to generate shaded fragments or pixels output to the raster operation unit 526. The fragment / pixel processing unit 524 can read data stored in a parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade with samples, pixels, tiles, or other granularity depending on the sampling rate configured for the processing unit.

[0151] Raster operations unit 526 is a processing unit that performs raster operations including but not limited to stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data to be stored in a graphics memory (e.g., Figure 2A The parallel processor memory 222 and / or Figure 1Raster operations unit 526 may be configured to compress z or color data written to memory and decompress z or color data read from memory.

[0152] Machine Learning Overview

[0153] A machine learning algorithm is an algorithm that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a data set. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numerical value given an input; and a pattern recognition algorithm can be used to generate converted text or perform text-to-speech and / or speech recognition.

[0154] An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating output in the output layer. The nodes of the network are fully connected to the nodes in the adjacent layers via edges, but there are no edges between nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes of each successive layer in the network based on coefficients ("weights") associated with each edge connecting the layers. Depending on the specific model represented by the algorithm being executed, the output from the neural network algorithm can take a variety of forms.

[0155] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves selecting a network topology, using a training data set that represents the problem being modeled by the network, and adjusting weights until the network model behaves with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output produced by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and the weights associated with the connections are adjusted to minimize the error as the error signal propagates back through the layers of the network. The network is considered "trained" when the error for each output generated from an instance of the training data set is minimized.

[0156] The quality of the data set used to train the algorithm can significantly affect the accuracy of the machine learning algorithm. The training process can be computationally intensive and may take a lot of time on a traditional general-purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, because the calculations performed when adjusting the coefficients in the neural network are naturally suitable for parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to take advantage of the parallel processing hardware in general-purpose graphics processing devices.

[0157] Figure 6 6 is a generalized diagram of a machine learning software stack 600. Machine learning applications 602 may be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. Machine learning applications 602 may include training and inference functions for a neural network and / or specialized software that may be used to train a neural network prior to deployment. Machine learning applications 602 may implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0158] Hardware acceleration for machine learning applications 602 can be implemented via a machine learning framework 604. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are basic operations that are typically performed by machine learning algorithms. Without the machine learning framework 604, developers of machine learning algorithms will need to create and optimize the main computing logic associated with the machine learning algorithm, and then re-optimize the computing logic when developing new parallel processors. Instead, machine learning applications can be configured to use the primitives provided by the machine learning framework 604 to perform the necessary calculations. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations that are performed while training a convolutional neural network (CNN). The machine learning framework 604 can also provide primitives to implement basic linear algebra subroutines, such as matrix and vector operations, that are performed by many machine learning algorithms.

[0159] The machine learning framework 604 can process input data received from the machine learning application 602 and generate appropriate inputs to the computation framework 606. The computation framework 606 can abstract the underlying instructions provided to the GPGPU driver 608 to enable the machine learning framework 604 to take advantage of hardware acceleration via the GPGPU hardware 610 without requiring the machine learning framework 604 to have extensive knowledge of the architecture of the GPGPU hardware 610. In addition, the computation framework 606 can implement hardware acceleration for the machine learning framework 604 across various types and generations of GPGPU hardware 610.

[0160] GPGPU machine learning acceleration

[0161] Figure 7 A highly parallel general purpose graphics processing unit 700 is shown in accordance with an exemplary embodiment. In one embodiment, a general purpose processing unit (GPGPU) 700 can be configured to be particularly efficient in processing the type of computational workload associated with training deep neural networks. Additionally, a GPGPU 700 can be directly linked to other instances of a GPGPU to create a multi-GPU cluster to improve training speed for particularly deep neural networks.

[0162] GPGPU 700 includes a host interface 702 to enable connection to a host processor. In one embodiment, host interface 702 is a PCI Express interface. However, the host interface may also be a vendor-specific communication interface or communication structure. GPGPU 700 receives commands from the host processor and distributes execution threads associated with those commands to a set of computing clusters 706A-H using a global scheduler 704. Computing clusters 706A-H share a cache memory 708. Cache memory 708 may act as a higher-level cache for cache memories within computing clusters 706A-H.

[0163] GPGPU 700 includes memory 714A-B coupled to computing cluster 706A-H via a set of memory controllers 712A-B. In various embodiments, memory 714A-B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory unit 224A-N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0164] In one embodiment, each computing cluster 706A-H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessors of the compute clusters include multiple types of integer and floating point logic units that can perform computational operations with a range of precisions suitable for machine learning computations. For example, and in one embodiment, at least a subset of the floating point units in each of the compute clusters 706A-H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units can be configured to perform 64-bit floating point operations.

[0165] Multiple instances of GPGPU 700 can be configured to act as a computing cluster. The communication mechanism used by the computing cluster for synchronization and data exchange varies from embodiment to embodiment. In one embodiment, multiple instances of GPGPU 700 communicate through a host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709, which couples GPGPU 700 with a GPU link 710, which implements a direct connection to other instances of GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU to GPU bridge, which implements communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 700 are located in separate data processing systems and communicate via a network device accessible via a host interface 702. In one embodiment, in addition to or in lieu of host interface 702, GPU link 710 can be configured to implement a connection to a host processor.

[0166] Although the illustrated configuration of GPGPU 700 can be configured to train neural networks, one embodiment provides an alternative configuration of GPGPU 700 that can be configured for deployment within a high-performance or low-power reasoning platform. In the reasoning configuration, GPGPU 700 includes fewer computing clusters 706A-H relative to the training configuration. In addition, the memory technology associated with memory 714A-B can be different between the reasoning configuration and the training configuration. In one embodiment, the reasoning configuration of GPGPU 700 can support reasoning-specific instructions. For example, the reasoning configuration can provide support for one or more 8-bit integer dot product instructions, which are typically used for reasoning operations during deployed neural networks.

[0167] Figure 8 A multi-GPU computing system 800 is shown according to an exemplary embodiment. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI express switch device that couples the processor 802 to a PCI express bus, through which the processor 802 can communicate with the set of GPGPUs 806A-D. Each of the plurality of GPGPUs 806A-D may be a Figure 7 GPGPU 700 of the embodiment. GPGPU 806A-D can be interconnected via a set of high-speed point-to-point GPU to GPU links 816. High-speed GPU to GPU links can be connected via dedicated GPU links (e.g., Figure 7806A-D. The P2P GPU link 816 enables direct communication between each of the GPGPUs 806A-D without the need to communicate through a host interface bus to which the processor 802 is connected. With GPU-to-GPU traffic directed to the P2P GPU link, the host interface bus remains available for system memory access or communication with other instances of the multi-GPU computing system 800 (e.g., via one or more network devices). Although in the illustrated embodiment, the GPGPUs 806A-D are connected to the processor 802 via the host interface switch 804, in one embodiment, the processor 802 includes direct support for the P2P GPU link 816 and can be directly connected to the GPGPUs 806A-D.

[0168] Machine Learning Neural Network Implementation

[0169] The computing architecture provided by the embodiments described herein can be configured to perform parallel processing of a type particularly suitable for training and deploying neural networks for machine learning. Neural networks can be generalized as networks of functions with graphical relationships. As is known in the art, there are various types of neural network implementations for use in machine learning. One exemplary type of neural network is a feedforward network, as previously described.

[0170] The second exemplary type of neural network is a convolutional neural network (CNN). CNN is a specialized feedforward neural network that is used to process data with a known grid-like topology, such as image data. Therefore, CNNs are commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to the nodes in the successive layers of the network. The calculation of a CNN includes applying a convolution mathematical operation to each filter to produce the output of the filter. Convolution is a special type of mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to a convolution layer can be a multidimensional data array that defines the various color components of the input image. The convolution kernel can be a multidimensional parameter array, where the parameters are adapted through the training process of the neural network.

[0171] Recurrent neural networks (RNNs) are a family of feedforward neural networks that include feedback connections between layers. RNNs achieve modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture for RNNs includes loops. Loops represent the effect of the current value of a variable on its own value at a future time, because at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature of the language data that can be composed.

[0172] The accompanying drawings described below present exemplary feedforward, CNN and RNN networks, and describe the general process of training and deploying each of these types of networks, respectively. It should be understood that these descriptions are exemplary and non-limiting to any specific embodiment described herein, and the concepts shown can be generally applied to deep neural networks and machine learning techniques.

[0173] The above exemplary neural network can be used to perform deep learning. Deep learning is machine learning using deep neural networks. A deep neural network used in deep learning is an artificial neural network composed of multiple hidden layers, as opposed to a shallow neural network that includes only a single hidden layer. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output errors relative to shallow machine learning techniques.

[0174] A deep neural network for deep learning typically includes a front-end network for performing feature recognition coupled to a back-end network that represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning allows machine learning to be performed without the need to perform handcrafted feature engineering for the model. Instead, a deep neural network can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map detected features to outputs. The mathematical model used by the network is typically dedicated to the specific task to be performed, and different models will be used to perform different tasks.

[0175] Once a neural network is built, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights in the model to reduce the output error of the network. Backpropagation of errors is a common method used to train neural networks. An input vector is presented to the network for processing. A loss function is used to compare the output of the network to the desired output, and an error value is calculated for each neuron in the output layer. The error values ​​are then propagated backwards until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm such as the stochastic gradient descent algorithm to update the weights of the neural network.

[0176] Fig. 9A -B shows an exemplary convolutional neural network. Fig. 9A The various layers within a CNN are shown. Fig. 9A As shown, an exemplary CNN for modeling image processing can receive an input 902 describing the red, green, and blue (RGB) components of an input image. The input 902 can be processed by multiple convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The output from multiple convolutional layers can be optionally processed by a set of fully connected layers 908. The neurons in the fully connected layer have full connections to all activations in the previous layer, as previously described for the feedforward network. The output from the fully connected layer 908 can be used to generate output results from the network. Matrix multiplication can be used instead of convolution to calculate the activation within the fully connected layer 908. Not all CNN implementations use the fully connected layer 908. For example, in some embodiments, the convolutional layer 906 can generate outputs for the CNN.

[0177] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 908. Traditional neural network layers are fully connected so that each output unit interacts with each input unit. However, the convolutional layers are sparsely connected because the output of the convolution of the domain is input (rather than the corresponding state value of each node in the domain) to the nodes of the subsequent layer, as shown. The kernel associated with the convolutional layer performs the convolution operation, and its output is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0178] Fig. 9BExemplary computational stages within a convolutional layer of a CNN are shown. An input 912 to a convolutional layer of a CNN may be processed in three stages of a convolutional layer 914. The three stages may include a convolution stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 may then output data to a successive convolutional layer. The final convolutional layer of the network may generate output feature map data or provide input to a fully connected layer, such as to generate a classification value for the input to the CNN.

[0179] In the convolution stage 916, the convolution layer 914 can perform several convolutions in parallel to produce a set of linear activations. The convolution stage 916 can include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to a specific area in the input, which can be determined as a local area associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the area in the local input to which the neuron is connected. The output from the convolution stage 916 defines a set of linear activations that are processed by successive stages of the convolution layer 914.

[0180] The linear activations may be processed by a detector stage 918. In the detector stage 918, each linear activation is processed by a nonlinear activation function. The nonlinear activation function increases the nonlinear properties of the entire network without affecting the corresponding domain of the convolutional layer. Several types of nonlinear activation functions may be used. One specific type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x) so that the activation threshold is zero.

[0181] The pooling stage 920 uses a pooling function that replaces the output of the convolutional layer 906 with summary statistics of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that small transformations of the input do not change the pooled output. In scenarios where the presence of features in the input data is more important than the precise location of the features, invariance to local transformations can be useful. Various types of pooling functions can be used during the pooling stage 920, including maximum pooling, average pooling, and l2-norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such an implementation replaces any additional convolution stage with an increased stride relative to the previous convolution stage.

[0182] The output from the convolutional layer 914 may then be processed by the next layer 922. The next layer 922 may be an additional convolutional layer or one of the fully connected layers 908. For example, Fig. 9AThe first convolutional layer 904 can output to the second convolutional layer 906, and the second convolutional layer can output to the first layer of the fully connected layer 908.

[0183] Fig.10 An exemplary recursive neural network 1000 is shown. In a recursive neural network (RNN), the previous state of the network affects the output of the current state of the network. RNNs can be built in various ways using various functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous word sequence. The RNN 1000 shown can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 for implementing the recursive function, a feedback mechanism 1005 for implementing a 'memory' of the previous state, and an output layer 1006 for outputting the result. The RNN 1000 operates based on time-steps. The state of the RNN at a given time-step is affected via the feedback mechanism 1005 based on the previous time-step. For a given time-step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time-step. The initial input (x) of the first time-step 1 ) can be processed by the hidden layer 1004. 1 ) is processed by the hidden layer 1004 to process the second input (x 2 ). A given state can be calculated as s t =f(Ux t +Ws t-1 ), where U and W are parameter matrices. Function f is typically nonlinear, such as a variation of the hyperbolic tangent function (Tanh) or the rectifier function f(x)=max(0,x). However, the specific mathematical function used in hidden layer 1004 may vary depending on the specific implementation details of RNN 1000.

[0184] In addition to the basic CNN and RNN networks described, variations of those networks can be enabled. An exemplary RNN variation is the long short-term memory (LSTM) RNN. LSTM RNN is able to learn long-term dependencies necessary for processing longer language sequences. A variation of CNN is a convolutional deep belief network, which has a structure similar to that of a CNN and is trained in a manner similar to a deep belief network. A deep belief network (DBN) is a generative neural network consisting of multiple layers of random (random) variables. Greedy unsupervised learning can be used to train DBN layer by layer. Then, by determining the optimal initial set of weights for the neural network, the learned weights of the DBN can be used to provide a column pre-trained neural network.

[0185] Fig.11 An exemplary training and deployment of a deep neural network is shown. Once a given network has been constructed for a task, the neural network is trained using a training data set 1102. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6 The machine learning framework 604 can be configured as a training framework 604. The training framework 604 can hook into the untrained neural network 1106 and train the untrained neural network to generate a trained neural network 1108 using the parallel processing resources described herein.

[0186] To start the training process, initial weights can be chosen randomly or by pre-training with a deep belief network. The training cycle is then performed in a supervised or unsupervised manner.

[0187] Supervised learning is a learning method in which training is performed as a mediated operation, such as when the training data set 1102 includes inputs paired with the expected outputs of the inputs, or when the training data set includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs with a set of expected or desired outputs. Errors are then propagated back through the system. The training framework 1104 can be adjusted to adjust the weights that control the untrained neural network 1106. The training framework 1104 can provide tools to monitor the degree to which the untrained neural network 1106 converges to a model suitable for generating the correct answer based on the known input data. The training process repeats as the weights of the network are adjusted to refine the outputs generated by the neural network. The training process can continue until the neural network reaches a statistically expected accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0188] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the entire data set. Unsupervised training can be used to generate a self-organizing map, which is a trained neural network 1108 that is capable of performing operations useful in reducing the dimensionality of the data. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from regular data patterns.

[0189] Variations of supervised and unsupervised training may also be employed. Semi-supervised learning is a technique where the training data set 1102 includes a mixture of labeled and unlabeled data of the same distribution. Incremental learning is a variation of supervised learning where input data is continuously used to further train the model. Incremental learning enables a trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge instilled into the network during initial training.

[0190] The training process of a particular deep neural network, whether supervised or unsupervised, may be too computationally intensive for a single computing node. The training process can be accelerated using a distributed network of computing nodes instead of using a single computing node.

[0191] Fig.12 is an exemplary block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. Each distributed computing node may include one or more main processors and one or more general processing nodes in a general processing node, such as Figure 7 A highly parallel general purpose graphics processing unit 700 in FIG. As shown, distributed learning can be performed through model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1206.

[0192] In model parallelism 1202, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. The benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks, where the weights of all layers would not fit into the memory of a single computing node. In some instances, model parallelism is particularly useful in performing unsupervised training of large neural networks.

[0193] In data parallelism 1204, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from different nodes are then combined. Although different methods of data parallelism are possible, data parallel training methods all require techniques for combining results and synchronizing model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that instead of transmitting parameters from nodes to parameter servers, updates to the model are transmitted. In addition, update-based data parallelism can be performed in a decentralized manner, in which updates are compressed and transmitted between nodes.

[0194] Combined model and data parallelism 1206 can be implemented, for example, in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, where a separate GPU within each node is used to train different parts of the model.

[0195] Distributed training already has increased overhead relative to training on a single machine. However, both the parallel processors and GPGPUs described herein can implement various techniques to reduce the overhead of distributed training, including techniques for implementing high-bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization.

[0196] Example Machine Learning Applications

[0197] Machine learning can be applied to solve various technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The application range of computer vision ranges from reproducing human visual capabilities (e.g., recognizing faces) to creating new categories of visual capabilities. For example, computer vision applications can be configured to identify sound waves from vibrations caused in objects visible in a video. Parallel processors accelerate machine learning, enabling computer vision applications to be trained using significantly larger training data sets than were previously feasible, and enabling the use of low-power parallel processors to deploy reasoning systems.

[0198] Parallel processors accelerate machine learning with autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described in this article can enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0199] Parallel processors accelerating deep neural networks have enabled machine learning methods for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely language sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks has enabled the replacement of hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0200] Parallel processors accelerate machine learning can also be used to accelerate natural language processing. The automated learning process can utilize statistical inference algorithms to produce models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0201] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 7 The highly parallel general purpose graphics processing unit 700 and Figure 8 800. In contrast, deployed machine learning platforms typically include lower-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0202] Fig.13 An exemplary on-chip reasoning system (SOC) 1300 suitable for performing reasoning using a trained model is shown. The SOC 1300 can integrate processing components, including a media processor 1302, a visual processor 1304, a GPGPU 1306, and a multi-core processor 1308. The SOC 1300 can additionally include an on-chip memory 1305 that can implement a shared on-chip data pool accessible by each processing component. The processing components can be optimized for low-power operation to enable deployment to various machine learning platforms, including autonomous vehicles and autonomous robots. For example, an embodiment of the SOC 1300 can be used as part of a master control system for an autonomous vehicle. In the case where the SOC 1300 is configured for an autonomous vehicle, the SOC is designed and configured to comply with the relevant functional safety standards of the deployment jurisdiction.

[0203] During operation, the media processor 1302 and the visual processor 1304 can work together to accelerate computer vision operations. The media processor 1302 can implement low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video stream can be written to a buffer in the on-chip memory 1305. The visual processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames using a trained image recognition model. For example, the visual processor 1304 can accelerate the convolution operations of a CNN for performing image recognition on high-resolution video data, while the back-end model calculations are performed by the GPGPU 1306.

[0204] The multi-core processor 1308 may include control logic to assist in the sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also act as an application processor for executing software applications that may utilize the inference computing capabilities of the GPGPU 1306. For example, at least a portion of the navigation and drive logic may be implemented in software executing on the multi-core processor 1308. Such software may issue computational workloads directly to the GPGPU 1306, or the computational workloads may be issued to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0205] GPGPU 1306 may include a computing cluster, such as a low-power configuration of computing clusters 706A-706H within a highly parallel general-purpose graphics processing unit 700. The computing cluster within GPGPU 1306 may support instructions that are specifically optimized to perform inference calculations on trained neural networks. For example, GPGPU 1306 may support instructions for performing low-precision calculations, such as 8-bit and 4-bit integer vector operations.

[0206] Depth channel camera device and image

[0207] Figure 14-16An exemplary image capture system for an image capture device is shown. In some embodiments, the image capture device is a stand-alone device, such as a digital camera. In other embodiments, the image capture device is part or a subcomponent of another computing device that requires image capture capabilities, such as a portable or handheld computing device with a digital camera for capturing images. In an exemplary embodiment, the image capture device is integrated with a convolutional neural network (CNN) computational process that can provide CNN data in real time or simultaneously with image capture and storage by the image capture device or when image capture and storage is performed by the image capture device. Therefore, the image capture device disclosed herein can provide both image and color information as well as deep machine learning information, such as feature detection using a CNN.

[0208] Fig.14 1 is an exemplary block diagram of an image capture system 1400 having an image capture device 1401 having a color sensor array 1402 integrated with a field programmable gate array (FPGA) 1404 programmed with a CNN 1406. The image capture system 1400 includes a depth channel memory storing a depth channel image 1416. Examples of the image capture device 1401 may include a digital camera or any type of computing device, such as a portable or handheld device having an image capture mechanism, such as the color sensor array 1402 coupled to the FPGA 1404.

[0209] The color sensor array 1402 can be any type of light sensor, light detector, CMOS sensor, or pixel array with a light sensor array to detect light energy that forms a color image captured by the color sensor array 1402. Alternatively, the color sensor 1402 can be configured to detect non-color images. In one embodiment, the color sensor array 1402 captures images in a red, green, and blue (RGB) format, and in other embodiments, the color sensor array captures images in a color space pixel (YUV) format that stores brightness, luminance, and color chromaticity values. The data or values ​​of each of these components form a separate output channel, such as color channel 1408. The value of color channel 1408 can be stored as an image of color channel 141 in a depth channel image 1416 within a depth channel memory 1412.

[0210] exist Fig.14In the example of , the color sensor array 1402 outputs its array values ​​or data directly to the FPGA 1404 and is used for the color channel 1408. In one embodiment, the color sensor array 1402 outputs values ​​in RGB format to the FPGA 1404, or alternatively, outputs values ​​in YUV format to the FPGA 1404. Although not shown, an analog-to-digital (A / D) converter converts the output values ​​from the color sensor array 1402 into digital signals or data for further processing and storage. In some embodiments, the A / D converter is placed in the image capture device 1401 to convert the output from the color sensor array 1402 into digital signals or data. The A / D converter can also be formed in the FPGA 1404 to convert the values ​​from the color sensor array 1402 into digital data for the CNN 1406 to perform CNN calculations.

[0211] In one embodiment, the output of color sensor array 1402 is the input to CNN 1406 programmed in FPGA 1404. The CNN can be any type of CNN, where any number of convolutional layers and nodes at each layer can perform CNN processing, such as with respect to Fig. 9A and 9B In other examples, a hardwired circuit or a programmable logic array (PLA) may be used instead of FPGA 1404, wherein CNN 1406 is programmed or hardwired in the corresponding circuit or array in the same manner. In other embodiments, FPGA 1404 may be programmed with hardware acceleration, such as Figure 6 As described in the description of machine learning application 602, machine learning framework 604, and computational framework work 606.

[0212] The nodes of the first or input layer of the CNN 1406 receive the output of the color sensor array 1402. The nodes of each layer of the CNN 1406 can be programmed as filters or feature detectors to detect specific features or feature maps in the captured image. The feature map data of each layer can represent a CNN channel, which can be stored in the depth channel memory 1412 as part of the depth channel image 1416. In this example, the CNN processing performed by the CNN 1406 is integrated with the image capture device 1401. The CNN 1406 can perform CNN calculations in real time, simultaneously, or at the time of image capture performed by the color sensor array 1402, thereby providing CNN processing efficiency. In this way, the image capture device 1401 also provides additional CNN information on the CNN channel 1410 and color information on the color channel 1408.

[0213] refer to Fig.14, the depth channel memory 1412 stores the output from the color sensor array 1402 on the color channel 1408 and the output from the CNN 1406 on the CNN channel 1410 as part of the depth channel image 1416. In one embodiment, the depth channel image 1416 includes a color image for the color channel 1414 and a CNN image for the CNN channel 1418. The color image for the color channel 1414 can be an RGB image, and the image for the CNN channel 1418 can be a filtered image or a feature map of the RGB image. In one embodiment, the images for the color channel 1414 and the CNN channel 1418 are combined and stored in the depth channel memory 1412. In other embodiments, the images for the color channel 1414 and the CNN channel 1418 are stored in adjacent memory locations or connected in the depth channel memory 1412.

[0214] Fig.15 FIG. 1 is a flowchart of an exemplary operation 1500 for generating a depth channel image using a CNN. In one embodiment, at operation 1502, a color sensor array (e.g., Fig.14 The color sensor array 1402 or Fig.16 The image is captured by capturing light values ​​by a plurality of light sensors, CMOS sensors, or other types of light detectors in the sensor array. At operation 1504, the array values ​​output from the color sensor array are input to an FPGA (e.g., Fig.14 FPGA1404 or Fig.16 In other embodiments, the output array values ​​are input to a hardwired circuit or programmable logic array configured or programmed for the CNN. At operation 1508, the color channel data (e.g., from Fig.14 The data of CNN channel 1410 in Fig.16 In one embodiment, the depth channel image is stored in a memory (e.g., Fig.14 The depth channel memory 1412 and Fig.16 In the depth channel memory 1620).

[0215] Fig.16 An example diagram showing the portion where RGB and CNN channel data are stored as a depth channel image. Fig.16, an exemplary system with a depth channel camera 1600 and a depth channel memory 1620 is shown. The depth channel camera 1600 includes a color sensor 1602 and an FPGA unit 1604. The color sensor 1602 includes a plurality of sensors arranged in an array to capture color data of an image 1603A. The image 1603A may be an RGB image or a YUV image. The color sensor 1602 outputs image values ​​or data to the depth channel memory 1620 and the FPGA unit 1604.

[0216] In one embodiment, the FPGA unit 1604 is programmed with a standard very deep CNN, such as the Visual Geometry Group (VGG) CNN, which is labeled as a standard VGG network 1606. In other embodiments, other types of CNNs can be programmed in the FPGA unit 1604 as disclosed herein. In this example, the VGG network 1606 is programmed to have five (5) convolutional layers labeled "Conv1" to "Conv5". Each convolutional layer Conv2 to Conv5 includes a data "pool" that provides summary statistics of nearby outputs. In other embodiments, any number of convolutional layers can be used, including a single convolutional layer. Each Conv1 to Conv5 layer performs a convolution operation that provides filtered image or feature map data labeled "Conv1 data" to "Conv5 data". In this feed-forward CNN network, the output of each convolutional layer is passed to the next layer to the final prediction layer 1625. At the prediction layer 1625, classification 1630 can be performed, such as determining the image type based on the CNN processing and the CNN data.

[0217] The depth channel memory 1620 stores an image 1603B for the RGB channels 1614 derived from the image 1603A. The data of Conv1 (1610A) to Conv5 (1610E) is stored for the CNN channel 1618. In this embodiment, each convolution channel Conv1 to Conv5 represents a CNN channel having five channels for the CNN channel 1618. The data of Conv1 (1610A) to Conv5 (1610E) can be different filtered images or feature maps of the image 1603A, depending on the convolution process performed at each layer. In the depth channel memory 1620, the images for the RGB color channels 1614 and the CNN channels are stored in adjacent memories or connected together.

[0218] CNN image formats for camera devices

[0219] Figure 17-18An exemplary system for storing feature maps using the first layer of a CNN for a camera device is shown. A single or first convolutional layer for providing feature maps can be used to implement a general convolutional kernel for a camera device so as to use less data and computational processes required by a multi-layer CNN, thereby improving the throughput of the camera device.

[0220] Fig.17 An exemplary diagram of an image processing system 1700 for a camera device having a sensor array 1702 for capturing images is shown. The sensor array 1702 captures a color image using a plurality of photodetectors that detect light intensity values. The image 1704 may be an image in RGB or YUV format. The output values ​​of the image 1704 are input to a CNN network 1706, wherein a single or first layer 1708 has a CNN kernel 1710 to perform CNN operations. In one embodiment, only a single or first layer 1707 of the CNN network 1706 is implemented. The first layer performs filtering of the color image 1704 captured by the sensor array 1702. The CNN kernel 1710 may be generalized to obtain a general feature map of the image 1704 in order to reduce CNN computational processing. The output of the first layer 1708 of the CNN is stored as a feature map 1714 in a feature map memory 1712.

[0221] In one embodiment, CNN network 1706 is implemented as follows: Figure 14-16 In an alternative embodiment, the CNN network 1706 is implemented by a digital signal processor (DSP) or a processor and processing unit disclosed herein, which can directly receive the output of the sensor array 1702. In other embodiments, the first layer 1708 and the CNN network 1706 can be implemented by, for example, Figure 6 The first layer 1708 is implemented with hardware acceleration as described in relation to the machine learning application 602, the machine learning framework 604, and the computational framework work 606. In other embodiments, the first layer 1708 is implemented and integrated on the same chipset or system on chip (SoC) as the components of the image capture device having the sensor array 1702.

[0222] Fig.18 FIG. 1 is a flowchart of an exemplary operation 1800 for storing feature maps using the first layer of a CNN. Fig.17 and 18 In one embodiment, at operation 1802, an image (e.g., image 1704) is captured by a sensor array (e.g., sensor array 1702). At operation 1804, image data of the captured image is output to a CNN network (e.g., CNN network 1706). In one embodiment, the CNN network is implemented in an FPGA (e.g., Figure 14-16 ) or hardware acceleration (for example, Figure 6 ). At operation 1806, convolution is performed on the image data at the first layer (e.g., the first layer 1708). A general kernel CNN (e.g., CNN kernel 1710) can be implemented to perform CNN processing on the image data at the first layer. At operation 1808, the data generated by the first layer of the CNN is output. The output data from the first layer of the CNN is stored in a feature map (e.g., feature map 1714) of a feature map memory (e.g., feature map memory 1712).

[0223] Graphics System Overview

[0224] Fig.19 1 is a block diagram of a processing system 1900 according to an exemplary embodiment. In various embodiments, the system 1900 includes one or more processors 1902 and one or more graphics processors 1908, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1902 or processor cores 1907. In one embodiment, the system 1900 is a processing platform contained within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0225] Embodiments of system 1900 may include or be included in the following: a server-based game platform; a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 1900 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. Data processing system 1900 may also include, be coupled with, or be integrated in: a wearable device, such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In some embodiments, data processing system 1900 is a television or set-top box device having one or more processors 1902 and a graphical interface generated by one or more graphics processors 1908.

[0226] In some embodiments, one or more processors 1902 each include one or more processor cores 1907 to process instructions, which when executed perform operations for system and user software. In some embodiments, each processing core in one or more processor cores 1907 is configured to process a specific instruction set 1909. In some embodiments, the instruction set 1909 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1907 can each process different instruction sets 1909, which can include instructions for facilitating the simulation of other instruction sets. The processor core 1907 can also include other processing devices, such as a digital signal processor (DSP).

[0227] In some embodiments, the processor 1902 includes a cache memory 1904. Depending on the architecture, the processor 1902 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared between various components of the processor 1902. In some embodiments, the processor 1902 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared between the processor cores 1907 using known cache coherence techniques. A register file 1906 is additionally included in the processor 1902, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1902.

[0228] In some embodiments, the processor 1902 is coupled to a processor bus 1910 to send communication signals such as address, data, or control signals between the processor 1902 and other components in the system 1900. In one embodiment, the system 1900 uses an exemplary "hub" system architecture, including a memory controller hub 1916 and an input-output (I / O) controller hub 1930. The memory controller hub 1916 facilitates communication between memory devices and other components of the system 1900, while the I / O controller hub (ICH) 1930 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 1916 is integrated within the processor.

[0229] Memory device 1920 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable properties to act as process memory. In one embodiment, memory device 1920 may act as system memory for system 1900 to store data 1922 and instructions 1921 for use when one or more processors 1902 execute applications or processes. Memory controller hub 1916 is also coupled to an optional external graphics processor 1912, which may communicate with one or more graphics processors 1908 in processor 1902 to perform graphics and media operations.

[0230] In some embodiments, the ICH 1930 enables peripheral devices to connect to the memory device 1920 and the processor 1902 via a high-speed I / O bus. The I / O peripheral devices include, but are not limited to, an audio controller 1946, a firmware interface 1928, a wireless transceiver 1926 (e.g., Wi-Fi, Bluetooth), a data storage device 1924 (e.g., a hard drive, flash memory, etc.), and a traditional I / O controller 1940 for coupling traditional (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1942 connect input devices, such as a keyboard and mouse 1944 combination. A network controller 1934 may also be coupled to the ICH 1930. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 1910. It should be appreciated that the system 1900 shown is exemplary and not limiting, as other types of differently configured data processing systems may also be used. For example, I / O controller hub 1930 may be integrated within one or more processors 1902 , or memory controller hub 1916 and I / O controller hub 1930 may be integrated into a discrete external graphics processor, such as external graphics processor 1912 .

[0231] Fig. 20 is a block diagram of an exemplary embodiment of a processor 2000 having one or more processor cores 2002A- 2002N, an integrated memory controller 2014 , and an integrated graphics processor 2008 . Fig. 20Those elements having the same reference numerals (or names) as elements of any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 2000 may include additional cores, up to and including additional core 2002N represented by a dashed box. Each of processor cores 2002A-2002N includes one or more internal cache units 2004A-2004N. In some embodiments, each processor core may also have access to one or more shared cache units 2006.

[0232] Internal cache units 2004A-2004N and shared cache unit 2006 represent a cache memory hierarchy within processor 2000. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level cache before external memory is classified as LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 2006 and 2004A-2004N.

[0233] In some embodiments, the processor 2000 may also include a set of one or more bus controller units 2016 and a system agent core 2010. The one or more bus controller units 2016 manage a set of peripheral buses, such as one or more peripheral component interconnect buses. (e.g., PCI, PCI Express). The system agent core 2010 provides management functions for various processor components. In some embodiments, the system agent core 2010 includes one or more integrated memory controllers 2014 to manage access to various external memory devices (not shown).

[0234] In some embodiments, one or more of the processor cores 2002A-2002N include support for simultaneous multithreading. In such embodiments, the system agent core 2010 includes components for coordinating and operating the cores 2002A-2002N during multithreaded processing. The system agent core 2010 may additionally include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 2002A-2002N and the graphics processor 2008.

[0235] In some embodiments, the processor 2000 additionally includes a graphics processor 2008 to perform graphics processing operations. In some embodiments, the graphics processor 2008 is coupled to a shared cache unit 2006 set and a system agent core 2010 (including one or more integrated memory controllers 2014). In some embodiments, a display controller 2011 is coupled to the graphics processor 2008 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 2011 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 2008 or the system agent core 2010.

[0236] In some embodiments, a ring-based interconnect unit 2012 is used to couple the internal components of the processor 2000. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some embodiments, the graphics processor 2008 is coupled to the ring interconnect 2012 via an I / O link 2013.

[0237] Exemplary I / O links 2013 represent at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2018, such as an eDRAM module. In some embodiments, each of the processor cores 2002A-2002N and graphics processor 2008 uses embedded memory module 2018 as a shared last level cache.

[0238] In some embodiments, processor cores 2002A-2002N are homogeneous cores that execute the same instruction set architecture. In another embodiment, processor cores 2002A-2002N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores in processor cores 2002A-2002N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 2002A-2002N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In addition, in addition to other components, processor 2000 can also be implemented on one or more chips or as a SoC integrated circuit with the components shown.

[0239] Fig.2121 is a block diagram of a graphics processor 2100, which may be a discrete graphics processing unit, or may be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via an I / O interface that is memory mapped to registers on the graphics processor and with commands placed in processor memory. In some embodiments, the graphics processor 2100 includes a memory interface 2114 for accessing memory. The memory interface 2114 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0240] In some embodiments, the graphics processor 2100 also includes a display controller 2102 for driving display output data to a display device 2120. The display controller 2102 includes hardware for one or more overlay planes of the display and a combination of multiple layers of video or user interface elements. In some embodiments, the graphics processor 2100 includes a video codec engine 2106 to encode, decode media, or transcode to, from, or between one or more media coding formats, including but not limited to Moving Picture Experts Group (MPEG) formats, such as MPEG-2, Advanced Video Coding (AVC) formats (e.g., H.264 / MPEG-4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats, such as JPEG and Motion JPEG (MJPEG) formats.

[0241] In some embodiments, the graphics processor 2100 includes a block image transfer (BLIT) engine 2104 to perform two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2110. In some embodiments, the GPE 2110 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0242] In some embodiments, GPE 2110 includes a 3D pipeline 2112 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 2112 includes programmable and fixed function elements that perform various tasks within the elements and / or spawn execution threads to 3D / media subsystem 2115. While 3D pipeline 2112 can be used to perform media operations, embodiments of GPE 2110 also include a media pipeline 2116 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0243] In some embodiments, the media pipeline 2116 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of or on behalf of the video codec engine 2106. In some embodiments, the media pipeline 2116 additionally includes a thread generation unit that generates threads for execution on the 3D / media subsystem 2115. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 2115.

[0244] In some embodiments, the 3D / media subsystem 2115 includes logic for executing threads generated by the 3D pipeline 2112 and the media pipeline 2116. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 2115, which includes thread dispatch logic for arbitrating and dispatching various requests for available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2115 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and store output data.

[0245] Graphics processing engine

[0246] Fig. 22 is a block diagram of a graphics processing engine 2210 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2210 is Fig.21 A version of the GPE 2110 is shown. Fig. 22 Elements having the same reference numeral (or name) as elements of any other figure herein may operate or function in any manner similar to (but not limited to) that described elsewhere herein. Fig.21 2110. The 3D pipeline 2112 and the media pipeline 2116 of the GPE 2210. The media pipeline 2116 is optional in some embodiments of the GPE 2210 and may not be explicitly included in the GPE 2210. For example, and in at least one embodiment, separate media and / or image processors are coupled to the GPE 2210.

[0247] In some embodiments, the GPE 2210 is coupled to or includes a command streamer 2203 that provides a command stream to the 3D pipeline 2112 and / or the media pipeline 2116. In some embodiments, the command streamer 2203 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 2203 receives commands from the memory and sends the commands to the 3D pipeline 2112 and / or the media pipeline 2116. The commands are instructions obtained from a ring buffer that stores commands for the 3D pipeline 2112 and the media pipeline 2116. In one embodiment, the ring buffer may additionally include a batch command buffer that stores a batch of multiple commands. Commands for the 3D pipeline 2112 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 2112 and / or image data and memory objects for the media pipeline 2116. The 3D pipeline 2112 and the media pipeline 2116 process the commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 2214.

[0248] In various embodiments, the 3D pipeline 2112 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs by processing instructions and dispatching execution threads to the graphics core array 2214. The graphics core array 2214 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution unit) within the graphics core array 2214 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0249] In some embodiments, graphics core array 2214 also includes execution logic to perform media functions, such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution units additionally include general purpose logic that can be programmed to perform parallel general purpose computing operations. The general purpose logic can be performed in parallel or in combination with Fig.19 Processor core 1907 or Fig. 20 The general logic within cores 2002A-2002N in the processor is used to perform processing operations.

[0250] Output data generated by threads executing on graphics core array 2214 may output data to memory in unified return buffer (URB) 2218. URB 2218 may store data for multiple threads. In some embodiments, URB 2218 may be used to send data between different threads executing on graphics core array 2214. In some embodiments, URB 2218 may additionally be used for synchronization between threads on the graphics core array and fixed function logic of shared function logic 2220.

[0251] In some embodiments, graphics core array 2214 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 2210. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0252] The graphics core array 2214 is coupled to shared function logic 2220, which includes a plurality of resources shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 2220 are hardware logic units that provide specialized supplemental functions to the graphics core array 2214. In various embodiments, the shared function logic 2220 includes, but is not limited to, samplers 2221, math 2222, and inter-thread communication (ITC) 2223 logic. In addition, some embodiments implement one or more caches 2225 within the shared function logic 2220. Shared functions are implemented where the demand for a given specialized function is insufficient to be included within the graphics core array 2214. Instead, a single instantiation of the specialized function is implemented as an independent entity in the shared function logic 2220 and is shared between execution resources within the graphics core array 2214. The exact set of functions that are shared between and included within the graphics core array 2214 varies between embodiments.

[0253] Fig.23 is a block diagram of another exemplary embodiment of a graphics processor 2300 . Fig.23 Elements having the same reference numeral (or name) as elements of any other figure herein may operate or function in any manner similar to (but not limited to) that described elsewhere herein.

[0254] In some embodiments, graphics processor 2300 includes ring interconnect 2302, pipeline front end 2305, media engine 2337, and graphics cores 2380A-2380N. In some embodiments, ring interconnect 2302 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated into a multi-core processing system.

[0255] In some embodiments, the graphics processor 2300 receives batches of commands via the ring interconnect 2302. The incoming commands are interpreted by the command streamer 2303 in the pipeline front end 2305. In some embodiments, the graphics processor 2300 includes scalable execution logic for performing 3D geometry processing and media processing via the graphics cores 2380A-2380N. For 3D geometry processing commands, the command streamer 2303 supplies the commands to the geometry pipeline 2336. For at least some media processing commands, the command streamer 2303 supplies the commands to the video front end 2334, which is coupled to the media engine 2337. In some embodiments, the media engine 2337 includes a video quality engine (VQE) 2330 for video and image post-processing and a multi-format encoding / decoding (MFX) 2333 engine for providing hardware accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2336 and the media engine 2337 each generate execution threads for the thread execution resources provided by at least one graphics core 2380A.

[0256] In some embodiments, the graphics processor 2300 includes scalable thread execution resources featuring modular cores 2380A-2380N (sometimes referred to as core slices), each of which has multiple sub-cores 2350A-2350N, 2360A-2360N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2300 can have any number of graphics cores 2380A to 2380N. In some embodiments, the graphics processor 2300 includes a graphics core 2380A having at least a first sub-core 2350A and a second sub-core 2360A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2350A). In some embodiments, the graphics processor 2300 includes multiple graphics cores 2380A-2380N, each of which includes a group of first sub-cores 2350A-2350N and a group of second sub-cores 2360A-2360N. Each sub-core in the group of first sub-cores 2350A-2350N includes at least a first group of execution units 2352A-2352N and a media / texture sampler 2354A-2354N. Each sub-core in the group of second sub-cores 2360A-2360N includes at least a second group of execution units 2362A-2362N and a sampler 2364A-2364N. In some embodiments, each sub-core 2350A-2350N, 2360A-2360N shares a group of shared resources 2370A-2370N. In some embodiments, the shared resources include a shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0257] Execution Unit

[0258] Fig.24 Thread execution logic 2400 is shown, which includes an array of processing elements employed in some exemplary embodiments of a GPE. Fig.24 Elements having the same reference numeral (or name) as elements of any other figure herein may operate or function in any manner similar to (but not limited to) that described elsewhere herein.

[0259] In some embodiments, the thread execution logic 2400 includes a shader processor 2402, a thread dispatcher 2404, an instruction cache 2406, a scalable execution unit array including a plurality of execution units 2408A-2408N, a sampler 2410, a data cache 2412, and a data port 2414. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any execution unit in execution units 2408A, 2408B, 2408C, 2408D, to 2408N-1 and 2408N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, the thread execution logic 2400 includes one or more connections to a memory (e.g., a system memory or a cache memory) through the instruction cache 2406, the data port 2414, the sampler 2410, and one or more of the execution units 2408A-2408N. In some embodiments, each execution unit (e.g., 2408A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, execution unit arrays 2408A-2408N are scalable to include any number of individual execution units.

[0260] In some embodiments, execution units 2408A-2408N are primarily used to execute shader programs. Shader processor 2402 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2404. In one embodiment, thread dispatcher includes logic for performing the following operations: arbitrating thread initiation requests from graphics and media pipelines, and instantiating the requested threads on one or more execution units in execution units 2408A-2408N. For example, the geometry pipeline (e.g., Fig.23 2336) can dispatch vertex, tessellation or geometry shaders to thread execution logic 2400 ( Fig.24 ) for processing. In some embodiments, thread dispatcher 2404 can also process runtime thread generation requests from executing shader programs.

[0261] In some embodiments, execution units 2408A-2408N support an instruction set including native support for many standard 3D graphics shader instructions so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal conversion. The execution unit supports vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). Each execution unit in execution units 2408A-2408N is capable of multi-issue single instruction multiple data (SIMD) execution, and multithreaded operations implement an effective execution environment in the face of high latency memory access. Each hardware thread in each execution unit has a dedicated high-bandwidth register file and an associated independent thread state. For pipelines capable of integer, single-precision and double-precision floating-point operations, SIMD branching capabilities, logical operations, transcendental operations, and other miscellaneous operations, execution is multi-issue per clock. While waiting for data from memory or one of the shared functions, dependency logic within execution units 2408A-2408N causes the waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources can be devoted to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations of a pixel shader, a fragment shader, or another type of shader program, including a different vertex shader.

[0262] Each of the execution units 2408A-2408N operates on an array of data elements. The number of data elements is the "execution size" or number of lanes of the instruction. An execution lane is a logical execution unit used for data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) of a particular graphics processor. In some embodiments, the execution units 2408A-2408N support integer and floating point data types.

[0263] The execution unit instruction set includes SIMD instructions. Various data elements can be stored as packed data types in registers, and the execution unit will process various elements based on the data size of the element. For example, when a 256-bit wide vector is operated, a 256-bit vector is stored in a register, and the execution unit operates as four independent 64-bit packed data elements (quad-word (QW) size data elements), eight independent 32-bit packed data elements (double-word (DW) size data elements), sixteen independent 16-bit packed data elements (word (W) size data elements) or thirty-two independent 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0264] One or more internal instruction caches (e.g., 2406) are included in the thread execution logic 2400 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2412) are included to cache thread data during thread execution. In some embodiments, a sampler 2410 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2410 includes a specialized texture or media sampling function to process the texture or media data during the sampling process before providing the sampled data to the execution unit.

[0265] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2400 via thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2402 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the values ​​of various vertex attributes to be interpolated across the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 2402 then executes the pixel or fragment shader program provided by the application programming interface (API). In order to execute the shader program, the shader processor 2402 dispatches the thread to the execution unit (e.g., 2408A) via the thread dispatcher 2404. In some embodiments, the pixel shader 2402 uses the texture sampling logic in the sampler 2410 to access the texture data in the texture map stored in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels from further processing.

[0266] In some embodiments, data port 2414 provides a memory access mechanism for thread execution logic 2400 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2414 includes or is coupled to one or more cache memories (e.g., data cache 2412) to cache data for memory access via the data port cache.

[0267] Fig.25 25 is a block diagram illustrating a graphics processor instruction format 2500 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in a variety of formats. Solid line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the instruction format 2500 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations that are decoded from the instruction once the instruction is processed.

[0268] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit instruction format 2510. Based on the selected instruction, instruction options, and the number of operands, 64-bit compressed instruction format 2530 can be used for some instructions. The native 128-bit instruction format 2510 provides access to all instruction options, while some options and operations are restricted in 64-bit instruction format 2530. The native instructions available in 64-bit instruction format 2530 vary from embodiment to embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in index field 2513. The execution unit hardware references a set of compression tables based on the index values, and uses the compression table output to reconstruct the native instructions in 128-bit instruction format 2510.

[0269] For each format, the instruction opcode 2512 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2514 implements control of certain execution options, such as channel selection (e.g., prediction) and data channel order (e.g., swizzle). For the instructions in the 128-bit instruction format 2510, the exec-size field 2516 limits the number of data channels to be executed in parallel. In some embodiments, the exec-size field 2516 is not available in the 64-bit compact instruction format 2530.

[0270] Some execution unit instructions have up to three operands, including two source operands src0 2520, src1 2522, and a destination 2518. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2524), where the instruction opcode 2512 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0271] In some embodiments, the 128-bit instruction format 2510 includes an access / address mode field 2526 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0272] In some embodiments, the 128-bit instruction format 2510 includes an access / address mode field 2526 that specifies an address mode and / or an access mode for the instruction. In one embodiment, the access mode is used to define data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source operands and destination operands, and when in a second mode, the instruction may use 16-byte aligned addressing for all source and destination operands.

[0273] In one embodiment, the address mode portion of the access / address mode field 2526 determines whether the instruction uses direct addressing or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0274] In some embodiments, instructions are grouped based on the opcode 2512 bit field to simplify opcode decoding 2540. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is only an example. In some embodiments, the move and logic opcode group 2542 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2542 shares five most significant bits (MSB), wherein the move (mov) instruction takes the form of 0000xxxxb, and the logic instruction takes the form of 0001xxxxb. The flow control instruction group 2544 (e.g., call (call), jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2546 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2548 includes component-wise arithmetic instructions (e.g., add, mul) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 2548 performs arithmetic operations in parallel across data lanes. The vector math group 2550 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands.

[0275] Graphics Pipeline

[0276] Fig.26 is a block diagram of another embodiment of a graphics processor 2600 . Fig.26 Elements having the same reference numeral (or name) as elements of any other figure herein may operate or function in any manner similar to (but not limited to) that described elsewhere herein.

[0277] In some embodiments, the graphics processor 2600 includes a graphics pipeline 2620, a media pipeline 2630, a display engine 2640, a thread execution logic 2650, and a rendering output pipeline 2670. In some embodiments, the graphics processor 2600 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 2600 via a ring interconnect 2602. In some embodiments, the ring interconnect 2602 couples the graphics processor 2600 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2602 are interpreted by a command stream transmitter 2603, which supplies instructions to individual components of the graphics pipeline 2620 or the media pipeline 2630.

[0278] In some embodiments, command streamer 2603 directs the operation of vertex fetcher 2605, which reads vertex data from memory and executes vertex processing commands provided by command streamer 2603. In some embodiments, vertex fetcher 2605 provides vertex data to vertex shader 2607, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 2605 and vertex shader 2607 execute vertex processing instructions by dispatching execution threads to execution units 2652A-2652B via thread dispatcher 2631.

[0279] In some embodiments, execution units 2652A-2652B are vector processor arrays with instruction sets for performing graphics and media operations. In some embodiments, execution units 2652A-2652B have an attached L1 cache 2651 that is specific to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0280] In some embodiments, the graphics pipeline 2620 includes a tessellation component to perform hardware accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 2611 configures the tessellation operation. The programmable domain shader 2617 provides back-end evaluation of the tessellation output. The tessellation 2613 operates at the direction of the hull shader 2611 and contains dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model, which is provided as an input to the graphics pipeline 2620. In some embodiments, if tessellation is not used, the tessellation components (e.g., the hull shader 2611, the tessellation 2613, and the domain shader 2617) can be bypassed.

[0281] In some embodiments, the complete geometric object may be processed by the geometry shader 2619 via one or more threads dispatched to execution units 2652A-2652B, or may proceed directly to the clipper 2629. In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2619 receives input from the vertex shader 2607. In some embodiments, the geometry shader 2619 is programmable via a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0282] Prior to rasterization, a limiter 2629 processes the vertex data. The limiter 2629 may be a fixed function limiter or a programmable limiter with limit and geometry shader functionality. In some embodiments, a rasterizer and depth test component 2673 in the render output pipeline 2670 dispatches a pixel shader to convert geometric objects into their per-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 2650. In some embodiments, an application may bypass the rasterizer and depth test component 2673 and access unrasterized vertex data via the stream output unit 2623.

[0283] Graphics processor 2600 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, execution units 2652A-2652B and associated caches 2651, texture and media samplers 2654, and texture / sampler caches 2658 are interconnected via data ports 2656 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 2654, caches 2651, 2658, and execution units 2652A-2652B each have a separate memory access path.

[0284] In some embodiments, the rendering output pipeline 2670 includes a rasterizer and a depth test component 2673, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. In some embodiments, an associated rendering cache 2678 and a depth cache 2679 are also available. A pixel operation component 2677 performs pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., bit block image transfers with mixing) are performed by a 2D engine 2641, or are replaced by a display controller 2643 that covers the display plane when displayed. In some embodiments, a shared L3 cache 2675 can be used for all graphics components to allow data to be shared without using main system memory.

[0285] In some embodiments, the graphics processor media pipeline 2630 includes a media engine 2637 and a video front end 2634. In some embodiments, the video front end 2634 receives pipeline commands from the command streamer 2603. In some embodiments, the media pipeline 2630 includes a separate command streamer. In some embodiments, the video front end 2634 processes the media commands before sending the commands to the media engine 2637. In some embodiments, the media engine 2637 includes a thread generation function for generating threads for dispatching to the thread execution logic 2650 via the thread dispatcher 2631.

[0286] In some embodiments, the graphics processor 2600 includes a display engine 2640. In some embodiments, the display engine 2640 is external to the processor 2600 and is coupled to the graphics processor via the ring interconnect 2602 or some other interconnect bus or structure. In some embodiments, the display engine 2640 includes a 2D engine 2641 and a display controller 2643. In some embodiments, the display engine 2640 includes dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 2643 is coupled to a display device (not shown), which can be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0287] In some embodiments, graphics pipeline 2620 and media pipeline 2630 can be configured to perform operations based on multiple graphics and media programming interfaces, and are not specific to any one application programming interface (API). In some embodiments, the driver software for the graphics processor converts API calls specific to a specific graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for open graphics library (OpenGL), open computing language (OpenCL) and / or Vulkan graphics and computing API (all from Khronos Group). In some embodiments, support can also be provided for the Direct3D library from Microsoft. In some embodiments, a combination of these libraries can be supported. Support can also be provided for the open source computer vision library (OpenCV). If it is possible to map from the pipeline of the future API to the pipeline of the graphics processor, future APIs with compatible 3D pipelines will also be supported.

[0288] Graphics Pipeline Programming

[0289] Fig.27A is a block diagram illustrating a graphics processor command format 2700 according to some embodiments. Fig.27B is a block diagram illustrating a graphics processor command sequence 2710 according to an embodiment. Fig.27A Solid-line boxes in show components that are typically included in a graphics command, while dashed lines include components that are optional or included only in a subset of graphics commands. Fig.27A An exemplary graphics processor command format 2700 includes data fields for identifying the target client of the command 2702, a command operation code (opcode) 2704, and associated data for the command 2706. A subopcode 2705 and a command size 2708 are also included in some commands.

[0290] In some embodiments, client 2702 specifies the client unit of the graphics device that processes the command data. In some embodiments, the graphics processor command parser checks the client field of each command to adjust the further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once the client unit receives the command, the client unit reads the opcode 2704, and if present, also reads the sub-opcode 2705 to determine the operation to be performed. The client unit uses the information in the data field 2706 to execute the command. For some commands, the explicit command size 2708 is expected to be the size of the specified command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, the command is aligned via a multiple of a double word.

[0291] Fig.27B An exemplary graphics processor command sequence 2710 is shown in the flowchart of FIG. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for purposes of example only, as embodiments are not limited to these particular commands or to the command sequence. In addition, commands may be issued as batch commands in a command sequence so that the graphics processor will process the command sequence at least partially simultaneously.

[0292] In some embodiments, the graphics processor command sequence 2710 may begin with a pipeline flush command 2712, which is used to cause any active graphics pipeline to complete the currently pending commands of the pipeline. In some embodiments, the 3D pipeline 2722 and the media pipeline 2724 do not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline flush, the command parser for the graphics processor will suspend command processing until the active drawing engine completes the suspended operation and the associated read cache is invalidated. Optionally, any data marked as "dirty" in the rendering cache can be flushed to memory. In some embodiments, the pipeline flush command 2712 can be used for pipeline synchronization or before the graphics processor is placed in a low power state.

[0293] In some embodiments, when a command sequence requires the graphics processor to explicitly switch between pipelines, pipeline select command 2713 is used. In some embodiments, pipeline select command 2713 is only required once within an execution context before issuing pipeline commands, unless the context is to issue commands for two pipelines. In some embodiments, pipeline flush command 2712 is required immediately before a pipeline switch via select command 2713.

[0294] In some embodiments, pipeline control commands 2714 configure the graphics pipeline for operation and are used to program 3D pipeline 2722 and media pipeline 2724. In some embodiments, pipeline control commands 2714 configure pipeline states for an active pipeline. In one embodiment, pipeline control commands 2714 are used for pipeline synchronization and for clearing data from one or more cache memories within an active pipeline before processing a batch of commands.

[0295] In some embodiments, commands for return buffer state 2716 are used to configure a set of return buffers for a corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, configuring return buffer state 2716 includes selecting the size and number of return buffers for a set of pipeline operations.

[0296] The remaining commands in the command sequence vary based on the active pipeline for operation. Based on pipeline determination 2720, the command sequence is customized for 3D pipeline 2722 starting from 3D pipeline state 2730, or for media pipeline 2724 starting from media pipeline state 2740.

[0297] The commands for configuring the 3D pipeline state 2730 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API used. In some embodiments, the 3D pipeline state 2730 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0298] In some embodiments, the 3D primitive 2732 command is used to submit a 3D primitive to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 2732 command are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 2732 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 2732 command is used to perform vertex operations on the 3D primitive via a vertex shader. In order to process the vertex shader, the 3D pipeline 2722 dispatches the shader execution thread to the graphics processor execution unit.

[0299] In some embodiments, the 3D pipeline 2722 is triggered via an execute 2734 command or event. In some embodiments, a register write triggers the command execution. In some embodiments, the execution is triggered via a "go" or "kick" command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger the command execution to clear the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is completed, the resulting geometric object is rasterized and the pixel engine shades the generated pixels. For those operations, additional commands for controlling pixel shading and pixel backend operations may also be included.

[0300] In some embodiments, the graphics processor command sequence 2710 follows the media pipeline 2724 path when performing media operations. Typically, the specific purpose and programming of the media pipeline 2724 depends on the media or computing operations to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and the media decoding can be performed in whole or in part using resources provided by one or more general processing cores. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0301] In some embodiments, the media pipeline 2724 is configured in a similar manner to the 3D pipeline 2722. A set of commands for configuring the media pipeline state 2740 are dispatched to or placed in the command queue before the media object commands 2742. In some embodiments, the commands for the media pipeline state 2740 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the commands for the media pipeline state 2740 also support the use of one or more pointers to "indirect" state elements that contain bulk state settings.

[0302] In some embodiments, media object commands 2742 supply pointers to media objects for media pipeline processing. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 2742. Once the pipeline states are configured and media object commands 2742 are queued, media pipeline 2724 is triggered via execution commands 2744 or equivalent execution events (e.g., register writes). Then, the output from media pipeline 2724 can be post-processed by operations provided by 3D pipeline 2722 or media pipeline 2724. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0303] Graphics software architecture

[0304] Fig.28 An exemplary graphics software architecture for data processing system 2800 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 2810, an operating system 2820, and at least one processor 2830. In some embodiments, processor 2830 includes a graphics processor 2832 and one or more general purpose processor cores 2834. Graphics application 2810 and operating system 2820 are both executed in system memory 2850 of the data processing system.

[0305] In some embodiments, the 3D graphics application 2810 includes one or more shader programs, including shader instructions 2812. The shader language instructions can be a high-level shader language, such as a high-level shader language (HLSL) or an OpenGL shader language (GLSL). The application also includes executable instructions 2814 in a machine language suitable for execution by a general-purpose processor core 2834. The application also includes graphics objects 2816 defined by vertex data.

[0306] In some embodiments, operating system 2820 is from Microsoft Corporation Operating system, private UNIX-like operating system, or open source UNIX-like operating system using a variant of the Linux kernel. Operating system 2820 can support graphics API 2822, such as Direct3D API, OpenGL API or Vulkan API. When using Direct3D API, operating system 2820 uses front-end shader compiler 2824 to compile any shader instruction 2812 in HLSL into a lower-level shader language. Compilation can be just-in-time (JIT) compilation, or the application can perform shader precompilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of 3D graphics application 2810. In some embodiments, shader instructions 2812 are provided in an intermediate form, such as a version of the standard portable intermediate representation (SPIR) used by Vulkan API.

[0307] In some embodiments, the user mode graphics driver 2826 includes a backend shader compiler 2827 for converting shader instructions 2812 into hardware specific representations. When using the OpenGL API, shader instructions 2812 in the GLSL high-level language are passed to the user mode graphics driver 2826 for compilation. In some embodiments, the user mode graphics driver 2826 uses the operating system kernel mode function 2828 to communicate with the kernel mode graphics driver 2829. In some embodiments, the kernel mode graphics driver 2829 communicates with the graphics processor 2832 to dispatch commands and instructions.

[0308] IP Core Implementation

[0309] One or more aspects of at least one embodiment may be implemented by representative codes stored on a machine-readable medium, which represent and / or define logic within an integrated circuit such as a processor. For example, a machine-readable medium may include instructions representing various logics within a processor. When read by a machine, the instructions may enable the machine to manufacture logic to perform the techniques described herein. This representation, referred to as an "IP core", is a reusable logic unit for an integrated circuit that may be stored on a tangible machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model onto a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0310] Fig.292900 is a block diagram showing an IP core development system 2900 that can be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 2900 can be used to generate modular, reusable designs that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 2930 can generate a software simulation 2910 for the IP core design in a high-level programming language (e.g., C / C++). The software simulation 2910 can be used to design, test, and verify the behavior of the IP core using a simulation model 2912. The simulation model 2912 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 2915 can then be created or synthesized based on the simulation model 2912. The RTL design 2915 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, and the behavior includes associated logic that is executed using the modeled digital signals. In addition to the RTL design 2915, a low-level design at a logic level or transistor level can also be created, designed, or synthesized. Therefore, the specific details of the initial design and simulation can vary.

[0311] The RTL design 2915 or equivalent can be further synthesized into a hardware model 2920 (which can be in hardware description language (HDL)) or some other representation of physical design data by a design facility. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored for transmission to a third-party manufacturing facility 2965 using a non-volatile memory 2940 (e.g., a hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design can be sent (e.g., via the Internet) on a wired connection 2950 or a wireless connection 2960. Then, the manufacturing facility 2965 can manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0312] Exemplary System-on-Chip Integrated Circuit

[0313] Figure 30-32 An exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0314] Fig.303000 is a block diagram illustrating an exemplary system-on-chip integrated circuit 3000 that can be manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 3000 includes one or more application processors 3005 (e.g., CPUs), at least one graphics processor 3010, and may additionally include an image processor 3015 and / or a video processor 3020, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 3000 includes peripherals or bus logic, including a USB controller 3025, a UART controller 3030, an SPI / SDIO controller 3035, and an I 2 S / I 2 The integrated circuit may include a display device 3045 coupled to one or more of a high-definition multimedia interface (HDMI) controller 3050 and a mobile industry processor interface (MIPI) display interface 3055. Storage may be provided by a flash memory subsystem 3060 including flash memory and a flash memory controller. A memory interface may be provided via a memory controller 3065 for accessing SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 3070.

[0315] Fig.31 is a block diagram illustrating an exemplary graphics processor 3110 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 3110 may be Fig.30 A variation of the graphics processor 3010 of FIG. The graphics processor 3110 includes a vertex processor 3105 and one or more fragment processors 3115A-3115N (e.g., 3115A, 3115B, 3115C, 3115D, to 3115N-1 and 3115N). The graphics processor 3110 can execute different shader programs via separate logic so that the vertex processor 3105 is optimized to perform the operations of the vertex shader program, while one or more fragment processors 3115A-3115N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 3105 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processors 3115A-3115N use the primitives and vertex data generated by the vertex processor 3105 to generate a frame buffer displayed on a display device. In one embodiment, the fragment processors 3115A-3115N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct3D API.

[0316] The graphics processor 3110 additionally includes one or more memory management units (MMUs) 3120A-3120B, caches 3125A-3125B, and circuit interconnects 3130A-3130B. The one or more MMUs 3120A-3120B provide virtual to physical address mappings for the graphics processor 3110 (including for the vertex processor 3105 and / or the fragment processors 3115A-3115N), and the one or more MMUs may reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in the one or more caches 3125A-3125B. In one embodiment, the one or more MMUs 3120A-3120B may be synchronized with other MMUs within the system, including with Fig.30 One or more MMUs associated with one or more application processors 3005, image processors 3015, and / or video processors 3020, so that each processor 3005-3020 can participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 3130A-3130B enable the graphics processor 3110 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0317] Fig.32 is a block diagram illustrating an additional exemplary graphics processor 3210 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 3210 may be Fig.30 A variation of the graphics processor 3010 of FIG. The graphics processor 3210 includes one or more MMUs 3220A-3220B, caches 3225A-3225B, and circuit interconnects 3230A-3230B.

[0318] The graphics processor 3210 includes one or more shader cores 3215A-3215N (e.g., 3215A, 3215B, 3215C, 3215D, 3215E, 3215F, to 3215N-1 and 3215N) that provide a unified shader core architecture in which a single core or a single type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary between embodiments and implementations. In addition, the graphics processor 3210 includes an inter-core task manager 3205 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 3215A-3215N and a tiling unit 3218 for accelerating tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0319] Examples of methods and systems include image processing systems and methods for deep channel convolutional neural network (CNN) images and formats, including camera devices.

[0320] In one example, an image processing method includes capturing image values ​​through a color sensor array, the image values ​​providing color channel data. The image values ​​captured by the color sensor array are input into a convolutional neural network (CNN) having at least one CNN layer. The CNN provides CNN channel data for each layer. The color channel data and the CNN channel data form a depth channel image. The depth channel image is stored in a memory.

[0321] In one example, the captured image values ​​are received from the color sensor array via a field programmable gate array (FPGA) programmed with the CNN.

[0322] In one example, CNN processing is performed at each CNN layer in real-time with the capture of the image values ​​by the color sensor array.

[0323] In one example, the color channel data includes RGB data or YUV data, and the CNN channel data includes filtered RGB data or filtered YUV data.

[0324] In one example, an image processing method includes capturing image values ​​through a sensor array. The image values ​​captured through the color sensor array are input into a CNN having a first convolutional neural network (CNN) layer. Using the image values ​​captured through the color sensor array, an output is generated at the first CNN layer. The output of the first CNN layer is stored as a feature map of the captured image.

[0325] In one example, image values ​​captured by the color sensor array are processed at the first CNN layer by a general CNN kernel.

[0326] In one example, processing the captured image values ​​is performed by a field programmable gate array (FPGA), a hardwired circuit, a programmable logic array (PLA), or a hardware accelerator.

[0327] In one example, the CNN is programmed in the field programmable gate array (FPGA), hardwired circuit, programmable logic array (PLA), or hardware accelerator.

[0328] In one example, the feature map image is a filtered image of an image captured by the sensor array.

[0329] In one example, an image processing system includes a sensor array, a field programmable gate array (FPGA), and a memory. The sensor array captures image values, and the image values ​​provide color channel data. The field programmable gate array (FPGA) is programmed with a CNN having at least one convolutional neural network (CNN) layer. The FPGA inputs the image values ​​captured by the color sensor array into the CNN convolutional neural network (CNN) having at least one CNN layer. The FPGA also uses the CNN to process the captured image values ​​and provides CNN channel data for each layer. The memory stores the color channel data and the CNN channel data. The color channel data and the CNN channel data form a depth channel image.

[0330] In one example, the memory stores the color channel data as an image in an RGB format or a YUV format, and stores the CNN channel data as a filtered image of the image in the RGB format or the YUV format.

[0331] In one example, the FPGA performs CNN processing at each CNN layer in real time with the capture of the image values ​​by the color sensor array.

[0332] In one example, an image processing system includes a sensor array, a hardware accelerator, and a memory. The sensor array captures image values. The hardware accelerator implements a CNN having a first convolutional neural network (CNN) layer. The hardware accelerator also receives the image values ​​captured by the sensor array into the first CNN layer. The hardware accelerator also uses the image values ​​captured by the color sensor array to generate an output at the first CNN layer. The memory stores the output of the first CNN layer as a feature map of the captured image.

[0333] In one example, the hardware accelerator processes image values ​​captured by the color sensor array through a general CNN kernel at the first CNN layer.

[0334] In one example, the hardware accelerator includes a field programmable gate array (FPGA), a hardwired circuit, a programmable logic array (PLA), a digital signal processor (DSP), or a processor.

[0335] In one example, the feature map image is a filtered image of an image captured by the sensor array.

[0336] The foregoing description and drawings are to be regarded as illustrative rather than restrictive. It will be appreciated by those skilled in the art that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Claims

1. An image processing method, comprising: capturing image values ​​via a color sensor array, the image values ​​providing color channel data; Inputting image values ​​captured by the color sensor array into a convolutional neural network (CNN) having at least one convolutional neural network (CNN) layer, the convolutional neural network (CNN) providing CNN channel data for each layer, wherein the CNN channel data includes output data from each convolutional neural network layer, and the output data from each convolutional neural network layer includes a feature map that is part of a depth channel image; as well as The depth channel image is stored in a memory, wherein the color channel data and the CNN channel data are used to form the depth channel image.

2. The image processing method according to claim 1, further comprising: The captured image values ​​are received from the color sensor array via a field programmable gate array (FPGA) programmed with the CNN.

3. The image processing method according to claim 1, further comprising: CNN processing is performed at each CNN layer in real time using the capture of the image values ​​through the color sensor array.

4. The image processing method according to claim 1, wherein: The color channel data includes red, green, and blue (RGB) data or color space pixel (YUV) data, and the CNN channel data includes filtered RGB data or filtered YUV data.

5. An image processing method, comprising: Capturing image values ​​via a sensor array; Inputting image values ​​captured by the sensor array into a convolutional neural network (CNN) having a first CNN layer; generating an output at the first convolutional neural network (CNN) layer using image values ​​captured by the sensor array; as well as A depth channel image is stored, the depth channel image comprising the output of the first convolutional neural network (CNN) layer as a feature map of the captured image values ​​and the captured image values.

6. The image processing method according to claim 5, further comprising: Image values ​​captured by the sensor array are processed at the first convolutional neural network (CNN) layer by a general CNN kernel.

7. The image processing method according to claim 6, wherein: Processing the captured image values ​​is performed by a field programmable gate array (FPGA), hardwired circuits, a programmable logic array (PLA), or a hardware accelerator.

8. The image processing method according to claim 7, wherein: The CNN is programmed in the field programmable gate array (FPGA), the hardwired circuit, the programmable logic array (PLA), or the hardware accelerator.

9. The image processing method according to claim 5, wherein: The feature map image is a filtered image of an image captured by the sensor array.

10. An image processing system, comprising: a sensor array for capturing image values ​​providing color channel data; A field programmable gate array (FPGA) programmed with a convolutional neural network (CNN) having at least one CNN layer, wherein the FPGA is used to: The image values ​​captured by the sensor array are input into the CNN convolutional neural network (CNN) having at least one CNN layer, and Processing the captured image values ​​using the CNN and providing CNN channel data for each layer, wherein the CNN channel data includes output data from each convolutional neural network layer, and the output data from each convolutional neural network layer includes a feature map that is part of a depth channel image; and A memory is used to store the color channel data and the CNN channel data, wherein the color channel data and the CNN channel data form a depth channel image.

11. The image processing system according to claim 10, wherein: The memory stores the color channel data as an image in a red-green-blue (RGB) format or a color space pixel (YUV) format, and stores the CNN channel data as a filtered image of the image in the RGB format or the YUV format.

12. The image processing system according to claim 10, wherein: The FPGA is used to perform CNN processing at each CNN layer in real time using the capture of the image values ​​by the sensor array.

13. An image processing system, comprising: a sensor array for capturing image values; A hardware accelerator for: implementing a CNN having at least a first convolutional neural network (CNN) layer, receiving image values ​​captured by the sensor array into the first convolutional neural network (CNN) layer, and using the image values ​​captured by the sensor array to generate outputs at the first convolutional neural network (CNN) layer; as well as A memory for storing a depth channel image comprising the output of the first convolutional neural network (CNN) layer as a feature map of the captured image values ​​and the captured image values.

14. The image processing system according to claim 13, wherein: The hardware accelerator is used to process image values ​​captured by the sensor array through a general convolutional neural network (CNN) kernel at the first CNN layer.

15. The image processing system according to claim 13, wherein: The hardware accelerator includes a field programmable gate array (FPGA), a hardwired circuit, a programmable logic array (PLA), a digital signal processor (DSP), or a processor.

16. The image processing system according to claim 13, wherein: The feature map image is a filtered image of an image captured by the sensor array.

17. An image processing system comprising: means for capturing image values ​​via a color sensor array, the image values ​​providing color channel data; means for inputting image values ​​captured by the color sensor array into a convolutional neural network (CNN) having at least one CNN layer, the CNN providing CNN channel data for each layer, wherein the CNN channel data comprises output data from each CNN layer, and the output data from each CNN layer comprises a feature map that is part of a depth channel image; as well as Unit for storing the depth channel image in a memory, wherein the color channel data and the CNN channel data are used to form the depth channel image.

18. The image processing system according to claim 17, further comprising: Unit for performing CNN processing at each CNN layer in real time using the capture of said image values ​​by said color sensor array.

19. The image processing system of claim 17, further comprising means for receiving captured image values ​​from the color sensor array via a field programmable gate array (FPGA) programmed with the CNN.

20. The image processing system of claim 17, further comprising means for storing red green blue (RGB) filtered data or color space pixel (YUV) filtered data in a memory as the depth channel image.

21. An image processing system, comprising: a unit for capturing image values ​​via a sensor array; means for inputting image values ​​captured by the sensor array into a convolutional neural network (CNN) having a first CNN layer; means for generating an output at said first convolutional neural network (CNN) layer using image values ​​captured by said sensor array; as well as Means for storing in a memory a depth channel image comprising said output of said first convolutional neural network (CNN) layer as a feature map of captured image values ​​and captured image value units.

22. The image processing system of claim 21, further comprising a unit for programming the CNN in a field programmable gate array (FPGA), a hardwired circuit, a programmable logic array (PLA), or a hardware accelerator.

23. The image processing system of claim 21, further comprising means for processing the captured image values ​​at the first convolutional neural network (CNN) layer by a general CNN kernel.

24. The image processing system of claim 21, further comprising means for storing the feature map as a filtered image.

25. At least one machine-readable medium comprising a plurality of instructions that are executed on a computing device to facilitate the computing device to perform one or more operations comprising: capturing image values ​​via a color sensor array, the image values ​​providing color channel data; Inputting the image values ​​captured by the color sensor array into a convolutional neural network (CNN) having at least one CNN layer, the CNN providing CNN channel data for each layer, wherein the CNN channel data includes output data from each CNN layer, and the output data from each CNN layer includes a feature map that is part of a depth channel image; as well as The depth channel image is stored in a memory, wherein the color channel data and the CNN channel data are used to form the depth channel image.

26. The machine-readable medium of claim 25, wherein: The computing device is used to perform one or more operations, including: performing CNN processing at each CNN layer in real time using the capture of the image values ​​through the color sensor array.

Images