Semiconductor wafer, semiconductor chip, and method for manufacturing semiconductor wafer

Abstract

The present invention relates to a semiconductor wafer, a semiconductor chip and a method for manufacturing a semiconductor wafer. In an embodiment, a semiconductor wafer is provided, which includes a plurality of component locations, wherein a scribe line region is positioned at least one of adjacent to and between the component locations. The component location includes an active device structure. At least one auxiliary structure is located in one or more of the scribe line regions. The auxiliary structure is electrically coupled to an auxiliary contact pad including tungsten.

Description

Background Art

[0001] In various semiconductor manufacturing processes, semiconductor wafers are separated into individual chips. This separation process may also be referred to as slicing or singulation. The separation process typically occurs in a kerf region located between component locations. The kerf region may contain various auxiliary structures, such as, for example, process control monitor (PCM) structures, photolithography structures, alignment structures, metal pads, contacts, and the like. Separating semiconductor wafers by cutting or sawing along the kerf region also results in cutting or sawing through the auxiliary structures located in the kerf region. This can result in undesirable effects, such as sidewall crushing, slicing tool wear, and the like.

[0002] US 2015 / 006487781 discloses a method which seeks to avoid these undesirable effects, wherein the auxiliary structures in the kerf region are removed and thereafter the semiconductor wafer is separated along the kerf region. However, further improvements would be desirable. Summary of the invention

[0003] In an embodiment, a semiconductor wafer is provided, comprising a plurality of component locations, wherein a scribe region is positioned at least one of adjacent to and between the component locations. The component locations include active device structures. At least one auxiliary structure is located in one or more of the scribe regions. The auxiliary structure is electrically coupled to an auxiliary contact pad comprising tungsten.

[0004] In some embodiments, the auxiliary contact pad includes tungsten and has an exposed tungsten surface. Therefore, the outermost surface of the auxiliary contact pad is formed by tungsten metal and is not covered by another material to provide a contact surface. The auxiliary contact pad can have a thickness of 50nm to 1000nm and can be located in the scribe line area.

[0005] In some embodiments, the auxiliary contact pad is substantially coplanar with a first conductive layer of a metallization structure, the first conductive layer being located on and electrically coupled to an active device structure in a component location. The metallization structure may further include a second conductive layer, the second conductive layer being located in the component location, and the scribe line region being free of the second conductive layer. The total thickness of the auxiliary contact pad is less than the total thickness of the metallization structure in the component location.

[0006] In some embodiments, the auxiliary structure and the active device structure each include a transistor device structure, the transistor device structure including a cell region laterally surrounded by an edge termination region. The cell region may include a semiconductor layer including a first conductivity type forming a drift region, a body region including a second conductivity type opposite to the first conductivity type on the drift region, a source region including the first conductivity type on the body region, and a plurality of trenches, each trench including at least one of a field plate and a gate electrode.

[0007] In some embodiments, the plurality of trenches include a plurality of columnar trenches, each columnar trench includes a field plate and a plurality of elongate trenches, each elongate trench includes a gate electrode. The transistor device structure may also include one or more insulating layers disposed on the elongated trenches and on the source region and a tungsten plug extending through the one or more insulating layers and disposed on the field plate. The first conductive layer is disposed on the tungsten plug and electrically coupled to the source region and the body region.

[0008] In an embodiment, a method of manufacturing a semiconductor wafer includes: providing a semiconductor wafer; forming active device structures in component locations, wherein a scribe region is positioned at least one of adjacent to and between the component locations; forming one or more auxiliary structures in one or more of the scribe regions; forming a metallization structure on the component locations and the scribe regions, wherein a first conductive layer of the metallization structure includes tungsten; and forming one or more auxiliary contact pads in the tungsten layer arranged in the scribe region, which are electrically coupled to one or more of the auxiliary structures. The auxiliary tungsten pads may include an uncovered or exposed outermost surface formed of tungsten metal.

[0009] In some embodiments, the method may further include forming a second conductive layer of the metallization structure. The second conductive layer is located at the component position and exposes one or more auxiliary contact pads in the scribe area. The second conductive layer is free of tungsten. The second conductive layer may include aluminum and / or copper.

[0010] In some embodiments, forming the auxiliary structure and / or forming the active device structure includes forming a body region including a second conductivity type opposite to the first conductivity type in a semiconductor layer including a first conductivity type forming a drift region; forming a source region including the first conductivity type on the body region; forming a plurality of columnar trenches, forming a field plate in each columnar trench; forming an elongated trench in an area of ​​the semiconductor layer between the columnar trenches; forming a gate electrode in the elongated trench; forming one or more insulating layers arranged on the columnar trenches, the elongated trenches, and the source region; forming an opening in one or more insulating layers above the field plate; and inserting tungsten into the opening and onto the field plate. A first conductive layer is formed on the tungsten in the opening, and the first conductive layer is electrically coupled to the source region and the body region.

[0011] In some embodiments, the method further comprises applying an external contact to the auxiliary contact pad and measuring one or more parameters of the auxiliary structure.

[0012] In some embodiments, the method further includes singulating the wafer by cutting along the scribe line regions and through the auxiliary structures and the auxiliary contact pads.

[0013] In an embodiment, a semiconductor chip includes: a semiconductor substrate including an active device region and a peripheral edge region laterally surrounding the active device region. A separation region including a layer of tungsten is arranged in the peripheral edge region. The separation region may include tungsten metal and have an outermost surface formed of tungsten.

[0014] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The elements of the drawings are not necessarily drawn to scale relative to each other. The same reference numerals represent corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. Exemplary embodiments are depicted in the drawings and detailed in the following description.

[0016] Figure 1 A schematic plan view of the top side of a semiconductor wafer is shown.

[0017] Figure 2 Picture shows Figure 1 Schematic cross-sectional view of a semiconductor wafer.

[0018] Figure 3 The diagram shows Figure 1 and 2 Semiconductor wafer. Top view of isolated semiconductor chips.

[0019] Figure 4 A cross-sectional view of an auxiliary structure located in a scribe line region of a semiconductor wafer is illustrated.

[0020] Figure 5 A cross-sectional view of a scribe line area including a trench is illustrated.

[0021] Figure 6 A flow chart of a method of manufacturing a semiconductor wafer is illustrated. DETAILED DESCRIPTION

[0022] In the following detailed description, reference is made to the accompanying drawings forming a part thereof, and specific embodiments in which the present invention can be practiced are shown by way of illustration. In this regard, directional terms such as "top", "bottom", "front", "back", "front part", "tail part", etc. are used with reference to the orientation of the (one or more) figures being described. Because the components of the embodiments can be located in many different orientations, directional terms are used for the purpose of illustration and are by no means restrictive. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present invention. The following detailed description thereof should not be considered to have a restrictive meaning, and the scope of the present invention is defined by the appended claims.

[0023] A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference numerals in the figures. In the context of this description, "lateral" or "lateral direction" is understood to mean a direction or range extending generally parallel to the lateral extent of a semiconductor material or a semiconductor carrier or a semiconductor wafer. Therefore, the lateral direction extends approximately parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is understood to mean a direction extending generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Therefore, the vertical direction extends in the thickness direction of the semiconductor material or the semiconductor carrier or the semiconductor wafer.

[0024] As used in this specification, when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or directly extend onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present.

[0025] As employed in this specification, when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0026] Figure 1 A schematic plan view is shown, and Figure 2 A cross-sectional view of a semiconductor wafer 10 is illustrated.

[0027] Figure 1 A top side 11 of a semiconductor wafer 10 is illustrated. The semiconductor wafer 10 includes a plurality of component locations 12, wherein scribe regions 13 are positioned at least one of adjacent to and between the component locations 12. Each component location 12 is surrounded on all lateral sides by scribe regions 13. The component locations 12 include active device structures 14. At least one auxiliary structure 15 is located in one or more of the scribe regions 13. The auxiliary structures 15 are electrically coupled to auxiliary contact pads 16 comprising tungsten.

[0028] Component locations 12 are typically arranged in rows and columns and are separated from their nearest neighbors by scribe regions 13. Scribe regions 13 may also be referred to as separation regions or saw streets. Scribe regions 13 are located adjacent to the outermost component locations 12 so that each component location 12 is delimited on all lateral sides by scribe regions 13. Scribe regions 13 typically form a regular grid structure. In order to separate semiconductor wafer 10 into individual chips, wafer 10 is cut along scribe regions 13.

[0029] The scribe line region 13 has a width w s, which is usually slightly larger than the width of the material removed by the separation process, such as w cut The width w of the scribe area 13 is s It may be in the range of 40 μm to 120 μm or 60 μm to 90 μm. The area of ​​the scribe area 13 that is cut and removed to separate the chip from the wafer is called the kerf area. The kerf area has a width w cut , which is smaller than the width w of the scribe line region 13 s .

[0030] Semiconductor wafer 10 is separated along scribe line regions 13 to produce semiconductor chips from component locations 12 including active device structures 14. Typically, each component location 12 of the semiconductor wafer includes an active device structure 14 and may include the same active device structure. However, in some embodiments, the active device structure in one or more of the component locations 12 may be different from the active device structure of one or more other component locations 12.

[0031] Semiconductor wafer 10 may include a single crystal silicon wafer, which may include an epitaxially deposited silicon layer, commonly referred to as an epitaxial layer.

[0032] The auxiliary structures 15 in the scribe line areas 13 are structures formed during the processing of the semiconductor wafer that do not interact with or affect the active device structures 14 in the component locations 12 of the processed semiconductor wafer 10. The auxiliary structures 15 can be used to evaluate the manufacturing process of semiconductor devices (such as the active device structures 14 in the component locations 12). Examples of auxiliary structures 15 include, for example, process control monitor (PCM) devices (e.g., electronic PCM devices), photolithographic structures, metal pads, contacts for electrochemical etching, and alignment structures. The wafer 10 may also include different types of auxiliary structures for different purposes.

[0033] In some embodiments, at least one auxiliary structure 15 has the same structure as the active device structure 14. For example, the auxiliary structure 15 and the active device structure 14 may be transistor device structures. The auxiliary structure 15 may be a laterally smaller version of the active device structure 14.

[0034] In some embodiments, at least one auxiliary structure 15 may include a structure for measuring one or more parameters of one or more characteristics of a transistor device structure, wherein the auxiliary structure 15 itself does not have a transistor device structure or a transistor device structure that replicates the active transistor device structure 14. For example, the auxiliary structure 15 may be without a trench and used to measure the sheet resistance of the source and body regions of the active transistor device structure in the component location, or the auxiliary structure 15 may include a trench filled with polysilicon and used to measure the resistance of the polysilicon in the trench.

[0035] Two or more auxiliary contact pads 16 can be coupled to a single auxiliary structure. The auxiliary contact pad 16 includes tungsten and can be located in the scribe area 13. The auxiliary contact pad 16 can be formed of tungsten metal. In some embodiments, the auxiliary contact pad 16 includes an exposed tungsten surface. Therefore, at least a portion of the outermost surface of the auxiliary pad 16 is formed of tungsten and is not covered by another material including a metal layer. The exposed tungsten surface provides a free-lying contact surface.

[0036] In some embodiments, the auxiliary contact pad 16 has a multi-layer structure, whereby tungsten (pure tungsten metal in some embodiments) forms the outermost sublayer of the multi-layer structure of the auxiliary contact pad 16. The lower sublayer of the multi-layer structure may include a Ti / TiN structure for improving adhesion.

[0037] The auxiliary contact pad 16 may have a thickness of 50 nm to 1000 nm. The auxiliary contact pad 16 may be formed of a conductive layer including tungsten, which is located on the scribe area 13. The scribe area 13 may include another portion of the conductive layer in addition to the auxiliary contact pad 16 or a pad coupled to the auxiliary structure 15.

[0038] In some embodiments, the active device structure 14 is a transistor device structure. The active device structure 14 may also include a metallization structure 17 disposed on the top surface 11 of the semiconductor wafer 10 in at least the component location 12, such as may be Figure 2 as seen in a cross-sectional view.

[0039] The metallization structure 17 arranged in the component location 12 is located on the active device structure 14 and is electrically coupled with the active device structure 14 in the component location 12. The metallization structure 17 in the component location 12 may have a thickness greater than the thickness of the auxiliary contact pad 16 and any other conductive layer or layers arranged in the scribe area 13. For example, the metallization layer may have a thickness that is at least 5 times or at least 10 times greater than the thickness of the auxiliary contact pad 16. For example, the metallization structure 17 may have a thickness of about 5 μm.

[0040] The reduced thickness of the auxiliary contact pads 16 and the further conductive layer (if present) in the scribe area 13 can help reduce defects or defective chips, such as reducing undesirable crushing of the top side, sidewalls and / or back surface of the semiconductor material during separation of the semiconductor chips from the semiconductor wafer 10 by a cutting action along the scribe area 13 and through the auxiliary contact pads 16 and / or through the auxiliary structures 15. The reduced thickness of the tungsten auxiliary contact pads 16 and the further conductive layer (if present) in the scribe area 13 can help improve the yield. Since the semiconductor wafer 10 is cut through the auxiliary structures 15, a width w of the scribe area 13 that enables cuts to be formed laterally adjacent to the auxiliary structures 15 is avoided. s Furthermore, an additional process of removing the auxiliary structures and / or the auxiliary pads from the scribe line region before separating the semiconductor wafer into chips can be avoided.

[0041] The metallization structure 17 may include a first conductive layer 18 disposed on the top surface 11 of the semiconductor wafer 10 and a second conductive layer 19 disposed on the first layer 18. In some embodiments not shown, an insulating layer may be disposed between the first conductive layer 18 and the second conductive layer 19, and at least portions of the two conductive layers 18, 19 may be electrically connected by vias extending through the intermediate insulating layer. The first conductive layer 18 and the second conductive layer 19 are generally configured to provide a redistribution structure. The redistribution structure may provide two or more conductive redistribution paths that are electrically insulated from each other. For example, for a transistor device structure, a redistribution structure may be provided for each of the source, drain, and gate of the transistor device in the component position 12.

[0042] The first conductive layer 18 may include tungsten and may be substantially coplanar with the auxiliary contact pad 16 coupled to the auxiliary structure 15 arranged in the scribe area 13. In some embodiments, the thickness of the first conductive layer 18 and the auxiliary contact pad 16 are substantially the same. The first conductive layer 18 of the metallization structure 17 may have a thickness of 100 nm to 900 nm. The second conductive layer 19 may have a thickness of about 5 μm.

[0043] The first conductive layer 18 includes tungsten, and in some embodiments, the second conductive layer 19 includes a metal or layer or alloy without tungsten. In some embodiments, the second conductive layer 19 includes aluminum and / or copper. The second conductive layer 19 may also include two or more sublayers and may include a stack of metals and / or alloys. For example, the second conductive layer 19 may be a nickel-based metallization (such as nickel-based NiV, NiP, NiMoP, NiPPd, and NiPPd systems), or an Au-based metallization or a silver-based metallization (such as a Ti / NiV / Ag stack).

[0044] The auxiliary contact pads 16 may be formed using the same process as the first conductive layer 18. This may be useful, for example, if the first conductive layer 18 forms part of a metallization layer 17 for the active device structures 14. The first conductive layer may be deposited onto both the scribe areas 13 and the component locations 12 of the semiconductor wafer 10 and patterned to form the first conductive layer 18 of the redistribution structures 17 in the component locations 12 and the auxiliary contact pads 16 in the scribe areas 13.

[0045] After patterning the first conductive layer 18 to form auxiliary contact pads 16 in the scribe area 13 and / or a layer of conductive layers and metallization layers 17 in the component location 12, the scribe area 13 can be covered during subsequent construction of the metallization structure 17 in the component location 12, for example during formation of the second conductive layer 18.

[0046] In some embodiments, the metallization structure 17 includes more than two conductive layers. The lowermost conductive layer of the three or more conductive layers of such a metallization structure 17 may include tungsten and be coplanar with the auxiliary contact pad 16 .

[0047] In some embodiments, the auxiliary structure 15 and the active device structure 14 both include transistor device structures. The auxiliary structure 15 and the active device structure 14 both include the same transistor device structure. The transistor device structure may include a cell region laterally surrounded by an edge termination region. The transistor device structure may be a field effect transistor device structure, such as a MOSFET device structure, such as a superjunction MOSFET using a charge compensation principle.

[0048] The lateral dimensions of the transistor device for auxiliary structures 15 may be smaller than the lateral dimensions of the transistor device for active device structures 14 with the same transistor device structure. For example, the cell region of auxiliary structures 15 may include fewer cells than the cell region of active device structures 14.

[0049] Figure 3A plan view of a semiconductor chip 20 singulated from a wafer 10 by slicing or sawing along a scribe line region 13 is illustrated. The semiconductor chip 20 is formed by component locations 12 and includes an active device structure 14. The active device structure 14 includes a cell field 21 that is laterally surrounded by an edge termination region 22. The edge termination region 22 is in turn laterally surrounded by a peripheral edge region 23 that extends to a side 24 of the semiconductor chip 20. The peripheral edge region 23 is formed by the remaining portion of the scribe line region 13. The semiconductor chip 20 includes a separation region 25 that includes a tungsten layer in the peripheral edge region 23. A side 26 of the separation region 25 may form a portion of the side 24 of the semiconductor chip 40. The separation region 25 that includes a tungsten layer may be a remaining portion of an auxiliary contact pad 16 formed in the scribe line region 13. The peripheral edge region 23 may also include a remaining portion or all of the auxiliary structure 15.

[0050] In order to separate the semiconductor wafer 10 into individual semiconductor chips, parts of the scribe area 13 are removed, for example by mechanical sawing or laser cutting through the thickness of the semiconductor wafer. The sawing or cutting inserted into the scribe area 13 has a width w cut , which is smaller than the width w of the scribe line region 13 s Thus, the most peripheral region of the semiconductor chip 20 is formed by the portion of the scribe area 13 that is not removed by the separation action and that is located adjacent to the edge termination region 22 of the active device structure 14. Portions of the auxiliary pads 16 and / or the auxiliary structures 15 located on this remaining portion of the scribe area can be discerned at the peripheral edge region 23 of the separated semiconductor chip 20.

[0051] As described above, in some embodiments, the auxiliary structures 15 and the active device structures 14 both include transistor device structures.

[0052] Figure 4 Illustrated is a cross-sectional view of a transistor device structure 30. The transistor device structure 30 comprises a cell region or cell field 31 which is laterally surrounded by an edge termination region 32. Figure 4 The inset of illustrative embodiment illustrates an enlarged view of a portion of the cell region 31. The transistor device structure 30 may be a field effect transistor device structure.

[0053] In the illustrated embodiment, the transistor device structure 30 is an auxiliary structure 15 that is located in the scribe line area 13 of the semiconductor wafer 10. However, the active device structure 14 and the component location 12 may also include the transistor device structure 30, so that Figure 4 Can also refer to Figures 1 to 3 An active device structure 14 in the component location 12 is illustrated in FIG.

[0054] The transistor structures 30 forming the auxiliary structures 15 are typically laterally smaller versions of the transistor structures of the active device structures 14 in the component location 12 and include not only the cell region 31 but also the edge termination region 32. However, the number of cells in the cell region 31 of the auxiliary structures 15 is less than the number of cells in the cell region of the active device structures 14. For process monitoring purposes, the smaller lateral dimensions of the transistor structures 30 of the auxiliary structures 15 may be useful because the smaller lateral area results in a higher on-resistance that can be measured more easily and accurately. Additional characteristics of the transistor structures that can be measured on the auxiliary structures 15 include the breakdown voltage.

[0055] In some embodiments, the cell region 31 includes a semiconductor layer 33, which can be formed of a material of the semiconductor wafer 10 (e.g., silicon) or an epitaxial layer of silicon formed on a single crystal silicon wafer. The semiconductor layer 33 includes a first conductivity type and forms a drift region 34. The cell region 31 also includes a body region 35 and a source region 36, the body region 35 includes a second conductivity type opposite to the first conductivity type, the body region 35 is arranged on the drift region 34, and the source region 36 includes the first conductivity type and is arranged on the body region 35. The first conductivity type can be n-type and the second conductivity type can be p-type, or vice versa. The transistor structure 30 also includes a plurality of trenches 37 extending from the first surface 41 into the semiconductor layer 33.

[0056] In such Figure 4 In some embodiments illustrated in the figure, a first plurality of trenches 37 are provided, which have a columnar form and each include a field plate 38. In this embodiment, the cell region 31 also includes a second plurality of trenches 39 in the form of elongated or strips, each elongated trench 39 including a gate electrode 40. The elongated trenches 39 may extend substantially parallel to each other into the plane of the figure. The elongated trenches 39 are alternately arranged with a row of separated columnar trenches 37, whereby the row extends into the plane of the figure and is substantially parallel to the elongated trenches 39.

[0057] The body region 35 and the source region 36 extend between the columnar trenches 37, and an elongated trench 39 including a gate electrode 40 extends from a top surface 41 through the source region 36 and the body region 35 into the semiconductor wafer 33. The elongated trench 39 is lined with an insulating layer 42, thereby forming a gate insulation or gate oxide. The base of the elongated trench 39 may extend into the top of the drift region 34. The columnar trench 37 extends from the first surface 41 of the semiconductor wafer 10 to a greater depth into the body of the semiconductor layer 33. The columnar trench 37 is also lined with an insulating layer 43, which insulates the field plate 38 from the drift region 34.

[0058] The transistor device structure 30 further includes one or more insulating layers 44 disposed on the first surface 41 of the semiconductor wafer 10 and on the elongated trench 39 including the gate electrode 40 and on the source region 36. The insulating layer 44 or the uppermost insulating layer (if two or more insulating layers are provided) may be BPSG (borophosphosilicate glass). The first conductive layer 18 or the auxiliary contact pad 16 is disposed on the insulating layer 44.

[0059] The transistor device structure 30 also includes vertical metal contacts 45, which may include tungsten and have the form of tungsten plugs. Each tungsten plug 45 extends through one or more insulating layers 44 and is arranged on a field plate 38 in one of the pillar trenches 37. The first conductive layer 18 or auxiliary contact pad 16 is arranged on the insulating layer 44 and on the tungsten plug 45, and is electrically coupled to the field plate 38, the source region 36, and the body region 35.

[0060] The edge termination region 32 also includes a pillar-shaped trench 46 containing a field plate 47. The field plate 47 is electrically coupled to the first conductive layer 18 through a tungsten plug 48, as in the cell region 31. However, the edge termination region 32 does not include an elongated trench of a gate electrode and a source region, so that the semiconductor layer 33 extends to the upper surface 41 and directly contacts the one or more insulating layers 44. The body region may be located in some portions of the edge termination region 32.

[0061] In some embodiments, a barrier is located below the tungsten material of the auxiliary contact pad 16, the first conductive layer 18, and the tungsten plug 45. The Ti / TiN barrier may be deposited first, and the tungsten of the auxiliary contact pad 16, the first conductive layer 18, or the tungsten plug 45 may be deposited on top. The Ti layer may have a thickness of about 30 nm, and the thickness of the TiN layer may be about 40 nm. Tungsten may be deposited using chemical vapor deposition (CVD). The Ti and TiN barriers may be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), such as sputtering.

[0062] However, the transistor device structure 31 is not limited to this particular structure and may have other structures. For example, in some embodiments, each trench including a field plate is elongated. In some embodiments, each trench includes a field plate and a gate electrode disposed on the field plate and electrically isolated from the field plate. In some embodiments, each trench is elongated and a plurality of trenches form a series of strips bounded by a strip-shaped mesa in which a drift region, a body region, and a source region are disposed.

[0063] In some embodiments, the scribe line region 13 includes additional structures that are not part of the auxiliary structures 15 or the active device structures 14 . Figure 5A view of such a location is illustrated. At this location of the scribe line region 13, a further trench, in particular a columnar trench 49 comprising a field plate 50, is arranged in the scribe line region 13 and thus at a location adjacent to the transistor structure 30 of the auxiliary structure 15. The columnar trench 49 is lined with an insulating layer 51 which electrically insulates the field plate 50 from the semiconductor layer 33.

[0064] The columnar trench 49 and the field plate 50 are covered by one or more insulating layers 44, and the auxiliary contact pad 16 or another conductive layer 52 including tungsten is arranged on the insulating layer 44. These field plates 50 are not coupled to the auxiliary contact pad 16 or the other conductive layer and can be considered as filled trenches or dummy trenches. These filled trenches or dummy trenches can be used to adjust the opening area by etching the trench so that it is substantially equal to a predetermined value. This helps to achieve the desired etching characteristics when using etching conditions optimized for a predetermined opening area. Filled or dummy trenches can also help to evenly distribute mechanical stress across the semiconductor wafer 10.

[0065] Figure 6 A flow chart 60 of a method for manufacturing a semiconductor wafer is illustrated.

[0066] In box 61, a semiconductor wafer is provided. In box 62, active device structures are formed in component locations, wherein the scribe regions are located at least one of adjacent to and between the component locations. In box 63, one or more auxiliary structures are formed in one or more of the scribe regions. In box 64, a metallization structure is formed on the component locations and the scribe regions. The first conductive layer of the metallization structure includes tungsten. In box 65, one or more auxiliary pads are formed in the tungsten layer arranged in the scribe regions, the one or more pads being electrically coupled to one or more of the auxiliary structures.

[0067] In another alternative method, a second conductive layer of the metallization structure is formed, which is located at the component position and exposes one or more auxiliary contact pads in the scribe area. The second conductive layer may include a different material from the first conductive layer and may be free of tungsten. The second conductive layer may include aluminum and / or copper, or nickel-based metallization (such as nickel-based NiV, NiP, NiMoP, NiPPd and NiPPd systems), or Au-based metallization or silver-based metallization (such as Ti / NiV / Ag stack).

[0068] The total thickness of the conductive layer in the component position may be greater than the thickness of the auxiliary contact pad in the scribe line area. For example, the tungsten layer and therefore the auxiliary contact pad may have a thickness of 100 nm to 900 nm. The second conductive layer may have a thickness that is at least 5 or 10 times greater than the thickness of the auxiliary contact pad and the thickness of the first conductive layer. The second conductive layer may have a thickness of about 5 μm.

[0069] In some embodiments, the method further includes forming a transistor device structure in the scribe area and the component position. The transistor device area may include a cell area or a cell field laterally surrounded by an edge termination area. In some embodiments, in the cell area, the method includes forming a main body area including a second conductivity type in a semiconductor layer including a first conductivity type forming a drift region, forming a source region including the first conductivity type on the main body area and forming a plurality of trenches. The second conductivity type is opposite to the first conductivity type. The semiconductor wafer may include a single crystal silicon wafer, which may include an epitaxially deposited silicon layer (commonly referred to as an epitaxial layer) that provides a drift region.

[0070] A trench may be formed in the first surface of the semiconductor wafer and extend through the source region, the body region and into the drift region.

[0071] In some embodiments, the trenches may have different lateral shapes. In some embodiments, the method further includes forming a plurality of columnar trenches, forming a field plate in each columnar trench, and forming a plurality of elongated trenches, thereby forming elongated trenches in the region of the semiconductor layer between the columnar trenches, and forming gate electrodes in the elongated trenches. The method may also include forming one or more insulating layers on the first surface, forming openings in the one or more insulating layers above the field plates, and inserting tungsten into the openings and onto the field plates. A first conductive layer is formed on the tungsten in the openings to electrically couple the first conductive layer to the field plates, the source regions, and the body regions.

[0072] In some embodiments, the tungsten filling the opening and the first conductive layer including tungsten are formed in a single process, such as a single deposition process. In some embodiments, the opening is filled with tungsten in a first deposition process, and the first conductive layer is deposited in a second deposition process. In some embodiments, an interface is discernible between the tungsten in the opening and the first conductive layer, indicating that two deposition processes were used.

[0073] After fabricating the wafer, the method may further comprise applying external contacts to the auxiliary contact pads and measuring one or more parameters of the auxiliary structures.

[0074] In some embodiments, the method may further include singulating the wafer by cutting along the scribe line regions and through the auxiliary structures and the auxiliary contact pads to form a plurality of semiconductor chips from the semiconductor wafer.

[0075] The manufacturing method described herein can be used to increase the yield of semiconductor chips from a wafer that meet desired standards, because the occurrence of undesirable effects such as sidewall crushing, slicing tool wear, etc. can be reduced due to the use of tungsten contact pads in the scribe area coupled to the auxiliary structure. These tungsten contact pads have a smaller thickness than the metallization structure of the active device in the component position, and can be manufactured using the process for forming a cross section of the metallization structure (e.g., one conductive layer) and excluded from the process for forming other parts of the metallization structure (e.g., subsequent conductive layers). If laser sawing is used to singulate the wafer into individual semiconductor chips, the processing time can be shorter and the processing window wider due to the reduced thickness of the tungsten pads in the scribe area. For example, the penetration depth in the slicing foil can be smaller in the area of ​​the kerf area without tungsten.

[0076] For ease of description, spatially relative terms such as "lower," "below," "below," "above," "upper," etc. are used to explain the positioning of one element relative to a second element. These terms are intended to include different orientations of the device in addition to orientations that are different from those depicted in the figures. In addition, terms such as "first," "second," etc. are also used to describe various elements, regions, portions, etc., and are also not intended to be limiting. The same terms refer to the same elements throughout the description.

[0077] As used herein, the terms "having", "containing", "including", "comprising", etc. are open terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" are intended to include the plural as well as the singular. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically stated.

[0078] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor wafer, comprising: a plurality of component locations, wherein the scribe line region is positioned at least one of adjacent to and between component locations, the component locations including active device structures, at least one auxiliary structure located in one or more of the scribe line regions, wherein the auxiliary structure is electrically coupled to an auxiliary contact pad comprising tungsten, wherein the auxiliary contact pad comprises an exposed tungsten surface, wherein the auxiliary contact pad is coplanar with a first conductive layer of a metallization structure located on and electrically coupled to the active device structure in the component location, The metallization structure further includes a second conductive layer, wherein the second conductive layer is located in the component position, and the scribe line area is free of the second conductive layer. 2 . The semiconductor wafer according to claim 1 , wherein the auxiliary contact pad has a thickness of 50 nm to 1000 nm. 3 . The semiconductor wafer according to claim 1 , wherein the auxiliary contact pad is located in the scribe line region.

4. A semiconductor wafer according to claim 1 or claim 2, wherein the auxiliary structures and the active device structures each comprise a transistor device structure comprising a cell region laterally surrounded by an edge termination region.

5. A semiconductor chip according to claim 4, wherein the unit area includes a semiconductor layer including a first conductivity type forming a drift region, a main region including a second conductivity type opposite to the first conductivity type on the drift region, a source region including the first conductivity type on the main region, and a plurality of trenches, each trench including at least one of a field plate and a gate electrode. 6 . The semiconductor wafer of claim 5 , wherein the plurality of trenches comprises a plurality of pillar-shaped trenches, each pillar-shaped trench comprising a field plate and a plurality of elongated trenches, each elongated trench comprising a gate electrode.

7. The semiconductor wafer of claim 6 , wherein the transistor device structure further comprises one or more insulating layers disposed on the elongated trench and on the source region and a tungsten plug extending through the one or more insulating layers and disposed on the field plate, wherein the first conductive layer is disposed on the tungsten plug and is electrically coupled to the source region and the body region.

8. A method for manufacturing a semiconductor wafer, comprising: Providing semiconductor wafers; forming active device structures in component locations, wherein the scribe line regions are positioned at least one of adjacent to and between the component locations; forming one or more auxiliary structures in one or more of the scribe line regions; forming a metallization structure on the component location and the scribe line area, wherein a first conductive layer of the metallization structure comprises tungsten; forming one or more auxiliary contact pads in the tungsten layer arranged in the scribe line region, which are electrically coupled to one or more of the auxiliary structures; A second conductive layer of the metallization structure is formed, the second conductive layer being located over the component location and exposing one or more auxiliary contact pads in the scribe line region, wherein the second conductive layer is free of tungsten.

9. The method of claim 8, wherein at least one of forming the auxiliary structure and forming the active device structure comprises: forming a body region including a second conductivity type opposite to the first conductivity type in a semiconductor layer including a first conductivity type forming a drift region; forming a source region including the first conductivity type on the body region; forming a plurality of columnar trenches, and forming a field plate in each columnar trench; forming elongated trenches in regions of the semiconductor layer between the pillar-shaped trenches; forming a gate electrode in the elongated trench; forming one or more insulating layers disposed on the pillar-shaped trench, the elongated trench, and the source region; forming openings in one or more insulating layers above the field plates; inserting tungsten into the opening and onto the field plate, The first conductive layer is formed on the tungsten in the opening to electrically couple the first conductive layer to the source region and the body region.

10. A method according to claim 8 or claim 9, further comprising applying an external contact to the auxiliary contact pad and measuring one or more parameters of the auxiliary structure.

11. The method of claim 8 or claim 9, further comprising singulating the wafer by cutting along the scribe line regions and through the auxiliary structures and the auxiliary contact pads.

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