Semiconductor packaging system

Abstract

A semiconductor packaging system is provided. The semiconductor packaging system includes: a substrate; a first semiconductor package on the substrate; a second semiconductor package on the substrate; a first passive component on the substrate; a heat dissipation structure above the first semiconductor package, the second semiconductor package, and the first passive component; and a first heat conduction layer between the first semiconductor package and the heat dissipation structure. The sum of the height of the first semiconductor package and the thickness of the first heat conduction layer is greater than the height of the first passive component. The height of the first semiconductor package is greater than the height of the second semiconductor package.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Korean Patent Application No. 10-2018-0054304, filed on May 11, 2018, Korean Patent Application No. 10-2018-0054305, filed on May 11, 2018, Korean Patent Application No. 10-2018-0054307, filed on May 11, 2018, Korean Patent Application No. 10-2018-0055081, filed on May 14, 2018, and Korean Patent Application No. 10-2018-0110511, filed on September 14, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure herein relates to semiconductor packaging systems, and more particularly to semiconductor packaging systems having heat dissipation structures. Background Art

[0004] Semiconductor packages are implemented in a form suitable for use in electronic products. Generally, semiconductor packages are usually mounted with a semiconductor chip on a printed circuit board (PCB), and the printed circuit board and the semiconductor chip are electrically connected to each other using bonding wires or bumps. As the speed and capacity of semiconductor packages increase, the power consumption of semiconductor packages is also increasing. Therefore, the thermal characteristics of semiconductor packages become more important. Summary of the invention

[0005] The inventive concept relates to a semiconductor package having improved thermal characteristics and a semiconductor module including the semiconductor package.

[0006] According to an embodiment of the present inventive concept, a semiconductor packaging system may include: a substrate; a first semiconductor package on the substrate; a second semiconductor package on the substrate; a first passive element on the substrate; a heat dissipation structure disposed above the first semiconductor package, the second semiconductor package, and the first passive element; and a first heat conduction layer between the first semiconductor package and the heat dissipation structure. The sum of the height of the first semiconductor package and the thickness of the first heat conduction layer may be greater than the height of the first passive element. The height of the first semiconductor package may be greater than the height of the second semiconductor package.

[0007] In an embodiment of the present inventive concept, a semiconductor packaging system may include: a substrate; a first semiconductor package located on an upper surface of the substrate, the first semiconductor package including a first semiconductor chip, the first semiconductor chip including one or more logic circuits; a second semiconductor package on the upper surface of the substrate; a passive element on the upper surface of the substrate; a heat dissipation structure above the first semiconductor package, the second semiconductor package and the passive element; and a plurality of heat-conducting layers, each of the plurality of heat-conducting layers being in physical contact with a lower surface of the heat-dissipating structure. The plurality of heat-conducting layers may include a first heat-conducting layer located on the upper surface of the first semiconductor package, and among the plurality of heat-conducting layers, the first heat-conducting layer may have the thinnest thickness.

[0008] In an embodiment of the present inventive concept, a semiconductor packaging system may include: a substrate; a first semiconductor package on the substrate, the first semiconductor package including a first semiconductor chip, the first semiconductor chip including one or more logic circuits; a second semiconductor package on the substrate; a passive component on the substrate; a heat dissipation structure above the first semiconductor package, the second semiconductor package and the passive component; a first thermal conductive layer on the first semiconductor package, the first thermal conductive layer being in physical contact with the heat dissipation structure; and a second thermal conductive layer on the second semiconductor package, the second thermal conductive layer being in physical contact with the heat dissipation structure. The thickness of the first thermal conductive layer may be less than the thickness of the second thermal conductive layer. The upper surface of the first thermal conductive layer may be disposed at a higher level than the upper surface of the passive component. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate example embodiments of the inventive concept and, together with the description, are used to explain the principles of the inventive concept. In the accompanying drawings:

[0010] Figure 1A is a top view showing a packaging system according to an example embodiment;

[0011] Figure 1B is a top view showing a packaging system according to an example embodiment;

[0012] Figure 1C is along Figure 1A A cross-sectional view taken along line I-II in FIG.

[0013] Figure 1D yes Figure 1C An enlarged view of area A in FIG.

[0014] Figure 1Eyes Figure 1C An enlarged view of region B in FIG.

[0015] Figure 1F is a view showing a packaging system according to an example embodiment;

[0016] Figure 1G Corresponds to Figure 1A An enlarged view of region III in FIG.

[0017] Figure 1H is along Figure 1G A cross-sectional view taken along line I'-II' in FIG.

[0018] Fig. 1I is a view for explaining a first semiconductor package according to example embodiments;

[0019] Figure 2A is a top view showing a packaging system according to an example embodiment;

[0020] Figure 2B is along Figure 2A A cross-sectional view taken along line I-II in FIG.

[0021] Figure 2C is a top view showing a packaging system according to an example embodiment;

[0022] Figure 2D is along Figure 2C A cross-sectional view taken along line I-II in FIG.

[0023] Figure 2E is a cross-sectional view showing a packaging system according to an example embodiment;

[0024] Figure 3A is a cross-sectional view showing a packaging system according to an example embodiment;

[0025] Figure 3B is a cross-sectional view showing a packaging system according to an example embodiment;

[0026] Figure 3C is a cross-sectional view showing a packaging system according to an example embodiment;

[0027] Figure 4A is a cross-sectional view showing a packaging system according to an example embodiment;

[0028] Figure 4B is a cross-sectional view showing a packaging system according to an example embodiment;

[0029] Figure 4C is a cross-sectional view showing a packaging system according to an example embodiment;

[0030] Figure 5Ais a cross-sectional view showing a semiconductor module according to an example embodiment;

[0031] Figure 5B is a view for explaining a second passive element according to an example embodiment, and is a view showing Figure 5A A cross-sectional view of an enlarged view of region C in FIG.

[0032] Figure 5C is a view for explaining a lower pad and a conductive terminal according to an example embodiment; and

[0033] Figure 5D is a view for explaining a lower pad according to example embodiments. DETAILED DESCRIPTION

[0034] In this specification, the same reference numerals refer to the same components throughout the specification. Hereinafter, a packaging system according to the inventive concept and a semiconductor module including the packaging system will be described. The semiconductor packaging system may be a packaging system or a semiconductor module including the packaging system.

[0035] Figure 1A is a top view illustrating a packaging system according to example embodiments. Figure 1B is a top view illustrating a packaging system according to example embodiments. Figure 1C is along Figure 1A A cross-sectional view taken along line I-II in FIG. Figure 1D yes Figure 1C Magnified view of area A in FIG. Figure 1E yes Figure 1C Magnified view of area B in FIG.

[0036] Reference Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E , the packaging system 1 includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive element 400, a heat dissipation structure 600, and a first heat-conducting layer 710. As an example, a printed circuit board (PCB) having a circuit pattern can be used as the substrate 500. The conductive terminal 550 can be disposed on the lower surface of the substrate 500. The conductive terminal 550 can include at least one of a solder ball, a bump, and a column. The conductive terminal 550 can include, for example, a metal.

[0037] The first semiconductor package 100 may be mounted on the upper surface 500a of the substrate 500. As described later, the first semiconductor package 100 may include a logic chip or a system-on-chip. The first connection terminal 150 may be inserted between the substrate 500 and the first semiconductor package 100. The first semiconductor package 100 may be electrically connected to the substrate 500 through the first connection terminal 150. In this specification, the electrical connection with the substrate 500 may mean an electrical connection with the interconnections 505 in the substrate 500. The first connection terminal 150 may include a solder ball, a column, a bump, or a ball grid array. The height H1 of the mounted first semiconductor package 100 may be defined as the height including the first connection terminal 150. In this specification, the height of any component may represent the maximum distance from the upper surface of the component to the upper surface 500a measured in a direction perpendicular to the upper surface 500a of the substrate 500. The pitch of the first connection terminal 150 may be smaller than the pitch of the conductive terminal 550.

[0038] The second semiconductor package 200 may be mounted on the upper surface 500a of the substrate 500. In the top view of the packaging system 1, the second semiconductor package 200 may be spaced apart from the first semiconductor package 100. The second semiconductor package 200 may be a semiconductor package of a different type from the first semiconductor package 100. The second connection terminal 250 may be inserted between the substrate 500 and the second semiconductor package 200. The second semiconductor package 200 may be electrically connected to the substrate 500 through the second connection terminal 250. The second connection terminal 250 may include a solder ball, a column, a bump, or a ball grid array. The pitch of the second connection terminal 250 may be less than the pitch of the conductive terminal 550. The height H2 of the mounted second semiconductor package 200 may be defined as the height including the second connection terminal 250. A plurality of second semiconductor packages 200 may be provided. The second semiconductor packages 200 may be spaced apart from each other. However, various modifications may be made to the number and planar arrangement of the second semiconductor package 200.

[0039] The third semiconductor package 300 may be mounted on the substrate 500. In a top view of the packaging system 1, the third semiconductor package 300 may be spaced apart from the first semiconductor package 100 and the second semiconductor package 200. The third semiconductor package 300 may be a semiconductor package of a different type from the first semiconductor package 100 and the second semiconductor package 200. Figure 1A As shown, a third semiconductor package 300 may be provided. As another example, Figure 1BAs shown, a plurality of third semiconductor packages 300 may be provided. In this case, the third semiconductor packages 300 may be spaced apart from each other. The number and planar arrangement of the third semiconductor packages 300 may be variously modified without limitation. Figure 1A and Figure 1B Hereinafter, a case of a third semiconductor package 300 will be described. Figure 1C As shown, the third connection terminal 350 may be inserted between the substrate 500 and the third semiconductor package 300. The third semiconductor package 300 may be electrically connected to the substrate 500 through the third connection terminal 350. The third connection terminal 350 may include a solder ball, a pillar, a bump, or a ball grid array. The pitch of the third connection terminal 350 may be smaller than the pitch of the conductive terminal 550. The height H3 of the mounted third semiconductor package 300 may be defined as the height including the third connection terminal 350. The height H1 of the mounted first semiconductor package 100 may be greater than the height H3 of the mounted third semiconductor package 300.

[0040] The first passive component 400 may be mounted on the upper surface 500a of the substrate 500. In the top view of the packaging system 1, the first passive component 400 may be spaced apart from the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300. The first passive component 400 may include any one of an inductor, a resistor, and a capacitor. A first connection terminal portion 401 may also be provided between the substrate 500 and the first passive component 400, such as Figure 1D As shown. The first connection terminal portion 401 may include, for example, solder, a column, a bump, or a ball grid array. The height H4 of the installed first passive component 400 may be defined as including the height of the first connection terminal portion 401. For example, the height H4 of the first passive component 400 may be equal to the sum of the height H41 of the first connection terminal portion 401 and the height H40 of the first passive component 400' before installation. The height H4 of the installed first passive component 400 may be substantially equal to the distance between the upper surface 500a of the substrate 500 and the uppermost surface of the first passive component 400. A plurality of first passive components 400 may be provided. As Figure 1A and Figure 1B As shown, the first passive elements 400 may be spaced apart from each other. The number and planar arrangement of the first passive elements 400 may be variously modified. Hereinafter, a case where one first passive element 400 is used will be described. Figure 1D The first connection terminal portion 401 is omitted in other drawings, but the present inventive concept is not limited thereto.

[0041] The heat dissipation structure 600 may be disposed on the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, and the first passive component 400. The lower surface 600b of the heat dissipation structure 600 may face the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300. The lower surface 600b of the heat dissipation structure 600 may be substantially flat. For example, the lower surface 600b of the heat dissipation structure 600 above the first semiconductor package 100, the lower surface 600b of the heat dissipation structure 600 above the second semiconductor package 200, the lower surface 600b of the heat dissipation structure 600 above the third semiconductor package 300, the lower surface 600b of the heat dissipation structure 600 above the first semiconductor package 300, and the lower surface 600b of the heat dissipation structure 600 above the first passive component 400 may be disposed at substantially the same horizontal plane. Additional processing of the lower surface 600b of the heat dissipation structure 600 is omitted, so that the manufacture of the heat dissipation structure 600 can be simplified. The processing may include forming grooves or forming protrusions. The heat dissipation structure 600 may include a thermally conductive material. The thermally conductive material may include a metal (e.g., copper and / or aluminum) or a carbonaceous material (e.g., graphene, graphite and / or carbon nanotubes). The heat dissipation structure 600 may have a relatively high thermal conductivity. As an example, a single metal layer or a plurality of stacked metal layers may be used as the heat dissipation structure 600. As another example, the heat dissipation structure 600 may include a radiator or a heat pipe. As another example, the heat dissipation structure 600 may use a water cooling method. The heat dissipation structure 600 may include a first heat dissipation structure 610. The first heat dissipation structure 610 may be spaced apart from the substrate 500.

[0042] The first heat conducting layer 710 may be inserted between the first semiconductor package 100 and the heat dissipation structure 600. The first heat conducting layer 710 may be in physical contact with the upper surface of the first semiconductor package 100 and the lower surface 600b of the heat dissipation structure 600. The first heat conducting layer 710 may include a thermal interface material (TIM). The thermal interface material may include, for example, a polymer and heat conducting particles. The heat conducting particles may be dispersed in the polymer. During operation of the first semiconductor package 100, the heat generated from the first semiconductor package 100 may be transferred to the heat dissipation structure 600 through the first heat conducting layer 710.

[0043] According to example embodiments, a sum of a height H1 of the mounted first semiconductor package 100 and a thickness A1 of the first heat conductive layer 710 may be greater than a height H4 of the mounted first passive component 400. Even if the first passive component 400 is disposed on the upper surface 500a of the substrate 500, the first heat conductive layer 710 may be in physical contact with the first semiconductor package 100 and the heat dissipation structure 600.

[0044] The second heat-conducting layer 720 may be disposed between the second semiconductor package 200 and the heat dissipation structure 600. The second heat-conducting layer 720 may be in physical contact with the upper surface of the second semiconductor package 200 and the lower surface 600b of the heat dissipation structure 600. For example, the second heat-conducting layer 720 may include a thermal interface material. During operation of the second semiconductor package 200, heat generated from the second semiconductor package 200 may be transferred to the heat dissipation structure 600 through the second heat-conducting layer 720.

[0045] The third heat-conducting layer 730 may be disposed between the third semiconductor package 300 and the heat dissipation structure 600. The third heat-conducting layer 730 may be in physical contact with the upper surface of the third semiconductor package 300 and the lower surface 600 b of the heat dissipation structure 600. For example, the third heat-conducting layer 730 may include a thermal interface material. During operation of the third semiconductor package 300, heat generated from the third semiconductor package 300 may be transferred to the third semiconductor package 300 through the third heat-conducting layer 730.

[0046] During operation of the packaging system 1, a large amount of heat may be generated from the first semiconductor package 100. For example, the first semiconductor package 100 may generate more heat than the second semiconductor package 200, the third semiconductor package 300, and the first passive element 400. The thermal characteristics of the first semiconductor package 100 may have a greater impact on the operating characteristics of the packaging system 1 than the thermal characteristics of the second semiconductor package 200 and the third semiconductor package 300. As the thermal characteristics of the first semiconductor package 100 are improved, the operating characteristics of the packaging system 1 may be improved. The first heat conductive layer 710, the second heat conductive layer 720, and the third heat conductive layer 730 may each have a thermal conductivity lower than that of the heat dissipation structure 600. As the thickness A1 of the first heat conductive layer 710 decreases, the heat generated from the first semiconductor package 100 may be dissipated faster to the heat dissipation structure 600. According to example embodiments, among the thicknesses of the heat conductive layers contacting the lower surface 600b of the heat conductive structure 600, the thickness A1 of the first heat conductive layer 710 may be the smallest. Here, the heat conducting layer may include a first heat conducting layer 710, a second heat conducting layer 720, and a third heat conducting layer 730. The heat conducting layer may further include a conductive adhesive pattern 741, which will be referred to later. FIG. 2A to FIG. 2D A conductive adhesive pattern 741 is described. For example, a thickness A1 of the first heat conductive layer 710 may be less than a thickness A2 of the second heat conductive layer 720 and less than a thickness A3 of the third heat conductive layer 730. Therefore, heat generated from the first semiconductor package 100 may be transferred to the heat dissipation structure 600 more quickly. The packaging system 1 may exhibit improved operating characteristics.

[0047] An electronic component 430 may also be disposed on the upper surface 500a of the substrate 500. The electronic component 430 may include an oscillator such as a crystal oscillator or a real-time clock. Figure 1E As shown, the conductive connection terminal 403 may be further disposed between the electronic component 430 and the upper surface 500a of the substrate 500 to electrically connect to the electronic component 430 and the substrate 500. The height H5 of the installed electronic component 430 may be defined as including the height H51 of the conductive connection terminal 403. The height H5 of the installed electronic component 430 may be equal to the sum of the height H51 of the conductive connection terminal 403 and the height H50 of the electronic component 430' before installation. The sum of the height H1 of the installed first semiconductor package 100 and the thickness A1 of the first heat-conducting layer 710 may be greater than the height H5 of the installed electronic component 430. Although the electronic component 430 is disposed on the upper surface 500a of the substrate 500, the heat generated from the first semiconductor package 100 can still be smoothly discharged to the heat dissipation structure 600 through the first heat-conducting layer 710. As another example, the electronic component 430 may not be disposed. For simplicity, except for Figure 1E The conductive connection terminal 403 is omitted in the other drawings, but the inventive concept is not limited thereto. Hereinafter, electrical connection of the semiconductor package 100 , the semiconductor package 200 , and the semiconductor package 300 will be described.

[0048] The first semiconductor package 100 is electrically connected to the second semiconductor package 200, the third semiconductor package 300, and the conductive terminal 550 through the interconnect 505 in the substrate 500. Figure 1C The second semiconductor package 200 may be electrically connected to the first semiconductor package 100, the third semiconductor package 300, and the conductive terminal 550 through the interconnection 505 in the substrate 500. The third semiconductor package 300 may be electrically connected to the first semiconductor package 100, the second semiconductor package 200, and the conductive terminal 550 through the interconnection 505 in the substrate 500.

[0049] The first bottom filling film 160 may be disposed in the gap between the substrate 500 and the first semiconductor package 100 to seal the first connection terminal 150. The second bottom filling film 260 may be disposed in the gap between the substrate 500 and the second semiconductor package 200 to seal the second connection terminal 250. The third bottom filling film 360 may be disposed in the gap between the substrate 500 and the second semiconductor package 200 to seal the third connection terminal 350. The first bottom filling film 160, the second bottom filling film 260, and the third bottom filling film 360 may include an insulating polymer such as an epoxy-based polymer. When the first bottom filling film 160, the second bottom filling film 260, and the third bottom filling film 360 are disposed, the bonding reliability of the first connection terminal 150, the second connection terminal 250, and the third connection terminal 350 may be improved. Unlike the illustrated embodiment, at least one of the first bottom filling film 160, the second bottom filling film 260, and the third bottom filling film 360 may be omitted.

[0050] A dam structure 590 may be further provided on the upper surface 500a of the substrate 500. The dam structure 590 may be provided between the third semiconductor package 300 and the first passive element 400. The dam structure 590 may be formed by using a liquid resin. Although not shown in the figure, the substrate 500 may include a plurality of layers, and the uppermost layer of the plurality of layers may include an insulating polymer such as a solder resist material. In one example, the dam structure 590 may be formed integrally with the uppermost layer of the substrate 500. In this case, the dam structure 590 may be connected to the uppermost layer of the substrate 500 without an interface. As another example, the dam structure 590 may include a material different from the substrate 500. For example, the dam structure 590 may be formed of the same material as any one of the first bottom fill film 160, the second bottom fill film 260, and the third bottom fill film 360. The height of the dam structure 590 may be equal to or less than the sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first heat conducting layer 710.

[0051] Various modifications may be made to the arrangement and number of the dam structure 590. For example, the dam structure 590 may be disposed between the first semiconductor package 100 and the first passive element 400. As another example, the dam structure 590 may be disposed between the second semiconductor package 200 and the first passive element 400. Figure 1A As shown, a plurality of dam structures 590 may be provided. The plurality of dam structures 590 may be spaced apart from each other. Hereinafter, each of the first semiconductor package 100 , the second semiconductor package 200 , and the third semiconductor package 300 will be described in more detail.

[0052] Figure 1F is a view showing a packaging system according to an example embodiment, corresponding to Figure 1A The cross section is taken along the line I-II in FIG. In the following, the contents repeated with the above contents will be omitted. Figure 1F In the description of Figure 1A , Figure 1B and Figure 1C .

[0053] Reference Figure 1F The packaging system 1a includes a substrate 500 , a first semiconductor package 100 , a second semiconductor package 200 , a third semiconductor package 300 , a first passive component 400 , a first heat conducting layer 710 , a second heat conducting layer 720 , a third heat conducting layer 730 and a heat dissipation structure 600 .

[0054] The first semiconductor package 100 may include a first substrate 110, a first semiconductor chip 120, and a first molding layer 130. As an example, a printed circuit board (PCB) may be used as the substrate 500. As another example, a redistribution layer may be used as the substrate 500. The first semiconductor chip 120 may be a flip chip mounted on the first substrate 110. The connection portion may be provided between the first semiconductor chip 120 and the first substrate 110. The connection portion may include a solder ball, a column, a bump, or a ball grid array. The first semiconductor chip 120 may be a system on a chip (SOC), a logic chip, or an application processor (AP) chip. The first semiconductor chip 120 may include circuits with different functions. The first semiconductor chip 120 may include a logic circuit and a storage circuit. The first semiconductor chip 120 may also include at least one of a digital integrated circuit (IC), a wireless radio frequency integrated circuit (RFIC), and an input / output circuit. Generating heat from the first semiconductor package 100 may refer to generating heat from the first semiconductor chip 120.

[0055] The first mold layer 130 may be disposed on the first substrate 110 to cover the first semiconductor chip 120. The first mold layer 130 covers the side surface and the upper surface of the first semiconductor chip 120 to seal the first semiconductor chip 120. In this case, the upper surface of the first semiconductor package 100 may correspond to the upper surface of the first mold layer 130. The first mold layer 130 may include an insulating polymer such as an epoxy molding compound. The first mold layer 130 may further extend into the gap between the first substrate 110 and the first semiconductor chip 120. Unlike the case shown, an additional bottom fill pattern may be filled in the gap between the first substrate 110 and the first semiconductor chip 120. The bottom fill pattern may be formed by a method of hot pressing a non-conductive paste or a non-conductive film or by a capillary bottom fill process. The height H1 of the mounted first semiconductor package 100 is defined as the sum of the height of the first connection terminal 150, the height of the first substrate 110, and the height of the first mold layer 130.

[0056] The second semiconductor package 200 may include a second substrate 210, a second semiconductor chip 220, and a second molding layer 230. A printed circuit board (PCB) or a redistribution layer may be used as the substrate 500. The second semiconductor chip 220 may be a semiconductor chip of a different type from the first semiconductor chip 120. For example, the second semiconductor chip 220 may be used as a memory chip. The memory chip may include a DRAM chip. As another example, the memory chip may include an SRAM, an MRAM, and / or a NAND flash memory. Generating heat from the second semiconductor package 200 may refer to generating heat from the second semiconductor chip 220. The second semiconductor chip 220 may be mounted by a flip-chip method or a wire bonding method. When the second semiconductor chip 220 is mounted by a flip-chip method, an additional bottom fill pattern may be filled in the gap between the second substrate 210 and the second semiconductor chip 220. The second semiconductor package 200 may include a plurality of second semiconductor chips 220. As another example, the second semiconductor package 200 may include a single second semiconductor chip 220. The second molding layer 230 covers the side surface and the upper surface of the second semiconductor chip 220 to seal the second semiconductor chip 220. In this case, the upper surface of the second semiconductor package 200 may correspond to the upper surface of the second mold layer 230. Unlike the case shown, the second mold layer 230 covers the side surface of the second semiconductor chip 220 and may expose the upper surface of the second semiconductor chip 220. In this case, the upper surface of the second semiconductor package 200 may correspond to the upper surface of the second mold layer 230 and the upper surface of the second semiconductor chip 220 exposed by the second mold layer 230. The second mold layer 230 may include an insulating polymer such as an epoxy polymer. The height H2 of the mounted second semiconductor package 200 is defined as the sum of the height of the second connection terminal 250, the height of the second substrate 210, and the height of the second mold layer 230.

[0057] The third semiconductor package 300 may include a third substrate 310, a third semiconductor chip 320, and a third mold layer 330. A redistribution layer or a printed circuit board may be used as the third substrate 310. When the redistribution layer is used as the third substrate 310, the third semiconductor package 300 may be manufactured with a fan-out panel level package or a fan-out wafer level package. The third semiconductor chip 320 may be a semiconductor chip of a different type from the first semiconductor chip 120 and the second semiconductor chip 220. For example, the third semiconductor chip 320 may include a power management integrated circuit (PMIC) used as a power management chip. Generating heat from the third semiconductor package 300 may mean heat generated from the third semiconductor chip 320. The third mold layer 330 may be disposed on the third substrate 310 to cover the upper surface and side surface of the third semiconductor chip 320. In this case, the upper surface of the third semiconductor package 300 may correspond to the upper surface of the third mold layer 330. Unlike the case shown, the third mold layer 330 covers the side surface of the third semiconductor chip 320 and may expose the upper surface of the third semiconductor chip 320. In this case, the upper surface of the third semiconductor package 300 may correspond to the upper surface of the third mold layer 330 and the upper surface of the third semiconductor chip 320 exposed by the third mold layer 330. The third mold layer 330 may include an insulating polymer such as an epoxy-based polymer. The height H3 of the mounted third semiconductor package 300 is defined as the sum of the height of the third connection terminal 350, the height of the third substrate 310, and the height of the third mold layer 330. The formation of the third semiconductor package 300 may include: arranging the third semiconductor chip 320 on a carrier substrate; forming the third mold layer 330 covering the third semiconductor chip 320; removing the carrier substrate to expose the lower surface of the third semiconductor chip 320; and forming a redistribution layer on the lower surface of the exposed third semiconductor chip 320 and the lower surface of the mold layer. In this case, the redistribution layer may be the third substrate 310.

[0058] Figure 1G Corresponds to Figure 1A Magnified view of region III. Figure 1H is along Figure 1G In the following description, reference is made to Figure 1A , Figure 1B , Figure 1C and Figure 1D .

[0059] Reference Figure 1G and Figure 1H, the first mark 139 may be disposed on the first mold layer 130. For example, the first mark 139 may be disposed on the upper surface of the first mold layer 130. Different from this, the first mark 139 may be disposed on the side surface of the first mold layer 130. The first mark 139 may be a recessed portion on one side surface of the first mold layer 130. The formation of the first mark 139 may include removing a portion of the first mold layer 130. When the first mark 139 is formed on the first semiconductor chip 120, the first semiconductor chip 120 may be damaged during the formation of the first mark 139. For example, a crack may be formed on or in the first semiconductor chip 120. According to example embodiments, the first mark 139 may be disposed on the first mold layer 130 so that the first semiconductor chip 120 is not damaged in the process of forming the first mark 139. The first mark 139 may provide and display information about the first semiconductor package 100. For convenience, in addition to Figure 1G to Figure 1I The first mark 139 is omitted in other drawings, but the present inventive concept is not limited thereto.

[0060] The first heat-conducting layer 710 may be formed on the upper surface of the first semiconductor package 100. The formation of the first heat-conducting layer 710 may include providing a thermal interface material on the first semiconductor package 100 and then curing the thermal interface material. The thermal interface material before curing may have fluidity. In the process of forming the first heat-conducting layer 710, even if the thermal interface material on the edge region of the upper surface of the first semiconductor package 100 flows down to the side surface 100c of the first semiconductor package 100, the thermal interface material on the central region of the upper surface of the first semiconductor package 100 does not flow downward. Therefore, the first heat-conducting layer 710 may well fill the gap between the central region of the upper surface of the first semiconductor package 100 and the heat dissipation structure 600. For example, the upper surface 710a of the first heat-conducting layer 710 in the central region of the first semiconductor package 100 may be in physical contact with the heat dissipation structure 600. According to example embodiments, since the first mold layer 130 is provided, the first semiconductor chip 120 may be provided in the central region of the first semiconductor package 100 in a top view of the packaging system 1. Therefore, even if the thermal interface material partially flows downward during the process of forming the first heat conductive layer 710, the first heat conductive layer 710 can well transfer the heat of the first semiconductor chip 120 to the first heat dissipation structure 610. When the first mold layer 130 includes the first mark 139, the first heat conductive layer 710 can extend into the first mark 139. Figure 1C, the second heat-conducting layer 720 may be disposed on the upper surface of the second molding layer 230. The formation of the second heat-conducting layer 720 may be performed by a method substantially the same as the method of forming the first heat-conducting layer 710 described. Although the thermal interface material partially flows downward during the formation of the second heat-conducting layer 720, the second heat-conducting layer 720 may well fill the gap between the central area of ​​the upper surface of the second semiconductor package 200 and the heat dissipation structure. The central area of ​​the second semiconductor package 200 may be an area where the second semiconductor chip 220 is disposed. Therefore, the heat generated from the second semiconductor chip 220 may be well discharged to the heat dissipation structure 600 through the second heat-conducting layer 720.

[0061] Although not shown in the drawings, a second mark may be further provided on the second mold layer 230. The second mark may be a recessed portion of the second mold layer 230.

[0062] The third heat-conducting layer 730 may be formed on the upper surface of the third mold layer 330. The formation of the third heat-conducting layer 730 may be performed by a method substantially the same as the method of forming the first heat-conducting layer described. At this time, although the thermal interface material partially flows downward during the formation of the third heat-conducting layer 730, the third heat-conducting layer 730 may well fill the gap between the central area of ​​the upper surface of the third semiconductor package 300 and the heat dissipation structure 600. The central area of ​​the third semiconductor package 300 may be an area where the third semiconductor chip 320 is disposed. Therefore, the thermal characteristics of the third semiconductor package 300 may be improved. Although not shown in the drawings, a third mark may be further disposed on the third mold layer 330. The third mark may be a recessed portion of the third mold layer 330.

[0063] Fig. 1I is a view for explaining a first semiconductor package according to an example embodiment, and corresponds to Figure 1G The cross section is taken along line I'-II'.

[0064] Reference Figure 1G and Fig. 1I, the first semiconductor package 100 may include a first substrate 110, a first semiconductor chip 120, and a first mold layer 130. The first mold layer 130 covers the side surface of the first semiconductor chip 120 and may expose the upper surface of the first semiconductor chip 120. In this case, the upper surface of the first semiconductor package 100 may correspond to the upper surface of the first mold layer 130 and the upper surface of the first semiconductor chip 120 exposed by the first mold layer 130. The exposed upper surface of the first semiconductor chip 120 may be in direct physical contact with the first heat conducting layer 710. The heat generated from the first semiconductor chip 120 may be transferred to the heat dissipation structure 600 through the first heat conducting layer 710. Therefore, the heat dissipation characteristics of the first semiconductor chip 120 may be further improved.

[0065] Figure 2A is a top view illustrating a packaging system according to example embodiments. Figure 2B is along Figure 2A A cross-sectional view taken along line I-II in FIG.

[0066] Reference Figure 2A and Figure 2B The packaging system 1b includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive component 400, a first heat-conducting layer 710, a second heat-conducting layer 720, a third heat-conducting layer 730, and a heat dissipation structure 600. The substrate 500, the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, the first passive component 400, and the first heat-conducting layer 710, the second heat-conducting layer 720, and the third heat-conducting layer 730 can be the same as those described above. FIG. 1A to FIG. 1I Those described are essentially the same.

[0067] A ground pattern may be provided on the upper surface 500a of the substrate 500. The ground pattern may include a ground pad 510G. At least one of the conductive terminals 550 may be used as a ground terminal. A ground voltage may be applied to the ground pad 510G through the ground terminal and the substrate 500.

[0068] The heat dissipation structure 600 may include a second heat dissipation structure 620. The second heat dissipation structure 620 may include a main body portion 621 and a leg portion 622. The main body portion 621 of the second heat dissipation structure 620 may be similar to the previously described Figures 1A to 1CThe first heat dissipation structure 610 described above. The lower surface 600b of the heat dissipation structure 600 may include the lower surface of the main body portion 621 of the second heat dissipation structure 620. For example, the main body portion 621 may be disposed above the upper surface of the first semiconductor package 100, the upper surface of the second semiconductor package 200, and the upper surface of the first passive component 400. The first thermal conductive layer 710 may be in physical contact with the lower surface of the main body portion 621 of the second heat dissipation structure 620.

[0069] The leg portion 622 of the second heat dissipation structure 620 may be disposed between the edge region of the main body portion 621 and the substrate 500. The leg portion 622 of the second heat dissipation structure 620 may be connected to the main body portion 621. Figure 2A As shown, the first semiconductor package 100, the second semiconductor package 200 and the first passive component 400 may be spaced apart from the leg 622 of the second heat dissipation structure 620. In the top view of the package system 1b, the leg 622 may be disposed in the edge region of the substrate 500. The second heat dissipation structure 620 may include a thermally conductive material.

[0070] The second heat dissipation structure 620 has conductivity and can protect the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 from electromagnetic interference (EMI). EMI refers to electromagnetic waves radiated or conducted from electrical components that interfere with the receiving / transmitting functions of other electrical components. Through the second heat dissipation structure 620, the operation of the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, and the first passive component 400 will not interrupt the operation of another package or will not be interrupted by another package.

[0071] The adhesive patterns 741 and 742 may be disposed between the substrate 500 and the leg portion 622 of the second heat dissipation structure 620 to fix the second heat dissipation structure 620 to the substrate 500. The adhesive patterns 741 and 742 may include a conductive adhesive pattern 741 and an insulating adhesive pattern 742. The conductive adhesive pattern 741 may be disposed between the ground pad 510G and the leg portion 622 of the second heat dissipation structure 620. The second heat dissipation structure 620 may be connected to the ground pad 510G through the conductive adhesive pattern 741.

[0072] If more than a certain amount of charge is accumulated in the heat dissipation structure 600, the charge may flow from the heat dissipation structure 600 into another conductive component to damage the conductive component. The conductive component includes at least one of the following: integrated circuits and wires in the first semiconductor chip 120, the second semiconductor chip 220, and the third semiconductor chip 320, wires in the first substrate 110, the second substrate 210, and the third substrate 310, the first connection terminal 150, the second connection terminal 250, and the third connection terminal 350, and the interconnection in the substrate 500. According to example embodiments, a ground voltage may be applied to the second heat dissipation structure 620 through the conductive adhesive pattern 741. Therefore, the second heat dissipation structure 620 may limit and / or prevent electrical damage to the package system 1b due to electrostatic discharge (ESD).

[0073] The insulating adhesive pattern 742 may be disposed between the substrate 500 and the heat dissipation structure 600. Thus, the heat dissipation structure 600 is insulated from the substrate 500, thereby limiting and / or preventing an electrical short circuit. The thickness A5 of the conductive adhesive pattern 741 may be substantially the same as the thickness of the insulating adhesive pattern 742.

[0074] The height B of the leg 622 of the second heat dissipation structure 620 may be less than the height H1 of the mounted first semiconductor package 100. At this time, the height B of the leg 622 may be equal to the height of the inner surface of the second heat dissipation structure 620. The conductive adhesive pattern 741 may be in physical contact with the lower surface of the leg 622. Therefore, the thickness A1 of the first heat conductive layer 710 may be less than the thickness of the adhesive patterns 741 and 742 (e.g., the thickness A5 of the conductive adhesive pattern 741). Since the thickness A1 of the first heat conductive layer 710 is small, the heat generated from the first semiconductor package 100 may be transferred to the heat dissipation structure 600 through the first heat conductive layer 710 more quickly.

[0075] Figure 2C is a top view illustrating a packaging system according to example embodiments. Figure 2D is along Figure 2C A cross-sectional view taken along line I-II in FIG.

[0076] Reference Figure 2C and Figure 2D The packaging system 1c includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive component 400, a first heat-conducting layer 710, a second heat-conducting layer 720, a third heat-conducting layer 730, and a heat dissipation structure 600. The heat dissipation structure 600 may include a reference Figure 2A and Figure 2BThe second heat dissipation structure 620 is described. For example, the second heat dissipation structure 620 may include a main body portion 621 and a leg portion 622 .

[0077] The conductive adhesive pattern 741 may be disposed between the ground pad 510G and the leg portion 622 of the second heat dissipation structure 620 to connect with the second heat dissipation structure 620 and the ground pad 510G. Figure 2A and Figure 2B Unlike the example of , the insulating adhesive pattern 742 may not be provided. The thickness A1 of the first heat conductive layer 710 may be smaller than the thickness A5 of the conductive adhesive pattern 741 .

[0078] The substrate 500, the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, the first passive element 400, the first heat conducting layer 710, the second heat conducting layer 720 and the third heat conducting layer 730 may be the same as those described above. FIG. 1A to FIG. 1I Those described are essentially the same.

[0079] Figure 2E is a view showing a packaging system according to an example embodiment, corresponding to Figure 2C A cross section taken along line I-II in FIG. hereinafter, contents repeated with the above contents will be omitted.

[0080] Reference Figure 2C and Figure 2E The packaging system 1d includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive component 400, a first heat-conducting layer 710, a second heat-conducting layer 720, a third heat-conducting layer 730, and a heat dissipation structure 600. The substrate 500, the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, the first passive component 400, the first heat-conducting layer 710, the second heat-conducting layer 720, and the third heat-conducting layer 730 can be the same as those described above. Figures 1A to 1E Those described are essentially the same.

[0081] The heat dissipation structure 600 may include a first heat dissipation structure 610, a second heat dissipation structure 620 and a heat dissipation layer 630. The first heat dissipation structure 610 may be the same as that described above. Figures 1A to 1C The first heat dissipation structure 610 described above is substantially the same as that described above. However, the first heat dissipation structure 610 may be disposed on an upper surface of the second heat dissipation structure 620. The second heat dissipation structure 620 may be the same as that described above. FIG. 2A to FIG. 2DThe second heat dissipation structure 620 described above is substantially the same. For example, the second heat dissipation structure 620 may include a body portion 621 and a leg portion 622. The width of the first heat dissipation structure 610 may be equal to or wider than the width of the second heat dissipation structure 620. The conductive adhesive pattern 741 may be disposed between the ground pad 510G and the second heat dissipation structure 620. As another example, a conductive adhesive pattern 741 may be further provided between the ground pad 510G and the second heat dissipation structure 620. Figure 2A and Figure 2B The insulating adhesive pattern 742 described in the example of FIG. The heat dissipation layer 630 may be interposed between the first heat dissipation structure 610 and the second heat dissipation structure 620. The heat dissipation layer 630 may include, for example, a thermal interface material.

[0082] Figure 3A is a cross-sectional view showing a packaging system according to an example embodiment, corresponding to the Figure 2A A cross section taken along line I-II in FIG. hereinafter, contents repeated with the above contents will be omitted.

[0083] Reference Figure 2C and Figure 3A The packaging system 1e includes a substrate 500 , a first semiconductor package 100 , a second semiconductor package 200 , a third semiconductor package 300 , a first passive component 400 , a first heat conducting layer 710 , a second heat conducting layer 720 , a third heat conducting layer 730 and a heat dissipation structure 600 .

[0084] The first semiconductor package 100 includes a first adhesive layer 141 and a first heat-conducting structure 140 in addition to a first substrate 110, a first semiconductor chip 120, and a first molding layer 130. The first heat-conducting structure 140 may have a relatively high thermal conductivity. Figures 1A to 1C In one example, the first heat conductive structure 140 may include a metal layer, a heat sink, or a heat pipe. As another example, the first heat conductive structure 140 may use a water cooling method. The first adhesive layer 141 may be disposed between the first molding layer 130 and the first heat conductive structure 140. The first adhesive layer 141 may include a thermal interface material. During operation of the first semiconductor package 100, heat generated from the first semiconductor chip 120 may be transferred to the first heat conductive layer 710 through the first adhesive layer 141 and the first heat conductive structure 140.

[0085] According to example embodiments, the upper surface of the first semiconductor package 100 may correspond to the upper surface of the first heat conducting structure 140. The height H1 of the mounted first semiconductor package 100 is defined as the sum of the height of the first connection terminal 150, the height of the first substrate 110, the height of the first mold layer 130, the height of the first adhesive layer 141, and the height of the first heat conducting structure 140. Even if the upper surface of the first mold layer 130 is disposed lower than the upper surface of the second semiconductor package 200 or the upper surface of the third semiconductor package 300, the height H1 of the mounted first semiconductor package 100 may be greater than the height H2 of the mounted second semiconductor package 200 and the height H3 of the mounted third semiconductor package 300 by disposing the first adhesive layer 141 and the first heat conducting structure 140. The thickness A1 of the first heat conducting layer 710 may be less than the thickness A2 of the second heat conducting layer 720 and less than the thickness A3 of the third heat conducting layer 730. Therefore, the thermal characteristics of the first semiconductor package 100 may be improved.

[0086] The substrate 500, the second semiconductor package 200, the third semiconductor package 300, the first passive element 400, the first heat conducting layer 710, the second heat conducting layer 720, the third heat conducting layer 730 and the heat dissipation structure 600 may be similar to the reference Figures 1A to 1F and FIG. 2A to FIG. 2E Those described are essentially the same.

[0087] Figure 3B is a cross-sectional view showing a packaging system according to an example embodiment, corresponding to the Figure 2C A cross section taken along line I-II in FIG. hereinafter, contents repeated with the above contents will be omitted.

[0088] Reference Figure 2C and Figure 3B , the packaging system 1f includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive component 400, a first heat-conducting layer 710, a second heat-conducting layer 720, a third heat-conducting layer 730, and a heat dissipation structure 600. The substrate 500, the first semiconductor package 100, the first passive component 400, the first heat-conducting layer 710, the second heat-conducting layer 720, the third heat-conducting layer 730, and the heat dissipation structure 600 may be substantially the same as those described above.

[0089] In addition to the second substrate 210, the second semiconductor chip 220 and the second mold layer 230, the second semiconductor package 200 also includes a second adhesive layer 241 and a second heat-conducting structure 240. The second heat-conducting structure 240 may include a heat-conducting material and may have a relatively high thermal conductivity. The second heat-conducting structure 240 may include a metal layer, a heat sink or a heat pipe. The second adhesive layer 241 may be disposed between the second mold layer 230 and the second heat-conducting structure 240. The second adhesive layer 241 may include a thermal interface material. During the operation of the second semiconductor package 200, the heat generated from the second semiconductor chip 220 may be transferred to the second heat-conducting layer 720 through the second adhesive layer 241 and the second heat-conducting structure 240.

[0090] The upper surface of the second semiconductor package 200 may correspond to the upper surface of the second heat conducting structure 240. The height H2 of the mounted second semiconductor package 200 is defined as the sum of the height of the second connection terminal 250, the height of the second substrate 210, the height of the second mold layer 230, the height of the second adhesive layer 241, and the height of the second heat conducting structure 240. The height H1 of the mounted first semiconductor package 100 may be greater than the height H2 of the mounted second semiconductor package 200. Therefore, the thickness A1 of the first heat conducting layer 710 may be less than the thickness A2 of the second heat conducting layer 720.

[0091] The third semiconductor package 300 includes, in addition to the third substrate 310, the third semiconductor chip 320 and the third mold layer 330, a third adhesive layer 341 and a third heat-conducting structure 340. The third heat-conducting structure 340 may include a heat-conducting material and may have a relatively high thermal conductivity. The third heat-conducting structure 340 may include a metal layer, a heat sink or a heat pipe. The third adhesive layer 341 may be disposed between the third mold layer 330 and the third heat-conducting structure 340. The third adhesive layer 341 may include a thermal interface material. During the operation of the third semiconductor package 300, the heat generated from the third semiconductor chip 320 may be transferred to the third heat-conducting layer 730 through the third adhesive layer 341 and the third heat-conducting structure 340.

[0092] The upper surface of the third semiconductor package 300 may correspond to the upper surface of the third heat conducting structure 340. The height H3 of the mounted third semiconductor package 300 is defined as the sum of the height of the third connection terminal 350, the height of the third substrate 310, the height of the third mold layer 330, the height of the third adhesive layer 341, and the height of the third heat conducting structure 340. The height H1 of the mounted first semiconductor package 100 may be greater than the height H3 of the mounted third semiconductor package 300. Therefore, the thickness A1 of the first heat conducting layer 710 may be less than the thickness A3 of the third heat conducting layer 730.

[0093] Unlike shown, the second adhesive layer 241 and the second thermally conductive structure 240 are omitted, and the second thermally conductive layer 720 may be as shown. Figure 2D As shown, the third heat conducting layer 730 is in direct contact with the upper surface of the second mold layer 230. As another example, the second adhesive layer 341 and the third heat conducting structure 340 are omitted, and the third heat conducting layer 730 can be in direct contact with the upper surface of the third mold layer 330.

[0094] Figure 3C is a cross-sectional view showing a packaging system according to an example embodiment, corresponding to the Figure 2A A cross section taken along line I-II in FIG. hereinafter, contents repeated with the above contents will be omitted.

[0095] Reference Figure 2C and Figure 3C , the packaging system 1g includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive component 400, a first heat-conducting layer 710, a second heat-conducting layer 720, a third heat-conducting layer 730, and a heat dissipation structure 600. The substrate 500, the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, the first passive component 400, the first heat-conducting layer 710, the second heat-conducting layer 720, the third heat-conducting layer 730, and the heat dissipation structure 600 are substantially the same as those described above.

[0096] The first semiconductor package 100 may be Figure 3A The first semiconductor package 100 described in the example of FIG. 1 is substantially the same. For example, the first semiconductor package 100 includes a first substrate 110, a first semiconductor chip 120, a first molding layer 130, a first adhesive layer 141, and a first thermal conductive structure 140. The second semiconductor package 200 and the third semiconductor package 300 may be respectively Figure 3B The second semiconductor package 200 includes a second substrate 210, a second semiconductor chip 220, a second mold layer 230, a second adhesive layer 241 and a second thermal conductive structure 240. The third semiconductor package 300 includes a third substrate 310, a third semiconductor chip 320, a third mold layer 330, a third adhesive layer 341 and a third thermal conductive structure 340.

[0097] The height H1 of the mounted first semiconductor package 100 may be greater than the height H2 of the mounted second semiconductor package 200 and greater than the height H3 of the mounted third semiconductor package 300. The thickness A1 of the first heat conductive layer 710 may be less than the thickness A2 of the second heat conductive layer 720 and less than the thickness A3 of the third heat conductive layer 730.

[0098] Figure 4Ais a cross-sectional view showing a packaging system according to an example embodiment, corresponding to the Figure 2C The cross section is taken along line I-II in FIG. Figure 4B is a cross-sectional view showing a packaging system according to an example embodiment, corresponding to the Figure 2C A cross section taken along line I-II in FIG. hereinafter, contents repeated with the above contents will be omitted.

[0099] Reference Figure 2C , Figure 4A and Figure 4B , the packaging system 1h or 1i includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive component 400, a first heat-conducting layer 710, and a heat dissipation structure 600. The substrate 500, the first semiconductor package 100, the second semiconductor package 200, the third semiconductor package 300, the first passive component 400, the first heat-conducting layer 710, and the heat dissipation structure 600 are substantially the same as those described above.

[0100] like Figure 4A As shown, the packaging system 1h may not include the second heat conducting layer 720. The sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first heat conducting layer 710 may be greater than the height H2 of the mounted second semiconductor package 200.

[0101] like Figure 4B As shown, the packaging system 1i may not include the third heat conducting layer 730. The sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first heat conducting layer 710 may be greater than the height H3 of the mounted third semiconductor package 300.

[0102] Figure 4C is a cross-sectional view showing a packaging system according to an example embodiment, corresponding to the Figure 2C A cross section taken along line I-II in FIG. hereinafter, contents repeated with the above contents will be omitted.

[0103] Reference Figure 2C and Figure 4C The packaging system 1j includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first passive component 400, a first heat-conducting layer 710, a second heat-conducting layer 720, a third heat-conducting layer 730, and a heat dissipation structure 600. The thickness A1 of the first heat-conducting layer 710 may be less than the thickness A2 of the second heat-conducting layer 720 and less than the thickness A3 of the third heat-conducting layer 730.

[0104] The fourth heat-conducting layer 740 is disposed between the first passive component 400 and the heat dissipation structure 600, so that the fourth heat-conducting layer 740 can be in physical contact with the upper surface of the first passive component 400 and the lower surface 600b of the heat dissipation structure 600. The fourth heat-conducting layer 740 may include a thermal interface material. The heat generated from the first passive component 400 may be transferred to the heat dissipation structure 600 through the fourth heat-conducting layer 740. The height H1 of the mounted first semiconductor package 100 may be greater than the height H4 of the mounted first passive component 400. For example, the upper surface of the first semiconductor package 100 may be higher than the upper surface of the first passive component 400. Therefore, the thickness A1 of the first heat-conducting layer 710 may be less than the thickness A4 of the fourth heat-conducting layer 740.

[0105] As another example, the second heat conducting layer 720 or the third heat conducting layer 730 may be omitted.

[0106] exist FIG. 3A to FIG. 3C and FIG. 4A to FIG. 4C In the description of FIG. 6 , the first heat dissipation structure 610 or the second heat dissipation structure 620 may be omitted. In this case, the heat dissipation layer 630 may not be provided.

[0107] exist FIG. 4A to FIG. 4C In the description, the first semiconductor package 100 may further include a first adhesive layer 141 and a first thermal conductive structure 140. The second semiconductor package 200 may further include a second adhesive layer 241 and a second thermal conductive structure 240. The third semiconductor package 300 may further include a third adhesive layer 341 and a third thermal conductive structure 340.

[0108] Figure 5A is a cross-sectional view illustrating a semiconductor module according to example embodiments. Figure 5B is a view for explaining a second passive element according to an example embodiment, and is a view showing Figure 5A A cross-sectional view of an enlarged view of area C in FIG. Figure 5C is a view for explaining a lower pad and a conductive terminal according to an example embodiment, and shows Figure 5A Enlarged area in VI. Figure 5D 2 is a view for explaining a lower pad according to an example embodiment. Hereinafter, contents repeated with the above contents will be omitted.

[0109] Reference Figure 1A , Figure 5A and Figure 5B, the semiconductor module 10 may include a board 1000 and a packaging system 1. For example, a printed circuit board may be used as the board 1000. A conductive pad 1500 may be provided on an upper surface 1000a of the board 1000. The conductive pad 1500 may be electrically connected to an internal wire (not shown) of the board 1000. Electrical connection with the board 1000 in this specification may mean electrical connection with an internal wire of the board 1000.

[0110] refer to Figures 1A to 1C The described packaging system 1 may be mounted on a board 1000, thereby forming a semiconductor module 10. As another example, Figure 1F Packaging system 1a, Figure 2A and Figure 2B Packaging system 1b, Figure 2C and Figure 2D Packaging system 1c, Figure 2E Packaging system 1d, Figure 3A Packaging system 1e, Figure 3B Packaging system 1f, Figure 3C Packaging system 1g, Figure 4A Packaging system 1h, Figure 4B Package system 1i or Figure 4C The packaging system 1j is mounted on the board 1000, so that the semiconductor module 10 can be formed. For convenience, the semiconductor module 10 mounted on the board 1000 is shown and described. Figures 1A to 1C However, the present invention is not limited thereto.

[0111] The packaging of the packaging system 1 includes: arranging the packaging system 1 on the board 1000 so that the conductive terminal 550 faces the board 1000, and electrically connecting the conductive terminal 550 to the conductive pad 1500. The pitch of the conductive terminal 550 can be substantially the same as the pitch P4 of the conductive pad 1500. The pitch P4 of the conductive pad 1500 can be standardized. For example, the pitch P4 of the conductive pad 1500 can meet the Joint Electronic Device Engineering Council (JEDEC) standard. The pitch P4 of the conductive pad 1500 can be large. For example, the pitch P4 of the conductive pad 1500 can be 0.65 mm or larger.

[0112] When the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 are directly mounted on the board 1000, the pitch P1 of the first connection terminals 150, the pitch P2 of the second connection terminals 250, and the pitch P3 of the third connection terminals 350 may be required to be substantially the same as the pitch P4 of the conductive pads 1500. According to example embodiments, the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 may be connected to the board 1000 through the substrate 500. Therefore, the pitch P1 of the first connection terminals 150, the pitch P2 of the second connection terminals 250, and the pitch P3 of the third connection terminals 350 are freely designed without being restricted by the pitch P4 of the conductive pads 1500.

[0113] The pitch P1 of the first connection terminal 150 may be smaller than the pitch P4 of the conductive pad 1500. For example, the pitch P1 of the first connection terminal 150 may be 0.4 mm or less. Therefore, the first connection terminal 150 is arranged more densely so that the plane area of ​​the first semiconductor package 100 can be reduced. The pitch P2 of the second connection terminal 250 and the pitch P3 of the third connection terminal 350 may be smaller than the pitch P4 of the conductive pad 1500. For example, the pitch P2 of the second connection terminal 250 and the pitch P3 of the third connection terminal 350 may both be 0.4 mm or less. Therefore, the second semiconductor package 200 and the third semiconductor package 300 may be miniaturized. Since the first semiconductor package 100, the second semiconductor package 200 and the third semiconductor package 300 are miniaturized, the distance between the first semiconductor package 100, the second semiconductor package 200 and the third semiconductor package 300 may be reduced. Therefore, the length of the electrical signal path between the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 may be reduced. The operation speed and reliability of the packaging system 1 may be improved.

[0114] The second passive element 420 may be mounted on the lower surface 1000b of the board 1000. Figure 5BAs shown, the second connection terminal portion 402 may be further disposed between the board 1000 and the second passive element 420. The second passive element 420 may be connected to the board 1000 via the second connection terminal portion 402. The second connection terminal portion 402 may include, for example, solder, a column, a bump, or a ball grid array. The height H6 of the installed second passive element 420 may be defined as including the height H61 of the second connection terminal portion 402. For example, the height H6 of the installed second passive element 420 is equal to the sum of the height H61 of the second connection terminal portion 402 and the height H60 of the second passive element 420' before installation. For example, the height H6 of the installed second passive element 420 may be greater than the sum of the height H1 of the installed first semiconductor package 100 and the thickness A1 of the first heat conducting layer 710. Even if the height H6 of the installed second passive element 420 is large, the second passive element 420 may be electrically connected to the packaging system 1 via the substrate 500.

[0115] The second passive element 420 may be electrically connected to one of the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300. In a top view of the semiconductor module 10, the second passive element 420 may be disposed overlapping or adjacent to one of the semiconductor packages 100, 200, and 300. Therefore, the length of the electrical signal path between the second passive element 420 and one of the semiconductor packages 100, 200, and 300 may be reduced. Therefore, the electrical characteristics of the semiconductor module 10 may be improved.

[0116] A plurality of second passive elements 420 may be provided. In this case, the heights H6 of the second passive elements 420 may be equal to or different from each other. The number of second passive elements 420 may be variously modified. Figure 5C and Figure 5D The conductive terminal 550 and the lower pad 540 are depicted.

[0117] The lower pad 540 may be disposed on the lower surface of the substrate 500. The lower pad 540 may include a connection pad 541 and a test pad 542. During the manufacturing process of the packaging system 1 or before the packaging system 1 is mounted on the board 1000, the electrical characteristics of the packaging system 1 may be evaluated. The test pad 542 may be used to perform the evaluation of the electrical characteristics. For example, when a probe (not shown) contacts the test pad 542, the electrical characteristics and connection relationship of at least one of the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300, the first passive component 400, and the electronic component 430 may be evaluated. Thereafter, the conductive terminal 550 is formed, and the packaging system 1 may be mounted on the board 1000.

[0118] like Figure 5CAs shown, the conductive terminal 550 may include a first terminal 551 and a second terminal 552. The first terminal 551 is disposed on the lower surface of the connection pad 541 and may be connected to the connection pad 541 and a corresponding one of the conductive pads 1500. The first terminal 551 may electrically connect the packaging system 1 to the board 1000. The first terminal 551 may be used as a path for signal transmission.

[0119] The second terminal 552 is disposed on the lower surface of the test pad 542 and can be connected to the test pad 542. For example, the second terminal 552 can be used as a ground terminal. The ground voltage is transmitted to the packaging system 1 through the board 1000 and the second terminal 552. As another example, the second terminal 552 can be a dummy terminal. For example, the second terminal 552 may not be electrically connected to the internal wire in the board 1000. Alternatively, the second terminal 552 may not be electrically connected to the packaging system 1.

[0120] like Figure 5D As shown, the second terminal ( Figure 5C 552 in FIG. 5). The test pad 542 may be spaced apart from the board 1000 and electrically insulated. Although not shown in the figure, an underfill material may be filled in the gap between the board 1000 and the test pad 542. The underfill material may include an insulating polymer.

[0121] According to the present invention, during the operation of the packaging system, the first semiconductor package can generate a large amount of heat. The thickness of the first heat-conducting layer can be less than the thickness of the second heat-conducting layer and can be less than the thickness of the third heat-conducting layer. As the thickness of the first heat-conducting layer decreases, the thermal characteristics of the first semiconductor package can be improved. The packaging system can show improved operating characteristics.

[0122] Although some example embodiments of the inventive concept have been described, it should be understood that the inventive concept should not be limited to these embodiments and that a person skilled in the art may make various changes and modifications within the spirit and scope of the inventive concept as defined in the appended claims.

Claims

1. A semiconductor packaging system, comprising: substrate; a first semiconductor package on the substrate; a second semiconductor package on the substrate; a first passive component on the substrate; a heat dissipation structure over the first semiconductor package, the second semiconductor package, and the first passive component; as well as a first heat-conducting layer between the first semiconductor package and the heat dissipation structure, The sum of the height of the first semiconductor package and the thickness of the first heat conducting layer is greater than the height of the first passive component, and The height of the first semiconductor package is greater than the height of the second semiconductor package, Wherein, the semiconductor packaging system further includes: a ground pattern on an upper surface of the substrate; and A conductive adhesive pattern between the ground pattern and the heat dissipation structure, wherein: The heat dissipation structure comprises a main body and a leg portion, The main body portion extends parallel to the upper surface of the substrate, The legs are connected to the body portion, The leg portion is located between the base plate and the body portion, and The heat dissipation structure is electrically connected to the ground pattern through the conductive adhesive pattern, Wherein, the thickness of the first heat-conducting layer is smaller than the thickness of the conductive adhesive pattern.

2. The semiconductor packaging system according to claim 1, further comprising: A second heat-conducting layer is provided between the second semiconductor package and the heat dissipation structure, wherein: The thickness of the first heat conducting layer is smaller than the thickness of the second heat conducting layer.

3. The semiconductor packaging system according to claim 2, wherein: The first heat conducting layer and the second heat conducting layer are in physical contact with the heat dissipation structure.

4. The semiconductor packaging system according to claim 1, wherein: The first semiconductor package includes a first substrate, a first semiconductor chip and a first molding layer, and The first semiconductor chip is a system on a chip.

5. The semiconductor packaging system according to claim 4, wherein: The first semiconductor package also includes a first heat conductive structure on the first molding layer.

6. The semiconductor packaging system according to claim 5, wherein: An upper surface of the first mold layer is located at a lower level than an upper surface of the second semiconductor package.

7. The semiconductor packaging system according to claim 1, wherein: The second semiconductor package includes a second substrate, a second semiconductor chip, a second molding layer, and a second heat conducting structure on the second molding layer.

8. The semiconductor packaging system according to claim 1, further comprising: a plate on a lower surface of the substrate; conductive terminals connected to the substrate and the board; as well as a second passive component on the lower surface of the board, wherein The height of the second passive component is greater than the height of the first semiconductor package.

9. The semiconductor packaging system according to claim 8, further comprising: A first connection terminal between the substrate and the first semiconductor package, wherein A pitch of the first connecting terminals is smaller than a pitch of the conductive terminals.

10. A semiconductor packaging system, comprising: substrate; a first semiconductor package located on the upper surface of the substrate, the first semiconductor package including a first semiconductor chip including one or more logic circuits; a second semiconductor package on the upper surface of the substrate; passive components on the upper surface of the substrate; a heat dissipation structure over the first semiconductor package, the second semiconductor package, and the passive component; as well as a plurality of heat-conducting layers, each of the plurality of heat-conducting layers being in physical contact with the lower surface of the heat dissipation structure, The plurality of heat-conducting layers include a first heat-conducting layer located on an upper surface of the first semiconductor package, and among the plurality of heat-conducting layers, the first heat-conducting layer has the thinnest thickness, Wherein, the semiconductor packaging system further includes: a ground pattern on the upper surface of the substrate; and A conductive adhesive pattern between the ground pattern and the heat dissipation structure, wherein: The heat dissipation structure comprises a main body and a leg portion, The main body portion extends parallel to the upper surface of the substrate, The legs are connected to the body portion, The leg portion is located between the base plate and the body portion, and The heat dissipation structure is electrically connected to the ground pattern through the conductive adhesive pattern, Wherein, the thickness of the first heat-conducting layer is smaller than the thickness of the conductive adhesive pattern.

11. The semiconductor packaging system according to claim 10, wherein: A height of the first semiconductor package is greater than a height of the second semiconductor package.

12. The semiconductor packaging system according to claim 11, wherein: The first semiconductor package further includes a first substrate, a first molding layer and a first heat conducting structure. The first semiconductor chip is located on the first substrate. The first molding layer is configured to cover the first semiconductor chip, and The first heat conducting structure is located on the first molding layer.

13. The semiconductor packaging system according to claim 10, wherein: A sum of a height of the first semiconductor package and a thickness of the first heat conducting layer is greater than a height of the passive component.

14. The semiconductor packaging system according to claim 10, wherein: The plurality of heat conducting layers further includes a second heat conducting layer located on an upper surface of the second semiconductor package.

15. The semiconductor packaging system according to claim 14, wherein: The second semiconductor package includes a power management chip or a memory chip.

16. A semiconductor packaging system, comprising: substrate; a first semiconductor package on the substrate, the first semiconductor package comprising a first semiconductor chip, the first semiconductor chip comprising one or more logic circuits; a second semiconductor package on the substrate; passive components on the substrate; a heat dissipation structure over the first semiconductor package, the second semiconductor package, and the passive component; a first heat-conducting layer on the first semiconductor package, the first heat-conducting layer being in physical contact with the heat dissipation structure; as well as a second heat-conducting layer on the second semiconductor package, the second heat-conducting layer being in physical contact with the heat dissipation structure, The thickness of the first heat-conducting layer is smaller than the thickness of the second heat-conducting layer, and The upper surface of the first heat-conducting layer is arranged at a higher level than the upper surface of the passive element, Wherein, the semiconductor packaging system further includes: a ground pattern on an upper surface of the substrate; and A conductive adhesive pattern between the ground pattern and the heat dissipation structure, wherein: The heat dissipation structure comprises a main body and a leg portion, The main body portion extends parallel to the upper surface of the substrate, The legs are connected to the body portion, The leg portion is located between the base plate and the body portion, and The heat dissipation structure is electrically connected to the ground pattern through the conductive adhesive pattern, Wherein, the thickness of the first heat-conducting layer is smaller than the thickness of the conductive adhesive pattern.

17. The semiconductor packaging system according to claim 16, further comprising: a third semiconductor package on the substrate; as well as A third heat conducting layer on the third semiconductor package, wherein: The third heat-conducting layer is in physical contact with the heat dissipation structure, and The thickness of the first heat conducting layer is smaller than the thickness of the third heat conducting layer.

18. The semiconductor packaging system according to claim 16, wherein: The second semiconductor package further includes a second substrate, a second semiconductor chip, and a second molding layer, and The second semiconductor chip is a semiconductor chip of a different type than the first semiconductor chip.

19. The semiconductor packaging system according to claim 18, wherein: The second semiconductor package further includes a second heat conducting structure located on the second molding layer, and The second heat-conducting layer is located on the second heat-conducting structure.

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