Reset circuit, corresponding device and method

Abstract

Embodiments of the present application relate to reset circuits, corresponding devices, and methods. A circuit includes a first node configured to receive a reset signal. A reset driver stage drives the reset node. The reset driver stage is coupled to the first node via a reset signal path for propagating the reset signal to the reset driver stage. The reset driver stage is activated as a result of asserting a reset excitation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level at the reset node reaching a reset threshold. A reset signal holding circuit block is coupled to the first node and configured to receive a reset command signal and assert a reset excitation state of the reset signal at the first node as a result of receiving the reset command signal.

Description

[0001] Cross-references to applications

[0002] This application claims the benefit of Italian patent application serial number 102018000005511 filed on May 18, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0003] The instructions relate to a reset circuit. Background Art

[0004] A generally recognized problem in devices such as microcontrollers may be to make an internal reset event (always) visible on the device reset pin, by also considering that the number of GPIO (General Purpose Input Output) pins may differ between one device (such as a microcontroller unit or MCU) and another and that a reset functionality (dedicated pin) is a highly desirable feature.

[0005] A possible solution to this problem may involve implementing a hold-off function to allow the reset to propagate towards, for example, the circuit board on which the device is mounted.

[0006] The disadvantage of this solution can be recognized as the maximum allowable load capacitance for the reset pin specified in the device data sheet. Summary of the invention

[0007] One or more embodiments may help provide an improved solution that overcomes the shortcomings of this conventional approach.

[0008] One or more embodiments may be directed to a corresponding device (eg, MCU). One or more embodiments may be directed to a corresponding method. One or more embodiments may be applicable, for example, to an electronic controller such as a microcontroller.

[0009] As an example, an embodiment relates to a circuit, including a first node configured to receive a reset signal. A reset driver stage drives the reset node. The reset driver stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset driver stage. The reset driver stage is activated as a result of assertion of a reset excitation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal holding circuit block is coupled to the first node and configured to receive a reset command signal and assert the reset excitation state of the reset signal at the first node as a result of the received reset command signal, wherein the reset signal holding circuit block is coupled to the sensing node and configured to de-assert the reset excitation state of the reset signal at the first node as a result of the signal level at the reset node reaching the reset threshold.

[0010] One or more embodiments may provide one or more of the following advantages: presented reset line drive capability independent of external capacitive load, nominally no constraints on the customer system regarding the reset line (maximum) capacitance value, and package pin count optimization.

[0011] One or more embodiments may be directed to reset keeper logic that facilitates flexible configuration of pin functionality and / or specific schemes to control pads depending on user options.

[0012] One or more embodiments may facilitate a reset action to be (always) visible on an external reset line, regardless of capacitive loading on the pin (eg, related to circuit board characteristics). BRIEF DESCRIPTION OF THE DRAWINGS

[0013] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0014] Figure 1 is an exemplary block diagram of a possible usage scenario of an embodiment,

[0015] Figure 2 is an exemplary functional circuit diagram of an embodiment,

[0016] Figure 3 includes various example diagrams of the timing behavior of signals that may occur in an embodiment,

[0017] Figure 4 is a more general schematic diagram of an embodiment as applied to a (micro)controller unit, and

[0018] Figure 5 is an example of a possible circuit implementation of an embodiment.

[0019] Specific implementation

[0020] In the following description, one or more specific details are described for the purpose of providing a deeper understanding of the examples of the embodiments of the description. The embodiments may be obtained without using one or more specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations will not be described or described in detail so as not to obscure certain features of the embodiments.

[0021] Reference to "an embodiment" or "an embodiment" in the framework of this specification is intended to indicate that a particular arrangement, structure or feature described with respect to that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in an embodiment" that may be present in one or more places in this specification do not necessarily refer to one and the same embodiment. Further, particular configurations, structures or features may be combined in any suitable manner in one or more embodiments.

[0022] The references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0023] Throughout this specification, for convenience of explanation reference will be made to certain features that may be employed in devices such as the STM32 series of microcontrollers commercially available from the ST Group of Companies and to reference numerals currently employed in documents (eg datasheets) relating to the STM32 series of microcontrollers.

[0024] This is based on a design to provide MCU users with new degrees of freedom by offering products that combine high performance, real-time capabilities, digital signal processing, low power and low voltage operation, and connectivity while maintaining full integration and ease of development. 32-bit Flash microcontroller family of processors.

[0025] It should also be understood that reference to a microcontroller such as the STM32 as an example of a device to which the embodiments may be applicable has the sole purpose of facilitating a comprehensive, clear, concise and precise description of the manner in which the embodiments are implemented, and should not even be indirectly interpreted as limiting the embodiments in some sense.

[0026] The embodiments are not linked to special features of controllers such as, for example, microcontrollers of the STM32 series. More specifically, the embodiments may be applicable to contexts where a reset signal is generated (internally) and propagated via a pad toward the outside of the chip, for example, on a system board. One or more embodiments are therefore applicable to various contexts and are not limited to use in microcontrollers.

[0027] The embodiments are therefore applicable to all devices encompassed by the language of the claims.

[0028] Figure 1 1 is an exemplary block diagram of a possible use scenario of an embodiment in an architecture for sharing a reset function between a device MCU (e.g., a microcontroller) and a system S (e.g., a circuit board). It is re-emphasized in this feature aspect that the microcontroller is only a possible example of a device to which the embodiment can be applied, and therefore the embodiment should not be interpreted even indirectly as being limited to a controller such as a microcontroller.

[0029] In the device (microcontroller as an example) the reset function should hopefully be controllable both "externally" (ie circuit board S to microcontroller MCU) and "internally" (ie microcontroller MCU to circuit board S).

[0030] Various factors may be addressed by having a package with a reduced pin count (cost reasons as an example of these), so the package pin NRST supporting the reset function may be shared with other functions.

[0031] like Figure 1As shown in , a GPIO (General Purpose Input Output) function may be an example of such a function that is shared with a reset function.

[0032] This arrangement can be managed by the device implementation within the device MCU, where the same pin is bonded to two pads: one dedicated to the reset function ( Figure 1 NRST block), and one dedicated to another function (see Figure 1 GPIO block).

[0033] This facilitates the same output pin ( Figure 1 The NRST / GPIO) shown on the left hand side is coupled to other circuits besides the NRST logic 10 such as another logic OL.

[0034] In such Figure 1 In the device illustrated in , reset input / output sharing can provide desirable features such as: an internally generated reset (internal_rst) can propagate toward the NRST / GPIO pin and thus be externally visible (e.g., on circuit board S); the device (e.g., a microcontroller MCU) can be reset as a result of a reset request generated internally by the device and as a result of an externally generated (i.e., on a circuit board) reset request received at the NRST / GPIO pin; or power consumption on the reset pad is reduced due to the pull-up drive being disabled as a result of a reset prompted by the device MCU, so that useless DC current does not flow through the pad.

[0035] Figure 2 A more detailed representation of the reset pad structure 10 is provided, which facilitates understanding the operation of conventional reset pad schemes as well as the operation of the embodiments. In this regard, it is again recalled that for simplicity reference is made here to certain features and the reference numerals employed in microcontrollers such as the STM32 series microcontrollers should not even indirectly interpret the embodiments in a limiting manner.

[0036] In such Figure 2 In the arrangement illustrated in , an internal reset request internal_rst comprising a reset pulse (of variable width) as generated internally by the device MCU (in a manner known to those skilled in the art) may propagate towards the AV33M input pin of the reset pad 10 .

[0037] The signal received at the AV33M input pin may be filtered (conditioned) by logic 100 to remove potential glitch interference by a delay block, critical for reset implementation, and "stretched" by a fixed amount of time at its second stage (rising or falling depending on the signal pulse polarity).

[0038] The resulting stretched pulse may be used (possibly after flipping at 102) to drive an output stage 104 (eg, an NMOS transistor) that resets I / O pad 10. This may include generating a pulse capable of driving pin IOFT of pad 10.

[0039] As exemplified here, pin IOFT (actually an input / output pin as described below) may have been Figure 2 The dashed line on the right is shown coupled with a capacitive load C.

[0040] So far Figure 2 The components in the circuit board can be considered as implementing an open loop device, and are not provided on the circuit board according to a reset pulse generated inside the device MCU, for example. Figure 1 S) on any control that effectively drives the reset line.

[0041] In this sense, the reset signal received by the reset pad at the AV33M input pin, filtered at 100 and time stretched can be sent back towards the device MCU (feedback_rst) by sending it towards the output pin ZIV33M of the reset pad 10 (eg through an AND gate 106).

[0042] Furthermore, an external reset request may be received by the reset pad 10 at the (input / output) pin IOFT and passed to the Schmitt trigger block 108 and filter 110 for filtering and buffering to be sent back to the device MCU.

[0043] This can be done via AND logic gate 106 (which can also sense the reset request on internal paths 100, 102, 104) and output pin ZIV33M of reset pad 10 (see again Figure 2 feedback_rst).

[0044] In such Figure 2 In the arrangement illustrated in , as a result of the filtering and delay logic 100 asserting reset to drive the output stage 104 of the reset I / O pad 10, a corresponding signal can be sent to the pull-up logic control block (PUC) 112, which disables the connection to the power supply VDD (e.g., electronic switch VDDIOM) and avoids useless power consumption.

[0045] It can be seen that the operations described thus far may suffer from inherent limitations, primarily with respect to propagating the internally generated reset (internal_rst) towards NRST / GPIO to cause it to be externally visible.

[0046] In practice, the reset pulse generated by the stall logic 100 may not be long enough (in terms of duration) to cause the internally generated reset to be visible externally to, for example, a device MCU on the circuit board S.

[0047] Due to the fixed time for stretching the reset pulse (which can be done, for example, Figure 2 20 microseconds), the reset line on the circuit board side may not actually be at the desired reset value due to the presence of the capacitive load C seen at the IOFT pin of the reset I / O pad 10.

[0048] It should be noted that even though the stall logic in block 100 may still keep the driver stage 104 (e.g. NMOS) activated for, e.g., 20 microseconds after the falling edge of the internal_rst signal (as input downstream of the glitch filtering), this may be sufficient for the signal at IOFT to reach the desired (e.g. low) value since the (large) capacitor C coupled to pin IOFT will be discharged.

[0049] As a result, at the application level, the system implemented on the circuit board S and comprising the microcontroller MCU may not receive correct information from the device MCU about the reset condition generated in the device MCU.

[0050] This may, for example, result in the loss of certain intended system actions and / or the implementation of erroneous actions due to unstable or erroneous values ​​on the reset line.

[0051] An attempt may be made to mitigate this risk by indicating in the device datasheet the maximum tolerable load capacitance C on the IOFT pin, which facilitates correct propagation of internally generated reset requests. This may result in constraints / limitations imposed on the on-board system comprising the device.

[0052] like Figure 2 One or more of the embodiments illustrated in (primarily the left-hand side thereof) aim to overcome this limitation by implementing closed-loop control over reset generation. This results in eliminating the dependency on load capacitance C and removes the constraints affecting customer implementations (as reported on the datasheet).

[0053] like Figure 2 One or more of the embodiment designs illustrated in provide a dedicated digital control logic 200 (NRST logic) intended for use as a reset keeper.

[0054] like Figure 2 As shown in the example, the NRST logic 200 can be set "in front of" the reset input / output pad 10, capable of maintaining the reset pulse internal_rst from the internal reset source long enough to allow the reset line (e.g., IOFT) to reach the desired (e.g., lower) threshold, and (only) releasing the reset pulse as a result of the notification that a reset has occurred on the reset line as desired.

[0055] This may occur, for example, via the signal IOFT_filt, provided on a dedicated output 120 of the reset pad 10 .

[0056] Figure 2 The left hand side of is shown a (first) possible implementation example of the NRST logic 200 .

[0057] In the example shown, the NRST logic 200 includes an internal reset holder block IRH including a first input configured to receive an internal reset signal (pulse) internal_rst, and an output providing a reset pulse hold_rst to be applied to the AV33M pin.

[0058] Depend on Figure 3 The two upper curves in the figure illustrate possible timing behaviors of the signals internal_rst and hold_rst.

[0059] exist Figure 2 In the example of , the second input of the OR gate 202 is coupled to the output from a bistable element (e.g., a set-reset latch) 204, which has a set input coupled to pin 122 to receive therefrom a signal int_rst from the signal propagation path from the AV33M pin to the driver stage 104, e.g., between logic 100 and inverter 102, which may be the same signal applied to one of the inputs of the (AND) gate 106. The reset input is coupled to pin 120 to thereby receive a signal IOFT_filt originating from a Schmitt trigger 108 coupled to the input / output pin IOFT and indicating that the signal at the pin IOFT has reached the desired (lower) threshold.

[0060] Depend on Figure 3 The two lower curves in the figure illustrate possible timing behaviors of the signal at the input / output pin IOFT and the signal IOFT_filt.

[0061] In such Figure 2 and Figure 3 In the arrangement illustrated in FIG, an internal reset request internal_rst (which, as previously described, may be generated by different reset sources, possibly with different pulse widths) is handled by logic 200 which combines it with the output of a storage element (set-reset latch 204) via an OR logic gate 202.

[0062] In this manner, the output signal from OR gate 202 , namely hold_rst, provides a “new” AV33M input to reset input / output pad 10 .

[0063] like Figure 3As shown in the figure, the rising edge of internal_rst (point 1 in the figure) propagates as hold_rst to pin AV33M of pad 10 and is able to reach logic 100, and then propagates to the output stage 104, possibly after flipping at 102, so as to start driving the output reset line IOFT and return to the device MCU (int_rst) through output pin 122.

[0064] This latter signal is used in logic 200 to drive the set input of latch 204 and thus cause hold_rst to remain asserted ( Figure 3 midpoint 2), even though the internal_rst pulse is no longer asserted, for example by being driven low by a reset source of the device.

[0065] At the same time, the pad's output stage 104 has begun driving the output IOFT so as to force the desired (low) value with the instantaneous timing presented by the load capacitance C coupled to the IOFT.

[0066] The hold_rst signal remains high and drives the NMOS output stage until the reset line reaches the input buffer (lower) threshold as set in the Schmitt trigger buffer 108 .

[0067] As a reset line (IOFT signal) with a lower threshold (such as Figure 3 As a result of the crossing of φ(R) and φ(D) (indicated by midpoint 3), input buffer 108 switches its output from high to low.

[0068] This signal (possibly filtered to remove glitches on the input) may be sent towards the device as IOFT_filt through a dedicated output pin 120 of the reset input / output pad 10 .

[0069] The signal IOFT_filt may be used by the reset keeper logic 200 as a notification that an appropriate reset is propagated to the IOFT pin, ie, from the device MCU to the circuit board S. As shown in FIG.

[0070] As illustrated herein, the signal IOFT_filt may be used to drive the reset input of the latch 204 such that the hold_rst signal is de-asserted on the falling edge of hold_rst (as indicated by Figure 3 midpoint 4).

[0071] As a result, the stall logic 100 in the pad 10 can start counting the fixed time interval (see Figure 3 The output stage 104 is turned off after a TEMPO of, for example, 20 microseconds, which value is exemplary only and not limiting of the embodiments, so that additional time can be allowed to complete the output reset drive (eg, from the input buffer lower threshold voltage level toward ground).

[0072] From a nominal point of view, one or more embodiments may therefore facilitate the elimination of the stall logic 100. However, retaining the stall may be helpful, within the limits that promote the minimum duration of the reset line. For example, with a small capacitor C and a fast reset activation at IOFT, stalling at 100 will facilitate avoiding the risk of a reset pulse being too fast to adequately reset the system.

[0073] In one or more embodiments as illustrated herein, at the end of the fixed time imposed (calculated) by stall block 100, reset pad output stage 104 will turn off, thereby removing drive on node IOFT (eg, to "0").

[0074] In addition, the logic 112 in the reset pad 10 can be driven to the node IOFT ( Figure 3 The pull-up connection at midpoint 5) drives (eg, "1") to return the reset line to an inactive state (the reset line is "active low" in the illustrated embodiment).

[0075] Furthermore, in one or more embodiments illustrated herein, the rising edge on the IOFT node will propagate through the Schmitt trigger block 108 and invalidate the IOFT_filt signal (return to, for example, "1"), thereby restoring the initial adjustment of the reset holder 200 (latch 204) in preparation for the next reset generation.

[0076] One or more embodiments as exemplified herein facilitate overcoming the need for load capacitance ( Figure 2 C) while reducing—and nominally avoiding—the risk that the reset request may not propagate toward the external circuit board S.

[0077] In one or more embodiments as illustrated herein, a closed loop control arrangement facilitates “tuning” the pulse duration of NMOS stage 104 driving the reset input / output pad according to the capacitive load C seen at the pad output (node ​​IOFT).

[0078] Figure 4 and Figure 5 is an example of a possible implementation of a microcontroller in which a "load independent" reset input / output pad 10 according to one embodiment is shown combined with a general purpose input / output GPIO function on the same pad within the MCU, which is inherently different from the embodiment; this is only partially shown for simplicity.

[0079] exist Figure 4 and Figure 5 The same reference numerals are used to designate the same parts or elements as those already discussed in connection with the previous figures, thereby making it unnecessary to repeat the detailed description thereof.

[0080] As described, the general purpose input / output GPIO functionality is essentially different from the embodiment. For this reason, when visible in the drawings, no explicit reference is made to those parts of the pads 10 dedicated to interfacing with the GPIO logic GPIO-L.

[0081] By again using the terminology of a microcontroller (e.g. STM32) purely by way of example and not limiting the scope of the embodiments, Figure 4 It involves the V12 / V33 part, including the V12 logic with a reset sampling block RS that interfaces with V33, and V33 is an optional bit sampling logic SL that cooperates with the reset I / O control logic CL.

[0082] This in turn includes reset logic circuit RLS (which may include NRST logic 200 as previously described) and GPIO logic circuit GPIO-L.

[0083] For direct reference only, use Figure 2 The same mark indicates Figure 4 The pins of the reset input / output pad 10 designed to cooperate with the reset logic circuit RLS, in addition to the possible insertion of the intermediate mark RESET for AV33M and ZIV33M, that is:

[0084] AV33M→ARESETV33M

[0085] ZIV33M→ZIRESETV33M

[0086] And for the newly assigned pins 120 and 122, that is:

[0087] pin 120→ZIEXTRESETV33M

[0088] pin 122→ZIINTRESETV33M

[0089] from Figure 4 It should be appreciated that one or more embodiments are not limited to pad sharing features and may be governed by conventional device configuration options.

[0090] Figure 5 yes Figure 2 FIG. 2 is an example of another possible implementation of the reset keeper logic circuit 200 .

[0091] exist Figure 5 In the drawings, like symbols are used to indicate parts or elements similar to those already discussed in connection with previous figures in order to facilitate direct reference thereto.

[0092] Figure 5The implementation of comprises a D flip-flop as a bistable component 204, having its Q node coupled to one input of an OR gate 202, the OR gate receiving a reset signal internal_rst on the other input (core_rst_cmd).

[0093] In such Figure 5 In the implementation illustrated in , flip-flop 204 receives a combination of two configuration signals on its data input D (eg, via AND gate 206 ), which may identify a possible operating mode of reset logic 200 .

[0094] For example, irh_en_opt may be a configuration signal for statically or dynamically enabling / disabling the reset keeper logic 200. In addition, rst_inout_mode may be another configuration signal indicating whether the reset pad is configured for reset from MCU to system and system to MCU (as described above) to selectively enable the reset keeper logic 200.

[0095] These signals can be generated in a manner known to those skilled in the art. In addition, those skilled in the art should be aware that similar gating arrangements (e.g., AND gates sensitive to signals such as irh_en_opt and rst_inout_mode) can also be designed for use in Figure 3 The example shown in selectively enables a latch-based arrangement.

[0096] Figure 5 The pin marked as pad_int_rstn corresponds to Figure 2 Pin 122 (i.e. Figure 4 ZIINTRESETV33M) and therefore corresponds to Figure 2 The latch based embodiment receives the set input of signal int_rst 204 .

[0097] Its falling edge samples the value on the D input (as the clock input to flip-flop 204) and allows the reset command ( Figure 2 hold_rst), for example, if irh_en_opt and rst_inout_mode are both "1": This is Figure 3 The timing diagram of the hold begins the reset phase.

[0098] In such Figure 5 In the implementation shown in the example, pad_rst_cmd(hold_rst) is removed along with the input pad_ext_rstn, which corresponds to Figure 2 Pin 120 (i.e. Figure 4 ZIEXTRESETV33M) and therefore corresponds to Figure 2In the latch based embodiment, the reset input to 204 receives the signal IOFT_filt having a falling edge, due to the reset that ships to the IOFT node.

[0099] This is made visible to the system (e.g., board S) and propagates back to the device via the Schmitt trigger buffer 108, since the flip-flop 204 is asynchronously cleared via its clear input CL: this corresponds to the end of the hold reset phase and as Figure 3 The timing diagram describes the start of the delay performed internally by the reset pad.

[0100] In such Figure 5 In the implementation illustrated in the example, the signal IOFT_filt on input pad_ext_rstn is provided to the clear input CL of the flip-flop 204 by applying it to the input of an AND gate 208 which receives on the other input a signal pwr_on_rstn for providing a defined value to the flip-flop D of the reset keeper at MCU startup when reset.

[0101] and Figure 2 Compare, Figure 5 The implementation shown in the example facilitates the use of commercially available standard cell technology and provides enable / disable configuration via irh_en_opt (and rst_inout_mode). Figure 5 The implementation shown in can produce a more robust solution, which can also promote control from a testing point of view.

[0102] Figure 5 The implementation is an example of configurability (enable / disable) and can be used in different scenarios without introducing limitations, for example by acting via configuration options (static or dynamic), having a dedicated reset pad or a reset pad shared with a GPIO feature and / or a reset pad that provides reset only in the MCU to system direction or in both directions.

[0103] In one or more embodiments, the circuit (eg, 10) may include a first node (eg, Figure 2 AV33M or Figure 4 ARESETV33M). The reset driver stage (e.g., 104) drives the reset node (e.g., IOFT). The reset driver stage is coupled to the first node via the reset signal path (e.g., 100, 102) to propagate the reset signal to the reset driver stage. Assertion of the reset stimulus state of the reset signal (e.g., to "1" see Figure 3 ) results in the reset driver stage being activated (eg, “active low”). The sensing node (eg Figure 2 and Figure 4 Middle 120; Figure 4ZIEXTRESETV33M; Figure 5 , pad_ext_rstn) is coupled to the reset node via a signal sensing path (e.g., 108, 110). The sensing node is sensitive to the signal level (e.g., IOFT_filt) of the reset node reaching a reset threshold (e.g., set in 108). The reset signal holding circuit block (e.g., 200) is coupled to the first node and is configured to receive (e.g., at 202) a reset command signal (e.g., internal_rst) and assert the reset excitation state of the reset signal at the first node as a result of receiving the reset command signal. The reset signal holding circuit block (200) is coupled to the sensing node and is configured to de-assert the reset excitation state of the reset signal at the first node (e.g., to "0", see Figure 3 ).

[0104] One or more embodiments may include a delay circuit block (e.g., 100) in the first signal path, the delay circuit block configured to maintain activation of the reset driver stage for a time interval after de-asserting the reset activation state of the reset signal at the first node (see Figure 3 TEMPO).

[0105] One or more embodiments may include a pull-up circuit block (eg, 112 ) coupled to the stall circuit block and the reset node, the pull-up circuit block configured to force the reset node to an inactive state (eg, VDDIOM) as a result of expiration of the time interval.

[0106] One or more embodiments may include a threshold circuit device (e.g., Schmitt trigger 108) providing a reset threshold (108) in a signal sensing path, wherein a sensing node coupled to the reset node via the signal sensing path is at a first / second signal level (e.g., IOFT_filt, “1” and “0”) as a result of a signal level at a reset node of a reset driver stage not having reached / having reached the reset threshold.

[0107] One or more embodiments may include an OR-type logic circuit device (e.g., 202) having an output coupled to a first node for providing a reset signal to the first node, a first input configured to receive a reset command signal, and a second input coupled to a sense node. With the sense node at a first level, the output of the OR-type logic circuit device maintains the reset signal provided to the first node in an asserted state (e.g., "1") regardless of the value of the reset command signal.

[0108] One or more embodiments may include another sensing node (eg, Figure 2 and Figure 4 122 in China; Figure 4ZIINTRESTV33M; Figure 5 pad_int_rstn) and wherein the reset signal holding circuit block includes a bistable circuit block (eg, 204, such as Figure 2 The latch shown in or Figure 5 ), having an output coupled to a second input of an OR-type logic circuit device, and coupled to a sensing node (e.g. Figure 2 120 / ZIEXTRESETV33M coupled to rst or Figure 5 The state switching input (e.g. pad_ext_rstn) coupled to CL Figure 2 The set / reset input of the latch in the Figure 5 CL inputs to the flip-flop), and another sensing node (e.g. Figure 2 122 / ZIINTRESETV33M, or Figure 5 pad_int_rstn of the clock coupled to the flip-flop).

[0109] In one or more embodiments, the bistable circuit block may include an enable / disable input (eg, 206 ; irh_en_opt; rst_intout_mode) to selectively enable / disable the reset signal holding circuit block.

[0110] In one or more embodiments, the bistable circuit block may include a latch circuit block having an output coupled to a second input of an OR-type logic circuit device, and a set / reset input coupled to another sense node (e.g., 122 coupled to a set input) and a sense node (e.g., 120 coupled to a reset input).

[0111] In one or more embodiments, the bistable circuit block may include a flip-flop having an output (e.g., Q) coupled to a second input of an OR-type logic circuit device, and clock and clear inputs coupled to another sense node (e.g., pad_int_rstn coupled to a clock input) and a sense node (e.g., pad_ext_rstn coupled to CL).

[0112] In one or more embodiments, a device (such as, for example, a microcontroller MCU) may include a reset circuit according to one or more embodiments.

[0113] In one or more embodiments, the device can be configured to generate an internal reset command signal (e.g., internal_rst) generated internally within the device, and the internal reset command signal is applied to a reset signal holding circuit block in the reset circuit to assert the reset excitation state of the reset signal at the first node as a result of receiving the internal reset command signal.

[0114] One or more embodiments may include a reset pin (eg, Figure 1 NRST / GPIO), where the reset pin of the device is sensitive to an internal reset command signal generated inside the device.

[0115] One or more embodiments may include a reset pin (NRST / GPIO) coupled to a reset node in a reset circuit, wherein the reset pin may be configured to receive an external reset command signal generated external to the device, wherein the reset circuit includes a logic combination circuit device (e.g., 106) coupled to a first signal path (e.g., 100, 102) and a signal sensing path (e.g., 108, 110) and configured (see e.g., Figure 2 In the ZIV33M, a signal indicating an internal reset command signal generated inside the device and an external reset command signal generated outside the device (eg, Figure 1 and Figure 2 (feedback_rst).

[0116] A method of operating a circuit according to one or more embodiments may include applying a reset command signal (e.g., internal_rst) to a reset signal holding circuit block (e.g., 200) and sensing a signal level (e.g., IOFT_filt) reaching a reset threshold at a reset node. The signal level reaching the reset threshold at the reset node indicates a reset command signal applied to the reset signal holding circuit block that has been driven at the reset node of the reset driver stage (104).

[0117] Without prejudice to the following principles, details and embodiments may be varied, even substantially, with respect to what has been described merely by way of example, without departing from the scope of protection.

[0118] The scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: A first node configured to receive a reset signal; a reset driver stage configured to drive a reset node, the reset driver stage being coupled to the first node via a reset signal path to propagate the reset signal to the reset driver stage, wherein the reset driver stage is activated as a result of assertion of a reset activation state of the reset signal; a sensing node coupled to the reset node via a signal sensing path, the sensing node being sensitive to a signal level of the reset node reaching a reset threshold; as well as A reset signal holding circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset excitation state of the reset signal at the first node as a result of receiving the reset command signal, wherein the reset signal holding circuit block is coupled to the sensing node and is configured to de-assert the reset excitation state of the reset signal at the first node as a result of the signal level at the reset node reaching the reset threshold.

2. The circuit of claim 1 , comprising a stall circuit block in the reset signal path, the stall circuit block being configured to maintain activation of the reset driver stage for a time interval after de-assertion of the reset activation state of the reset signal at the first node.

3. The circuit of claim 2, further comprising a pull-up circuit block coupled to the stall circuit block and the reset node, the pull-up circuit block configured to force the reset node to an inactive state as a result of expiration of the time interval.

4. The circuit of claim 1 , comprising a threshold circuit arrangement in the signal sensing path, the threshold circuit being configured to provide the reset threshold, wherein the sensing node coupled to the reset node via the signal sensing path is at a first signal level as a result of the signal level at the reset node of the reset driver stage not having reached the reset threshold, or is at a second signal level as a result of the signal level at the reset node of the reset driver stage having reached the reset threshold.

5. The circuit according to claim 4, further comprising an OR-type logic circuit device having: an output coupled to the first node to provide the reset signal to the first node; a first input configured to receive the reset command signal; as well as A second input is coupled to the sensing node.

6. The circuit of claim 5 , wherein the output of the OR-type logic circuit device is configured to maintain the reset signal provided to the first node in the asserted reset excitation state when the sense node is at the first signal level regardless of the value of the reset command signal.

7. The circuit according to claim 5 further includes another sensing node coupled to the reset signal path, and wherein the reset signal holding circuit block includes a bistable circuit block, the bistable circuit block having an output coupled to the second input of the OR-type logic circuit device, and a state switching input coupled to the sensing node and the another sensing node.

8. The circuit of claim 7, wherein the bistable circuit block includes an enable / disable input to selectively enable / disable the reset signal holding circuit block.

9. The circuit of claim 7 , wherein the bistable circuit block comprises a latch circuit block having an output coupled to the second input of the OR-type logic circuit device and a set / reset input coupled to the other sensing node and the sensing node.

10. The circuit of claim 7, wherein the bistable circuit block comprises a flip-flop having an output coupled to the second input of the OR-type logic circuit device, and clock and clear inputs coupled to the another sense node and the sense node.

11. A method of operating the circuit according to claim 1, the method comprising: applying the reset command signal to the reset signal holding circuit block; as well as The signal level at the reset node reaching the reset threshold is sensed, wherein the signal level at the reset node reaching the reset threshold indicates that the reset command signal applied to the reset signal holding circuit block has been activated at the reset node of the reset driver stage.

12. A microcontroller unit formed in an integrated circuit chip, the microcontroller unit comprising: a common input / output pin that can be coupled to a node outside the integrated circuit chip; a first internal pad coupled to the common input / output pin, the first internal pad being coupled to a circuit within the integrated circuit chip; a second internal pad coupled to the common input / output pin, the second internal pad being coupled to a first node, the first node being configured to receive a reset signal; a reset driver stage configured to drive a reset node, the reset driver stage being coupled to the first node via a reset signal path to propagate the reset signal to the reset driver stage, wherein the reset driver stage is activated as a result of assertion of a reset activation state of the reset signal; a sensing node coupled to the reset node via a signal sensing path, the sensing node being sensitive to a signal level of the reset node reaching a reset threshold; as well as A reset signal holding circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset excitation state of the reset signal at the first node as a result of receiving the reset command signal, wherein the reset signal holding circuit block is coupled to the sensing node and is configured to de-assert the reset excitation state of the reset signal at the first node as a result of the signal level at the reset node reaching the reset threshold.

13. A microcontroller unit according to claim 12, wherein the microcontroller unit is configured to generate an internal reset command signal generated inside the microcontroller unit, and the internal reset command signal will be applied to the reset signal holding circuit block to assert the reset excitation state of the reset signal at the first node as a result of receiving the internal reset command signal.

14. The microcontroller unit of claim 12, wherein the common input / output pin is sensitive to an internal reset command signal generated inside the microcontroller unit.

15. A microcontroller unit according to claim 14, wherein the common input / output pin is configured to receive an external reset command signal generated outside the microcontroller unit, wherein the microcontroller unit includes a logic combination circuit device, which is coupled to the reset signal path and the signal sensing path and is configured to propagate signals indicative of the internal reset command signal and the external reset command signal.

16. A microcontroller unit according to claim 12, comprising a threshold circuit device in the signal sensing path, the threshold circuit being configured to provide the reset threshold, wherein the sensing node coupled to the reset node via the signal sensing path is at a first signal level as a result that the signal level at the reset node of the reset driver stage has not yet reached the reset threshold, or is at a second signal level as a result that the signal level at the reset node of the reset driver stage has reached the reset threshold.

17. The microcontroller unit according to claim 16, further comprising an OR-type logic circuit device having: an output coupled to the first node to provide the reset signal to the first node; a first input configured to receive the reset command signal; as well as a second input coupled to the sensing node; Wherein the output of the OR-type logic circuit device is configured to maintain the reset signal provided to the first node in the asserted reset energized state when the sense node is at the first signal level regardless of the value of the reset command signal.

18. The microcontroller unit according to claim 17 further comprises another sensing node coupled to the reset signal path, and wherein the reset signal holding circuit block comprises a bistable circuit block having an output coupled to the second input of the OR-type logic circuit device and a state switching input coupled to the sensing node and the another sensing node.

19. A method of operating an integrated circuit chip, the method comprising: receiving an internal reset signal from a circuit device within the integrated circuit chip; As a result of the internal reset signal being received, asserting a reset activation state of a reset signal at an internal reset node of the integrated circuit chip; sensing a signal level at an external reset node of the integrated circuit chip, the external reset node being configured to receive an external reset signal from outside the integrated circuit chip; as well as As a result of the signal level at the external reset node reaching a reset threshold, the reset energized state of the reset signal at the internal reset node is de-asserted.

20. The method of claim 19, wherein the de-assertion is performed upon lapse of a time interval after the signal level at the external reset node reaches the reset threshold.

21. The method of claim 19, wherein sensing the signal level comprises: A first signal level is sensed when the signal level at the external reset node has not reached a reset threshold, and a second signal level is sensed when the signal level at the external reset node has reached the reset threshold.

22. The method according to claim 21, comprising: The external reset node remains in the reset activation state when at the first signal level regardless of the value of the internal reset signal.

Images