A ΔΣ modulator based on time-division multiplexing ASAR ADC

Abstract

The present invention relates to a ΔΣ modulator based on time-division multiplexing ASAR ADC, comprising a ΔΣ modulator circuit module, an ASAR1 functional module, and an ASAR2 functional module; the ASAR1 and ASAR2 functional modules are implemented by an ASAR ADC circuit module through time-division multiplexing, which can reduce power consumption. The ASAR1 functional module is arranged at the input end of the ΔΣ modulator circuit module; the ASAR2 functional module realizes the quantization function and is arranged in the loop of the ΔΣ modulator; the input signal is processed by the ASAR ADC, and the quantization noise is used as the input signal of the ΔΣ modulator, which can reduce the output swing of the integrator and improve the stability of the ΔΣ modulator; the ΔΣ modulator adopts a feedforward structure, which can also reduce the output swing of the integrator; the reduction of the integrator swing can effectively reduce power consumption.

Description

Technical Field

[0001] The invention belongs to the technical field of analog-to-digital conversion signal processing, and in particular relates to a ΔΣ modulator based on time-division multiplexing ASAR ADC. Background Art

[0002] Analog-to-digital converters for medium and low frequency bandwidth signals are key modules in audio and measurement applications. With the reduction of CMOS process nodes, especially the development of wearable and portable devices, higher requirements are placed on the power consumption of integrated chips. Lower power consumption means longer standby time for battery-powered devices. The present invention is mainly aimed at low-power, high-precision analog-to-digital conversion applications, and realizes low-power, high-precision analog-to-digital conversion through system architecture design and circuit design.

[0003] ΔΣ modulators are very suitable for processing medium and low frequency signals, and can achieve very high accuracy (high SNR). ΔΣ modulators are mainly divided into continuous and discrete types. The discrete type does not have high requirements for process matching and circuits, and is very suitable for processing signals with medium and low frequency bandwidths. However, the problem faced by discrete ΔΣ modulators is that since the integrator in the ΔΣ modulator loop needs to achieve the required settling accuracy within the specified integration period, the power consumption is relatively large, especially when the output swing of the integrator is large and the equivalent load capacitance is large, the integrator needs to output a larger current to complete the settling.

[0004] Therefore, in the present invention, the power consumption is reduced by reducing the output swing of the integrator. Summary of the invention

[0005] The present invention provides a ΔΣ modulator based on time-division multiplexing ASAR ADC, wherein the system architecture comprises a ΔΣ modulator module, an ASAR1 functional module, and an ASAR2 functional module; the ASAR1 functional module is arranged at the input end of the ΔΣ modulator module; the ASAR2 functional module is arranged in the loop of the ΔΣ modulator module to realize the function of multi-bit quantization.

[0006] The input end of the ASAR1 functional module is electrically connected to the signal input end Vi of the ΔΣ modulator module, and the output end of the ASAR1 functional module outputs a digital signal D1.

[0007] The input end of the ASAR2 functional module is electrically connected to the signal output end Vo of the ΔΣ modulator module, and the output end of the ASAR2 functional module outputs a digital signal D2.

[0008] The output end of the ASAR1 functional module also outputs quantization noise E1.

[0009] The output end of the ASAR2 functional module also outputs quantization noise E2.

[0010] The ASAR1 functional module and the ASAR2 functional module are implemented by the same ASAR circuit module through time-division multiplexing.

[0011] The ASAR ADC circuit is an asynchronous successive approximation analog-to-digital conversion circuit.

[0012] Beneficial effects of the present invention: In the ΔΣ modulator based on time-division multiplexing ASAR ADC provided by the present invention, in terms of system architecture design, the input signal is processed by ASAR ADC, and the quantization noise is used as the input signal of the ΔΣ modulator, which can reduce the output swing of the integrator; the ASAR ADC is used in the ΔΣ modulator loop for multi-bit quantization, which can also reduce the output swing of the integrator; at the same time, the architecture of the ΔΣ modulator is a feedforward structure, and there is only a quantization noise component in the loop, and there is no ΔΣ modulator input signal component, so the output swing of the integrator is very low. In terms of circuit implementation, the functions of ASAR1 and ASAR2 are completed by time-division multiplexing of an ASARADC, saving power consumption and area.

[0013] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a system diagram of the ΔΣ modulator based on time-division multiplexing ASAR ADC.

[0015] Figure 2 It is a circuit diagram of a ΔΣ modulator based on time-division multiplexing ASAR ADC.

[0016] Figure 3 It is the timing diagram of the ΔΣ modulator based on time-division multiplexing ASAR ADC.

[0017] Figure 4 The schematic diagram of the ASAR ADC circuit is based on the ΔΣ modulator of the time-division multiplexing ASAR ADC.

[0018] Figure 5 It is a schematic diagram of the integrator circuit of the ΔΣ modulator based on the time-division multiplexing ASAR ADC. DETAILED DESCRIPTION

[0019] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined purpose, the specific implementation methods, structural features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and embodiments.

[0020] Example 1

[0021] This embodiment provides a Figure 1 , Figure 2The ΔΣ modulator based on time-division multiplexing ASAR ADC shown includes a ΔΣ modulator module, an ASAR1 functional module, and an ASAR2 functional module; the ASAR1 functional module is arranged at the input end of the ΔΣ modulator module; the ASAR2 functional module is arranged in the loop of the ΔΣ modulator; the ΔΣ modulator module is combined with the ASAR1 functional module and the ASAR2 functional module to reduce the output swing of the integrator, thereby reducing the requirements for the establishment of the integrator signal, thereby reducing power consumption; based on time-division multiplexing, the functions of ASAR1 and ASAR2 are realized by one ASAR ADC circuit module, and the power consumption of the ASAR ADC circuit is low, and the working speed of the ASAR circuit is relatively fast under deep submicron technology. Using the ASAR ADC circuit as the quantizer of the ΔΣ modulator can realize the function of multi-bit quantization at low power consumption; the ASAR1 functional module and the ASAR2 functional module are multi-bit quantizers, which are realized by the same ASAR ADC circuit module. In this embodiment, the ASAR ADC circuit module is a 3-bit asynchronous successive approximation ADC.

[0022] The input end of the ASAR1 functional module is electrically connected to the input end Vi of the ΔΣ modulator module, and the output end of the ASAR2 functional module outputs a digital signal D1.

[0023] The input end of the ASAR2 functional module is electrically connected to the signal output end Vo of the ΔΣ modulator module, and the output end of the ASAR2 circuit module outputs a digital signal D2.

[0024] The output end of the ASAR1 functional module also outputs quantization noise E1.

[0025] The output end of the ASAR2 functional module also outputs quantization noise E2.

[0026] like Figure 3 As shown in the timing diagram, the ASAR1 functional module works in the ph2 phase, and the ASAR2 functional module works in the ph1 phase. Since the ASAR1 functional module and the ASAR2 functional module can work in different clock phases, the ASAR1 functional module and the ASAR2 functional module can be multiplexed through time division, and the same ASAR ADC circuit can be used to implement the ASAR1 functional module and the ASAR2 functional module, thereby saving power consumption and circuit area. This is also one of the main contents of this patent.

[0027] like Figure 4 The figure shows the ASAR ADC circuit structure, which realizes the time-sharing multiplexing of the ASAR1 functional module and the ASAR2 functional module. The specific description is as follows:

[0028] like Figure 5The circuit structure of the first integrator of the ΔΣ modulator module is shown in the figure. Cs1 is the feedback capacitor in DAC1, Cs2 is the feedback capacitor in DAC2, and Ci is the integration capacitor. In the ph1 phase (also called the sampling phase), that is, the φ1 phase, the input signal is sampled to Cs1, and Cs2 performs a charge zeroing operation; in the ph2 phase (also called the integration phase), that is, the φ2 phase, the V1 and V2 signals are fed back to the input of the OTA through Cs1 and Cs2, thus completing a cycle of operation.

[0029] The specific contents of ASAR1 and ASAR2 in the overall system are as follows: ASAR1 samples the input signal Vi, extracts the quantization noise E1 and generates a 3-bit digital signal D1 after conversion. The quantization noise E1 is injected into the ΔΣ modulator loop through the feedforward branch, and the digital signal D1 is fed through DAC1 (a feedback circuit composed of switched capacitors). Figure 5 The Cs1 in the circuit is fed back to the first integrator; the ASAR2 functional module samples the output Vo of the adder, and outputs the quantization noise E2 and the 3-bit digital signal D2 after conversion. The quantization noise E2 is coupled to the ΔΣ modulator loop through the noise coupling technology, and the digital signal D2 is coupled to the DAC2, that is, Figure 5 Cs2 in is fed back to the first integrator, and the specific time-division multiplexing operation is as follows.

[0030] The ASAR circuit module is a 3-bit asynchronous successive approximation ADC with a fully differential structure. The ASAR circuit implements the work of the ASAR1 functional module in the ph2 phase. First, in the ph2 clock phase, clks1 is high, that is, the sampling clock of the ASAR1 functional module is turned on, and its sampling switch is closed. MSB , C MSB-1 , C MSB-2 and C LSB1 The lower plates of the ASAR1 module are connected to the common mode voltage (Vcm), and the upper plates sample the input signals vip and vin, which are the input signals Vi in the system architecture. After the ASAR1 functional module completes the sampling, the comparator is used for comparison, and the logic control module determines the comparison result of the comparator, and then controls the capacitor switch logic module to control C MSB , C MSB-1 , C MSB-2 The lower plate switches to the power supply voltage, Vcm or ground voltage. After three comparisons and switching, the analog-to-digital conversion of the ASAR1 functional module is completed. After the conversion is completed, the charge of E1 is sampled to C LSB1 At this time, the clk1 switch is turned off and the clka1 switch is turned on, thereby putting the capacitor C LSB1The upper plate is connected to the input terminal Va of the adder; at the same time, the logic control module outputs D1. At this point, the ASAR circuit module completes the work of the ASAR1 functional module in the ph2 phase.

[0031] The ASAR circuit implements the operation of the ASAR2 functional module in the ph1 phase. In the ph1 phase, clks2 is high, that is, the sampling clock of the ASAR2 functional module is turned on, and its sampling switch is closed. MSB , C MSB-1 , C MSB-2 and C LSB2 The lower plates are connected to the common mode level (Vcm), and the upper plates sample the output signal Vo of the adder. After sampling, the sampling switch is disconnected, the comparator compares the voltages Vp and Vn, and the logic control module determines the output of the comparator and then controls C MSB , C MSB-1 , C MSB-2 The lower plate of E2 is switched to the power supply voltage, Vcm or ground voltage. After three comparisons and switching, the analog-to-digital conversion of the ASAR2 functional module is completed. After the conversion is completed, the charge of E2 is sampled to C LSB2 At this time, the clk2 switch is opened and the clka2 switch is closed, thereby the capacitor C LSB2 The upper plate is connected to the input terminal Va of the adder; at the same time, the logic control module outputs D2. At this point, the ASAR circuit module completes the work of the ASAR2 functional module in the ph1 phase.

[0032] In summary, the ΔΣ modulator based on time-division multiplexing ASAR ADC provided in this embodiment processes the input signal through ASAR ADC and uses the quantization noise as the input signal of the ΔΣ modulator, which can reduce the output swing of the integrator; the use of ASAR ADC for multi-bit quantization in the ΔΣ modulator loop can also reduce the output swing of the integrator; at the same time, the architecture of the ΔΣ modulator is a feedforward structure, and there is only a quantization noise component in the loop, and there is no ΔΣ modulator input signal component, so the output swing of the integrator can also be reduced. The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. A ΔΣ modulator based on time-division multiplexing ASAR ADC, comprising a ΔΣ modulator circuit module, characterized in that: It also includes an ASAR1 functional module and an ASAR2 functional module; the ASAR1 functional module is arranged at the input end of the ΔΣ modulator circuit module, and is used to sample the input signal Vi in the integration phase ph2 of the ΔΣ modulator; the ASAR2 functional module is arranged in the ΔΣ modulator loop, as a multi-bit quantizer, and is used to sample the output signal Vo of the adder in the sampling phase ph1 of the ΔΣ modulator; the ASAR1 functional module and the ASAR2 functional module are implemented by the same ASAR ADC circuit module through time-division multiplexing, and the time-division multiplexing is based on the working cycle of the ΔΣ modulator, and the working cycle includes the ph1 phase and the ph2 phase, wherein the ph1 phase is the sampling phase and the ph2 phase is the integration phase; the ASAR1 functional module works in the ph2 phase, and the ASAR2 functional module works in the ph1 phase, and the working timings of the two do not overlap.

2. The ΔΣ modulator based on time-division multiplexing ASAR ADC according to claim 1, characterized in that: The ASARADC circuit module is an asynchronous successive approximation analog-to-digital converter, including a sampling switch, a capacitor array, a comparator and a logic control module; the sampling switch includes clks1 and clks2, wherein clks1 controls the sampling of the input signal Vi by the ASAR1 functional module, and clks2 controls the sampling of the adder output signal Vo by the ASAR2 functional module.

3. The ΔΣ modulator based on time-division multiplexing ASAR ADC according to claim 1, characterized in that: The input end of the ASAR1 functional module is electrically connected to the signal input end Vi of the ΔΣ modulator module, and its output end outputs a digital signal D1 and a quantization noise E1; the input end of the ASAR2 functional module is electrically connected to the output end Vo of the adder in the ΔΣ modulator loop, and its output end outputs a digital signal D2 and a quantization noise E2.

4. The ΔΣ modulator based on time-division multiplexing ASAR ADC as claimed in claim 3, characterized in that: The ASARADC circuit module samples the input signal Vi by closing the clks1 switch in the ph2 phase, and injects the quantization noise E1 into the ΔΣ modulator loop after the conversion is completed; samples the adder output signal Vo by closing the clks2 switch in the ph1 phase, and injects the quantization noise E2 into the ΔΣ modulator loop after the conversion is completed.

5. The ΔΣ modulator based on time-division multiplexing ASAR ADC according to claim 1, characterized in that: The ΔΣ modulator adopts a feedforward structure, and the loop only contains a quantization noise component. The time-division multiplexing operation of the ASAR1 functional module and the ASAR2 functional module is achieved through timing control.

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