A method for transmitting multi-module control instructions and a blot analysis device

Abstract

The present invention relates to a method for transmitting a multi-module control instruction, comprising: an interface board processor receives an external instruction PEC interrupt trigger; in response to the external instruction PEC interrupt, the main program is interrupted, and the control instruction is transmitted from the communication interface buffer of the interface board to the frame receiving buffer by using the PEC channel; the control instruction in the frame receiving buffer is read and the control instruction is parsed; and in response to the control instruction being correctly received, the control instruction is forwarded to multiple parallel modules. The present invention transmits multi-module control instructions to a multi-module footprint analysis device through a PEC transmission method based on interrupt response, which can effectively reduce the delay problem of the multi-module control instructions and improve the stability of the multi-module footprint analysis device.

Description

Technical Field

[0001] The present invention relates to the technical field of medical devices, and in particular to a multi-module control instruction transmission method and a blot analysis device. Background Art

[0002] Imprint analysis equipment can automatically perform various protein sample separation, immunoassay, qualitative and quantitative analysis, and is widely used in many fields such as protein property identification, protein quantitative analysis, protein function research, protein modification and differential expression research. Existing imprint analysis equipment includes multiple independent control modules to ensure that more samples can be processed at the same time, improve the product's processing capacity, and reduce waiting time.

[0003] However, in order to ensure the accuracy of the analysis results, even if multiple control modules are used, each module must start working at the same time. However, when receiving instructions between modules of the multi-module blot analysis device, there may be loss or delay problems, which affects the accuracy of the analysis results. Summary of the invention

[0004] In view of the technical problems existing in the prior art, the present invention proposes a method for transmitting multi-module control instructions, including: an interface board processor receives an external instruction PEC interrupt trigger; in response to the external instruction PEC interrupt, the main program is interrupted, and the control instruction is transmitted from the communication interface buffer of the interface board to the frame receiving buffer by using the PEC channel; the control instruction in the frame receiving buffer is read and the control instruction is parsed; and in response to the control instruction being correctly received, the control instruction is forwarded to multiple parallel modules.

[0005] In the method as described above, the priority of the control instruction is higher than the priority of the common instruction.

[0006] In the method as described above, the priority of the control instruction is the highest level.

[0007] The method as described above, wherein the frame receiving buffer comprises a FIFO buffer.

[0008] In the method as described above, the buffer space of the FIFO buffer is 3-6KB.

[0009] In the method as described above, before storing the frame in the frame receiving buffer, it is determined whether the frame receiving buffer is full.

[0010] In the method as described above, before reading the frame receiving buffer, it is determined whether the frame receiving buffer is empty.

[0011] In the method as described above, a PEC interrupt is generated in response to the communication interface buffer of the interface board receiving a predetermined number of control instruction data.

[0012] In the method as described above, in response to transmitting a predetermined amount of control instruction data from the communication interface buffer of the interface board to the frame receiving buffer using the PEC channel, the PEC interrupt procedure is terminated.

[0013] The method as described above, wherein a plurality of PEC interrupt processes are generated continuously.

[0014] In the method as described above, in response to the frame receiving buffer being not empty, the control instruction in the frame receiving buffer is read and the control instruction is parsed.

[0015] In the method as described above, a high-speed bus is used to forward control instructions to multiple parallel modules.

[0016] According to another aspect of the present invention, an interface board is proposed, comprising: a processor; a communication interface, comprising a communication interface buffer, configured to communicate with a main control module; a frame receiving buffer, connected to the processor and configured to cache control instructions; and a bus interface, configured to communicate with multiple parallel modules; wherein the processor is configured to utilize a PEC channel to transmit the control instruction from the communication interface buffer of the interface board to the frame receiving buffer; and in response to the control instruction being correctly received, the control instruction is forwarded to the multiple parallel modules via the bus interface.

[0017] In the interface board as described above, the communication interface is configured to generate a PEC interrupt in response to the communication interface buffer of the interface board receiving a predetermined number of control instruction data.

[0018] In the interface board as described above, the processor is configured to terminate the current PEC interrupt processing in response to transmitting a predetermined amount of control instruction data from the communication interface buffer of the interface board to the frame receiving buffer using the PEC channel.

[0019] The interface board as described above, wherein the frame receiving buffer comprises a FIFO buffer.

[0020] In the interface board as described above, the buffer space of the FIFO buffer is 3-6KB.

[0021] The interface board as described above, wherein the processor is configured to determine whether the frame receiving buffer is full before storing the frame in the frame receiving buffer.

[0022] The interface board as described above, wherein the processor is configured to determine whether the frame receiving buffer is empty before reading the frame receiving buffer.

[0023] According to another aspect of the present invention, a multi-module blot analysis device is provided, comprising: a main control module; the interface board as described above; and a plurality of parallel modules; wherein the main control module and the plurality of parallel modules communicate with the interface board as described above.

[0024] The present invention transmits multi-module control instructions to a multi-module footprint analysis device through a PEC transmission method based on interrupt response, which can effectively reduce the time delay problem of the multi-modules and improve the stability of the multi-module footprint analysis device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The preferred embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:

[0026] Figure 1 is a schematic diagram of a dual-module blot analysis device according to one embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of a dual-module control structure according to an embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of a control instruction transmission method according to an embodiment of the present invention;

[0029] Figure 4 is a timing diagram of executing tasks using different transmission methods according to an embodiment of the present invention;

[0030] Figure 5 is a schematic diagram of a control instruction receiving process according to an embodiment of the present invention; and

[0031] Figure 6 It is a schematic diagram of a control instruction reading process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0034] Figure 1Schematic diagram of a dual-module blot analysis device according to one embodiment of the present invention. Figure 1 As shown, the blot analysis equipment includes two independent modules, which control two sets of shakers to work simultaneously. In order to ensure the accuracy of the analysis results, the two sets of shakers need to have very high synchronization. If the control instructions of one of the modules are lost or delayed, the detection results of the analysis equipment will be seriously affected.

[0035] Figure 2 1 is a schematic diagram of a dual-module control structure according to an embodiment of the present invention. As shown in the figure, the main control module (such as a PC) is connected to the interface board through a communication interface (such as an RS232 interface) for sending control instructions to the interface board. The interface board is respectively connected to module 1 and module 2 through a bus interface (such as a CAN bus) for sending control instructions.

[0036] Among them, module 1 and module 2 run in parallel to receive and execute control commands. Module 1 includes main board 1, function board 1-1, and function board 1-2, which are connected in bus communication mode and transmit commands with multiple modules; module 2 includes main board 2, function board 2-1, and function board 2-2. Function boards include but are not limited to drive system, temperature control system, image acquisition system, etc. Taking the function of the drive system as an example, the synchronization between module 1 and module 2 has very high requirements. Reference Figure 2 For a system with a distributed structure, the communication efficiency of the interface board directly affects the function and performance of the entire machine.

[0037] In order to solve the communication efficiency problem of the interface board, in an embodiment of the present invention, when the two modules are running in parallel, the communication interface adopts a PEC transmission method based on an interrupt mode, and completes the data transmission between any two memory addresses from the idle cycle of the current CUP process, thereby solving the delay problem of the parallel control instruction transmission of the two modules, so as to ensure fast and efficient transmission, thereby achieving a high degree of real-time performance.

[0038] Figure 3 FIG. 1 is a schematic diagram of a control instruction transmission method according to an embodiment of the present invention. As shown in the figure, the control instruction transmission method includes the following steps:

[0039] Step 310, the communication interface of the interface board is initialized. Before the control instruction transmission begins, the communication interface of the interface board needs to be initialized. In some embodiments, the communication interface of the interface board includes a communication interface buffer for communicating with the main control module. The communication interface between the main control module and the interface board is a serial port, such as an RS232 interface. Of course, the communication interface between the two can also be other types of interfaces or other types of serial ports.

[0040] In step 320, the interface board processor receives an external instruction PEC interrupt trigger. In some embodiments, a PEC interrupt is generated in response to the interface board communication interface buffer receiving a predetermined number of control instruction data. In the prior art, if a serial port receives a frame of 16 bytes of instructions as an example, an interrupt is generated for each byte received. In the PEC interrupt service routine, the interface board processor takes the byte out of the communication interface buffer and then sequentially puts it into the frame receiving buffer. When the entire frame is received, frame processing is performed.

[0041] When using the existing interrupt transmission method, the processor pauses the execution of the currently executing main program, saves the current processor state, PSW, the address of the executing program, etc. Then it performs context switching and executes the corresponding interrupt service program. After the interrupt service program ends, the processor continues to execute the interrupted main program. Since this interrupt transmission will generate many interrupts, a large amount of processor overhead will be generated when entering and exiting interrupts or forcing interrupt service programs, which not only wastes a lot of time, but also easily causes the loss or delay of control instruction transmission.

[0042] In some embodiments, the priority of the configuration control instruction is higher than that of the ordinary instruction, wherein the priority may be 14 or 15. By increasing the priority of the control instruction, the real-time performance of the multi-module parallel control instruction can be enhanced, allowing the processor to process the multi-module control instruction with priority, further improving the response speed of the multi-module action; in other embodiments, the priority of the configuration control instruction is the highest level; then the corresponding PEC service channel is defined, for example, the PEC source pointer and the destination pointer are defined, and the interrupt has the PEC function and becomes a PEC interrupt source outside the processor. When the PEC channel configuration is completed, the processor receives an interrupt trigger signal, and can use the PEC channel to complete the transmission of the control instruction.

[0043] In step 330, in response to the external command PEC interrupt, the main program is interrupted, and the control command is transmitted from the communication interface buffer of the interface board to the frame receiving buffer by using the PEC channel.

[0044] In some embodiments, in response to the triggering of the PEC interrupt by an external instruction, the processor determines that the priority meets the requirements, temporarily stops the operation of the main program, and gives the right of use to the PEC transmission channel. In some embodiments, in response to the use of the PEC channel to transfer a predetermined number of control instruction data from the communication interface buffer of the interface board to the frame receiving buffer, the PEC interrupt program ends. Still taking a frame of 16 bytes of instructions as an example, the PEC channel control register is assigned to 16, the source pointer is defined as the communication interface buffer in the main control module, and the destination pointer is defined as the first address of the frame receiving buffer. After each transmission is completed, the destination pointer is increased by 1. Every time the communication interface buffer receives a predetermined number of control instruction data, a PEC service is triggered, in which multiple PEC interrupt processing can be generated continuously. In this way, the control instruction is transferred from the communication interface buffer to the frame receiving buffer in a hardware manner, and the PEC interrupt program ends.

[0045] When an interrupt request triggers PEC, a single-cycle byte transfer is performed between the communication interface buffer and the frame receive buffer, reducing the interface board processor overhead when the CPU enters and exits the interrupt or forced interrupt service program. It is equivalent to "stealing" one cycle from the current CPU operation to implement the PEC operation, thereby reducing the interrupt request load of the interface board processor.

[0046] In step 340, the control instruction in the frame receiving buffer is read and the control instruction is parsed. In some embodiments, the reading and parsing of the control instruction can be performed simultaneously with the reception of the control instruction from the communication interface buffer. In some embodiments, the control instruction in the frame receiving buffer can also be read and the control instruction is parsed after the communication interface buffer has completed receiving the control instruction.

[0047] In step 350, in response to the control instruction being received, a CRC check is performed on the control instruction. After the control instruction is parsed and CRC checked, it is determined that the control instruction is correctly received.

[0048] In step 360, the control instruction is placed in the bus cache. The interface board processor places the control instruction in the bus cache to send the control instruction to the two modules through bus communication between module 1 and module 2. In some embodiments, the control instruction is forwarded to multiple parallel modules using a high-speed bus, such as a CAN bus. The bus communication between the interface board and the two parallel modules can ensure synchronization, such as synchronization at the order of us.

[0049] In step 370, reply command Ack to confirm that the control command has been correctly received and forwarded to multiple parallel modules. In some embodiments, the control command is issued by the application software running on the main control module, which sends the control command to the interface board. The interface board receives the control command and feeds back the response Ack, forming a closed-loop processing of the control command to improve the reliability and stability of the command transmission. In some embodiments, similarly, after receiving the control command, module 1 and module 2 also reply command Ack to confirm that the control command has been correctly received. Such a reply can also be returned to the application software to confirm the receipt of the control command. In some embodiments, the interface board waits for the reply command from module 1 and module 2 before replying command Ack to simplify the control process.

[0050] As understood by those skilled in the art, in the above embodiments, the reading, parsing and CRC checking of instructions in the interrupt handler are performed after the main program is restored. Placing these operations outside the interrupt handler can reduce the redundancy of the interrupt handler and enhance the real-time performance of dual-module parallel control instruction reception.

[0051] Figure 4 This is a task execution timing diagram of different transmission methods according to an embodiment of the present invention. As shown in the figure, when the imprint analysis device adopts the interrupt transmission transmission mode, the peripheral sends an interrupt request to the processor. Under certain conditions, the processor suspends the execution of the currently executing main program, saves the current processor state, PSW, the address of the executing program, etc., and the processor continues to execute the main program that was originally interrupted after the interrupt ends. Therefore, each time a byte is received during the interrupt transmission, an interrupt is generated, which generates a large amount of processor overhead when entering and exiting the interrupt or forced interrupt service program, and wastes a lot of time. If PEC transmission is adopted, as long as the PEC transmission channel is defined, when the peripheral sends an interrupt request to trigger the PEC transmission, it is not necessary to enter and exit the interrupt program. It only needs to "steal" a cycle from the processor to realize PEC transmission, which saves a lot of entry and exit time and greatly improves the transmission efficiency. Therefore, in order to solve the delay problem of multi-module parallel operation, a PEC transmission method based on interrupt mode is adopted. The following further illustrates the PEC transmission method through some embodiments.

[0052] The PEC transmission process is mainly divided into two stages: the instruction receiving stage and the instruction reading stage. According to an embodiment of the present invention, the instruction receiving stage is performed during the interrupt response stage; the instruction reading stage is performed after the main program is restored.

[0053] Figure 5 1 is a schematic diagram of a control instruction receiving process according to an embodiment of the present invention. As shown in the figure, the method includes the following steps:

[0054] In step 510, an external instruction PEC interrupt trigger signal is received to interrupt the main program. In some embodiments, the instruction needs to be identified before the PEC interrupt is triggered, wherein the identification conditions include but are not limited to instruction priority and instruction type. When the interface board processor determines that the identification conditions such as instruction priority and instruction type meet the preset regulations, the main program is interrupted and the PEC transmission channel is opened.

[0055] In step 520, the control instruction in the communication interface buffer of the interface board is read. In response to opening the PEC transmission channel, the control instruction from the communication interface buffer of the interface board is received according to the configured source pointer and destination pointer information.

[0056] In step 530, the remaining space of the frame receiving buffer is calculated. In some embodiments, the frame receiving buffer can be a FIFO buffer, which can cache continuous data streams. In order to ensure that the instructions are correctly written or read without overflow or empty reading, it must be ensured that the write operation cannot be performed when the FIFO is full, and the read operation cannot be performed when the FIFO is empty. In some embodiments, it is determined whether the frame receiving buffer is full before storing it in the frame receiving buffer. Therefore, before using PEC to transmit instructions, the remaining space of the FIFO must first be calculated and the FIFO boundary must be determined. If the number of instruction bytes written is less than or equal to the remaining space of the FIFO, then the instruction can be received, and the write pointer automatically increases by 1 after writing; if the number of instruction bytes written is greater than the remaining space of the FIFO, then it will be received in multiple times, and the write pointer automatically increases by 1 after writing.

[0057] In step 540, in response to the remaining space in the frame receiving buffer being greater than the length of the control instruction, the instruction is received through the PEC channel and placed in the frame receiving buffer. The traditional buffer storage space is small and prone to the risk of data loss. Therefore, in this solution, the buffer space of the FIFO buffer is increased to 3-6KB, which can effectively prevent data loss during data transmission and storage operations.

[0058] In step 550, the PEC source pointer and the destination pointer are reset. After the instruction is received, the processor resumes the main program, resets the PEC source pointer and the destination pointer, and returns to step 510 to wait for the next triggering of the external PEC interrupt.

[0059] In step 560, in response to the completion of instruction reception, the main program is resumed. After receiving the control instruction using the PEC transmission channel, the main program processing work is resumed, and the instruction is further read. Putting the instruction reading outside the interrupt program can reduce the redundancy of the interrupt processing program and improve the efficiency of PEC transmission instructions.

[0060] Figure 61 is a schematic diagram of a control instruction reading process according to an embodiment of the present invention. As shown in the figure, the control instruction reading method includes the following steps:

[0061] In step 610, it is determined whether the frame receiving buffer is empty. In some embodiments, before reading the instruction in the frame receiving buffer (e.g., FIFO), it is first determined whether the FIFO is in an empty state. The FIFO is configured with an empty flag. When the FIFO is empty or about to be empty, a signal is sent by the FIFO status circuit to prevent the FIFO read operation from continuing to read instructions from the FIFO, thereby causing invalid instructions to be read.

[0062] In step 620, the control instruction in the frame receiving buffer is read, and the output pointer is incremented by 1. When it is determined that the frame receiving buffer is not empty, the control instruction in the frame receiving buffer is read, and each time a data is read, the output pointer points to the next address, and the output pointer is automatically incremented by 1.

[0063] In step 630, the data in the control instruction is parsed. Parsing the data in the control instruction means extracting the content of the control instruction and responding according to the corresponding content. For example, if the instruction content is to start the dual-module drive system, the serial port processor will make a corresponding response instruction according to the control instruction requirements; if the instruction content is the status information of the device, it only needs to save the information locally without making a response instruction.

[0064] In step 640, in response to the completion of the control instruction reading, the instruction is checked to see if it is correct. The way to check the instruction includes CRC check, which is a method of checking with an error check code. The CRC check code is a check value obtained by a specific calculation method of the previous several sections of the instruction content and placed behind the information field. After receiving the instruction, the receiver uses the same calculation method to obtain the check code of the information field, and compares it with the actual check code received. If the check code is consistent, it means that the information is correct. If the check code is inconsistent, it means that the information is incorrect, delete the wrong instruction, and end the instruction check. In other embodiments, the way to check whether the instruction is correct includes checking whether each part of the instruction is complete. Usually, the control instruction format is: header + instruction length + instruction address + instruction text + check code. First, check whether the entire instruction length meets the preset value. If it does not meet the preset value, it means that part of the instruction is missing, then delete the wrong instruction, and end the instruction check; if the instruction length is consistent with the preset value, it means that the instruction is complete and enter the next step. There are many reasons for instruction errors, such as electromagnetic interference causing incomplete or wrong instructions, insufficient hardware driver efficiency causing instruction loss, etc.

[0065] In step 650, the control instruction is placed in an instruction queue. The instruction queue is used to temporarily store various pre-fetch instructions. When the instruction is confirmed to be correct, the instruction is placed in the instruction queue and processed according to the importance of the instruction. In some embodiments, the priority of the control instruction is increased, and the control instruction is always in a priority state to avoid delay problems.

[0066] In step 660, the feedback instruction is replied. The feedback instruction is a transmission control character sent by the receiving station to the sending station in data communication, indicating that the sent instruction has been confirmed. For the sending station, only after receiving the feedback instruction, it will be considered that the message has been correctly received or processed successfully. Therefore, replying the feedback instruction is equivalent to establishing a simple "guarantee" mechanism between the receiving station and the sending station. In some embodiments, when the communication interface receives the control instruction, it immediately replies to the feedback instruction, forming a closed-loop processing of the control instruction, thereby improving the reliability and stability of instruction transmission.

[0067] The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.

Claims

1. A method for transmitting multi-module control instructions, comprising: The interface board processor receives an external instruction PEC interrupt trigger, wherein a PEC interrupt is generated in response to the communication interface buffer of the interface board receiving a predetermined number of control instruction data, wherein the interface board includes the processor, the communication interface, the frame receiving buffer and the bus interface, and the communication interface includes the communication interface buffer; In response to an external instruction PEC interrupt, the main program is interrupted, and the control instruction is transmitted from the communication interface buffer of the interface board to the frame receiving buffer by using the PEC channel, wherein in response to transmitting a predetermined amount of control instruction data from the communication interface buffer of the interface board to the frame receiving buffer by using the PEC channel, the PEC interrupt program is terminated; Reading the control instructions in the frame receiving buffer and parsing the control instructions; and In response to the control instruction being correctly received, the control instruction is forwarded to the multiple parallel modules, wherein the interface board processor puts the control instruction into the bus cache and forwards the control instruction to the multiple parallel modules using the high-speed bus.

2. The method according to claim 1, wherein the priority of the control instruction is higher than the priority of the ordinary instruction. The method according to claim 1 , wherein the priority of the control instruction is the highest level. The method of claim 1 , wherein the frame reception buffer comprises a FIFO buffer.

5. The method according to claim 4, wherein the buffer space of the FIFO buffer is 3-6KB.

6. The method according to claim 1, wherein before storing the frame in the frame receiving buffer, it is determined whether the frame receiving buffer is full. 7 . The method according to claim 1 , wherein before reading the frame receiving buffer, it is determined whether the frame receiving buffer is empty.

8. The method of claim 7, wherein a plurality of PEC interrupt processes are generated consecutively. 9 . The method according to claim 1 , wherein in response to the frame receiving buffer being not empty, the control instruction in the frame receiving buffer is read and the control instruction is parsed.

10. An interface board, comprising: processor; a communication interface, comprising a communication interface buffer, configured to communicate with the main control module, wherein the communication interface is configured to generate a PEC interrupt in response to the communication interface buffer of the interface board receiving a predetermined number of control instruction data; a frame receiving buffer connected to the processor and configured to buffer control instructions; and a bus interface configured to communicate with a plurality of parallel modules; The processor is configured to transmit the control instruction from the communication interface buffer of the interface board to the frame receiving buffer by using the PEC channel, wherein the processor is configured to terminate the PEC interrupt processing in response to transmitting a predetermined number of control instruction data from the communication interface buffer of the interface board to the frame receiving buffer by using the PEC channel; read the control instruction in the frame receiving buffer and parse the control instruction; in response to the control instruction being correctly received, forward the control instruction to multiple parallel modules through the bus interface, wherein the processor puts the control instruction into the bus cache and forwards the control instruction to multiple parallel modules by using the high-speed bus.

11. The interface board of claim 10, wherein the frame reception buffer comprises a FIFO buffer.

12. The interface board according to claim 11, wherein the buffer space of the FIFO buffer is 3-6 KB.

13. The interface board of claim 10, wherein the processor is configured to determine whether the frame receive buffer is full before storing the frame in the frame receive buffer.

14. The interface board of claim 10, wherein the processor is configured to determine whether the frame reception buffer is empty before reading the frame reception buffer.

15. A multi-module blot analysis device comprising: Main control module; The interface board as claimed in claims 10-14; as well as Multiple parallel modules; Wherein, the main control module and the plurality of parallel modules communicate with the interface board as described in claims 10-14.

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