Low latency memory access

Abstract

Embodiments of the present application relate to low latency memory access. The memory device includes a receiver that uses CMOS signaling levels (or other relatively large signal swing levels) on the command / address and data interfaces of the memory device. The memory device also includes an asynchronous timing input that allows the reception of command and address information from the CMOS level receiver, which will be decoded and forwarded to the memory core (which is self-timing) without the need for a clock signal on the main clock input of the memory device. Therefore, the activation row command can be received and initiated by the memory core before the memory device has completed exiting the low power state. Because the row operation is started before the exit wait time has elapsed, the delay of one or more accesses (or other operations) after exiting the low power state is reduced.

Description

Technical Field

[0001] Various embodiments of the present application relate to low-latency memory access. Summary of the invention

[0002] According to a first aspect of the present disclosure, a memory component is provided, comprising: a memory core; a first timing signal interface for receiving a first timing signal, the first timing signal determining a synchronous sampling of a signal at a first group of links; a second timing signal interface for receiving a second timing signal, the second timing signal determining a synchronous sampling of a signal at a second group of links; and a memory core control circuit for accessing the memory core based at least in part on at least a first command, a first control, and a first address information received in a first mode in response to a first synchronous sampling of a signal at the first group of links using the first timing signal, and the memory core control circuit is also used to access the memory core based at least in part on a second command, a second control, and a second address information received in a second mode in response to a first asynchronous sampling of a signal at the first group of links and a signal at the second group of links using a third timing signal.

[0003] In the memory component, the memory core control circuit is used to activate a row in a bank of the memory core in response to the second command, the second control, and the second address information.

[0004] In the memory component, wherein in the first mode, information is to be communicated bidirectionally by the memory component synchronously via the second set of links using the second timing signals.

[0005] In the memory component, wherein in the second mode, information is to be communicated by the memory component synchronously bidirectionally via the second set of links using the second timing signals.

[0006] In the memory component, a first synchronous interface that synchronously samples the first set of links using the first timing signal when in the first mode and a second synchronous interface that synchronously communicates with the second set of links using the second timing signal when in the first mode will not be synchronously sampled when in the second mode.

[0007] In the memory component, wherein when in the second mode and when the first timing signal interface is receiving an inactivity signal, at least one transition of the third timing signal initiates the first asynchronous sampling of the first set of links to receive the second command, the second control, and the second address information.

[0008] In the memory component, wherein the signal interface is to be used in the first mode to receive a power control signal and is to be used in the second mode to receive the third timing signal, at least one transition of the third timing signal is used to initiate the first asynchronous sampling of the first set of links to receive the second command, the second control, and the second address information.

[0009] In the memory component, wherein exit from the second mode to the first mode is to be initiated by activating a first timing reference.

[0010] In the memory component, wherein the at least one transition of the third timing signal is to be detected based on sampling of the third timing signal using the first timing signal, the detected at least one transition of the third timing signal is used to initiate an exit from the second mode.

[0011] According to a second aspect of the present disclosure, a memory component is disclosed, comprising: a first interface for synchronously receiving commands, addresses and control signals relative to a first externally received timing reference in a first mode of the memory component; a second interface for synchronously bidirectionally communicating data relative to a second externally received timing reference in the first mode of the memory component; the first interface and the second interface for receiving commands, addresses and control signals in response to at least one transition of a third externally received timing reference in the second mode of the memory component; and a control circuit for sending a first control signal to the memory core to activate a first row in response to the command, address and control signal received synchronously relative to the first externally received timing reference in at least the first mode of the memory component, and sending a second control signal to the memory core to activate a second row in response to the command, address and control signal received in response to the at least one transition of the third externally received timing reference in at least the second mode of the memory component.

[0012] In the memory component, wherein the second mode of the memory component is a lower power mode relative to the first mode.

[0013] In the memory component, wherein in the second mode of the memory component, the second interface is further configured to communicate data synchronously with respect to the second externally received timing reference.

[0014] In the memory component, wherein in the second mode of the memory component, the control circuit is used to receive the command, the address and part of the control signal via the first interface, and the control circuit is used to receive the command, the address and the remaining part of the control signal via the second interface in response to at least one transition of the third externally received timing reference.

[0015] In the memory component, wherein the command, the address, and the remaining portion of the control signal include an address signal.

[0016] In the memory component, wherein in the first mode, when the first externally received timing reference signal is active, the command, the address and the control signal are enabled to be received by an enable signal on a signal input.

[0017] In said memory component, wherein in said second mode, said at least one transition of said third externally received timing reference to be provided is received via said signal input when said first timing reference signal is inactive.

[0018] According to a third embodiment of the present disclosure, a memory component is provided, comprising: a control circuit for operating the memory component in at least a first mode and a second mode; a first synchronous timing reference interface for receiving a first timing reference signal, which is periodic at a first frequency when active; a second synchronous timing reference interface for receiving a second timing reference signal, which is periodic at a second frequency when active; a signal interface for receiving a timing signal; and a command / address interface for receiving first information provided to the command / address interface synchronously with the first timing reference signal based at least in part on the memory component being operated in the first mode, the first information comprising address information sufficient to activate a first row of a first bank of a memory core , the command / address interface is also used to receive second information provided to the command / address interface asynchronously with the first timing reference signal and the second timing reference signal based at least in part on the memory component being operated in the second mode, the second information will be sampled from the command / address interface based at least in part on the timing signal; and, a data interface is used to receive third information provided to the data interface asynchronously with the first timing reference signal and the second timing reference signal based at least in part on the memory component being operated in the second mode, the third information will be sampled from the data interface based at least in part on the timing signal, the second information and the third information collectively include address information sufficient to activate a second row of a second bank of the memory core.

[0019] In the memory component, wherein receipt of the second information and the third information is used to initiate a self-timed activation of the second row of the second bank of the memory core.

[0020] In the memory component, wherein based on the memory component being operated in the first mode, the signal interface receives a control signal, the control signal enabling the command / address interface to receive command / address information synchronously with respect to the first timing reference signal and enabling the data interface to communicate data synchronously with respect to the second timing reference signal.

[0021] In the memory component, wherein during the self-timed activation, the second synchronous timing reference interface is to be activated and the data interface is to be enabled to synchronously communicate data. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a block diagram illustrating a memory system.

[0023] Figure 2 is a timing diagram illustrating an example low-latency access.

[0024] Figure 3 is a timing diagram illustrating an example deterministic asynchronous refresh followed by low latency access.

[0025] Figure 4 is a timing diagram illustrating an example semi-deterministic asynchronous refresh followed by a low-latency access.

[0026] Figure 5 is a block diagram illustrating memory components.

[0027] Figure 6 is a block diagram illustrating a memory component with asynchronously initiated column operations.

[0028] Figure 7 is a flow chart illustrating a method of operating a memory device.

[0029] Figure 8 is a flow chart illustrating a method of operating a memory device in at least two modes.

[0030] Fig. 9 is a flow chart illustrating a method of operating a memory device.

[0031] Fig.10 is a flow chart illustrating a method of operating a memory controller.

[0032] Fig.11 is a flow chart illustrating a method of operating a memory controller to control a memory device having at least two modes.

[0033] Fig.12 is a flow chart illustrating a method of operating a memory controller to control a memory device.

[0034] Fig.13 is a block diagram of a memory device.

[0035] Fig.14 is a block diagram of a memory device.

[0036] Fig.15 is a schematic diagram of a credit / debit counter for self-refresh.

[0037] Fig.16 It is a block diagram of the processing system. DETAILED DESCRIPTION

[0038] In an embodiment, a memory device (e.g., a dynamic random access memory DRAM, a flash memory, etc.) can be placed in a power saving state. In this power saving state, the interface (e.g., command / address, data, etc.) is turned off and the clock signal is stopped. When in this mode, the current required by the memory device is very low (e.g., ~3mA). The memory device includes a receiver that uses a complementary metal oxide semiconductor (CMOS) signal level (e.g., a high threshold voltage of 2.0V and a low threshold voltage of 0.8V, or other relatively large signal swing levels) on the command / address and data interfaces of the memory device. The memory device also includes an asynchronous timing input that allows command and address information to be transferred from the CMOS level receiver to the memory core (which is self-timed) without the need for a clock signal on the main clock input of the memory device. Therefore, the activation row command can be received and initiated by the memory core before the memory device has completed exiting the low power state. Because the row operation starts before the exit wait time has elapsed, the delay of one or more accesses (or other operations) after exiting the low power state is reduced.

[0039] Figure 1 is a block diagram illustrating a memory system. Figure 1 , the memory system 100 includes a controller 110 and a memory device 120. The memory device 120 includes a memory core 125, a mode #1 control circuit 121, and a mode #2 control circuit 122. The controller 110 includes a mode #1 control circuit 111 and a mode #2 control circuit 112. It should be understood that the separation of the mode #1 control circuit 121 and the mode #2 control circuit into separate blocks is only for illustrative purposes. The functions provided by the mode #1 circuit 121 and the mode #2 control circuit can be provided by a single circuit block. Similarly, the mode #1 control circuit 111 and the mode #2 control circuit 112 can be provided by a single circuit block.

[0040] The controller 110 is operatively coupled to the memory device 120. Specifically, Figure 1 , the controller 110 provides at least the following signals or uses at least the following signals to communicate with the memory device 120: one or more clock (e.g., CK) signals, one or more clock enable (e.g., CKE) signals, one or more chip select (e.g., CS) signals, one or more command / address signals (e.g., CA[0:5]), one or more asynchronous timing (e.g., ACK) signals, one or more bidirectional data (e.g., DQ[15:0]) signals, and one or more data select (e.g., DQS) signals.

[0041] It should be noted that in the discussion and drawings herein, the set of CA signals (and interfaces) may be labeled CA[5:0], which may imply that there are exactly six CA signals. However, this is merely exemplary for the purposes of the disclosure provided herein. Other numbers of CA signals, interfaces, and links are contemplated. Similarly, DQ[15:0] is merely exemplary and other numbers of DQ signals, interfaces, and links are also contemplated.

[0042] In an embodiment, the memory device 120 can operate in at least two modes. The first mode (e.g., mode #1) is a high-performance, higher-power mode. In this mode, commands and addresses are synchronously communicated to the memory device 120 on at least the CA interface. The clock enable (CKE) and chip select (CS) signals are also synchronously communicated to the memory device 120. The timing reference that synchronizes the sampling (or transfer) of these signals is a periodic (e.g., at the operating frequency) clock signal (CK). Similarly, data is synchronously communicated to / from the memory device 120 on at least the data interface DQ. The timing reference that synchronizes the sampling or transfer of data on the DQ interface is (one or more) data select signals DQS.

[0043] The second mode (e.g., mode #2) in which the memory device 120 can be operated is a power saving mode. In this mode, the synchronous operation of the CA and DQ interfaces is turned off. The synchronous timing reference CK is also stopped (i.e., it no longer switches states periodically). In addition, in this mode, one or more commands and addresses can be asynchronously communicated to the memory device 120 on the CA and DQ interfaces. The clock enable (CKE) and chip select (CS) signals are also asynchronously sampled by the memory device 120. The timing reference that controls the sampling (or transfer) of these signals is an asynchronous timing signal (ACK). Therefore, commands and addresses can be communicated to the memory device 120 via the CA and DQ interfaces in this mode using ACK to provide timing. The signals provided to the CA and DQ interfaces by the controller 110 may have different logic thresholds than the signals communicated in the first mode. For example, the signals communicated via the CA and DQ interfaces during the high-speed high-power operation mode may have very small signal swings (e.g., 1.2V). However, signals communicated via the CA and DQ interfaces during power save mode may have full CMOS voltage swings (eg, 3.0 or 3.3 V pp).

[0044] The selected transition of ACK (e.g., rising from low to high or falling from high to low) determines when the command and address information on the CA and DQ links are sampled by the memory device 120. The memory device 120 decodes the sampled signals to generate control signals to be applied to the memory core 125 to cause access. Thus, in response to the applied control signals, the memory core 125 may at least initiate a row activation operation at an address specified by the sampled command and address information from the CA and / or DQ interface.

[0045] In an embodiment, the asynchronous timing reference may be received on its own interface / pin / pad. In an embodiment, when the memory device 120 is in a high power mode, the asynchronous timing reference may be multiplexed on interfaces / pins / pads with different functions. For example, a clock enable (CKE) input may be used as a clock enable signal input when the memory device 120 is in a high power mode, and then used as an asynchronous timing reference when the memory device 120 is in a power saving mode. Therefore, the reference to ACK herein should be understood to include receiving an asynchronous timing reference via a non-dedicated (e.g., CKE) input to the memory device 120.

[0046] In an embodiment, upon a transition (e.g., rise) of an asynchronous timing reference (ACK), the row activation address and control are transferred to the memory core 125. This activation operation occurs in parallel with the memory device 120 being controlled to exit the power saving mode. Once the memory device 120 has exited the power saving mode, the controller 110 can use the high power synchronization mode of the interfaces CA and DQ to complete the column operation. Therefore, it should be understood that the memory device 120 can be controlled to start the access operation while still in the power saving mode and then complete the operation when in the high power mode. In other words, when the memory device 120 is in the power saving mode and is not receiving a periodic clock signal for synchronizing the command / address / and data transfer, the row operation can be initiated by the strobe signal on the asynchronous timing reference (ACK). The memory device 120 receives the information it needs to initiate the row operation using both the CA and DQ interfaces, and both the CA and DQ interfaces sample and forward the information presented to them in response to the strobe signal on the asynchronous timing reference ACK. Because the memory core 125 is self-timed. It can perform row operations without using the synchronous timing reference CK.

[0047] In an embodiment, the memory device 120 may be controlled by the controller 110 to perform other types of operations based on information received on the CA and / or DQ interface in response to the asynchronous timing reference ACK. For example, one or more of the following operations may be performed by the memory device 120: (1) the memory device 120 may refresh all banks at the refresh counter row address; (2) the memory device 120 may refresh one bank specified by the refresh timer bank / row address; (3) the memory device 120 may refresh all banks at the row address specified by the signal at the CA and / or DQ interface; (4) the memory device 120 may refresh one bank specified by the signal at the CA and DQ interface; (5) the memory device 120 may refresh one bank specified by the signal at the CA and / or DQ interface and the refresh counter row address; and (6) the credit / debit counter may be used to conditionally refresh at the refresh counter bank / row address if the refresh timer has elapsed.

[0048] An example of a single refresh followed by a column access may proceed as follows: (1) a refresh command and address are transmitted by the controller 110 to the memory device 120 over the CA and DQ interfaces; (2) upon receiving a selected transition of an ACK (e.g., transmitted by the controller 110), the memory device 120 performs an activation / precharge of the bank / row specified by the command received at the CA and DQ interfaces; (3) a row activation command and address for read or write are transmitted by the controller 110 to the memory device 120 over the CA and DQ interfaces; (4) on a second edge of the ACK (e.g., sent by the controller 110), a row activation address for a different bank (i.e., different from the previously specified bank) is used to access the memory core 125. Note that this second activation command may be executed in parallel with the memory device 120 being controlled to exit a power saving mode. One or more column operations (e.g., read or write) associated with the second activation command may be completed in a high power mode using the synchronization functionality of the CA and DQ interfaces.

[0049] An example of a conditional refresh followed by a column access may proceed as follows: (1) a self-refresh command and address are transmitted by controller 110 to memory device 120 over the CA and DQ interfaces; (2) upon receiving a selected transition of an ACK (e.g., sent by controller 110), if the credit / debit counter (internal to memory device 120, not in Figure 1 ) indicates that a refresh should be performed, the memory device 120 will perform the activation / precharge of the bank / row specified by the command received at the CA and DQ interfaces, which optimizes the refresh rate for the temperature of the memory device 120; (3a) after waiting for a minimum period of time to allow the refresh operation and the row precharge operation (conditionally) to be performed, and if a read or write is to be performed, the row activation command and address for the read or write are transmitted by the controller 110 to the memory device 120 on the CA and DQ interfaces; (3b) alternatively, if no read / write is to be performed during the current refresh interval, the controller 110 can proceed to step #1 at the end of the current refresh interval; (4) if a read or write is to be performed, then on the second edge of the ACK (e.g., transmitted by the controller 110), the row activation address for a different bank (i.e., different from the previously specified bank) is transferred to the memory core 125. Note that this second activation command can be executed in parallel with the memory device 120 being controlled to exit the power saving mode. One or more column operations (eg, read or write) associated with the second active command may be completed in high power mode using synchronization functionality of the CA and DQ interfaces.

[0050] Figure 2 is a timing diagram illustrating an example low-latency access. Figure 2 The steps and timings illustrated in FIG. 1 may be performed by at least one or more elements of the memory system 100. Figure 2 At the beginning of the timing diagram of , the memory device (e.g., memory device 120) has been controlled to operate in a power saving mode: the synchronous interface clocks (CK, DQS) are inactive and therefore not switching, the clock enable signal (CKE) is in an inactive state, the asynchronous timing signal (ACK) is in an inactive state, and the command address (CA), data (DQ), and chip select (CS) signals are in an unknown or "don't care" state.

[0051] The setup time before ACK is asserted, (e.g., by controller 110) the chip select signal is in an active state, the first activation row information (e.g., command opcode, bank / row address, partial command opcode, and / or partial address) (e.g., by controller 110) is provided to the CA interface, and the second activation row information (e.g., bank / row address, partial command opcode, and / or partial address) (e.g., by controller 110) is provided to the DQ interface. ACK is then converted (at time 253). This latches (samples) the first activation row information and the second activation row information and forwards the information to access the memory core (e.g., memory core 125). The memory core then activates the bank / row associated with the first activation row information and the second activation row information.

[0052] Note that in an embodiment, asynchronous timing signals may be received via the clock enable interface. Figure 2 271 on CKE. If the asynchronous timing signal can be received via the clock enable interface, the memory device may not include a dedicated ACK pin / pad / interface. In another embodiment, a mode or other control (e.g., a control register value) may specify whether the asynchronous timing signal is received via a dedicated ACK interface or whether the asynchronous timing signal is received via the clock enable interface.

[0053] exist Figure 2 1, concurrently with the memory device performing a specified row activation, the memory device is exited from power saving mode (e.g., by controller 110). Synchronous timing reference signal CK is activated and begins to periodically switch states at a certain frequency. After CK has stabilized, clock enable is asserted at time 254. This begins the process inside the memory device to exit power saving mode.

[0054] A specified interval (i.e., tXP) after the assertion of the clock enable signal (and while CK is running and stable), at time 255, the memory device has entered the high power mode. At time 256, which is a specified row-to-column delay (tXP) after the asynchronous activate row command is forwarded to the memory core, the memory device has entered the high power mode. RCD )), the first column access command is received synchronously via the CA interface (ie, synchronized by CK).

[0055] At time 257, which is the specified row-to-data delay (t RD )), data (Q0) begins to be synchronously received (i.e., synchronized by DQS) (for write) or sent (for read) via the DQ interface. At time 258 (which is the designated column access to column access (t CC )), the second column access command is synchronously received via the CA interface (i.e., synchronized by CK). In response to the second column access command, data (Q1) is to be synchronously received (i.e., synchronized by DQS) or sent via the DQ interface following the data corresponding to the first column access command. At time 259 (which is the designated column access to precharge delay (t RDP )), the precharge command is received synchronously via the CA interface (ie, synchronized by CK).

[0056] Figure 3 is a timing diagram illustrating an example deterministic asynchronous refresh followed by low latency access. Figure 3 The steps and timings illustrated in FIG. 1 may be performed by at least one or more elements of the memory system 100. Figure 3 At the beginning of the timing diagram of , the memory device (e.g., memory device 120) has been controlled to operate in a power saving mode: the synchronous interface clocks (CK, DQS) are inactive and therefore not switching periodically, the clock enable signal (CKE) is in an inactive state, the asynchronous timing signal (ACK) is in an inactive state, and the command address (CA), data (DQ), and chip select (CS) signals are in unknown or "don't care" states.

[0057] The setup time before ACK is first Figure 3 ACK is then asserted (at time 351). This latches (samples) the first and second activation row information and forwards the information to access the memory core (e.g., memory core 125). The memory core then activates the banks / rows associated with the first and second activation row information.

[0058] Note that in an embodiment, asynchronous timing signals may be received via the clock enable interface. Figure 3371 on CKE. If the asynchronous timing signal can be received via the clock enable interface, the memory device may not include a dedicated ACK pin / pad / interface. In another embodiment, a mode or other control (e.g., a control register value) may specify whether the asynchronous timing signal is received via a dedicated ACK interface or whether the asynchronous timing signal is received via the clock enable interface.

[0059] During the setup interval prior to time 353, the chip select signal is (held in) an active state (e.g., by the controller 110), third active row information (e.g., a second command opcode, a second bank / row address, a second partial command opcode, and / or a second partial address) (e.g., by the controller 110) is provided to the CA interface, and fourth active row information (e.g., a second command opcode, a second bank / row address, a second partial command opcode, and / or a second partial address) (e.g., by the controller 110) is provided to the DQ interface. ACK is then asserted (at time 353). Time 353 is at least the specified row operation to row operation delay (t ) after the first asynchronous active row command is forwarded to access the memory core. RR ), the second assertion of ACK latches (or alternatively, CKE is asserted 372) the third and fourth activation row information and forwards the information to the memory core (e.g., memory core 125). The memory core then activates the banks / rows associated with the third and fourth activation row information.

[0060] exist Figure 3 , concurrently with the memory device performing a second row activation, the memory device is exited from power saving mode (e.g., by controller 110). Synchronous timing reference signal CK is activated and begins to periodically switch states at a certain frequency. After CK has stabilized, clock enable is asserted at time 354. This begins the process inside the memory device to exit power saving mode.

[0061] A specified interval (i.e., t XP ), at time 355, the memory device has entered high power mode. At time 356 (which is the specified row-to-column delay (t) after the asynchronous activation row command is forwarded to access the memory core RCD )), the first column access command is received synchronously via the CA interface (ie, synchronized by CK).

[0062] At time 357, which is the specified row-to-data delay (t RD)), data (Q0) begins to be synchronously received (i.e., synchronized by DQS) (for write) or sent (for read) via the DQ interface. At time 358 (which is the designated column access to column access (t CC )), the second column access command is synchronously received via the CA interface (i.e., synchronized by CK). In response to the second column access command, data (Q1) is to be synchronously received (i.e., synchronized by DQS) or sent via the DQ interface after the data corresponding to the first column access command is received or sent, respectively.

[0063] Figure 4 is a timing diagram illustrating an example semi-deterministic asynchronous refresh followed by a low-latency access. Figure 4 The steps and timings illustrated in FIG. 1 may be performed by one or more elements of the memory system 100. Figure 4 At the beginning of the timing diagram of , the memory device (e.g., memory device 120) has been controlled to operate in a power saving mode: the synchronous interface clocks (CK, DQS) are inactive and therefore not switching, the clock enable signal (CKE) is in an inactive state, the asynchronous clocking signal (ACK) is in an inactive state, and the command address (CA), data (DQ), and chip select (CS) signals are in unknown or "don't care" states.

[0064] The setup time before ACK is first Figure 4 ACK is then asserted (at time 451). This latches (samples) the first self-refresh information and the second self-refresh information. If the credit / debit counter that received the ACK signal and the internal self-refresh timer signal indicates that a refresh should be performed, the memory device forwards the address from the refresh counter to the memory core (e.g., memory core 125). The memory core then refreshes the bank / row associated with the refresh counter. If the self-refresh timer signal does not indicate that a refresh should be performed, no refresh is performed during the current refresh interval.

[0065] Note that in an embodiment, asynchronous timing signals may be received via the clock enable interface. Figure 4 4 is shown by pulse 471 on CKE. If the asynchronous timing signal can be received via the clock enable interface, the memory device may not include a dedicated ACK pin / pad / interface. In another embodiment, a mode or other control (e.g., a control register value) may specify whether the asynchronous timing signal is received via a dedicated ACK interface or whether the asynchronous timing signal is received via the clock enable interface.

[0066] During the setup interval prior to time 453, the chip select signal is (held) in an active state (e.g., by the controller 110), third active row information (e.g., a second command opcode) is provided to the CA interface (e.g., by the controller 110), and fourth active row information (e.g., a second bank / row address) is provided to the DQ interface (e.g., by the controller 110). ACK is then asserted a second time at time 453 (or alternatively, CKE is asserted 472). Time 453 is at least the specified row operation plus the precharge operation delay (t 472) after the first ACK is received. RCD =t RAS +t PRE ). The second assertion of ACK latches (samples) the first activation row information (e.g., on the CA interface) and the second activation row information (e.g., on the DQ interface) and forwards the information to the memory core (e.g., memory core 125). The memory core then activates the banks / rows associated with the first activation row information and the second activation row information.

[0067] exist Figure 4 4, concurrently with the memory device performing a second row activation, the memory device is exited from power saving mode (e.g., by controller 110). Synchronous timing reference signal CK is activated and begins to periodically switch states at a certain frequency. After CK has stabilized, clock enable is asserted at time 454. This begins the process inside the memory device to exit power saving mode.

[0068] A specified interval (i.e., t XP ) elapses, at time 455, the memory device has entered high power mode. At time 456 (which is the specified row-to-column delay (t RCD )), the first column access command is received synchronously via the CA interface (ie, synchronized by CK).

[0069] At time 457, which is the specified row-to-data delay (t RD )), data (Q0) begins to be synchronously received (i.e., synchronized by DQS) (for write) or sent (for read) via the DQ interface. At time 458 (which is the designated column access to column access (t CC )), the second column access command is synchronously received via the CA interface (i.e., synchronized by CK). In response to the second column access command, data (Q1) is to be synchronously received (i.e., synchronized by DQS) or sent via the DQ interface after the data corresponding to the first column access command is received or sent, respectively.

[0070] It should be appreciated that by periodically asserting ACK using a self-refresh operation at, for example, a specified minimum refresh rate, a controller (eg, controller 110) may be configured not to assert ACK within t after the first ACK assertion. RCD =t RAS +t PRE The controller will then ensure that it can assert ACK at time 453 and bring the memory device out of power save mode without disturbance (e.g., unknown delay) caused by the occurrence of the internally timed self-refresh. In this way, the controller ensures the timing of the second assertion of ACK, the timing of when the activate row command should be output, and when the data on the DQ should be transferred (i.e., without disturbance / delay caused by the internally timed self-refresh).

[0071] Figure 5 is a block diagram illustrating a memory component. In an embodiment, the memory component 500 may correspond to Figure 1 The memory device 120 in FIG. 5 is a memory device 120 in FIG. The memory component 500 includes a first synchronous timing reference (CK) interface 521, a clock enable (CKE) interface 522, a clock enable latch / sampler 531, a synchronous chip select (CS) interface 523a, a synchronous command / address (CA) interface 524a, a synchronous data interface 526a, a second synchronous timing reference (DQS) interface 527, an asynchronous timing reference interface 525 (or alternatively 522), an asynchronous chip select (CS) interface 523b, an asynchronous command / address (CA) interface 524b, an asynchronous data interface 526b, a synchronous control 540, an asynchronous control 545, and a memory core 550. The asynchronous control 540 includes a command decoder 541, a refresh counter 542, and a self-refresh timer 543. The asynchronous control 545 includes a command decoder 546. The memory core 550 includes a row logic 551, a column logic 552, and a plurality of banks 554-555. Each library 554-555 includes rows 554a-555a.

[0072] The clock enable interface 522 is operatively coupled to the clock enable sampler 531. The clock enable interface 522 is optionally operatively coupled to the asynchronous command interface 524b and the asynchronous data interface 526b. The clock enable sampler 531 is operatively coupled to the synchronization control 540.

[0073] The synchronous timing reference interface 521 is operatively coupled to the synchronous clock enable sampler 531. The synchronous timing reference interface 521 is operatively coupled to the clock enable sampler 531 to synchronously receive (i.e., synchronize to CK) a transition of a clock enable signal (CKE) received at the clock enable interface 522 before passing the synchronized clock enable signal to the synchronization control 540.

[0074] The synchronous timing reference interface 521 is operatively coupled to the synchronous chip select interface 523a. The synchronous timing reference interface 521 is operatively coupled to the chip select interface 523a so as to synchronously receive (i.e., synchronize to CK) the chip select signal (CS) received at the chip select interface 523a before passing the synchronized chip select signal (CS) to the synchronization control 540.

[0075] The synchronous timing reference interface 521 is operatively coupled to the synchronous command / address interface 524a. The synchronous timing reference interface 521 is operatively coupled to the synchronous command / address interface 524a so as to synchronously receive (i.e., synchronize to CK) the command / address signal CA[5:0] received at the command / address interface 524a before passing the synchronized command / address signal CA[5:0] to the synchronous control 540.

[0076] The synchronous timing reference interface 527 is operatively coupled to the synchronous data interface 526a. The synchronous timing reference interface 527 is operatively coupled to the synchronous data interface 526a to synchronously receive or send (i.e., synchronized to DQS) the transfer of the data signal DQ[15:0] to / from the memory core 550 (specifically, and to / from the column logic 552). The synchronous data interface 526a is operatively coupled to the memory core 550 (specifically, and the column logic 522) to receive data read from the memory core 550 for transmission outside the memory device 500 and to provide data received by the memory device 500 to be written to the memory core 550.

[0077] The asynchronous timing reference interface 525 is operatively coupled to the asynchronous chip select interface 523b. The asynchronous timing reference interface 525 is operatively coupled to the chip select interface 523b so as to asynchronously sample (i.e., not synchronous to CK, but in response to a transition of ACK or optionally CKE) a chip select signal (CS) present at the chip select interface 523b before passing the sampled chip select signal (CS) to the asynchronous control 545.

[0078] The asynchronous timing reference interface 525 is operatively coupled to the asynchronous command / address interface 524b. The asynchronous timing reference interface 525 is operatively coupled to the asynchronous command / address interface 524b so as to asynchronously sample (i.e., not synchronous to CK, but in response to a transition of ACK or optionally CKE) the command / address signals CA[5:0] present at the command / address interface 524b before passing the sampled command / address signals CA[5:0] to the asynchronous control 545.

[0079] Asynchronous timing reference interface 525 is operatively coupled to asynchronous data interface 526 b to asynchronously sample command and / or address signals present at asynchronous data interface 526 b before passing the sampled signals to asynchronous control 545 .

[0080] The synchronous control 540 is operatively coupled to the row logic 551 of the memory core 550 via the synchronously initiated row control signal 571. The synchronous control 540 is operatively coupled to the column logic 552 of the memory core 550 via the synchronously initiated column control signal 573. The asynchronous control 545 is operatively coupled to the row logic 551 of the memory core 550 via the asynchronously initiated row control signal 572. The asynchronous control 545 may optionally be operatively coupled to at least one of the refresh counter 542 and the self-refresh counter 543.

[0081] In an embodiment, the synchronous timing reference (CK) interface 521 receives a first timing signal CK that determines synchronous sampling of CKE, CS, and CA signals. The synchronous timing reference (DQS) interface 527 receives a second timing signal DQS that determines synchronous sampling and / or transmission of DQ signals. The memory core 550 can be controlled by the synchronization control 540 (e.g., when in high power mode) to receive first command, first control, and first address information via first synchronous sampling of the CA link using CK.

[0082] The memory core 550 may also be controlled by the asynchronous control 545 (e.g., when in power saving mode) to receive a second command, a second control, and a second address information via asynchronous sampling of the CA link and the DQ link using ACK. The second command, the second control, and the second address information may convey activation of a row in a bank of the memory core. When the row in the bank is being activated, the memory device 500 may be controlled to exit the power saving mode and synchronously perform column operations (e.g., controlled by the synchronization control 540 and using CK and DQ to synchronize the column operations). See, e.g. Figure 2 and related discussions.

[0083] When in power saving mode, synchronization interfaces 523a, 524a and 526a can be placed in a low power state. The low power state may include shutting down the power supply of interfaces 523a, 524a and / or 526a. The low power state may include controlling interfaces 523a, 524a and / or 526a not to sample the links connected to them. In addition, when in power saving mode, CK may be inactivated (i.e., controlled not to trigger and remain in a stable logic state).

[0084] As discussed herein, in an embodiment, the CKE signal may be used to control entry into and / or exit from a power saving mode. Exit from a power saving mode may be initiated by first activating CK and then synchronous (to CK) sampling of the CKE signal by latch 531. CKE may also be used to receive an ACK signal that initiates asynchronous sampling of the CA link and the DQ link.

[0085] In an embodiment, interfaces 523a, 523b, 524a, 525b may be collectively considered as a first interface that receives commands, addresses, and control signals synchronously with respect to a received CK signal when the memory device 500 is in high power mode. Similarly, interfaces 526a and 526b may be collectively considered as a second interface that transfers data bidirectionally synchronously with respect to a received DQS signal when the memory device 500 is in high power mode. However, when the memory device 500 is in power saving mode, the first interface and the second interface receive commands, addresses, and control signals together in response to at least one transition on ACK (or when so enabled, CKE).

[0086] The memory core 550 can be controlled to activate the first row in response to commands, addresses, and control signals received synchronously with respect to CK via the first interface when the memory device 500 is in high power mode (e.g., by the synchronous control 540). The memory core 550 can be controlled to activate the second row in response to commands, addresses, and control signals sampled via ACK on the first interface and the second interface when the memory device 500 is in power saving mode (e.g., by the asynchronous control 545). After activating the second row, the memory device 500 can be controlled to exit the power saving mode so that the second interface can transfer read / write data synchronously with respect to DQS. When in power saving mode, the first interface can receive a portion of the command, address, and control signals while the second interface receives the remaining portion of the command, address, and control signals. For example, the first interface can receive command and control signal information while the second interface can receive (at least some) address signals.

[0087] Figure 6 6 is a block diagram illustrating a memory component with asynchronously initiated column operations. In an embodiment, the memory component 600 may correspond to Figure 1The memory device 120 in the embodiment of the present invention. The memory component 600 includes a first synchronous timing reference (CK) interface 621, a clock enable (CKE) interface 622, a clock enable sampler 631, a synchronous chip select (CS) interface 623a, a synchronous command / address (CA) interface 624a, a synchronous data interface 626a, a second synchronous timing reference (DQS) interface 627, an asynchronous timing reference interface 625 (or alternatively 622), an asynchronous chip select (CS) interface 623b, an asynchronous command / address (CA) interface 624b, an asynchronous data interface 626b, a synchronous control 640, an asynchronous control 645, and a memory core 650. The asynchronous control 640 includes a command decoder 641, a refresh counter 642, and a self-refresh timer 643. The asynchronous control 645 includes a command decoder 646. The memory core 650 includes a row logic 651, a column logic 652, and a plurality of banks 654-655. Each library 654-655 includes rows 654a-655a.

[0088] The clock enable interface 622 is operatively coupled to a clock enable sampler 631. The clock enable interface 622 is optionally operatively coupled to an asynchronous command interface 624b and an asynchronous data interface 626b. The clock enable sampler 631 is operatively coupled to a synchronization control 640.

[0089] The synchronous timing reference interface 621 is operatively coupled to the synchronous clock enable sampler 631. The synchronous timing reference interface 621 is operatively coupled to the clock enable sampler 631 to synchronously receive (i.e., synchronize to CK) the transition of the clock enable signal (CKE) received at the clock enable interface 622 before passing the synchronized clock enable signal to the synchronization control 640.

[0090] The synchronous timing reference interface 621 is operatively coupled to the synchronous chip select interface 623a. The synchronous timing reference interface 621 is operatively coupled to the chip select interface 623a so as to synchronously receive (i.e., synchronize to CK) the chip select signal (CS) received at the chip select interface 623a before passing the synchronized chip select signal (CS) to the synchronization control 640.

[0091] The synchronous timing reference interface 621 is operatively coupled to the synchronous command / address interface 624a. The synchronous timing reference interface 621 is operatively coupled to the synchronous command / address interface 624a so as to synchronously receive (i.e., synchronize to CK) the command / address signal CA[5:0] received at the command / address interface 624a before passing the synchronized command / address signal CA[5:0] to the synchronous control 640.

[0092] The synchronous timing reference interface 627 is operatively coupled to the synchronous data interface 626a. The synchronous timing reference interface 627 is operatively coupled to the synchronous data interface 626a to synchronously receive or send (i.e., synchronized to DQS) the transfer of the data signal DQ[15:0] to / from the memory core 650 (specifically, and to / from the column logic 652). The synchronous data interface 626a is operatively coupled to the memory core 650 (specifically, and the column logic 622) to receive data read from the memory core 650 for transmission outside the memory device 600 and to provide data received by the memory device 600 to be written to the memory core 650.

[0093] The asynchronous timing reference interface 625 is operatively coupled to the asynchronous chip select interface 623b. The asynchronous timing reference interface 625 is operatively coupled to the chip select interface 623b to asynchronously sample (i.e., not synchronous to CK, but in response to a transition of ACK or optionally CKE) a chip select signal (CS) present at the chip select interface 623b before passing the sampled chip select signal (CS) to the asynchronous control 645.

[0094] The asynchronous timing reference interface 625 is operatively coupled to the asynchronous command / address interface 624b. The asynchronous timing reference interface 625 is operatively coupled to the asynchronous command / address interface 624b so as to asynchronously sample (i.e., not synchronous to CK, but in response to a transition of ACK or optionally CKE) the command / address signals CA[5:0] present at the command / address interface 624b before passing the sampled command / address signals CA[5:0] to the asynchronous control 645.

[0095] Asynchronous timing reference interface 625 is operatively coupled to asynchronous data interface 626 b to asynchronously sample command and / or address signals present at asynchronous data interface 626 b before passing the sampled signals to asynchronous control 645 .

[0096] The synchronous control 640 is operatively coupled to the row logic 651 of the memory core 650 via a synchronously initiated row control signal 671. The synchronous control 640 is operatively coupled to the column logic 652 of the memory core 650 via a synchronously initiated column control signal 673. The asynchronous control 645 is operatively coupled to the row logic 651 of the memory core 650 via an asynchronously initiated row control signal 672. The asynchronous control 645 is operatively coupled to the column logic 652 of the memory core 650 via an asynchronously initiated column control signal 674. The asynchronous control 645 may optionally be operatively coupled to at least one of the refresh counter 642 and the self-refresh counter 643.

[0097] From the foregoing, it should be appreciated that memory device 600 is similar to memory device 500, with the added functionality of allowing asynchronously initiated column operations to be performed (e.g., in power save mode, in response to an ACK and controlled by asynchronous control 645). Therefore, it should also be appreciated that, in an embodiment, memory device 600 can perform all of the functionality described herein with respect to memory device 100 and memory device 500.

[0098] In an embodiment, the synchronous control 640 and the asynchronous control 645 cooperate to operate the memory device 600 in at least a first mode (e.g., high power) and a second mode (e.g., power saving). The synchronous control 640 and the asynchronous control 645 also cooperate to operate the interfaces 623a, 623b, 624a, and 624b as command / address interfaces. Similarly, the synchronous control 640 and the asynchronous control 645 also cooperate to operate the interfaces 626a, 626b as data interfaces. The timing reference interface 621 receives a first timing reference signal CK, which, when active, operates periodically at a first frequency. The timing reference interface 627 receives a second timing reference signal DQS, which, when active, operates periodically at a second frequency. The first frequency and the second frequency can be the same frequency or different frequencies. The asynchronous timing reference interface 625 receives a timing signal ACK.

[0099] The memory core 650 receives first information provided to the command / address interface synchronously with CK based at least in part on the memory component 600 operating in the first mode (e.g., by the synchronization control 640). The first information includes address information sufficient to activate the first row 654a-655a of the first bank 654-655 of the memory core 650.

[0100] The memory core 650 also receives second information provided to the command / address interface and third information provided to the data interface asynchronously with both CK and DQS based at least in part on the memory component 600 operating in the second mode (e.g., by the asynchronous control 645). The second information is sampled from the command / address interface based at least in part on the ACK. The third information is sampled from the data interface based at least in part on the ACK. The second information and the third information include address information sufficient to activate the second row 654a-655a of the second bank 654-655 of the memory core 650.

[0101] In an embodiment, the receipt of the second information and the third information by the memory core 650 initiates a self-timed activation of the second rows 654a-655a of the second bank 654-655 of the memory core 650. Based on the memory component 600 being operated in the first mode, the signal interface is to be provided with a control signal CKE, which enables the command / address interface to receive command / address information synchronously with respect to the first timing reference signal and enables the data interface to communicate data synchronously with respect to the second timing reference signal. As also discussed herein, the column operation can be received and / or performed after the memory device 600 has exited the power saving mode. Therefore, during the self-timed activation, the second asynchronous timing reference signal DQS can be activated and the data interface can be enabled to communicate data synchronously with respect to DQS.

[0102] Figure 7 is a flow chart illustrating a method of operating a memory device. Figure 7 The steps illustrated in the figure may be performed by one or more elements of the memory system 100, the memory device 500 and / or the memory device 600. A first timing signal that determines sampling of a first group of links is received (702). For example, the timing reference interface 521 may receive a timing signal CK that controls synchronous sampling of CA signals from a controller (e.g., the controller 110).

[0103] A second timing signal that determines synchronous sampling of a second set of links is received (704).For example, the timing reference interface 527 may receive a timing signal DQS that controls synchronous sampling of DQ signals from a controller (eg, controller 110).

[0104] Based on the first mode, the memory core receives the first command, the first control, and the first address information (706) via synchronous sampling of the first group of links using the first timing signal. For example, the memory core 550 can receive the command, control, and address information from the synchronous control 540. The synchronous control 540 may have received the command, control, and address information via synchronous sampling of the CA signal using CK (e.g., by interfaces 523a and 524a). Based on the second mode, the memory core receives the second command, the second control, and the second address information via asynchronous sampling of the first group of links and the second group of links using the third timing signal. For example, the memory core 550 can receive the command, control, and address information from the asynchronous control 545. The asynchronous control 545 may have received the command, control, and address information via asynchronous sampling of the CA signal using ACK (e.g., by interfaces 523b and 524b) and asynchronous sampling of the DQ signal using ACK (e.g., by interface 526b).

[0105] Figure 8 is a flow chart illustrating a method of operating a memory device in at least two modes. Figure 8 The steps illustrated in the figure may be performed by one or more elements of the memory system 100, the memory device 500 and / or the memory device 600. In a first mode, command, address and control signals are received synchronously with respect to a first externally received timing reference (802). For example, the memory device 120 may receive CKE, CS, CA signals sent by the controller 110 synchronously with respect to a CK signal sent by the controller 110.

[0106] In the first mode, data is bidirectionally communicated synchronously with respect to a second externally provided timing reference (804). For example, the memory device 120 may receive a DQ signal sent by the controller 110 synchronously with respect to a DQS signal sent by the controller 110, or may send a DQ signal to the controller 110 synchronously with respect to a DQS signal sent by the controller 110.

[0107] In the second mode, command, address, and control signals are received in response to at least one transition of a third externally received timing reference (806). For example, the memory device 120 may receive command, address, and control signals in response to a transition of an ACK signal sent by the controller 110. These command, address, and control signals may be received via the CKE, CS, CA, and DQ signal interfaces to the memory device 120.

[0108] In the first mode, the memory core is controlled to activate the first row in response to command addresses and control signals received synchronously with respect to the first timing reference (808). For example, the mode #1 control 121 can respond to command, address, and control signals received synchronously on the CA signal interface by activating the corresponding first row in the memory core 125.

[0109] In the second mode, the memory core is controlled to activate the second row in response to the command, address, and control signals received in response to at least one transition of the third timing reference (810). For example, the mode #2 control 122 can respond to the command, address, and control signals received in response to the transition on the ACK signal sent by the controller 110 by activating the corresponding second row in the memory core 125.

[0110] Fig. 9 is a flow chart illustrating a method of operating a memory device. Fig. 9The steps illustrated in can be performed by one or more elements of the memory system 100, the memory device 500, and / or the memory device 600. A first timing reference signal is received that operates periodically at a first frequency when active (902). For example, the memory device 500 can receive a clock signal CK at an interface 521 that operates periodically at a first frequency when active. A second timing reference signal is received that operates periodically at a second frequency when active (904). For example, the memory device 500 can receive a clock signal DQS at an interface 527 that operates periodically at a second frequency when active. A timing signal is received (906). For example, the memory device 500 can receive a timing signal from the controller 110 at an interface 522 (or, if so configured, an interface 525).

[0111] Based on operating in the first mode, first information is received at the memory core and provided to the command / address interface synchronously with the first timing reference signal. The information includes address information sufficient to activate a first row of a first bank of the memory core (908). For example, based on operating in the high power synchronous mode, the memory core 550 can receive command, control, and address information specifying a row activation command and a row address from the synchronization control 540, wherein the information is provided to the CKE, CS, and CA signal interfaces synchronously with respect to the CK signal.

[0112] A second information provided to the command / address interface is sampled asynchronously based at least in part on the timing signal relative to the first timing reference signal and the second timing reference signal (910). For example, the command, control, or address information is sampled asynchronously from the CKE, CS, or CA signal interface with the CK and DQS signals based at least in part on an edge on the ACK signal. A third information provided to the data interface is sampled asynchronously based at least in part on the timing signal relative to the first timing reference signal and the second timing reference signal (912). For example, the command, control, or address information is sampled asynchronously from the DQ signal interface with the CK and DQS signals based at least in part on transitions of the ACK signal.

[0113] Based on operating in the second mode, second information and third information are received at the memory core. The second information and third information collectively include address information sufficient to activate a second row of a second bank of the memory core (914). For example, based on operating in the save asynchronous mode, the memory core 550 can receive command, control, and address information specifying a row activation command and a row address from the asynchronous control 545, where the information is provided to the CA and DQ signal interfaces asynchronously with respect to the CK signal and the DQS signal.

[0114] Fig.10 is a flow chart illustrating a method of operating a memory controller. Fig.10The steps illustrated in the figure may be performed by one or more elements of the memory system 100. A first timing signal that determines synchronous sampling of a first set of links by a memory component is sent to a memory component (1002). For example, the controller 110 may send a timing reference signal CK that is used by the memory device 120 to sample the CKE, CS, and CA interfaces of the memory device 120.

[0115] A second timing signal that determines synchronous sampling of the second set of links by the memory component is sent to the memory component (1004). For example, the controller 110 may send a timing reference signal DQS used by the memory device 120 to sample a DQ interface of the memory device 120.

[0116] The memory component operates in a first mode, wherein the memory component sends first command, first control, and first address information received by the memory component via synchronous sampling of a first set of links using a first timing signal to a memory core (1006) based on operating in the first mode. For example, the controller 110 (specifically, and the mode #1 control circuit 111) can operate the memory device 120 in a high-power synchronous mode, wherein the CKE, CS, and CA signals are synchronously sampled by the memory device 120 relative to the CK. In the high-power synchronous mode, the controller 110 can send the first command, first control, and first address information to the memory device 120 via the CA signal.

[0117] The third timing signal is sent to the memory component (1008). For example, the controller 110 can send a timing transition to the CKE interface via the ACK interface or when appropriately configured. The memory component operates in a second mode, wherein the memory component sends a second command, a second control, and a second address information received by the memory component via asynchronous sampling of the first group of links and the second group of links using the third timing signal to the memory core (1010) based on operating in the second mode. For example, the controller 110 (specifically, and the mode #2 control circuit 112) can operate the memory device 120 in a power saving asynchronous mode, wherein the CKE, CS, and CA signals are sampled by the memory device 120 in response to the ACK but asynchronously with respect to the CK and DQS. In this power saving mode, the controller 110 can use at least some of the CA signal and the DQ signal to send the second command, the second control, and the second address information to the memory device 120.

[0118] Fig.11 is a flow chart illustrating a method of operating a memory controller to control a memory device having at least two modes. Fig.11The steps illustrated in the figure may be performed by one or more elements of at least the memory system 100. To cause the memory component to operate in the first mode, a first timing reference and a second timing reference are sent 1102. For example, the controller 110 may send a periodic CK timing reference signal and a periodic DQS timing reference signal to the memory device 120 when the memory device is in the first mode.

[0119] To operate the memory component in the first mode, command, address, and control signals are sent synchronously with respect to the first timing reference to control the memory core to activate the first row in response 1104. For example, the controller 110 may send a CA signal synchronously with the CK signal to control the memory device 120 to activate the corresponding row in response.

[0120] With the memory component operating in the first mode, data is communicated bidirectionally and synchronously relative to a second timing reference (1106). For example, the controller 110 may receive read data (in response to a read command) or send write data (based on a send write operation) to the memory device 120 via a DQ signal interface synchronously relative to a DQS signal.

[0121] When the memory component operates in the second mode, command, address, and control signals are sent to the memory component asynchronously with respect to the first timing reference to control the memory core to activate the first row in response 1108. For example, when the memory device 120 operates in the low power asynchronous mode, the controller 110 may send command, address, and control signals asynchronously with respect to the CK signal.

[0122] When the memory component is operating in the second mode, at least one transition of the third timing reference signal is sent to the memory component to cause command, address, and control signals to be received by the memory component asynchronously with respect to the first timing reference and the second timing reference. The command, address, and control signals to be received by the memory component include information sufficient to activate the second row in response (1110). For example, when the memory device 120 is operating in the low power asynchronous mode, the controller 110 may send a signal transition on ACK (or CKE, if so configured) to cause the memory device 120 to asynchronously sample at least CA and DQ (or a subset thereof).

[0123] Fig.12 is a flow chart illustrating a method of operating a memory controller to control a memory device having at least two modes. Fig.12The steps illustrated in 1204 may be performed by one or more elements of the memory system 100. A first timing reference signal is received that, when active, periodically operates at a first frequency (1202). For example, the controller 110 may send a periodic timing reference signal CK to the memory device 110. A second timing reference signal is received that, when active, periodically operates at a second frequency (1204). For example, the controller 110 may send a periodic timing reference signal DQS to the memory device 110.

[0124] Based on operating the memory component in the first mode, first information is sent to the command / address interface synchronously with respect to the first timing reference signal, wherein the information is then sent to the memory core of the memory component. The information includes address information sufficient to activate the first row of the first bank of the memory core (1208). For example, the controller 110 can send the command, address, and control information to the memory device 120 synchronously with respect to the timing reference signal CK.

[0125] Based on operating the memory component in the second mode, a timing signal is sent to cause the memory component to asynchronously sample the second information provided to the command / address interface and the third information provided to the data interface relative to the first timing reference signal and the second timing reference signal. The second information and the third information collectively include address information (1210) sufficient to activate the second row of the second bank of the memory core. For example, the controller 110 can send commands, addresses, and control information to the memory device 120 asynchronously relative to the timing reference signal CK and the timing reference signal DQS via CA and DQ. The controller 110 can asynchronously send a transition on the ACK interface relative to the timing reference signal CK and the timing reference signal DQS, wherein the transition on the ACK causes the memory device 120 to sample the commands, addresses, and control information of the memory device 120 provided to the CA and DQ interfaces.

[0126] Fig.13 is a block diagram of a memory device. Specifically, Fig.13 The memory device 1300 in FIG. 1 may be considered as a more detailed example of at least the memory device 500 and / or the memory device 100 . Fig.14 is a block diagram of a memory device. Specifically, Fig.14 The memory device 1400 in FIG. 1 may be considered a more detailed example of at least the memory device 600 and / or the memory device 100 .

[0127] Fig.15 1 is a schematic diagram of a self-refreshing credit / debit counter. Specifically, the credit / debit counter 1500 can be considered as the example credit / debit counter cited in this article. After reset, it should be understood that Fig.15 Both 3-bit counters shown in FIG. 1 are cleared to a logic value of zero.

[0128] The methods, systems and devices described above can be implemented in a computer system or stored by a computer system. The methods described above can also be stored on a non-transient computer-readable medium. The devices, circuits and systems described herein can be implemented using computer-aided design tools available in the art and embodied by computer-readable files containing software descriptions of such circuits. This includes but is not limited to one or more elements of system 100, controller 110, memory device 100, memory device 500, memory device 600, memory device 1300, memory device 1400, counter 1500 and parts thereof. These software descriptions can be: behavior, register transfer, logic unit, transistor and layout geometry level description. In addition, the software description can be stored on a storage medium or communicated by a carrier wave.

[0129] Data formats that may implement such descriptions include, but are not limited to, formats that support behavioral languages ​​like C, formats that support register transfer level (RTL) languages ​​like Verilog and VHDL, formats that support geometric description languages ​​such as GDSII, GDSIII, GDSIV, CIF, and MEBES, and other suitable formats and languages. In addition, data transfer of such files on machine-readable media may be accomplished electronically through various media on the Internet or, for example, via email. Note that the physical file may be implemented on a machine-readable medium such as a 4 mm tape, an 8 mm tape, a 3-1 / 2 inch floppy disk media, a CD, a DVD, and the like.

[0130] Fig.16 16 is a block diagram illustrating one embodiment of a processing system 1600 for including, processing, or generating representations of circuit components 1620. The processing system 1600 includes one or more processors 1602, memory 1604, and one or more communication devices 1606. The processor 1602, memory 1604, and communication devices 1606 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1608.

[0131] Processor 1602 executes instructions of one or more processes 1612 stored in memory 1604 to process and / or generate circuit components 1620 in response to user input 1614 and parameters 1616. Process 1612 can be any suitable electronic design automation (EDA) tool or portion thereof for designing, simulating, analyzing and / or verifying electronic circuits and / or generating photomasks for electronic circuits. As shown in the figure, representation 1620 includes data describing all or part of system 100, controller 110, memory device 100, memory device 500, memory device 600, memory device 1300, memory device 1400, counter 1500, and components thereof.

[0132] The representation 1620 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry level descriptions. In addition, the representation 1620 may be stored on a storage medium or communicated by a carrier wave.

[0133] Data formats in which representation 1620 may be implemented include, but are not limited to, formats supporting behavioral languages ​​like C, formats supporting register transfer level (RTL) languages ​​like Verilog and VHDL, formats supporting geometry description languages ​​such as GDSII, GDSIII, GDSIV, CIF, and MEBES, and other suitable formats and languages. Additionally, data transfer of such files on machine-readable media may be accomplished electronically through various media over the Internet or, for example, via email.

[0134] User input 1614 may include input parameters from a keyboard, mouse, voice recognition interface, microphone and speaker, graphic display, touch screen, or other type of user interface device. The user interface may be distributed among multiple interface devices. Parameters 1616 may include input to help define the specifications and / or characteristics of representation 1620. For example, parameters 1616 may include information defining device type (e.g., NFET, PFET, etc.), topology (e.g., block diagram, circuit description, schematic, etc.), and / or device description (e.g., device attributes, device size, supply voltage, simulation temperature, simulation model, etc.).

[0135] Memory 1604 comprises any suitable type, number, and / or configuration of non-transitory computer-readable storage media that stores processes 1612 , user inputs 1614 , parameters 1616 , and circuit components 1620 .

[0136] The communication device 1606 includes any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from the processing system 1600 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, the communication device 1606 can transmit the circuit component 1620 to another system. The communication device 1606 can receive the process 1612, the user input 1614, the parameter 1616, and / or the circuit component 1620 and cause the process 1612, the user input 1614, the parameter 1616, and / or the circuit component 1620 to be stored in the memory 1604.

[0137] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the specific form disclosed, and other modifications and variations may be possible in view of the above teachings. The embodiments are selected and described in order to best explain the principles of the invention and its practical application, so as to enable others skilled in the art to best utilize the invention in various embodiments and various modifications as suitable for the specific use foreseen. It is intended that the appended claims be understood to include other alternative embodiments of the invention unless limited by the prior art.

Claims

1. A memory component, comprising: Memory core; a first timing signal interface for receiving a first timing signal, the first timing signal determining synchronous sampling of a signal at a first set of links; a second timing signal interface for receiving a second timing signal, the second timing signal determining synchronous sampling of signals at a second set of links; as well as, A memory core control circuit is used to access the memory core based at least in part on at least a first command, a first control, and a first address information received in a first mode in response to a first synchronous sampling of a signal at the first set of links using the first timing signal, and the memory core control circuit is also used to access the memory core based at least in part on a second command, a second control, and a second address information received in a second mode in response to a first asynchronous sampling of a signal at the first set of links and a signal at the second set of links using a third timing signal.

2. The memory component of claim 1, wherein the memory core control circuit is operative to activate a row in a bank of the memory core in response to the second command, the second control, and the second address information.

3. The memory component of claim 1, wherein in the first mode, information is to be communicated by the memory component bidirectionally synchronously via the second set of links using the second timing signals.

4. The memory component of claim 1, wherein in the second mode, information is to be communicated by the memory component bidirectionally synchronously via the second set of links using the second timing signals.

5. The memory component of claim 1 , wherein a first synchronous interface that synchronously samples the first set of links using the first timing signal when in the first mode and a second synchronous interface that synchronously communicates with the second set of links using the second timing signal when in the first mode are not synchronously sampled when in the second mode.

6. The memory component of claim 1 , wherein when in the second mode and when the first timing signal interface is receiving an inactivity signal, at least one transition of the third timing signal initiates the first asynchronous sampling of the first set of links to receive the second command, the second control, and the second address information.

7. The memory component of claim 1 , wherein a signal interface is to be used in the first mode to receive a power control signal and is to be used in the second mode to receive the third timing signal, at least one transition of the third timing signal being used to initiate the first asynchronous sampling of the first set of links to receive the second command, the second control, and the second address information.

8. The memory component of claim 6, wherein exit from the second mode to the first mode is to be initiated by activating a first timing reference.

9. The memory component of claim 6 , wherein the at least one transition of the third timing signal is to be detected based on sampling of the third timing signal using the first timing signal, the at least one detected transition of the third timing signal being used to initiate an exit from the second mode.

10. A memory component, comprising: a first interface for receiving command, address and control signals synchronously with respect to a first externally received timing reference in a first mode of the memory component; a second interface for bidirectionally communicating data synchronously with respect to a second externally received timing reference in said first mode of said memory component; the first interface and the second interface being operable to receive command, address, and control signals in response to at least one transition of a third externally received timing reference in a second mode of the memory component; as well as, control circuitry for sending to a memory core, at least in the first mode of the memory component, a first control signal for activating a first row in response to the command, the address, and the control signal received synchronously with respect to the first externally received timing reference, and for sending to the memory core, at least in the second mode of the memory component, a second control signal for activating a second row in response to the command, the address, and the control signal received in response to at least one transition of the third externally received timing reference.

11. The memory component of claim 10, wherein the second mode of the memory component is a lower power mode relative to the first mode.

12. The memory component of claim 10, wherein in the second mode of the memory component, the second interface is further configured to communicate data synchronously with respect to the second externally received timing reference.

13. The memory component of claim 10 , wherein in the second mode of the memory component, the control circuit is operable to receive portions of the command, the address, and the control signal via the first interface, and the control circuit is operable to receive the remaining portions of the command, the address, and the control signal via the second interface in response to at least one transition of the third externally received timing reference.

14. The memory component of claim 13, wherein the command, the address, and the remainder of the control signal comprise an address signal.

15. The memory component of claim 10, wherein in the first mode, when the first externally received timing reference is active, the command, the address, and the control signals are enabled to be received by an enable signal on a signal input.

16. The memory component of claim 15, wherein in the second mode, the at least one transition of the third externally received timing reference to be provided is received via the signal input when the first externally received timing reference is inactive.

17. A memory component comprising: control circuitry to operate the memory component in at least a first mode and a second mode; a first synchronous timing reference interface for receiving a first timing reference signal, the first timing reference signal when active being periodic at a first frequency; a second synchronous timing reference interface for receiving a second timing reference signal, the second timing reference signal when active being periodic at a second frequency; A signal interface for receiving a timing signal; a command / address interface for receiving, based at least in part on the memory component being operated in the first mode, first information provided to the command / address interface synchronously with the first timing reference signal, the first information including address information sufficient to activate a first row of a first bank of a memory core, the command / address interface also for receiving, based at least in part on the memory component being operated in the second mode, second information provided to the command / address interface asynchronously with the first timing reference signal and the second timing reference signal, the second information to be sampled from the command / address interface based at least in part on the timing signal; as well as, A data interface for receiving third information provided to the data interface asynchronously with the first timing reference signal and the second timing reference signal based at least in part on the memory component being operated in the second mode, the third information to be sampled from the data interface based at least in part on the timing signal, the second information and the third information collectively including address information sufficient to activate a second row of a second bank of the memory core.

18. The memory component of claim 17, wherein receipt of the second information and the third information is used to initiate a self-timed activation of the second row of the second bank of the memory core.

19. The memory component of claim 18, wherein based on the memory component being operated in the first mode, the signal interface receives a control signal that enables the command / address interface to receive command / address information synchronously with respect to the first timing reference signal and enables the data interface to communicate data synchronously with respect to the second timing reference signal.

20. The memory component of claim 19, wherein during the self-timed activation, the second synchronous timing reference interface is to be activated and the data interface is to be enabled to synchronously communicate data.

Images