Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package includes: a lower substrate; a connecting substrate coupled to the lower substrate, the connecting substrate having a lateral portion surrounding a cavity and a first conductive pattern on a top surface of the lateral portion; a lower semiconductor chip on the lower substrate, the lower semiconductor chip being located in the cavity of the connecting substrate, the lower semiconductor chip including a second conductive pattern on the top surface of the lower semiconductor chip; a bonding member connecting the first conductive pattern and the second conductive pattern to each other; and a top package on the first conductive pattern and the second conductive pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0066049, entitled “Semiconductor package and method of manufacturing the same,” filed on June 8, 2018 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor package and a method for manufacturing the same. Background Art

[0004] Semiconductor packaging is used to achieve integrated circuit chips that are qualified for use in electronic products. In one type of semiconductor packaging, the semiconductor chip is mounted on a printed circuit board, and the semiconductor chip is electrically connected to the printed circuit board using bonding wires or bumps. With the recent development of the electronics industry, semiconductor packaging has been variously developed to achieve the goals of small size, light weight and / or low manufacturing cost. In addition, many types of semiconductor packaging also include, for example, large-capacity storage devices. Summary of the invention

[0005] According to some example embodiments, a semiconductor package may include: a lower substrate; a connecting substrate coupled to the lower substrate, the connecting substrate having a lateral portion surrounding a cavity and a first conductive pattern on a top surface of the lateral portion; a lower semiconductor chip on the lower substrate, the lower semiconductor chip being located in the cavity of the connecting substrate, the lower semiconductor chip including a second conductive pattern on the top surface of the lower semiconductor chip; a joining member connecting the first conductive pattern and the second conductive pattern to each other; and a top package on the first conductive pattern and the second conductive pattern.

[0006] According to some example embodiments, a semiconductor package may include: a connection substrate including a cavity in the connection substrate and a first conductive pattern on a top surface of the connection substrate; a semiconductor chip located in the cavity and including a second conductive pattern, the semiconductor chip having an inactive surface on which the second conductive pattern is disposed and an active surface facing the inactive surface; and a bonding member electrically connecting the first conductive pattern and the second conductive pattern to each other. The semiconductor chip and the second conductive pattern may be electrically insulated from each other. The connection substrate may also include a via that penetrates the connection substrate and is connected to the first conductive pattern.

[0007] According to some example embodiments, a method for manufacturing a semiconductor package may include: providing a lower semiconductor chip, the lower semiconductor chip including a first conductive pattern on a non-active surface of the lower semiconductor chip; providing a connecting substrate, the connecting substrate including a cavity in the connecting substrate and a second conductive pattern on a top surface of the connecting substrate; disposing the lower semiconductor chip and the connecting substrate on the lower substrate to place the lower semiconductor chip in the cavity of the connecting substrate; bonding the first conductive pattern and the second conductive pattern to each other; providing a top package, the top package including a plurality of connecting terminals on a bottom surface of the top package; and mounting the top package on the lower semiconductor chip and the connecting substrate to couple the connecting terminals to the first conductive pattern and the second conductive pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 A cross-sectional view of a semiconductor package according to some example embodiments is illustrated.

[0010] Figure 2 A plan view of a first conductive pattern, a second conductive pattern, and a bonding member is shown.

[0011] Figures 3 to 5 A cross-sectional view of a semiconductor package according to some example embodiments is illustrated.

[0012] Figures 6 to 12 Cross-sectional views are shown of some stages in a method of manufacturing a semiconductor package according to some example embodiments.

[0013] Figures 13 to 15 Cross-sectional views are shown of some stages in a method of manufacturing a semiconductor package according to some example embodiments.

[0014] Figures 16 to 23 Cross-sectional views are shown of some stages in a method of manufacturing a semiconductor package according to some example embodiments. DETAILED DESCRIPTION

[0015] A semiconductor package according to example embodiments is described below with reference to the accompanying drawings. Figure 1 A cross-sectional view of a semiconductor package according to some example embodiments is illustrated.

[0016] refer to Figure 1 , a bottom package P100 may be provided. The bottom package P100 may include a lower substrate 100 , a connection substrate 200 , a lower semiconductor chip 300 , and a lower molding member 400 .

[0017] For example, the lower substrate 100 may be or may include a printed circuit board (PCB) having a signal pattern disposed on a top surface thereof. In another example, the lower substrate 100 may have an alternating structure of dielectric layers and wiring layers.

[0018] The external terminals 110 may be disposed below the lower substrate 100, for example, on the bottom surface of the lower substrate 100 facing away from the lower semiconductor chip 300. The external terminals 110 may include solder balls or solder bumps, and based on the type of the external terminals 110, the bottom package P100 may include one of a ball grid array (BGA) type, a fine ball grid array (FBGA) type, and a land grid array (LGA) type.

[0019] The connection substrate 200 may be disposed on the lower substrate 100. The connection substrate 200 may be mounted on the top surface of the lower substrate 100, for example, on a surface opposite to the bottom surface of the lower substrate 100. For example, the connection substrate 200 may be mounted on the lower substrate 100 by solder bumps or solder balls. The connection substrate 200 may be electrically connected to the external terminal 110 through the lower substrate 100. In the present specification, the phrase "electrically connected / coupled" may include "directly or indirectly electrically connected / coupled".

[0020] The connection substrate 200 may include an opening OP, ie, a cavity OP, penetrating the connection substrate 200. For example, the opening OP may be shaped like an open hole, such as a cavity, connecting the bottom surface 200b and the top surface 200a of the connection substrate 200 to each other. Figure 1 As shown, the opening OP may pass through the entire thickness of the connection substrate 200 , and thus a lateral portion of the connection substrate 200 may surround the opening OP, for example, to provide a space for accommodating a lower semiconductor chip 300 described in more detail below.

[0021] The connection substrate 200 may include a base layer 210 and a conductive member 220 in the base layer 210. For example, the base layer 210 may include silicon oxide. The conductive member 220 may occupy the outer side (for example, the peripheral side) of the connection substrate 200, and the opening OP may occupy the inner side (for example, the central side) of the connection substrate 200. For example, Figure 1 As shown, the opening OP may pass through the entire thickness of the base layer 210, and the conductive member 220 may be located in and on the surface of a portion of the base layer 210 surrounding the opening OP (e.g., a lateral portion of the base layer 210 surrounding the opening OP). For example, the base layer 210 of the connection substrate 200 may surround the entire periphery of the opening OP ( Figure 2 ). The conductive member 220 may include a connection substrate pad 222 , a connection substrate via 224 , and a first conductive pattern 226 .

[0022] The connection substrate pad 222 may be disposed at a lower portion of the connection substrate 200, for example, on the bottom surface 200b of the connection substrate 200. The connection substrate 200 may be electrically connected to the lower substrate 100 via a solder ball or solder bump disposed on the connection substrate pad 222. The connection substrate via 224 may penetrate the base layer 210 and have an electrical connection with the connection substrate pad 222. The first conductive pattern 226 may be disposed at an upper portion of the connection substrate 200, for example, on the top surface 200a of the connection substrate 200. The first conductive pattern 226 may include a first pad CP1 on which the following top package P200 is mounted, a second pad CP2 coupled to the connection substrate via 224, a first wire EL1, and a first bonding pad BP1. The first wire EL1, the first pad CP1, the second pad CP2, and the first bonding pad BP1 may constitute a circuit. As Figure 1 As shown, the top package P200 may also be mounted on the second pad CP2. For example, the bottom package P100 may be configured such that the first pad CP1 has the same function as the second pad CP2. However, example embodiments of the present disclosure are not limited thereto.

[0023] The lower semiconductor chip 300 may be disposed on the lower substrate 100. Figure 1 As shown, the lower semiconductor chip 300 may be located in the opening OP of the connection substrate 200 (e.g., within the opening OP). When viewed in a plan view, the lower semiconductor chip 300 may have a planar shape that is smaller than the planar shape of the opening OP. For example, the lower semiconductor chip 300 may be spaced apart from the inner sidewall of the opening OP, for example, the connection substrate 200 may surround the periphery of the lower semiconductor chip 300 ( Figure 2 ).

[0024] The lower semiconductor chip 300 may have a bottom surface 300b facing the lower substrate 100 and a top surface 300a opposite to the bottom surface 300b. The bottom surface 300b of the lower semiconductor chip 300 may be an active surface, and the top surface 300a of the lower semiconductor chip 300 may be an inactive surface. The lower semiconductor chip 300 may be mounted on the top surface of the lower substrate 100. For example, the lower semiconductor chip 300 may be flip-chip bonded to the lower substrate 100. The lower semiconductor chip 300 may have a first circuit EC1, which is electrically connected to the lower substrate 100 by a lower chip terminal 310 (e.g., a solder ball or a solder bump) disposed on the lower chip pad 305. The flux 340 may fill the space between the lower semiconductor chip 300 and the lower substrate 100. The lower semiconductor chip 300 may be, for example, a logic chip or a memory chip. The logic chip may include a logic portion and a memory portion. The memory chip may be or may include, for example, one or more of a dynamic random access memory (DRAM), a NAND flash memory, a NOR flash memory, a phase change random access memory (PRAM), a resistance random access memory (ReRAM), and a magnetoresistive random access memory (MRAM). The lower semiconductor chip 300 may be electrically connected to the external terminal 110. Figure 1 Only one lower semiconductor chip 300 is shown, but the lower semiconductor chip 300 may be provided in plural.

[0025] The lower semiconductor chip 300 may include a second conductive pattern 320 on a top surface 300a as a non-active surface of the lower semiconductor chip 300. The top surface 300a of the lower semiconductor chip 300 may be located at the same height as the top surface 200a of the connection substrate 200, for example, the top surfaces 300a and 200a may be coplanar. The second conductive pattern 320 may include a third pad CP3, a second wire EL2, and a second bonding pad BP2 on which the top package P200 is mounted. The second wire EL2 may redistribute the electrical connection between the third pad CP3 and the second bonding pad BP2. The second conductive pattern 320 may not be directly electrically connected to the lower semiconductor chip 300, for example, the lower semiconductor chip 300 and the second conductive pattern 320 may be electrically insulated from each other via the non-active top surface 300a.

[0026] For example, the lower semiconductor chip 300 may include a chip via 330 passing therethrough. The chip via 330 may extend from the top surface 300a of the lower semiconductor chip 300 toward the bottom surface 300b. The chip via 330 may be coupled to one of the third pads CP3. The chip via 330 may also be coupled to the lower substrate 100. In this case, the chip via 330 may electrically connect the second conductive pattern 320 to the lower substrate 100. In this configuration, the chip via 330 may not be coupled to the first circuit EC1 of the lower semiconductor chip 300, or may be electrically insulated from the first circuit EC1 of the lower semiconductor chip 300, for example, the first circuit EC1 of the lower semiconductor chip 300 and the chip via 330 may extend through opposite ends of the lower semiconductor chip 300. In another example, Figure 1 Differently, the lower semiconductor chip 300 may not include the chip via 330 .

[0027] A bonding member BM may be provided. The bonding member BM may electrically connect the first bonding pad BP1 on the connection substrate 200 and the second bonding pad BP2 on the lower semiconductor chip 300 to each other. In some example embodiments, the bonding member BM may be or may include a bonding wire. The second electric wire EL2 and the third pad CP3 may be electrically connected to the connection substrate 200 and the lower substrate 100 through the first bonding pad BP1 and the second bonding pad BP2 and the bonding member BM.

[0028] Figure 2 It is used to illustrate Figure 1 FIG. 2 is a plan view of the first conductive pattern 226, the second conductive pattern 320, and the bonding member BM, wherein the lower semiconductor chip 300 and the connection substrate 200 are partially shown. Figure 2 , the first pad CP1, the second pad CP2 and the first bonding pad BP1 of the connection substrate 200 may be electrically connected to each other through the first wire EL1. The third pad CP3 and the second bonding pad BP2 of the lower semiconductor chip 300 may be electrically connected to each other through the second wire EL2. The first bonding pad BP1 and the second bonding pad BP2 may be electrically connected to each other through the bonding member BM. For ease of description, Figure 2 The arrangement of the pads CP1, CP2, and CP3 and the bonding pads BP1 and BP2 is arbitrarily shown, but the present disclosure is not limited thereto. For example, an additional second pad CP2 may be located at Figure 2 The right side is adjacent to the first pad CP1 and connected to the first pad CP1 through the first wire EL1 (eg Figure 1 shown).

[0029] Reference again Figure 1, the lower molding member 400 may be disposed on the lower substrate 100. The lower molding member 400 may fill the space between the connection substrate 200 and the lower semiconductor chip 300. The lower molding member 400 may cover the top surface 300a of the lower semiconductor chip 300 and the top surface 200a of the connection substrate 200. The lower molding member 400 may cover the first electric wire EL1, the second electric wire EL2, the first bonding pad BP1, the second bonding pad BP2, and the bonding member BM. The lower molding member 400 may have a first recess RS1 therein, and the first recess RS1 exposes the first pad CP1 and the second pad CP2 of the connection substrate 200 and the third pad CP3 of the lower semiconductor chip 300. The lower molding member 400 may include a polymer material, such as an Ajinomoto build-up film Epoxy polymer or thermosetting resin.

[0030] In some example embodiments, the lower molding member 400 may expose the top surface 300 a of the lower semiconductor chip 300 . Figure 3 1A and 1B illustrate cross-sectional views showing semiconductor packages according to some example embodiments. Figure 3 As shown, the lower molding member 400 may expose the second electric wires EL2 and the third pads CP3 on the top surface 300a of the lower semiconductor chip 300. In this case, the lower molding member 400 may bury the bonding member BM and the second bonding pads BP2 of the lower semiconductor chip 300.

[0031] Reference again Figure 1 , a top package P200 may be disposed on the bottom package P100. The top package P200 may include an upper substrate 500, an upper semiconductor chip 600, an upper molding member 700, and a connection terminal 510.

[0032] For example, the upper substrate 500 may be or may include a printed circuit board (PCB) having a signal pattern disposed on its top surface. In another example, the upper substrate 500 may have an alternating structure of dielectric layers and wiring layers. The width of the upper substrate 500 may be greater than the width W1 of the lower semiconductor chip 300, such as Figure 1 The width of the upper substrate 500 may be the same as or smaller than the width of the lower substrate 100, but example embodiments are not limited thereto. The width of the top package P200 (which may be the same as the width of the upper substrate 500) may be the same as the width of the connection substrate 200 (which may be the same as the width of the lower substrate 100).

[0033] The upper semiconductor chip 600 may be disposed on the upper substrate 500. The width W2 of the upper semiconductor chip 600 may be greater than the width W1 of the lower semiconductor chip 300. When viewed in a plan view, the upper semiconductor chip 600 may overlap with the lower semiconductor chip 300 and also overlap with a portion of the connection substrate 200, for example, the upper semiconductor chip 600 may completely overlap with the lower semiconductor chip 300 and the lower molding member 400 in the opening OP around the lower semiconductor chip 300. The upper semiconductor chip 600 may have a bottom surface 600b facing the upper substrate 500 and a top surface 600a opposite to the bottom surface 600b. The top surface 600a of the upper semiconductor chip 600 may be an active surface. The upper semiconductor chip 600 may be mounted on the top surface of the upper substrate 500. For example, the upper semiconductor chip 600 may be wire bonded to the upper substrate 500. The upper semiconductor chip 600 may be electrically connected to the upper substrate 500 by, for example, one or more bonding wires 610. The upper semiconductor chip 600 may be, for example, a logic chip or a memory chip. A logic chip may include a logic portion and a memory portion.

[0034] The upper molding member 700 may be disposed on the upper substrate 500. The upper molding member 700 may cover the top surface of the upper substrate 500 and the top surface 600a of the upper semiconductor chip 600. The upper molding member 700 may include a polymer material such as an Ajinomoto build-up film. Epoxy polymer or thermosetting resin.

[0035] The connection terminal 510 may be disposed below the upper substrate 500. The connection terminal 510 may include a solder ball or a solder bump, and the top package P200 may include one of a ball grid array (BGA) type, a fine ball grid array (FBGA) type, and a land grid array (LGA) type based on the type of the connection terminal 510. The upper semiconductor chip 600 may be electrically connected to the connection terminal 510.

[0036] The connection terminal 510 may include a first connection terminal 512 and a second connection terminal 514. The first connection terminal 512 may be provided on the connection substrate 200. The first connection terminal 512 may be coupled to the first pad CP1 of the connection substrate 200. The second connection terminal 514 may be provided on the lower semiconductor chip 300. The second connection terminal 514 may be coupled to the third pad CP3 of the lower semiconductor chip 300. The upper semiconductor chip 600 may be electrically connected to the first connection terminal 512 and the second connection terminal 514 through the upper substrate 500. The upper semiconductor chip 600 may include a second circuit EC2, which is electrically connected to the external terminal 110 through the second connection terminal 514, the second conductive pattern 320, the bonding member BM, and the first conductive pattern 226, and the upper semiconductor chip 600 may also include a third circuit EC2, and the third circuit EC3 is electrically connected to the external terminal 110 through the first connection terminal 512 and the first conductive pattern 226. The second circuit EC2 and the third circuit EC3 may be electrically disconnected from or electrically insulated from the first circuit EC1 of the lower semiconductor chip 300 . For example, the first connection terminal 512 may be electrically insulated from the lower semiconductor chip 300 .

[0037] Figure 4 and Figure 5 The diagram shows a cross-sectional view of a semiconductor package according to some example embodiments. Figure 4-5 In the previous reference Figure 1-3 The reference numerals in the description correspond to the descriptions of the elements.

[0038] refer to Figure 4 , a bonding member BM may be provided. The bonding member BM may electrically connect the first bonding pad BP1 and the second bonding pad BP2 to each other. In some example embodiments, the bonding member BM may be or may include a third conductive pattern 410. The third conductive pattern 410 may be disposed in the second recess RS2 of the lower mold member 400. The second recess RS2 may be located between the first bonding pad BP1 and the second bonding pad BP2. For example, in the second recess RS2 of the lower mold member 400, the third conductive pattern 410 may have a shape extending from the first bonding pad BP1 to the second bonding pad BP2.

[0039] refer to Figure 5, the bottom package P100 may be a fan-out panel level package (FO-PLP). For example, the lower substrate 100 may be a redistribution substrate, i.e., a redistribution layer. The lower substrate 100 may include, for example, a dielectric layer 102 and a conductive layer 104. The conductive layer 104 may include one or more vias penetrating the dielectric layer 102. For example, the dielectric layer 102 may include an inorganic insulating layer, such as a silicon oxide layer or a silicon nitride layer. In another example, the dielectric layer 102 may include a polymer material. The conductive layer 104 may be surrounded by or embedded in the dielectric layer 102. The conductive layer 104 may redistribute the electrical connection between the lower chip pad 305 of the lower semiconductor chip 300 and the external terminal 110 of the lower substrate 100. The bottom package P100 may have a fan-out structure through the lower substrate 100. The conductive layer 104 may include a metal. The conductive layer 104 may be connected to a substrate pad 106 disposed on the bottom surface of the lower substrate 100. The passivation layer 108 may be disposed on the bottom surface of the lower substrate 100. The passivation layer 108 may include an Ajinomoto deposition film. An organic material, an inorganic material, or an insulating polymer such as an epoxy polymer. The external terminal 110 may be disposed on the bottom surface of the lower substrate 100. The external terminal 110 may be disposed on the substrate pad 106. The external terminal 110 may be electrically connected to the conductive layer 104 through the substrate pad 106.

[0040] The lower substrate 100 may directly contact the bottom surface 200b of the connection substrate 200 and the bottom surface 300b of the lower semiconductor chip 300. For example, the lower substrate 100 may directly contact the lower chip pad 305 of the lower semiconductor chip 300 and the connection substrate pad 222 of the connection substrate 200.

[0041] In the semiconductor package according to some example embodiments, the conductive patterns 226 and 320 may be disposed on the top surface 200a of the connection substrate 200 and the top surface 300a of the lower semiconductor chip 300, and the top package P200 may be mounted on the conductive patterns 226 and 320. The connection terminals 510 of the top package P200 may all be disposed on the connection substrate 200 and the lower semiconductor chip 300. In this case, the connection terminals 510 may have an increased area for their positions, and as a result, the top package P200 may increase the number of output terminals (e.g., connection terminals 510) on the bottom package P100. The conductive patterns 226 and 320 may redistribute the circuits of the top package P200, which may result in an increase in the degree of freedom of wiring between the top package P200 and the bottom package P100. Therefore, the electrical characteristics of the semiconductor package may be improved.

[0042] In addition, redistribution between the bottom package P100 and the top package P200 may be performed without an additional substrate, and thus the thickness of the semiconductor package may be reduced. Even if a substrate for redistribution is not provided, the top package P200 may redistribute its electrical connections by using the conductive patterns 226 and 320 having a small thickness. Therefore, the semiconductor package may be advantageous in size reduction.

[0043] The reduction in the total thickness of the semiconductor package can allow the thickness of the lower semiconductor chip 300 to be increased, and therefore, the lower semiconductor chip 300 can have a heat dissipation advantage. In addition, the heat generated from the lower semiconductor chip 300 can be released through the conductive patterns 226 and 320. As a result, the semiconductor package can increase heat dissipation and operational stability.

[0044] Figures 6 to 12 Cross-sectional views are shown of some stages in a method of manufacturing a semiconductor package according to some example embodiments.

[0045] refer to Figure 6 , a lower semiconductor chip 300 may be provided. The lower semiconductor chip 300 may have a bottom surface 300b and a top surface 300a facing each other. The bottom surface 300b of the lower semiconductor chip 300 may be an active surface, and the top surface 300a of the lower semiconductor chip 300 may be an inactive surface. The lower semiconductor chip 300 may include a lower chip pad 305 disposed on its bottom surface 300b. The lower semiconductor chip 300 may include a chip via 330 passing therethrough. The chip via 330 may extend from the top surface 300a of the lower semiconductor chip 300 toward the bottom surface 300b. The lower chip terminal 310 may be attached to the lower chip pad 305.

[0046] refer to Figure 7 , the second conductive pattern 320 may be formed on the top surface 300a of the lower semiconductor chip 300. For example, a conductive layer may be formed on the top surface 300a of the lower semiconductor chip 300, and then the conductive layer may be patterned to form the second conductive pattern 320. In another example, a shadow mask may be formed on the top surface 300a of the lower semiconductor chip 300, and then a conductive material may be deposited in the pattern of the shadow mask, which may result in the formation of the second conductive pattern 320. The pattern of the shadow mask may partially expose the top surface 300a of the lower semiconductor chip 300, and may define an area where the second conductive pattern 320 is formed. After forming the second conductive pattern 320, the shadow mask may be removed. The second conductive pattern 320 may include a third pad CP3, a second electric wire EL2, and a second bonding pad BP2.

[0047] refer to Figure 8, the lower semiconductor chip 300 can be mounted on the lower substrate 100. The lower semiconductor chip 300 can be mounted in a flip-chip bonding manner. For example, a flux 340 can be applied on the bottom surface 300b as the non-active surface of the lower semiconductor chip 300, and then the lower semiconductor chip 300 can be positioned so that the lower chip terminal 310 on the bottom surface 300b faces the top surface of the lower substrate 100. At this stage, the flux 340 can protrude onto the lateral surface of the lower semiconductor chip 300. The flux 340 may include a resin, an activator, and a solvent. The solvent may include, for example, a glycol ether ester compound, a glycol ether compound, an ester compound, a ketone compound, or a cyclic ester compound. A reflow process may be performed on the lower chip terminal 310, so that the lower semiconductor chip 300 can be mounted on the lower substrate 100.

[0048] refer to Fig. 9 , a connection substrate 200 may be provided. The connection substrate 200 may include a base layer 210 and a conductive member 220 in the base layer 210. The conductive member 220 may include a connection substrate pad 222, a connection substrate via 224, and a first conductive pattern 226. The first conductive pattern 226 may include a first pad CP1, a second pad CP2, a first wire EL1, and a first bonding pad BP1. For example, the base layer 210 may be etched, and then a conductive material may be filled therein to form the connection substrate pad 222, the connection substrate via 224, and the first conductive pattern 226.

[0049] An opening OP (also referred to as a cavity) may be formed in the connection substrate 200. For example, a portion of the connection substrate 200 may be removed to form an opening OP that penetrates, for example, the entire thickness of the connection substrate 200, and for example, a portion of the base layer 210 may be removed to provide an opening OP, i.e., a cavity, for accommodating the lower semiconductor chip 300. The opening OP may be formed, for example, by an etching process such as drilling, laser ablation, or laser cutting.

[0050] The connection substrate 200 may be mounted on the lower substrate 100. At this stage, the connection substrate 200 may be arranged to place the lower semiconductor chip 300 in the opening OP, for example, so that a portion of the connection substrate 200 surrounds the lower semiconductor chip 300 in the opening OP. The solder balls or solder bumps on the connection substrate pads 222 may be reflowed to mount the connection substrate 200 on the lower substrate 100.

[0051] refer to Fig.10, a bonding member BM may be formed. For example, the first bonding pad BP1 of the connection substrate 200 and the second bonding pad BP2 of the lower semiconductor chip 300 may be connected to each other in a wire bonding manner. In some example embodiments, it may be desirable that the top surface 200a of the connection substrate 200 and the top surface 300a of the lower semiconductor chip 300 are at the same height, and this configuration may easily achieve wire bonding between the first bonding pad BP1 and the second bonding pad BP2.

[0052] refer to Fig.11 , a lower molding member 400 may be formed on the lower substrate 100. The lower molding member 400 may fill the space between the connection substrate 200 and the lower semiconductor chip 300. For example, an insulating substance may be injected into the space between the connection substrate 200 and the lower semiconductor chip 300, and then the insulating substance may be cured to form the lower molding member 400. The insulating substance may cover the first conductive pattern 226 of the connection substrate 200, the second conductive pattern 320 of the lower semiconductor chip 300, and the bonding member BM. The insulating substance may include an insulating polymer or a thermosetting resin.

[0053] For example, the lower molding member 400 may be etched to form a first recess RS1 exposing the first pad CP1, the second pad CP2, and the third pad CP3. In another example, the lower molding member 400 may be etched to further expose the top surface 300a of the lower semiconductor chip 300. For example, the lower molding member 400 may expose the first pad CP1, the second pad CP2, the third pad CP3, and the second electric wire EL2 located on the top surface 300a of the lower semiconductor chip 300. When the lower molding member 400 is formed to further expose the top surface 300a of the lower semiconductor chip 300, the lower molding member 400 may be manufactured. Figure 3 An example in which the lower molding member 400 selectively exposes the first pad CP1, the second pad CP2, and the third pad CP3 is described below.

[0054] refer to Fig.12 , an external terminal 110 may be formed on the bottom surface of the lower substrate 100. The external terminal 110 may include a solder ball or a solder bump. The external terminal 110 may be electrically connected to the first conductive pattern 226 and the second conductive pattern 320 through the lower substrate 100, the conductive member 220 of the connection substrate 200, and the bonding member BM. The bottom package P100 may be formed through the above process.

[0055] Reference again Figure 1, a top package P200 may be provided on the bottom package P100. The top package P200 may include an upper substrate 500, an upper semiconductor chip 600, an upper molding member 700, and a connection terminal 510. The upper substrate 500 may be or may include a printed circuit board (PCB) having a signal pattern provided on its top surface. The upper semiconductor chip 600 may be mounted on the upper substrate 500. The upper molding member 700 may cover the top surface of the upper substrate 500 and the top surface 600a of the upper semiconductor chip 600. The connection terminal 510 may be provided below the upper substrate 500. The connection terminal 510 may include a first connection terminal 512 and a second connection terminal 514. The second connection terminal 514 may be located further away from a position below the edge of the upper substrate 500 than the first connection terminal 512.

[0056] The bottom package P100 and the top package P200 may be aligned with each other to place the first connection terminal 512 on the first conductive pattern 226 and the second connection terminal 514 on the second conductive pattern 320. The first connection terminal 512 and the second connection terminal 514 may contact the first conductive pattern 226 and the second conductive pattern 320, respectively, and then reflow may be performed to mount the top package P200 on the bottom package P100. Through the above process, a Figure 1 semiconductor packaging.

[0057] Figures 13 to 15 Illustrated are cross-sectional views showing some stages in a method of manufacturing a semiconductor package according to some example embodiments.

[0058] refer to Fig.13 , can be found in reference Figures 1 to 9 A lower molding member 400 is formed on the manufactured structure. The lower molding member 400 may fill the space between the connection substrate 200 and the lower semiconductor chip 300. For example, an insulating substance may be injected into the space between the connection substrate 200 and the lower semiconductor chip 300, and then the insulating substance may be cured to form the lower molding member 400. The lower molding member 400 may cover the first conductive pattern 226 and the second conductive pattern 320.

[0059] refer to Fig.14 , the lower molding member 400 may be etched to form a first recess RS1 and a second recess RS2. The first recess RS1 may expose the first pad CP1, the second pad CP2, and the third pad CP3. When viewed in a plan view, the second recess RS2 may be formed between the connection substrate 200 and the lower semiconductor chip 300, or between the first bonding pad BP1 of the connection substrate 200 and the second bonding pad BP2 of the lower semiconductor chip 300. The second recess RS2 may expose the lateral surfaces of each of the first bonding pad BP1 and the second bonding pad BP2.

[0060] refer to Fig.15 , a third conductive pattern 410 may be formed in the second recess RS2. The third conductive pattern 410 may be formed by filling the second recess RS2 with a conductive material. For example, an electroplating process may be performed to fill the second recess RS2 with a conductive material. In another example, a printing process such as inkjet printing may be performed to fill the second recess RS2 with a conductive material. The bottom package P100 may be formed by the above process.

[0061] Afterwards, you can execute the reference Figure 1 For example, a top package P200 may be mounted on a bottom package P100 to manufacture Figure 4 semiconductor packaging.

[0062] Figures 16 to 23 Cross-sectional views are shown of some stages in a method of manufacturing a semiconductor package according to some example embodiments.

[0063] refer to Fig.16 , a connection substrate 200 may be provided. The connection substrate 200 may include a base layer 210 and a conductive member 220 in the base layer 210. The conductive member 220 may include a connection substrate pad 222, a connection substrate via 224, and a first conductive pattern 226. For example, the base layer 210 may be etched, and then the etched portion may be filled with a conductive material to form the connection substrate pad 222, the connection substrate via 224, and the first conductive pattern 226.

[0064] refer to Fig.17 , an opening OP may be formed in the connection substrate 200. A portion of the connection substrate 200 may be removed to form an opening OP penetrating the connection substrate 200. The opening OP may be formed, for example, by an etching process such as drilling, laser ablation, or laser cutting. The removed portion of the connection substrate 200 may be a region to which the lower semiconductor chip 300 is disposed in a subsequent process.

[0065] The connection substrate 200 may be attached to a carrier substrate 800. For example, the carrier substrate 800 may be an insulating substrate (including glass or polymer) or a conductive substrate (including metal). The top surface of the carrier substrate 800 may include an adhesive member for adhering the carrier substrate 800 to the bottom surface 200b of the connection substrate 200. The adhesive member may include, for example, an adhesive tape.

[0066] refer to Fig.18 , the lower semiconductor chip 300 may be disposed on the carrier substrate 800, for example, disposed in the opening OP of the connection substrate 200. The lower semiconductor chip 300 may be disposed as shown in FIG. Figure 6 and 7The lower semiconductor chip 300 of the manufacturing is the same. The lower semiconductor chip 300 can be disposed in the opening OP of the connection substrate 200. At this stage, the lower semiconductor chip 300 can be adhered to the carrier substrate 800. The lower semiconductor chip 300 can include a lower chip pad 305 on its lower portion. For example, the bottom surface 300b of the lower semiconductor chip 300 can correspond to an active surface in contact with the carrier substrate 800.

[0067] refer to Fig.19 , a bonding member BM may be formed. For example, the first bonding pad BP1 of the connection substrate 200 and the second bonding pad BP2 of the lower semiconductor chip 300 may be connected to each other in a wire bonding manner.

[0068] refer to Fig. 20 , a lower molding member 400 may be formed on the carrier substrate 800. The lower molding member 400 may fill the space between the connection substrate 200 and the lower semiconductor chip 300. For example, an insulating substance may be injected into the space between the connection substrate 200 and the lower semiconductor chip 300, and then the insulating substance may be cured to form the lower molding member 400. The lower molding member 400 may cover the first conductive pattern 226 of the connection substrate 200 and the second conductive pattern 320 of the lower semiconductor chip 300.

[0069] refer to Fig.21 , a support substrate 910 may be disposed on the connection substrate 200. The support substrate 910 may be, for example, an insulating substrate such as glass. The support substrate 910 may be adhered to the top surface of the lower molding member 400 using a glue layer 920. The glue layer 920 may be, for example, a resin film.

[0070] The carrier substrate 800 may be removed. The carrier substrate 800 may be removed as shown by dotted lines to expose the bottom surface 300b of the lower semiconductor chip 300 and the bottom surface 200b of the connection substrate 200. The carrier substrate 800 may be removed by applying a shear stress or by chemically treating the adhesion member.

[0071] refer to Fig. 22, the lower substrate 100 may be formed on the bottom surface 300b of the lower semiconductor chip 300 and the bottom surface 200b of the connection substrate 200. For example, a dielectric layer 102, a conductive layer 104, and a substrate pad 106 may be formed on the bottom surface 300b of the lower semiconductor chip 300 and the bottom surface 200b of the connection substrate 200, so that the lower substrate 100 may be manufactured. A dielectric material layer (e.g., a silicon oxide layer) may be formed on the bottom surface 300b of the lower semiconductor chip 300 and the bottom surface 200b of the connection substrate 200, and then the dielectric material layer may be patterned to form a portion of the dielectric layer 102. The lower chip pad 305 and the connection substrate pad 222 may be exposed through the dielectric layer 102. A conductive material layer may be formed on the bottom surface of the dielectric layer 102, and then the conductive material layer may be patterned to form a conductive layer 104 and a substrate pad 106. The conductive layer 104 may be electrically connected to the lower semiconductor chip 300 and the connection substrate 200. A dielectric material layer may be formed on the bottom surface of the conductive layer 104 and then patterned to form other portions of the dielectric layer 102. At this stage, the substrate pad 106 may be exposed through the dielectric layer 102.

[0072] External terminals 110 may be formed on the exposed substrate pads 106. The external terminals 110 may include solder balls or solder bumps.

[0073] refer to Fig.23 , the support substrate 910 may be removed. For example, the support substrate 910 may be removed by applying a shear stress or by chemically treating the glue layer 920. The support substrate 910 may be removed as shown by the dotted line to expose the top surface of the lower molding member 400.

[0074] The lower molding member 400 may be etched to form a first recess RS1 exposing the first, second, and third pads CP1, CP2, and CP3. The bottom package P100 may be manufactured through the above process.

[0075] Afterwards, you can execute the reference Figure 1 For example, a top package P200 may be mounted on a bottom package P100 to manufacture Figure 5 semiconductor packaging.

[0076] As a summary and review, some example embodiments provide semiconductor packages with improved electrical characteristics and methods of manufacturing the same. Some example embodiments also provide compact-sized semiconductor packages and methods of manufacturing the same. Some example embodiments also provide semiconductor packages with improved thermal stability and methods of manufacturing the same.

[0077] That is, the semiconductor package according to some example embodiments may be configured so that the connection terminals of the top package may all be disposed on the connection substrate and the lower semiconductor chip. Therefore, the conductive pattern may redistribute the circuit of the top package and increase the wiring freedom between the top package and the bottom package.

[0078] In addition, since no additional substrate is required for redistribution between the bottom package and the top package, the thickness of the semiconductor package can be reduced. As a result, the semiconductor package can have an overall reduced size. In addition, the reduction in the total thickness of the semiconductor package can allow the lower semiconductor chip to have an increased thickness, so the lower semiconductor chip can dissipate heat favorably. In addition, the heat generated from the lower semiconductor chip can be released through the conductive pattern, thereby increasing heat dissipation.

[0079] Example embodiments have been disclosed herein, and although specific terms are employed, these terms are used and should be interpreted only in a general, descriptive sense, and not for limiting purposes. In some cases, it will be clear to those of ordinary skill in the art at the time of filing this application that the features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically noted. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor package, comprising: lower base plate; A connecting substrate coupled to the lower substrate, the connecting substrate comprising: a lateral portion surrounding the cavity, and a first conductive pattern on a top surface of the lateral portion; a lower semiconductor chip on the lower substrate, the lower semiconductor chip being located in the cavity of the connection substrate, the lower semiconductor chip comprising a second conductive pattern on a top surface of the lower semiconductor chip; a bonding member connecting the first conductive pattern and the second conductive pattern to each other, wherein the bonding member includes a bonding wire; and a top package mounted on the first conductive pattern and the second conductive pattern, Wherein, the top package comprises: upper base plate; An upper semiconductor chip on the upper substrate; and A connection terminal on a bottom surface of the upper substrate, the connection terminal being coupled to the first conductive pattern and the second conductive pattern.

2. The semiconductor package according to claim 1, wherein The connection terminals are located on the lower semiconductor chip.

3. The semiconductor package according to claim 1, wherein: The connecting terminal comprises: a first connection terminal coupled to the first conductive pattern; and The second connection terminal is coupled to the second conductive pattern.

4. The semiconductor package according to claim 3, wherein: The second connection terminal is electrically coupled to the lower substrate through the second conductive pattern, the bonding member, and the connection substrate.

5. The semiconductor package according to claim 1, wherein The connection terminals are electrically insulated from the lower semiconductor chip.

6. The semiconductor package according to claim 1, wherein The width of the upper semiconductor chip is greater than the width of the lower semiconductor chip.

7. The semiconductor package according to claim 1, wherein: The top surface of the lower semiconductor chip is an inactive surface.

8. The semiconductor package according to claim 1, wherein The top surface of the lateral portion of the connection substrate and the top surface of the lower semiconductor chip are located at the same height.

9. The semiconductor package according to claim 1, further comprising a lower molding member burying the lower semiconductor chip and the connection substrate on the lower substrate, wherein the lower molding member exposes the first conductive pattern and the second conductive pattern.

10. The semiconductor package according to claim 1, wherein The lower semiconductor chip further includes a via hole penetrating the lower semiconductor chip and electrically connecting the second conductive pattern to the lower substrate.

11. The semiconductor package according to claim 1, wherein The lower substrate includes a redistribution layer directly coupled to a lower chip pad of the lower semiconductor chip and a substrate pad of the connection substrate.

12. A semiconductor package, comprising: Connecting base plate, including: The lateral portion surrounding the cavity, a first conductive pattern on a top surface of the lateral portion, and a via passing through the lateral portion and connected to the first conductive pattern; The semiconductor chip in the cavity comprises: a second conductive pattern on the inactive surface of the semiconductor chip, the semiconductor chip and the second conductive pattern being electrically insulated from each other, and an active surface facing the inactive surface; a bonding member electrically connecting the first conductive pattern and the second conductive pattern to each other, wherein the bonding member comprises a bonding wire; and A top package is mounted on the first conductive pattern and the second conductive pattern, and a connection terminal under the top package is coupled to the first conductive pattern and the second conductive pattern.

13. The semiconductor package according to claim 12, wherein: The top surface of the lateral portion of the connection substrate and the inactive surface of the semiconductor chip are coplanar with each other.

14. The semiconductor package according to claim 12, wherein: The connection terminal includes a first connection terminal and a second connection terminal, wherein the first connection terminal is coupled to the first conductive pattern, and The second connection terminal is coupled to the second conductive pattern.

15. The semiconductor package according to claim 12, wherein: The width of the top package is the same as the width of the connection substrate.

16. The semiconductor package according to claim 12, further comprising an additional substrate below the connection substrate, wherein the connection substrate and the semiconductor chip are coupled to the additional substrate, and The active surface of the semiconductor chip faces the additional substrate.

17. The semiconductor package according to claim 16, wherein: The semiconductor chip further includes a chip via passing through the semiconductor chip, the chip via electrically connecting the second conductive pattern to the additional substrate.

18. The semiconductor package according to claim 12, further comprising: A molding member covers the top surface of the lateral portion of the connection substrate and the inactive surface of the semiconductor chip, the molding member exposing the first conductive pattern and the second conductive pattern.

19. A method for manufacturing a semiconductor package, the method comprising: providing a lower semiconductor chip, the lower semiconductor chip comprising a first conductive pattern on an inactive surface of the lower semiconductor chip; providing a connection substrate, the connection substrate comprising a cavity in the connection substrate and a second conductive pattern on a top surface of the connection substrate; disposing the lower semiconductor chip and the connection substrate on the lower substrate so as to place the lower semiconductor chip in the cavity of the connection substrate; wire-bonding the first conductive pattern and the second conductive pattern to each other; providing a top package, the top package comprising a plurality of connection terminals on a bottom surface of the top package; as well as The top package is mounted on the first conductive pattern and the second conductive pattern to couple the plurality of connection terminals to the first conductive pattern and the second conductive pattern.

20. The method according to claim 19, wherein: Providing the lower semiconductor chip includes: providing a conductive layer on the inactive surface of the lower semiconductor chip; and The conductive layer is patterned.

21. The method according to claim 19, wherein: Joining the first conductive pattern and the second conductive pattern comprises: forming a molding member to cover the connection substrate and the lower semiconductor chip; performing an etching process on the molding member to form a first recess exposing the first conductive pattern and the second conductive pattern; and The first conductive pattern and the second conductive pattern are wire-bonded to each other.

Images