Method for manufacturing semiconductor device

Abstract

The present disclosure provides a method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device includes: designing a layout; manufacturing a photomask based on the designed layout; and performing a photolithography process using the photomask to form a pattern on a substrate. Manufacturing the photomask includes: preparing a photomask including a first chip area and a second chip area; extracting a first image and a second image from the first chip area and the second chip area, respectively; averaging the first image and the second image to generate an initial standard image from which a difference area between the first image and the second image is excluded; inserting a normal image into an area of ​​the initial standard image corresponding to the difference area based on the layout to generate a standard image; and comparing each of the first image and the second image with the standard image to detect defects in the first chip area and / or the second chip area.

Description

Technical Field

[0001] Embodiments of the inventive concept relate to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device including a method of inspecting a photomask. Background Art

[0002] Semiconductor devices are widely used in the electronics industry due to their small size, multifunctional characteristics and / or low manufacturing cost. Semiconductor devices can be divided into semiconductor memory devices configured to store logic data, semiconductor logic devices configured to process logic data, or hybrid semiconductor devices having the functions of both semiconductor memory devices and semiconductor logic devices. With the development of the electronics industry, there will be an increasing need for semiconductor devices with improved characteristics. For example, there will be an increasing need for semiconductor devices with high reliability, high speed and / or multifunctionality. In order to meet these requirements, semiconductor devices will be more highly integrated and the structure of semiconductor devices will become more and more complex. Summary of the invention

[0003] Embodiments of the inventive concept may provide a method of manufacturing a semiconductor device capable of more effectively inspecting defects of a photomask.

[0004] In one aspect, a method for manufacturing a semiconductor device may include: designing a layout; manufacturing a photomask based on the designed layout; and performing a photolithography process using the manufactured photomask to form a pattern on a substrate. Manufacturing the photomask may include: preparing a photomask including a first chip region and a second chip region; extracting a first image and a second image from the first chip region and the second chip region, respectively; averaging the first image and the second image to form or generate an initial standard image from which a difference region between the first image and the second image is excluded; inserting a normal image into a region of the initial standard image corresponding to the difference region based on the layout to form or generate a standard image; and comparing each of the first image and the second image with the standard image to detect defects in at least one of the first chip region and the second chip region.

[0005] In one aspect, a method for manufacturing a semiconductor device may include: designing a layout; manufacturing a photomask based on the designed layout; inspecting the manufactured photomask; and performing a photolithography process using the photomask to form a pattern on a substrate. Inspecting the photomask may include: extracting a first image and a second image from a first chip region and a second chip region of the photomask, respectively; averaging the first image and the second image to form or generate an initial standard image including a blank region; extracting an area of ​​the initial standard image as a patch; and inserting the extracted patch into the blank region to form or generate a standard image.

[0006] In one aspect, a method for manufacturing a semiconductor device may include: designing a layout including a first layout pattern and a second layout pattern, the second layout pattern having the same shape and size as the first layout pattern; manufacturing a photomask including a first chip region and a second chip region based on the designed layout, each of the first chip region and the second chip region including a first mask pattern and a second mask pattern formed by the first layout pattern and the second layout pattern, respectively; inspecting the manufactured photomask; and performing a photolithography process using the photomask to form a pattern on a substrate. Inspecting the photomask may include: extracting a first image and a second image from the first chip region and the second chip region, respectively, each of the first image and the second image including a first image pattern and a second image pattern corresponding to the first mask pattern and the second mask pattern, respectively; averaging the first image and the second image to form or generate an initial standard image from which a difference area between the first image and the second image is excluded, the difference area corresponding to the first image pattern; extracting a patch corresponding to an area on the second image pattern of the initial standard image; and inserting the extracted patch into an area of ​​the initial standard image corresponding to the difference area to form or generate a standard image. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the inventive concept will become more apparent in view of the drawings and the accompanying detailed description.

[0008] Figure 1 is a flowchart illustrating a method for designing and manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0009] Figure 2 is a conceptual diagram illustrating a lithography system using a photomask manufactured according to some embodiments of the inventive concept.

[0010] Figure 3 is a plan view illustrating a reticle according to some embodiments of the inventive concept.

[0011] Figure 4 It is along Figure 3 A cross-sectional view taken along line II'.

[0012] Figure 5 is a flow chart illustrating a method of detecting defects of a photomask.

[0013] Figure 6 A layout design for fabricating a photomask is shown.

[0014] Figure 7 Show Figure 3 An optical image of the first chip area of ​​the photomask.

[0015] Figure 8 Show Figure 3 An optical image of the second chip region of the photomask.

[0016] Fig. 9 shows overlapping images, where Figure 7 The first image with Figure 8 The second image is overlapped.

[0017] Fig.10 Shown by Figure 7 The first image and Figure 8 The initial standard image is obtained by averaging the second image.

[0018] Fig.11 is shown for Figure 6 The layout design defines a plan view of the operation of the first area and the second area.

[0019] Fig.12 is a plan view showing an operation for forming a standard image from an initial standard image.

[0020] Fig.13 is a plan view showing an operation for comparing a standard image with a first image.

[0021] Fig.14 is a plan view showing an operation for comparing a standard image with a second image. DETAILED DESCRIPTION

[0022] Figure 1 is a flowchart illustrating a method for designing and manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0023] Reference Figure 1 , a layout design process for implementing a semiconductor integrated circuit on a silicon substrate can be performed (S10, a first operation). The terms first, second, third, etc. are used here only to distinguish or differentiate one element, block, operation, etc. from another. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. The layout design process may include a process of placing and routing (e.g., connecting) various standard cells provided from a cell library based on predetermined design rules.

[0024] The cell library for the layout design process may also include information about the operation, speed and / or power consumption of the standard cell. In some embodiments, a cell library for representing the layout of a circuit with a specific gate level may be defined in multiple or most layout design tools. The layout design process may define or describe the shape and / or size of the pattern for forming or defining the transistor and metal interconnects that will actually be formed on the silicon substrate. For example, a layout pattern (e.g., a PMOS, NMOS, N hydrazine, a gate electrode, and a metal interconnect to be arranged thereon) may be appropriately placed to actually form an inverter circuit on a silicon substrate. To this end, first, a suitable one of the inverters defined in advance in the cell library may be searched and selected.

[0025] A routing process may be performed on the placed standard cells. Specifically, a routing process may be performed on the placed standard cells to connect them to the upper interconnects. Through the routing process, the standard cells may be electrically connected to each other to satisfy the design or to be connected in other ways according to the design. These processes may be performed automatically or manually by a layout design tool. In some embodiments, the process of placing and routing standard cells may be automatically performed by another placement and routing tool.

[0026] After the routing process, a verification process may be performed on the layout to verify whether there are parts that violate the design rules. In some embodiments, the verification process may include various verification items, such as design rule check (DRC) items, electrical rule check (ERC) items, and layout and schematic (LVS) items. The DRC item may be performed to check whether the layout properly meets the design rules. The ERC item may be performed to check whether there are electrical disconnect issues in the layout. The LVS item may be performed to check whether the layout is prepared to be consistent with the gate-level netlist.

[0027] An optical proximity correction (OPC) process (S20, second operation) may be performed. The layout pattern obtained by the layout design process may be implemented on a silicon substrate using a photolithography process. The OPC process may be performed to correct the optical proximity effect that may occur in the photolithography process. The optical proximity effect may be an unexpected optical effect (such as refraction or diffraction) that may occur in the photolithography process. In other words, the distortion phenomenon of the layout pattern that may be caused by the optical proximity effect may be corrected by the OPC process. The shape and position of the designed layout pattern may be slightly modified or offset by the OPC process. The first operation S10 and the second operation S20 may be collectively referred to as "design layout".

[0028] A photomask may be generated based on the layout modified or biased by the OPC process (S30, third operation). A chrome layer coated on a mask substrate (eg, a glass substrate) may be patterned using the layout pattern to form a mask pattern on the mask substrate. Thus, a photomask may be generated or manufactured.

[0029] The semiconductor device may be manufactured using the generated photomask (S40, fourth operation). Through a photolithography process using the generated photomask, the shape of a pattern obtained through a layout design process may be sequentially formed on a silicon substrate.

[0030] Figure 2 is a conceptual diagram illustrating a lithography system using a photomask manufactured according to some embodiments of the inventive concept.

[0031] Reference Figure 2 The photolithography system PLS may include a light source LS, a photomask PM, a reduced projection apparatus RPA and a substrate platform SS. The photomask PM may be referred to above. Figure 1 The first to third operations S10, S20 and S30 described above generate or manufacture. The photolithography system PLS may also include in addition to Figure 2 Components other than those shown. For example, the lithography system PLS may also include sensors for measuring the height and gradient of the surface of the substrate WF.

[0032] The light source LS may emit light. The light emitted from the light source LS may be irradiated or provided to the photomask PM. In some embodiments, a lens may be provided between the light source LS and the photomask PM to adjust the focus of the light. The light source LS may include an ultraviolet light source (e.g., a krypton fluoride (KrF) light source having a wavelength of about 234 nm or an argon fluoride (ArF) light source having a wavelength of about 193 nm). The light source LS may include a single point light source PO. However, embodiments of the inventive concept are not limited thereto. In some embodiments, the light source LS may include a plurality of point light sources.

[0033] The photomask PM may include a mask pattern to print (or implement) the designed layout onto the substrate WF. For example, the mask pattern may block the light emitted from the light source LS, and the region of the photomask PM on which the mask pattern is not formed may transmit the light emitted from the light source LS.

[0034] The reduced projection apparatus RPA may receive light transmitted through the photomask PM. The reduced projection apparatus RPA may match a layout pattern to be printed on the substrate WF with a mask pattern of the photomask PM. The substrate stage SS may support the substrate WF. For example, the substrate WF may include a silicon wafer.

[0035] The reduced projection apparatus RPA may include an aperture. The aperture may be used to increase the focal depth of the ultraviolet light emitted from the light source LS. For example, the aperture may include a dipole aperture or a quadrupole aperture. The reduced projection apparatus RPA may also include a lens for adjusting the focus of the light.

[0036] The light transmitted through the photomask PM can be irradiated to the substrate WF through the reduced projection apparatus RPA. Therefore, a resist pattern corresponding to the mask pattern of the photomask PM can be printed on the substrate WF.

[0037] Figure 3 is a plan view illustrating a mask according to some embodiments of the inventive concept. Figure 4 It is along Figure 3 A cross-sectional view taken along line II'.

[0038] Reference Figure 2 , Figure 3 and Figure 4 The mask RET may include a photomask PM, a pellicle PEL for protecting the photomask PM, and a frame FR between the photomask PM and the pellicle PEL. The mask RET including the photomask PM according to the present embodiment may be mounted on Figure 2 In the lithography system PLS, a lithography process can be performed on the substrate WF.

[0039] The photomask PM may include a mask substrate MS and a mask pattern MP on the mask substrate MS. The mask substrate MS may include first to fourth chip regions CR1 to CR4 for forming a resist pattern on a substrate WF. The mask pattern MP may be disposed on the first to fourth chip regions CR1 to CR4. For example, the mask pattern MP may include a plurality of first mask patterns extending in a first direction D1 and a plurality of second mask patterns extending in a second direction D2. Figure 3 and Figure 4 The shapes, sizes, and distances of the mask patterns MP are shown as examples and may be variously modified.

[0040] The first to fourth chip regions CR1 to CR4 may be substantially identical to each other. The resist pattern may be formed on the first to fourth dies of the substrate WF through the first to fourth chip regions CR1 to CR4. In other words, each of the first to fourth chip regions CR1 to CR4 may correspond to one die of the substrate WF.

[0041] The mask substrate MS may further include an auxiliary pattern region AP surrounding each of the first to fourth chip regions CR1 to CR4 , and a black border region BB located at the periphery of the mask substrate MS.

[0042] Auxiliary patterns that are not included in the pattern constituting or defining the desired integrated circuit may be provided on the auxiliary pattern region AP. The auxiliary pattern may include a pattern (e.g., an alignment key pattern) that is necessary in the process of manufacturing the integrated circuit but is not retained in the final semiconductor chip. The auxiliary pattern region AP may correspond to the scribe line region of the substrate WF, so the auxiliary pattern of the auxiliary pattern region AP may be transferred to the scribe line region of the substrate WF.

[0043] The black border area BB may be a non-pattern area on which a pattern to be transferred onto the substrate WF is not provided.

[0044] The first surface PELa of the film PEL may be exposed to the outside (for example, it may be facing away from the photomask PM or outside the photomask PM). The second surface PELb of the film PEL may face the photomask PM. A frame FR may be provided between the film PEL and the photomask PM. The film PEL may be spaced apart from the photomask PM by the frame FR. The frame FR may be provided on the black border region BB of the mask substrate MS. An adhesive layer may be provided between the film PEL and the frame FR. In addition, an adhesive layer may be provided between the frame FR and the mask substrate MS.

[0045] The mask film PEL may protect the photomask PM from external contaminants such as dust and / or resist. If the mask film PEL does not exist on the photomask PM, the external contaminants may adhere to the photomask PM and may cause various defects in the photolithography process.

[0046] Figure 5 is a flow chart illustrating a method of detecting defects of a photomask. Figure 6 A layout design that forms the basis for fabricating a photomask is shown.

[0047] Reference Figure 1 , Figure 3 , Figure 5 and Figure 6 , you can execute Figure 1 The layout design DE is obtained by performing a layout design process (S10) and an OPC process (S20). The layout design DE may include a layout pattern PA. In one embodiment, the layout pattern PA may include first to fourth layout patterns PA1 to PA4 extending parallel to each other in the first direction D1.

[0048] produce Figure 3 Operation S30 of manufacturing the photomask PM may include: manufacturing the photomask PM based on the layout design DE; inspecting or detecting whether defects exist on the first to fourth chip regions CR1 to CR4 of the manufactured photomask PM; and correcting the detected defects.

[0049] Specifically, each of the first to fourth chip regions CR1 to CR4 of the photomask PM may be formed based on the layout design DE. Next, an operation of inspecting or detecting defects of the first to fourth chip regions CR1 to CR4 of the photomask PM may be performed. Figure 5 The operation of inspecting defects is performed as shown in the flowchart.

[0050] Figure 7 Show Figure 3 An optical image of the first chip area of ​​the photomask. Figure 8 Show Figure 3 An optical image of the second chip region of the photomask. Figure 5 , Figure 7 and Figure 8 , the inspection images of the first chip region CR1 and the second chip region CR2 of the photomask PM can be acquired or extracted (S310). The extraction of the inspection image can be performed by the photomask inspection device. Specifically, the inspection image of the first chip region CR1 of the photomask PM can be extracted as a first image Ima, and the inspection image of the second chip region CR2 of the photomask PM can be extracted as a second image Imb. The first image Ima and the second image Imb can be optical images of the first chip region CR1 and the second chip region CR2 obtained by the photomask inspection device, respectively.

[0051] Each of the first image Ima and the second image Imb may include an image pattern IP. The image pattern IP may be an optical image of the mask pattern MP of the first chip region CR1 and the second chip region CR2.

[0052] For example, the image pattern IP of each of the first image Ima and the second image Imb may include first to fourth image patterns IP1 to IP4 extending parallel to each other in the first direction D1. The first to fourth image patterns IP1 to IP4 of each of the first image Ima and the second image Imb may correspond to first to fourth layout patterns PA1 to PA4 of the layout design DE, respectively. In the second image Imb, the second image pattern IP2 may include a protrusion PP protruding toward the first image pattern IP1.

[0053] Fig. 9 Shown in Figure 7 The first image with Figure 8 The second image is overlapped with the overlapping image. Figure 5 and Fig. 9, the first image Ima may be compared with the second image Imb to define a difference region DFR (S320). Specifically, the overlapped image OIm may be obtained by overlapping the first image Ima and the second image Imb with each other, for example, so that corresponding portions of the first image Ima and the second image Imb are aligned in a plan view. The overlapped image OIm may include an overlapped region OVR in which the first image Ima substantially overlaps with the second image Imb, and a difference region DFR in which there is a difference between the first image Ima and the second image Imb.

[0054] For example, the difference region DFR may be a protrusion PP of the second image pattern IP2 including the second image Imb and a region near the protrusion PP. Since the second image pattern IP2 of the first image Ima does not include the protrusion PP, the difference between the first image Ima and the second image Imb may exist in the region including the protrusion PP.

[0055] Fig.10 For example, by Figure 7 The first image and Figure 8 As will be appreciated, in some embodiments, averaging may refer to calculating the arithmetic mean of the respective values ​​of corresponding pixel positions in the first image and the second image. Figure 5 and Fig.10 , the first image Ima and the second image Imb may be averaged to form or generate an initial standard image AIM from which the difference region DFR is excluded (S330). For example, the formation of the initial standard image AIM may include: averaging the first image Ima and the second image Imb to obtain an average image, and leaving the previously defined difference region DFR blank or empty in the average image, for example, by deleting or removing the portion of the initial standard image AIM corresponding to the difference region DFR. Fig.10 , Fig.11 and Fig.12 In FIG. 1 , for convenience of explanation, the difference region DFR is shown by a dotted line.

[0056] Fig.11 is shown for Figure 6 The layout design defines a plan view of the operation of the first area and the second area. Figure 5 and Fig.11 , you can Figure 6 A first region RG1 corresponding to the difference region DFR is defined on the layout design DE (S340). Fig.10 The initial standard image AIM of FIG. 1 may be a first image pattern IP1 and a second image pattern IP2. The difference region DFR may be located between the first image pattern IP1 and the second image pattern IP2.

[0057] The area corresponding to the difference area DFR on the layout design DE may be defined as a first area RG1 based on information about the size and position of an area (e.g., a blank area) corresponding to the difference area DFR on the initial standard image AIM. The first area RG1 may be located on the second layout pattern PA2. The first area RG1 may be located between the first layout pattern PA1 and the second layout pattern PA2.

[0058] A second region RG2 substantially the same as the first region RG1 may be searched for on the layout design DE (S350). For example, the shapes and arrangements of the first and second layout patterns PA1 and PA2 may be substantially the same as the shapes and arrangements of the third and fourth layout patterns PA3 and PA4. The second region RG2 may correspond to a region between the third and fourth layout patterns PA3 and PA4, which has the same shape as the first region RG1 defined between the first and second layout patterns PA1 and PA2.

[0059] Fig.12 is a plan view showing an operation for forming a standard image from an initial standard image. Figure 5 and Fig.12 , the area corresponding to the second area RG2 of the layout design DE can be divided from the initial standard image AIM and extracted as a patch PAT (S360). For example, based on the size and position of the second area RG2 of the layout design DE, the area corresponding to the second area RG2 of the initial standard image AIM can be extracted as a patch PAT.

[0060] The extracted patch PAT may be inserted into the region of the initial standard image AIM corresponding to the difference region DFR to form or generate a standard or reference image SIM (S370). The standard image SIM may be formed by inserting a normal image into the region of the initial standard image AIM corresponding to the difference region DFR, and thus the standard image SIM may be used as a standard or reference in an operation for checking whether each of the first chip region CR1 to the fourth chip region CR4 of the photomask PM is manufactured normally (e.g., has been manufactured accurately according to the design).

[0061] In other words, the normal image may be a patch PAT extracted based on information obtained through the layout design DE. When the chip area of ​​the photomask is formed without defects, the normal image may be an optical image corresponding to the difference area DFR. As a result, when the photomask is manufactured normally from the layout design DE without defects, the standard image SIM may correspond to an optical image of a defect-free photomask.

[0062] Since the difference region DFR is a region in which there is a difference between the first image Ima and the second image Imb, an appropriate image (i.e., a normal image) can be inserted into the region corresponding to the difference region DFR of the initial standard image AIM to form a standard image SIM used as a standard for checking whether there is a defect. Here, it may be necessary to search for an appropriate image (i.e., a normal image). According to the present embodiment, an appropriate image (i.e., a normal image) to be inserted into the region corresponding to the difference region DFR can be easily searched and obtained through the layout design DE used as a basis for the design of the photomask PM.

[0063] Fig.13 is a plan view showing an operation for comparing a standard image with a first image. Figure 5 and Fig.13 , the first image Ima may be compared with the standard image SIM (S380). As a result of comparing the first image Ima with the standard image SIM, the first image Ima may be substantially the same as the standard image SIM. In other words, it may be recognized that there is no defect in the first chip region CR1.

[0064] Fig.14 is a plan view showing an operation for comparing a standard image with a second image. Figure 5 and Fig.14 , the second image Imb may be compared with the standard image SIM (S380). As a result of comparing the second image Imb with the standard image SIM, the second image pattern IP2 of the second image Imb may be different from the second image pattern IP2 of the standard image SIM. In other words, it may be recognized that the defect DEF exists in the second chip region CR2 (S390). It may be recognized that the defect DEF exists on one of the mask patterns MP of the second chip region CR2 corresponding to the second image pattern IP2, for example, in an area or portion thereof corresponding to the difference region DFR. In addition, defect inspection may also be performed on each of the third chip region CR3 and the fourth chip region CR4 by using the standard image SIM obtained above. The mask pattern MP of the second chip region CR2 on which the defect DEF exists may be appropriately corrected to produce or manufacture the final photomask PM.

[0065] For example, an image modeling (or simulation) method may be used to obtain a standard image used as a standard for defect detection of a photomask. However, expensive devices and / or programs may be required for accurate image modeling. According to an embodiment of the inventive concept, a standard or reference image SIM may be automatically obtained by comparing a first image Ima with a second image Imb without performing an operation for image modeling. In other words, a standard image SIM may be automatically generated without using expensive devices and / or programs. As a result, a method for effectively inspecting a photomask may be performed.

[0066] Although the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive but illustrative. Therefore, the scope of the inventive concept will be determined by the broadest permissible interpretation of the claims and their equivalents, and should not be limited or restricted by the foregoing description.

[0067] This application claims the priority of Korean Patent Application No. 10-2018-0069207 filed on June 15, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Design layout; manufacturing a photomask based on the layout; as well as Performing a photolithography process using the photomask to form a pattern on a substrate, in Manufacturing the photomask comprises: preparing the photomask including a first chip region and a second chip region; extracting a first image and a second image from the first chip region and the second chip region respectively; generating, based on the first image and the second image, an initial standard image from which a difference area between the first image and the second image is excluded; inserting a normal image into a region of the initial standard image corresponding to the difference region based on the layout to generate a standard image; and comparing each of the first image and the second image with the standard image to detect defects in at least one of the first chip region and the second chip region, Wherein inserting the normal image comprises: defining a first area of ​​the layout corresponding to the difference area; searching for another area of ​​the layout that is the same as the first area and defining the another area of ​​the layout as a second area; extracting a region of the initial standard image corresponding to the second region as a patch; and The patch is inserted into the region of the initial standard image corresponding to the difference region.

2. The method according to claim 1, wherein the first image and the second image are optical images of the first chip area and the second chip area, respectively, and are obtained by a photomask inspection device, and wherein generating the initial standard image includes averaging the first image and the second image.

3. The method according to claim 1, wherein manufacturing the photomask further comprises: The difference region including differences between the first image and the second image is defined by comparing the first image and the second image.

4. The method of claim 3, wherein defining the difference area comprises: The first image and the second image are aligned with each other in a plan view to generate an overlapping image, wherein the overlapping image includes: an overlapping area including portions of the first image and the second image that overlap each other; and the difference area including the difference between the first image and the second image.

5. The method according to claim 1, wherein the layout comprises a first layout pattern and a second layout pattern, wherein the shape and size of the first layout pattern are respectively the same as the shape and size of the second layout pattern, wherein the initial standard image comprises a first image pattern and a second image pattern corresponding to the first layout pattern and the second layout pattern respectively, wherein the area of ​​the initial standard image corresponding to the difference area is located in the first area of ​​the first image pattern, and Wherein the normal image is extracted from a second area of ​​the second image pattern.

6. A method for manufacturing a semiconductor device, the method comprising: Design layout; manufacturing a photomask based on the layout; inspecting the photomask; as well as Performing a photolithography process using the photomask to form a pattern on a substrate, Wherein inspecting the photomask comprises: extracting a first image and a second image from a first chip region and a second chip region of the photomask, respectively; averaging the first image and the second image to generate an initial standard image including a blank area; extracting a region of the initial standard image as a patch; and The patch is inserted into the blank area to generate a standard image. 7 . The method of claim 6 , wherein the blank area corresponds to an area including a difference between the first image and the second image when the first image and the second image are compared with each other.

8. The method of claim 7, wherein inspecting the photomask further comprises: aligning the first image and the second image with each other in a plan view to generate an overlapping image, wherein the overlapping image includes: an overlapping area including portions of the first image and the second image that overlap each other; and a difference area including the difference between the first image and the second image; and The area of ​​the initial standard image corresponding to the difference area is removed to define the blank area.

9. The method according to claim 6, wherein extracting the region of the initial standard image as the patch comprises: defining a first area of ​​the layout corresponding to the blank area; searching for another area of ​​the layout that is the same as the first area, and defining the another area of ​​the layout as a second area; as well as A region of the initial standard image corresponding to the second region is extracted as the patch. 10 . The method according to claim 6 , wherein the first image and the second image are optical images of the first chip region and the second chip region, respectively, and are obtained by a photomask inspection device.

11. The method according to claim 6, wherein the layout comprises a first layout pattern and a second layout pattern, wherein the shape and size of the first layout pattern are respectively the same as the shape and size of the second layout pattern, wherein the initial standard image comprises a first image pattern and a second image pattern corresponding to the first layout pattern and the second layout pattern respectively, wherein the blank area is located in the first area of ​​the first image pattern, and Wherein the patch is extracted from a second region of the second image pattern.

12. The method of claim 6, wherein inspecting the photomask further comprises: Each of the first image and the second image is compared with the standard image to detect defects in at least one of the first chip region and the second chip region.

13. A method for manufacturing a semiconductor device, the method comprising: designing a layout including a first layout pattern and a second layout pattern; manufacturing a photomask including a first chip region and a second chip region based on the layout, wherein each of the first chip region and the second chip region includes a first mask pattern and a second mask pattern corresponding to the first layout pattern and the second layout pattern, respectively; inspecting the photomask; as well as Performing a photolithography process using the photomask to form a pattern on a substrate, Wherein inspecting the photomask comprises: extracting a first image and a second image from the first chip region and the second chip region, respectively, wherein each of the first image and the second image includes a first image pattern and a second image pattern corresponding to the first mask pattern and the second mask pattern, respectively; averaging the first image and the second image to generate an initial standard image from which a difference region between the first image and the second image is excluded, the difference region corresponding to the first image pattern; extracting a patch corresponding to the second image pattern of the initial standard image; and The patch is inserted into a region of the initial standard image corresponding to the difference region to generate a standard image.

14. The method of claim 13, wherein extracting the patch comprises: defining a first area of ​​the first layout pattern corresponding to the difference area; defining a second area of ​​the second layout pattern that is the same as the first area; as well as An area of ​​the second image pattern of the initial standard image is extracted as the patch, wherein the area of ​​the second image pattern corresponds to the second area of ​​the second layout pattern. 15 . The method according to claim 13 , wherein a shape and a size of the first layout pattern are respectively the same as a shape and a size of the second layout pattern. 16 . The method according to claim 13 , wherein the first image and the second image are optical images of the first chip region and the second chip region, respectively, and are obtained by a photomask inspection device.

17. The method of claim 13, wherein inspecting the photomask further comprises: The difference region including the difference between the first image and the second image is defined by comparing the first image and the second image.

18. The method of claim 17, wherein defining the difference region comprises: aligning the first image and the second image with each other in a plan view to generate an overlay image, wherein the overlay image comprises: an overlapping area including a portion where the first image and the second image overlap each other; and The difference area includes the difference between the first image and the second image.

19. The method of claim 13, wherein inspecting the photomask further comprises: Each of the first image and the second image is compared with the standard image to detect defects in at least one of the first chip region and the second chip region.

Images