Resistive memory device including compensation circuit

Abstract

A memory device includes: a memory cell array, a plurality of bit lines, a compensation circuit, a holding circuit, and a control logic circuit. The memory cell array includes a plurality of memory cells. Each bit line is connected to at least one memory cell. Among the bit lines, a predetermined voltage is applied to a selection bit line connected to a selected memory cell. The compensation circuit includes a sampling circuit that generates a sampling value by sensing a leakage current applied to an unselected memory cell among the plurality of memory cells. The holding circuit compensates the voltage applied to the selection bit line based on the sampling value. The control logic circuit outputs a sampling enable signal that controls the enablement of the sampling circuit and a holding enable signal that controls the enablement of the holding circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority benefit of Korean Patent Application No. 10-2018-0068866 filed on June 15, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a resistive memory device and a memory system including the resistive memory device. More particularly, the present disclosure relates to a memory device including a compensation circuit and a memory system including the memory device. Background Art

[0004] There is a demand for storage devices with high volume and low power. Therefore, next-generation storage devices that do not require refresh have been studied. The next-generation storage device may require high integration of dynamic random access memory (DRAM), non-volatility of flash memory, and high speed of static RAM (SRAM). Phase change RAM (PRAM), nano floating gate memory (NFGM), polymer RAM (PoRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), etc. are proposed as next-generation storage devices to meet the above requirements. Summary of the invention

[0005] The present disclosure describes a memory device including a compensation circuit and a memory system including the memory device. More specifically, the present disclosure describes a memory device including a compensation circuit that compensates for a voltage drop caused by a leakage current flowing through an unselected memory cell.

[0006] According to one aspect of the present disclosure, a memory device includes: a memory cell array, a plurality of bit lines, a compensation circuit, a holding circuit, and a control logic circuit. The memory cell array includes a plurality of memory cells. Each bit line is connected to at least one memory cell, and in the bit line, a predetermined voltage is applied to a selection bit line connected to a selected memory cell. The compensation circuit includes a sampling circuit and a holding circuit, the sampling circuit generates a sampling value by sensing a leakage current applied to an unselected memory cell in the memory cell, and the holding circuit compensates the voltage applied to the selection bit line based on the sampling value. The control logic circuit outputs a sampling enable signal that controls the enablement of the sampling circuit and a holding enable signal that controls the enablement of the holding circuit.

[0007] According to another aspect of the present disclosure, a resistive memory device includes a memory cell array, a plurality of bit lines, a control logic circuit, and a compensation unit. The memory cell array includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. The control logic circuit outputs a row address of a plurality of word lines based on an address received from an external device. The compensation circuit includes a sampling circuit, a holding circuit, and a switch. The sampling circuit generates a sampled value by sensing a leakage current applied to a bit line of a selected memory cell connected to a memory cell performing a storage operation. The holding circuit holds the sampled value and compensates the voltage applied to the bit line connected to the selected memory cell based on the sampled value. One end of the switch is connected to the sampling circuit, and the other end is connected to the holding circuit.

[0008] According to another aspect of the present disclosure, a resistive memory device includes a memory cell array, a bit line, and a compensation unit. The memory cell array includes a plurality of memory cells arranged in rows and columns. The bit line includes a plurality of local bit lines respectively connected to the memory cells and a plurality of global bit lines connected to at least one of the plurality of local bit lines via local selection transistors. The compensation circuit includes a sampling circuit and a holding circuit. The sampling circuit generates a sampled value by sensing a leakage current applied to a bit line connected to a selected memory cell that performs one or more storage operations in the memory cell. The holding circuit compensates the voltage applied to the bit line connected to the selected memory cell based on the sampled value. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a storage system according to an exemplary embodiment;

[0011] Figure 2 is a block diagram illustrating a storage device according to an exemplary embodiment;

[0012] Figure 3 Show Figure 2 The detailed configuration of the memory cell array shown in;

[0013] Figure 4 It is shown Figure 3 A circuit diagram of an exemplary embodiment of a tile shown in FIG.

[0014] FIG. 5A to FIG. 5C It is shown separately Figure 4 A circuit diagram of an exemplary embodiment of a memory cell is shown;

[0015] Figure 6 is a diagram for illustrating and explaining the operation of a compensation circuit according to an exemplary embodiment;

[0016] FIG. 7A to FIG. 7Dis a diagram for illustrating and explaining the operation of a circuit diagram according to an exemplary embodiment;

[0017] Figure 8 It is shown Fig. 7A A circuit diagram showing an example of a detailed configuration of the second resistor shown;

[0018] Fig. 9 shows a resistance distribution of a memory cell in a memory device including a compensation circuit according to an exemplary embodiment;

[0019] Fig.10 is a diagram for illustrating and explaining the operation of a compensation circuit according to another exemplary embodiment;

[0020] Fig.11 is a diagram for illustrating and explaining the operation of a compensation circuit according to another exemplary embodiment; and

[0021] Fig.12 is a block diagram illustrating a computing system including a memory system according to an exemplary embodiment. DETAILED DESCRIPTION

[0022] The inventive concepts of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings.

[0023] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment.

[0024] Reference Figure 1 , the memory system 1 may include a memory controller 10 and a memory device 100. The memory device 100 may include a memory cell array 110 and a compensation circuit 170. The compensation circuit 170 is representative of a compensation circuit and may also be known or referred to herein as a compensation circuit.

[0025] In the figure, this includes Figure 1, the circuits may be shown as, for example, "memory controllers," "control logic," "voltage generators," and "processors." As is conventional in the art of the inventive concepts described herein, examples may be described and illustrated in terms of blocks that perform one or more functions described. These blocks (which may be referred to herein as memory controllers, control logic, voltage generators, circuits, processors, etc.) are physically implemented by analog and / or digital circuits, such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and may optionally be driven by firmware and / or software. For example, the circuits may be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards. The circuits that make up the blocks may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware that performs some functions of the blocks and a processor that performs other functions of the blocks. Without departing from the scope of the inventive concepts, each block of the examples may be physically divided into two or more interactive and discrete blocks. Similarly, without departing from the scope of the inventive concepts, the blocks of the examples may be physically combined into more complex blocks.

[0026] The memory controller 10 may control the memory device 100 to write data to the memory device 100 or read data stored in the memory device 100 in response to a read / write request from the host HOST. More specifically, the memory controller 10 may control programming (or writing), reading, and erasing operations on the memory device 100 by providing an address ADDR, a command CMD, and a control signal CTRL to the memory device 100. In addition, data DT to be written and read data DT may be transmitted and received between the memory controller 10 and the memory device 100. For example, when the memory cells are arranged in rows and columns in the memory cell array 110, the address ADDR may include a row address and a column address.

[0027] Despite Figure 1Although not shown in the figure, the memory controller 10 may also include a random access memory (RAM), a processor, a host interface, and a memory interface. The RAM may be used as an operating memory of the processor, and the processor may control the operation of the memory controller 10. The host interface may include a protocol for performing data exchange between the host HOST and the memory controller 10. For example, the memory controller 10 may be configured to communicate with the outside (e.g., a host) by using at least one of various interface protocols (including universal serial bus (USB), multimedia card (MMC), peripheral component interconnect express (PCI-E), advanced technology attachment (ATA), serial ATA, parallel ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), etc.).

[0028] The memory cell array 110 may include a plurality of memory cells (not shown), which are respectively arranged in regions where a plurality of first signal lines and a plurality of second signal lines intersect each other. In an exemplary embodiment, the first signal line may be a plurality of word lines, and the second signal line may be a plurality of bit lines. In another exemplary embodiment, the first signal line may be a plurality of bit lines, and the second signal line may be a plurality of word lines. The memory device 100 including the memory cell array 110 may be referred to as a cross-point memory device.

[0029] In an exemplary embodiment, each bit line may include a global bit line and at least one local bit line. For example, each bit line may include a global bit line and at least one local bit line electrically connected to the global bit line through a local-selected transistor. Figure 4 An example of the meaning of a bit line including a global bit line and at least one local bit line is shown in , where global bit lines GBL1, GBL2, and GBL3 are arranged horizontally on a page and connected to a plurality of local bit lines in a group of LBL11 / LBL12 / LBL13, LBL21 / LBL22 / LBL23, LBL31 / LBL32 / LBL33 arranged vertically on the page. Each combination of a global bit line and one or more connected local bit lines may be considered as a separate bit line, but even a combination of a single global bit line and a single connected local bit line may be referred to as a "bit line" in the plural form.

[0030] In an exemplary embodiment, the global bit line may be connected to the compensation circuit 170 through a global-selected transistor. For example, when the bit line is selected, the global-selected transistor and the local-selected transistor may be turned on. The memory cells may be connected to at least one local bit line, respectively.

[0031] The memory cell array 110 may include a plurality of memory cells arranged in rows and columns. In an embodiment, the memory cell may include a resistive memory cell, each of which includes a variable resistance device (not shown). For example, when the variable resistance device is a phase change material (GST, Ge-Sb-Te) having a resistance that changes according to temperature, the memory device 100 may be a phase change random access memory (PRAM). As another example, when the variable resistance device includes an upper electrode, a lower electrode, and a composite metal oxide therebetween, the memory device 100 may be a resistive random access memory (RRAM). As another example, when the variable resistance device includes a magnetic upper electrode, a magnetic lower electrode, and a dielectric therebetween, the memory device 100 may be a magnetic random access memory (MRAM). Therefore, the memory device 100 may be referred to as a resistive memory device, and the memory system 1 may be referred to as a resistive memory system.

[0032] In an exemplary embodiment, each memory cell may be a single-level cell (SLC) storing 1-bit data. In this case, the memory cell may have two resistance distributions according to the data stored in the memory cell. In another exemplary embodiment, each memory cell may be a multi-level cell (MLC) that can store 2-bit data. In this case, the memory cell may have four resistance distributions according to the data stored in the memory cell. In another exemplary embodiment, each memory cell may be a triple-level cell (TLC) that can store 3-bit data. In this case, the memory cell may have eight resistance distributions according to the data stored in the memory cell. However, the present disclosure is not limited thereto, and in another embodiment, the memory cell array 110 may include memory cells that can store data equal to or greater than 4 bits, respectively. In addition, the memory cell array 110 may include SLC, MLC, and TLC together.

[0033] For example, the compensation circuit 170 may be a circuit for compensating for a voltage drop caused by a leakage current generated by an unselected memory cell when a voltage is applied to a selected bit line. In an exemplary embodiment, the compensation circuit 170 may sense a leakage current applied to an unselected memory cell (i.e., a memory cell other than a selected memory cell in the memory cell). Based on the result of the sensing, the compensation circuit 170 may also apply the leakage current or a voltage corresponding to the leakage current to the selected bit line. Based on the compensation operation of the compensation circuit 170, a target voltage (e.g., a clamping voltage) may be more accurately applied to the selected memory cell connected to the selected bit line. In addition, by compensating for the leakage current caused by the unselected memory cell, the deviation between the voltages respectively applied to the selected memory cells may be reduced.

[0034] In this specification, a selected memory cell may indicate a memory cell on which a storage operation such as writing, reading, and / or erasing is performed. An unselected memory cell may indicate a memory cell other than the selected memory cell among the memory cells.

[0035] The memory controller 10 and the storage device 100 may be integrated into one semiconductor device. For example, the memory controller 10 and the storage device 100 may be integrated into one semiconductor device and form a memory card. For example, the memory controller 10 and the storage device 100 may be integrated into one semiconductor device and form a personal computer memory card (PCMCIA), a compact flash memory (CF) card, a smart media card (SM / SMC), a memory stick, a universal flash memory (UFS), a multimedia card (MMC), etc. Examples of multimedia cards include a reduced size multimedia card (RS-MMC), an MMCmicro (a micro-size version of MMC), or an SD card (SD). Examples of SD cards include mini SD and micro SD. As another example, the memory controller 10 and the storage device 100 may be integrated into one (ie, the same) semiconductor device and form a solid state disk / drive (SSD).

[0036] Figure 2 is a block diagram of a storage device according to an exemplary embodiment. For example, Figure 2 It can be shown Figure 1 Detailed block diagram of the storage device 100.

[0037] Reference Figure 2 , the memory device 100 may include a memory cell array 110, a control logic 120 (control logic circuit), a voltage generator 130, a row decoder 140, a column decoder 150, a read / write circuit 160, and a compensation circuit 170. Hereinafter, components included in the memory device 100 will be described in detail.

[0038] The memory cells included in the memory cell array 110 may be connected to a first signal line and a second signal line. In an exemplary embodiment, the first signal line may be a word line WL, and the second signal line may be a local bit line LBL and a global bit line GBL. Various voltage signals or current signals are provided via a plurality of word lines WL and a plurality of bit lines BL. Therefore, data DT is written to or read from a selected memory cell, and a write or read operation to an unselected memory cell may be prevented.

[0039] An address ADDR indicating access to a target memory cell may be received together with the command CMD. The address ADDR may include a row address X_ADDR for selecting a word line WL of the memory cell array 110 and a column address Y_ADDR for selecting a local bit line LBL and a global bit line GBL of the memory cell array 110. The address ADDR provided to the memory device 100 may correspond to a physical address PA converted from a logical address LA received from a host HOST in the memory system 1. The row decoder 140 may perform an operation of selecting a word line WL in response to the row address X_ADDR. The column decoder 150 may perform an operation of selecting a bit line BL in response to the column address Y_ADDR. Each of the bit lines BL may include a global bit line GBL and a local bit line LBL. Although each bit line BL is described as including a global bit line GBL and a local bit line LBL, the bit line BL is not limited thereto.

[0040] The control logic 120 (control logic circuit) may output various control signals CTRL_RW based on the command CMD, the address ADDR, and the control signal CTRL received from the memory controller 10 to write data DT to the memory cell array 110 or read data DT from the memory cell array 110. By doing so, the control logic 120 (control logic circuit) may control various operations performed in the memory device 100.

[0041] In an exemplary embodiment, the control logic 120 (control logic circuit) may output the row address X_ADDR to the compensation circuit 170. For example, the compensation circuit 170 may include a variable resistor for sampling the leakage current. The resistance of the variable resistor may vary according to the row address X_ADDR. For example, the variable resistor included in the compensation circuit 170 may vary based on the row address X_ADDR to have the same resistance as the resistance of the local bit line LBL.

[0042] In addition, in an exemplary embodiment, the control logic 120 (control logic circuit) may output the sampling enable signal ENb_SMP and the hold enable signal ENb_HD to the compensation circuit 170. For example, the compensation circuit 170 may perform a sampling operation based on the sampling enable signal ENb_SMP, and perform a hold and compensation operation based on the hold enable signal ENb_HD.

[0043] The voltage generator 130 may generate a write voltage V_write for a write operation and a read voltage V_read for a read operation. The write voltage V_write may include a set voltage, a reset voltage, etc., such as various voltages for a write operation. The write voltage V_write and the read voltage V_read may be provided to the global bit line GBL and the local bit line LBL via the column decoder 150, or may be provided to the word line WL via the row decoder 140.

[0044] The voltage generator 130 may also generate a clamping voltage V_clamp to be applied to the selected bit line. The clamping voltage V_clamp may be a voltage for clamping the bit line to which the selected memory cell is connected at an appropriate level. The clamping voltage V_clamp may have various patterns. For example, the clamping voltage V_clamp may increase according to time, and its step pattern may also increase according to time.

[0045] Although not shown, a reference signal generator may be further provided for generating a reference voltage for data identification. For example, to identify data written to a memory cell, the voltage of a node (e.g., a sensing node) of a local bit line LBL and a reference voltage generated from a reference signal generator may be compared with each other. Alternatively, when a current sensing method is adopted, the reference signal generator may generate a reference current and provide the current to the memory cell array 110. The data value may be identified by comparing the reference voltage with the voltage of the sensing node based on the reference current.

[0046] The read / write circuit 160 may be connected to the memory cell array 110 via the first signal line and / or the second signal line. The read / write circuit 160 may write data DT to the memory cell or read data DT from the memory cell. In addition, the read / write circuit 160 may provide a pass / fail signal P / F to the control logic 120 (control logic circuit) according to the result of identifying the read data. The control logic 120 (control logic circuit) may control the write and read operations of the memory cell array 110 with reference to the pass / fail signal P / F.

[0047] Although the read / write circuit 160 is shown connected to the word line WL via the row decoder 140 , the read / write circuit 160 may also be connected to the local bit line LBL and the global bit line GBL via a column decoder.

[0048] The compensation circuit 170 may be connected to the local bit line LBL and / or the global bit line GBL. The compensation circuit 170 may compensate for the fluctuation of the current (or voltage) to be applied to the selected memory cell based on the leakage current applied to the unselected memory cell in the memory cell. In an exemplary embodiment, the compensation circuit 170 may include: a sampling circuit for generating a sampled value, which is a value generated by sensing the leakage current applied to the unselected memory cell; and a holding circuit for holding the sampled value and compensating the voltage applied to the selected bit line based on the held sampled value. For example, the sampled value may be sensed based on information about the leakage current and information about the variable resistor. In other words, the sampling circuit may track the leakage current applied to the unselected memory cell, and the holding circuit may apply the current (or voltage) compensated based on the leakage current that has been tracked to the selected bit line. In an exemplary embodiment, the sampling circuit and the holding circuit are connected to each other via a switch, and the sampled value may be sent and received based on when the switch is turned on and off.

[0049] For example, in response to the sampling enable signal ENb_SMP, the compensation circuit 170 may perform sampling on the leakage current applied to the unselected memory cell. In addition, the compensation circuit 170 may maintain the sampled value of the leakage current in response to the hold enable signal ENb_HD. The compensation circuit 170 may perform a compensation operation based on the maintained sampled value. A detailed description thereof will be described later.

[0050] Figure 3 Show Figure 2 Detailed configuration of the memory cell array 110 is shown in FIG.

[0051] Reference Figure 3 , the memory cell array 110 may include a plurality of memory banks Bank_0 to Bank_N. The memory banks Bank_0 to Bank_N may be arranged in one direction in the memory cell array 110. Each of the memory banks Bank_0 to Bank_N may include a plurality of tiles Tile1 to TileM. For example, a body may be a unit including tiles Tile1 to TileM, and a tile may be a unit including a plurality of memory cells. Although the units of a body and a tile are shown for ease of explanation, the configuration of the body and the tile is not limited thereto. For example, a body may be classified into a plurality of area units, an area may be classified into a plurality of bay units, and a bay may be classified into a tile unit.

[0052] Figure 4 It is shown Figure 3 A circuit diagram of an exemplary embodiment of a tile is shown in FIG.

[0053] For example, the tile Tile1 may be a resistive memory having a three-dimensional structure including a plurality of layers F1 and F2, and Figure 3Each of the tiles Tile1 to TileM shown in FIG. Figure 4 As shown in the implementation. Tile1 may include a plurality of global bit lines GBL1 to GBL3, a plurality of local bit lines LBL11 to LBL33, a plurality of local bit line selection lines SLY1 to SLY3, and a plurality of word lines WL11 to WL24. Tile1 may also include a plurality of memory cells MC and a plurality of local selection transistors LY11 to LY33. The number of global bit lines, the number of local bit lines, the number of local bit line selection lines, the number of word lines, the number of memory cells, and the number of local selection transistors may vary according to the embodiment. In addition, although a resistive memory having a three-dimensional structure is described in the embodiment, it will be understood by those skilled in the art that the present disclosure is not limited thereto.

[0054] The global bit lines GBL1 to GBL3 are arranged away from each other in the first direction and can extend in the second direction. The global bit lines GBL1 to GBL3 can be connected to the local bit lines LBL11 to LBL33 via the local selection transistors LY11 to LY33, respectively. For example, one end (e.g., source end) of the local selection transistor LY11 can be connected to the global bit line GBL1. The other end (e.g., drain end) of the local selection transistor LY11 can be connected to the local bit line LBL11.

[0055] The local bit line selection lines SLY1 to SLY3 may be arranged away from each other at certain intervals in the second direction and may extend in the first direction. The local bit line selection lines SLY1 to SLY3 may be connected to the gate terminals of the local selection transistors LY11 to LY33. For example, the local bit line selection line SLY may be connected to the gate terminals of the local selection transistors LY11, LY21, and LY31.

[0056] The local bit lines LBL11 to LBL33 may be arranged away from each other at certain intervals in the first direction and the second direction, respectively, and may extend in the third direction. In addition, the word lines WL11 to WL24 having the local bit lines LBL11 to LBL33 therebetween may be arranged away from each other in the second direction and may extend in the first direction. For example, the local bit lines LBL11, LBL21, and LBL31 may be arranged between the word lines WL11 and WL12 or between the word lines WL21 and WL22.

[0057] One end of each memory cell MC may be connected to a word line. The other end of each memory cell MC may be connected to a local bit line. Therefore, a write current (or voltage) or a read current (or voltage) may be applied to each memory cell MC via a bit line or a word line connected to each memory cell MC.

[0058] FIG. 5A to FIG. 5CIt is shown separately Figure 4 A circuit diagram of an exemplary embodiment of a memory cell is shown in FIG.

[0059] Reference Figure 5A , the memory cell MC may include a variable resistance device R and a selection device S. In an embodiment, the variable resistance device R may be referred to as a variable resistor (or variable resistance material), and the selection device S may be referred to as a switching device.

[0060] In an embodiment, the variable resistance device R may be connected to the local bit line LBL11 and the selection device S. The selection device S may be connected to the variable resistance device R and the word line WL11. However, the above devices are not limited thereto, and optionally, the selection device S may be connected to the local bit line LBL11 and the variable resistance device R, and the variable resistance device R may be connected to the selection device S and the word line WL11.

[0061] The variable resistance device R can be changed to have one of a plurality of resistance states in response to an electric pulse applied to the variable resistance device R. According to an exemplary embodiment, the variable resistance device R may include a phase change material having a crystal state that changes with the amount of current. Various materials can be used as phase change materials, such as GaSb, InSb, InSe, Sb2Te3, GeTe generated by combining two elements, GeSbTe, GaSeTe, InSbTe, SnSb2Te4, InSbGe generated by combining three elements, AgInSbTe, (GeSn)SbTe, GeSb(SeTe), Te81Ge15Sb2S2, etc. generated by combining four elements.

[0062] The phase change material may have an amorphous state with relatively high resistance and a crystalline state with relatively low resistance. The phase of the phase change material may change due to Joule heat generated according to the amount of current. In addition, the above phase change may be used to write data.

[0063] In another embodiment, the variable resistance device R may replace the phase change material, including perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials.

[0064] The selection device S may control the current supply to the variable resistance device R according to the voltage applied to the word line WL11 connected to the selection device S. The selection device S may be an Ovonic threshold switch (OTS) including a chalcogenide compound. The OTS may be formed of a material including at least one of arsenic (AS), germanium (Ge), selenium (Se), tellurium (Te), silicon (Si), bismuth (Bi), sodium (S), and antimony (Sb). In particular, the OTS may be formed of a material included in a 6-element system formed by adding selenium (Se) and sulfur (S) to a compound including germanium (Ge), silicon (Si), arsenic (As), and tellurium (Te).

[0065] Reference Figure 5B , the memory cell MCa may include a variable resistance device Ra, and the variable resistance device Ra may be connected to the local bit line LBL11 and the word line WL11. The memory cell MCa may store data by using voltages respectively applied to the local bit line LBL11 and the word line WL11.

[0066] Reference Figure 5C , the memory cell MCb may include a variable resistance device Rb and a bidirectional diode Db. The variable resistance device Rb may include a resistance material for storing data. The bidirectional diode Db may be connected to the variable resistance device Rb and the local bit line LBL11. The variable resistance device Rb may be connected to the word line WL11 and the bidirectional diode Db. The positions of the bidirectional diode Db and the variable resistance device Rb may be changed with each other. By the bidirectional diode Db, the leakage current flowing in the unselected resistive memory cell may be blocked.

[0067] Figure 6 is a diagram for illustrating and explaining the operation of a compensation circuit according to an exemplary embodiment. Figure 6 There are shown a compensation circuit 170 and memory cells MC11, MC12, and MC21 connected to the compensation circuit 170. In the following description, the operation of the compensation circuit 170 may be described based on the assumption that the memory cell MC11 is a selected memory cell and MC12 and MC21 are respectively unselected memory cells.

[0068] Reference Figure 6 , since the memory cell MC11 is a selection memory cell, the global bit line GBL1 and the local bit line LBL11 may be selection bit lines. The global bit line GBL1 may include a parasitic resistor R_GBL. The local bit line LBL11 may include parasitic resistors R_LBL11_1 and R_LBL11_2. Each of the global selection transistor GY and the local selection transistor LY may include a parasitic resistor.

[0069] A current (or voltage) for writing and / or reading data may be applied to the selected memory cell MC11 via the selected bit line (i.e., the global bit line GBL1 and the local bit line LBL11). In this case, a leakage current (or leakage voltage) may be inevitably but undesirably applied to the unselected memory cells MC12 and MC21.

[0070] In other words, due to the parasitic resistance of the global bit line GBL1, the local bit line LBL11, the global selection transistor GY, and the local selection transistor LY, and also due to the leakage current applied to the unselected memory cells MC12 and MC21, the preset voltage (e.g., the clamping voltage V_clamp) may be irregularly applied to the selected memory cell MC11. However, the compensation circuit 170 according to the exemplary embodiment can regularly control the voltage applied to all selected memory cells by compensating for the voltage applied to the selected memory cell MC11 due to the parasitic resistance and the leakage current.

[0071] In detail, the compensation circuit 170 may include a sampling circuit 172 and a holding circuit 176. The compensation circuit 170 may include a switch, and the sampling circuit 172 and the holding circuit 176 may be connected to each other via the switch SW.

[0072] In an exemplary embodiment, the sampling circuit 172 may generate a sampling value, which is a value generated by sensing a leakage current applied to the unselected memory cells MC12 and MC21, in response to the sampling enable signal ENb_SMP and the row address X_ADDR. During the sampling operation of the sampling circuit 172, the switch SW may be turned on or off based on the sampling enable signal. For example, during the sampling operation of the sampling circuit 172, the holding circuit 176 may be disabled in response to the holding enable signal ENb_HD. However, the operation of the aforementioned circuit is not limited thereto.

[0073] In an exemplary embodiment, the holding circuit 176 may receive a sampled value from the sampling circuit 172 in response to the holding enable signal ENb_HD, hold the sampled value, and compensate the voltage applied to the selected bit line based on the held sampled value. The switch SW may be turned off during the holding and compensation operation of the holding circuit 176. For example, during the holding and compensation operation of the holding circuit 176, the sampling circuit 172 may be disabled in response to the sampling enable signal ENb_SMP. However, the operation of the aforementioned circuit is not limited thereto.

[0074] FIG. 7A to FIG. 7D is a diagram for illustrating and explaining the operation of a compensation circuit according to an exemplary embodiment. More specifically, Fig. 7A A diagram showing a compensation circuit and a storage cell. Figure 7B A timing diagram is shown for signals applied to the compensation circuit. Figure 7CAn equivalent circuit of the compensation circuit during sampling operation is shown. Fig.7D The equivalent circuit of the compensation circuit during the hold and compensation operation is shown.

[0075] Reference Fig. 7A , showing an example of a detailed configuration of a sampling circuit 172 and a holding circuit 176 included in a compensation circuit, for example, a compensation circuit 170 (see Figure 6 ). The sampling circuit 172 may include a first transistor TR1, a second transistor TR2, an amplifier AMP, a first resistor R_C1, and a second resistor R_C2. In an embodiment, the first resistor R_C1 is composed of one or more fixed resistors, and the second resistor R_C2 is composed of one or more variable resistors, but the embodiment is not limited thereto.

[0076] The power supply voltage VPP may be applied to one end of the first transistor TR1. A first signal, for example, a sampling enable signal ENb_SMP1, may be applied to the gate end of the first transistor TR1. In one example, the sampling enable signal ENb_SMP1 may be the same signal as the sampling enable signal ENb_SMP applied to the switch SW. As another example, the sampling enable signal ENb_SMP1 may be a signal different from the sampling enable signal ENb_SMP applied to the switch SW. The second transistor TR2 may be connected to the first transistor TR1 via a node. One end of the second transistor TR2 may be adjacent to and electrically connected to the first resistor R_C1, and electrically connected to the second resistor R_C2. The gate end of the second transistor TR2 may be connected to the output end of the amplifier AMP. A predetermined voltage, for example, a clamping voltage V_clamp, may be applied to the positive input end (or non-inverting input end) of the amplifier AMP. The negative input end (or inverting input end) of the amplifier AMP may be connected to the second resistor R_C2. In addition, the output end of the amplifier AMP may be connected to the gate end of the second transistor TR2 and the switch SW.

[0077] The holding circuit 176 may include a third transistor TR3 and a fourth transistor TR4. A power supply voltage VPP may be applied to one end of the third transistor TR3. A holding enable signal ENb_HD may be applied to the gate end of the third transistor TR3. The fourth transistor TR4 is connected to the third transistor TR3 via a node. One end of the fourth transistor TR4 is connected to the second resistor R_C2. The gate end of the fourth transistor TR4 may be connected to one end of the switch SW. As described above, the other end of the switch SW is connected to the gate end of the second transistor TR2 and the output end of the amplifier AMP.

[0078] The switch SW may include a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor connected in parallel to each other. Each of the PMOS transistor and the NMOS transistor of the switch SW may receive a sampling enable signal ENb_SMP and a compensation sampling enable signal EN_SMP. However, the foregoing embodiments are merely examples, and those skilled in the art will appreciate that the switch SW may be implemented in various configurations.

[0079] Further references Figure 7B , during the sampling operation of the sampling circuit 172, the sampling enable signal ENb_SMP and the compensation sampling enable signal EN_SMP may be activated. In addition, during the sampling operation of the sampling circuit 172, the hold enable signal ENb_HD may be deactivated. In an embodiment, although the sampling enable signal ENb_SMP and the hold enable signal ENb_HD are described as being activated with a logic low and the compensation sampling enable signal EN_SMP is described as being activated with a logic high, the activation of the above signals is only an example and is not limited thereto. For example, during the sampling operation of the sampling circuit 172, an unselected word line voltage may be applied to the word line WL.

[0080] Further references Figure 7C , the third transistor TR3 is turned off during the sampling operation of the sampling circuit 172. Therefore, no current may be applied to the fourth transistor TR4. The switch SW may be turned on or off based on the sampling enable signal. The amplifier AMP, the second transistor TR2, the first resistor R_C1, and the second resistor R_C2 form a negative feedback. Therefore, the clamping voltage V_clamp may be applied to the first node N1. In addition, when the leakage current applied to the unselected memory cells MC12 and MC21 is referred to as Ioff, the gate voltage of the second transistor R2 may be expressed as [Equation 1].

[0081] [Equation 1]

[0082] V1=VN1+Ioff×(R_C1+R_C2)+VGS_TR2

[0083] As described above, VN1 is equal to V_clamp, and VGS_TR2 may be a gate-source voltage of the second transistor TR2. In an exemplary embodiment, the resistance of the first resistor R_C1 may be substantially the same as (equal to) the sum of the resistance of the global bit line GBL1, the resistance of the global selection transistor GY, and the resistance of the local selection transistor LY. In an exemplary embodiment, the first resistor R_C1 may be based on a row address (e.g., a row address X_ADDR (see Figure 2 )) changes the resistance of the second resistor R_C2. For example, based on the row address, for example, the row address X_ADDR (see Figure 2), the second resistor R_C2 may be changed to have a resistance substantially the same as that of the local bit line LBL11.

[0084] In [Equation 1], the value of Ioff*(R_C1+R_C2) may be a sampled value calculated based on the leakage current applied to the unselected memory cells MC12 and MC21. That is, the value of Ioff*(R_C1+R_C2) may be a sampled value generated by sampling the leakage current in the form of a voltage. In other words, the sampled value generated by the sampling circuit 172 may include information about the leakage current, information about the resistance of the global bit line GBL1 and the local bit line LBL11, and information about the resistance of the global selection transistor GY and the local selection transistor LY. Therefore, the sampled value may include, reflect, or be based on information about the leakage current, and / or information about the resistance value of the first resistor R_C1 and / or information about the resistance value of the second resistor R_C2.

[0085] Refer again Figure 7B , the hold enable signal ENb_HD may be activated during the hold and compensation operation of the hold circuit 176. In addition, the sampling enable signal ENb_SMP and the compensation sampling enable signal EN_SMP may be deactivated during the hold and compensation operation of the hold circuit 176.

[0086] Further references Fig.7D , during the holding and compensation operation of the holding circuit 176, the first transistor TR1 is turned off. Therefore, the current may not be applied to the second transistor TR2, the first resistor R_C1 and the second resistor R_C2. The switch SW may be disconnected. In this case, at the gate terminal of the fourth transistor TR4, the voltage V1 represented by [Equation 1] may be maintained. For example, when the voltage of V1 is applied to the gate capacitor of the fourth transistor TR4 during the sampling operation and therefore the switch SW is disconnected during the holding and compensation operation, the gate voltage of the fourth transistor TR4 may be maintained as V1. As another exemplary embodiment, the holding circuit 176 may further include an additional capacitor connected to the gate terminal of the fourth transistor TR4 and ground.

[0087] When the third transistor TR3 is turned on and the gate voltage of the fourth transistor TR4 is maintained as V1, the voltage of the first node N1 may be expressed as the following [Equation 2].

[0088] [Equation 2]

[0089] VN1=V_clamp+Ioff×(R_C1+R_C2)

[0090] =V_clamp+Ioff×(R_GBL1_GY_LY+R_LBL11)

[0091] =V_clamp+ΔVBL

[0092] In other words, during the holding and compensation operation, the holding circuit 176 can output a voltage calculated by compensating the clamping voltage V_clamp using the sampled value to the selected bit line, that is, the global bit line GBL1 and the local bit line LBL11. As a result, the compensation circuit 170 can compensate for the leakage current applied to the unselected memory cells MC12 and MC21, the resistor R_GBL of the global bit line GBL1 by the resistance of the global selection transistor GY, the resistance of the local selection transistor, and the resistance of the local bit line LBL11. The compensation circuit 170 can be operated so that the clamping voltage V_clamp is regularly applied to the selected memory cell MC11.

[0093] The memory device according to the exemplary embodiment can more accurately apply the target voltage (e.g., the clamping voltage V_clamp) to the selected memory cell by including the compensation circuit 170. In addition, by compensating for the leakage current caused by the unselected memory cell, the deviation between the voltages respectively applied to the selected memory cells can be reduced. Therefore, the resistance distribution of the resistive memory cell can be improved, thereby improving the stability of the data stored in the resistive memory cell.

[0094] Figure 8 It is shown Fig. 7A A circuit diagram of an example of a detailed configuration of the second resistor R_C2 is shown in FIG.

[0095] Reference Figure 8 , the second resistor R_C2 may include a plurality of transistors TR11 to TR15 and a plurality of resistance devices R11 to R14. Although the second resistor R_C2 is illustrated as including five transistors and four resistance devices, this is only for convenience of explanation and the embodiment is not limited thereto.

[0096] In an exemplary embodiment, the resistance of the second resistor R_C2 may be changed based on the row address X_ADDR. For example, the transistors TR11 to TR15 may be turned on / off based on the row address X_ADDR. Based on the row address X_ADDR, the second resistor R_C2 may be changed to have a resistance substantially the same as that of the local bit line corresponding to the row address X_ADDR.

[0097] Fig. 9 A graph illustrating resistance distribution of a memory cell in a memory device including a compensation circuit according to an example embodiment.

[0098] Reference Fig. 9 , showing a distribution diagram of the number of cells representing resistance. The letter "A" indicates that a compensation circuit (e.g., Figure 1, and letter “B” represents a line showing a distribution of a comparative example in which no compensation circuit is provided. When there is a compensation circuit (e.g., compensation circuit 170 (see Figure 1 )), the gap ΔCRW1 between the set resistance distribution and the reset resistance distribution can be wider than the gap ΔCRW2 between the set resistance distribution and the reset resistance distribution. In other words, since the memory device can compensate for the loss of the clamping voltage due to the leakage current applied to the unselected memory cell, the resistance of the global bit line and the local bit line, and the resistance of the global selection transistor and the local selection transistor, the resistance distribution of the memory cell can be improved. Therefore, the stability of the data stored in the memory cell can be improved.

[0099] Fig.10 is a diagram for illustrating and explaining the operation of a compensation circuit according to another exemplary embodiment. Fig.10 The configuration shown in will not give Fig. 7A The description of the configuration that the configuration overlaps.

[0100] Reference Fig.10 , including in a compensation circuit (eg, compensation circuit 170 (see Figure 6 )) The sampling circuit 172a in may include a first transistor TR1a, a first resistor R_C1a, and a second resistor R_C2a. A power supply voltage VPP may be applied to one end of the first transistor TR1a, and a first switch SW1a may be applied to a gate end of the first transistor TR1a. The other end of the first transistor TR1a may be connected to the first resistor R_C1a, and may also be connected to one end of a third switch SW3a, and the other end of the third switch SW3a is connected to a boost capacitor C_B. The first resistor R_C1a and the second resistor R_C2a may be connected in series with each other.

[0101] The holding circuit 176a can be connected to the sampling circuit 172a via the first switch SW1a. The holding circuit 176a can include a third transistor TR3a, a fourth transistor TR4a, an amplifier AMPa and a boost capacitor C_B. The power supply voltage VPP is applied to one end of the third transistor TR3a. The gate terminal of the third transistor TR3a can be connected to one end of the first switch SW1a. The gate terminal of the third transistor TR3a can also be connected to the other end (e.g., drain terminal) of the third transistor TR3a. That is, one end of the third transistor is applied with the power supply voltage VPP, the other end is connected to the gate terminal of the third transistor TR3a, and the gate terminal is connected to one end of the first switch SW1a. One end of the fourth transistor TR4a can be connected to the gate terminal of the third transistor TR3a. The other end of the fourth transistor TR4a can be connected to the negative input terminal (or inverting input terminal) of the amplifier AMPa. In addition, the gate terminal of the fourth transistor TR4a can be connected to the output terminal of the amplifier AMPa.

[0102] The positive input terminal (or non-inverting input terminal) of the amplifier AMPa can be connected to one end of the second switch SW2, and the other end of the second switch SW2a is applied with a (predetermined) clamping voltage V_clamp. In addition, the positive input terminal (or non-inverting input terminal) of the amplifier AMPa can be connected to one end of the boost capacitor C_B, and the other end of the boost capacitor C_B is connected to the third switch SW3a.

[0103] In an exemplary embodiment, before the sampling operation of the sampling circuit 172a, the first switch SW1a and the third switch SW3a may be turned off, and the second switch SW2a may be turned on. Next, during the sampling operation of the sampling circuit 172a, the first switch SW1a may be turned on based on the sampling enable signal, and the second switch SW2a may be turned off based on the sampling enable signal. When the first switch SW1a is turned on, the first transistor TR1a and the third transistor TR3a may form a current mirror. In addition, as the voltage of the first node N1a, the clamping voltage V_clamp may be applied based on the sound feedback of the amplifier AMPa and the fourth transistor TR4a. Therefore, during the sampling operation, the leakage current applied to the unselected memory cells MC12 and MC21 may be copied by the current mirror and applied to the first resistor R_C1a and the second resistor R_C2a. Therefore, the voltage applied to the first resistor R_C1a and the second resistor R_C2a may be expressed as the following [Equation 3].

[0104] [Equation 3]

[0105] V=Ioff×(R_C1a+R_C2a)

[0106] In an exemplary embodiment, the resistance of the first resistor R_C1a may be substantially the same as (equal to) the sum of the resistance of the global bit line GBL1a, the resistance of the global selection transistor GYa, and the resistance of the local selection transistor LYa. In an exemplary embodiment, the first resistor R_C1a may be substantially the same as (equal to) the sum of the resistance of the global bit line GBL1a, the resistance of the global selection transistor GYa, and the resistance of the local selection transistor LYa. Figure 2 )) to change the resistance of the second resistor R_C2a. For example, based on the row address, for example, the row address X_ADDR (see Figure 2 ), the second resistor R_C2a may be changed to have substantially the same resistance as that of the local bit line LBL11a.

[0107] Next, during the holding and compensation operation of the holding circuit 176a, the third switch SW3a may be turned on. When the third switch SW3a is turned on, the boost capacitor C_B is boosted. Therefore, the voltage applied to the positive input terminal of the amplifier AMPa and the first node N1a may be expressed as the following [Equation 4].

[0108] [Equation 4]

[0109] VN1a=V_clamp+Ioff×(R_C1a+R_C2a)

[0110] =V_clamp+Ioff×(R_GBL1a_GYa_LYa+R_LBL11a)

[0111] =V_clamp+ΔVBL

[0112] In other words, during the holding and compensation operation, the holding circuit 176a may output a voltage calculated by compensating the clamp voltage V_clamp with the sampled value. The voltage is output to the selection bit lines, that is, the global selection bit line GBL1a and the local selection bit line LBL11a.

[0113] Fig.11 FIG. 1 is a diagram for illustrating and explaining the operation of a compensation circuit according to another exemplary embodiment. Fig.11 In the configuration shown in Fig. 7A The description of the configuration that the configuration overlaps.

[0114] Reference Fig.11 , including in a compensation circuit (eg, compensation circuit 170 (see Figure 6)) The sampling circuit 172b in may include a first transistor TR1b, a first resistor R_C1b, a second resistor R_C2b, and a first amplifier AMPb1. The transistor TR1b may have one end (first end) and the other end (second end). The power supply voltage VPP is applied to one end of the first transistor TR1b, and the first switch SW1b may be applied to the gate end of the first transistor TR1b. The other end of the first transistor TR1b may be connected to the first resistor R_C1b, and may also be connected to the positive input end (or non-inverting input end) of the first amplifier AMPb1 (hereinafter referred to as the second node N2b). The first resistor R_C1b and the second resistor R_C2b may be connected in series with each other.

[0115] The holding circuit 176b can be connected to the sampling circuit 172b via the first switch SW1b. The holding circuit 176a can include a third transistor TR3b, a fourth transistor TR4b and a second amplifier AMPb2. The power supply voltage VPP can be applied to one end of the third transistor TR3b. The gate end of the third transistor TR3b can be connected to one end of the first switch SW1b. The gate end of the third transistor TR3b can also be connected to the other end (e.g., drain end) of the third transistor TR3b. One end of the fourth transistor TR4b can be connected to the gate end of the third transistor TR3b, and the other end of the fourth transistor TR4b can be connected to the negative input end (or inverting input end) of the second amplifier AMPb2. In addition, the gate end of the fourth transistor TR4b can be connected to the output end of the first amplifier AMPb1 and the second amplifier AMPb2.

[0116] The ground voltage GND may be applied to a negative input terminal (or an inverting input terminal) of the first amplifier AMPb1 . The clamp voltage V_clamp may be applied to a positive input terminal (or a non-inverting input terminal) of the second amplifier AMPb2 .

[0117] In an exemplary embodiment, a sampling operation and a holding and compensation operation may be performed simultaneously. More specifically, during the sampling operation (or during the holding and compensation operation), the first switch SW1b may be turned on based on a sampling enable signal. When the first switch SW1b is turned on, the first transistor TR1b and the third transistor TR3b may form a current mirror. Therefore, the leakage current applied to the unselected memory cells MC12 and MC21 is applied to the first resistor R_C1b and the second resistor R_C2b via the current mirror. Therefore, the voltage of the second node N2b may be expressed as the following [Equation 5].

[0118] [Equation 5]

[0119] VN2b=Ioff×(R_C1b+R_C2b)

[0120] When the voltage of the second node N2b is expressed as [Equation 5] and the open-loop gains of the first amplifier AMPb1 and the second amplifier AMPb2 are A1 and A2, respectively, the voltage of the first node N1b may be expressed as the following [Equation 6].

[0121] [Equation 6]

[0122]

[0123]

[0124] In an embodiment, the first amplifier AMPb1 and the second amplifier AMPb2 may be referred to as a mixer. For example, A1 and A2 as open-loop gains may be substantially equal to each other. However, A1 and A2 are not limited thereto. As another example, A1 and A2 may be different from each other. Therefore, during a sampling operation (or during a holding and compensation operation), the holding circuit 176 may output a voltage generated by compensating the clamping voltage V_clamp with a sampled value to a selection bit line, that is, a global selection bit line GBL1b and a local selection bit line LBL11.

[0125] Fig.12 is a block diagram illustrating a computing system including a memory system according to an exemplary embodiment.

[0126] Reference Fig.12 , the computing system 1000 may include a storage system 1100, a processor 1200, a RAM 1300, an input / output device 1400, and a power supply 1500. Fig.12 Not shown, but computing system 1000 may also include ports that can communicate with video cards, sound cards, memory cards, USB devices, or other electronic devices. Computing system 1000 may be implemented as a personal computer or a mobile electronic device, such as a laptop, mobile phone, personal digital assistant (PDA), camera, etc.

[0127] The processor 1200 may perform a specific operation or task. According to an embodiment, the processor 1200 may be a microprocessor or a central processing unit (CPU). The processor 1200 may communicate with the RAM 1300, the input / output device 1400, and the storage system 1100 by using a bus 1600 including an address bus, a control bus, a data bus, etc. In this case, the storage system 1100 may communicate with the RAM 1300, the input / output device 1400, and the storage system 1100 according to the embodiment. Figures 1 to 11 This is achieved by the embodiments described in .

[0128] According to an embodiment, the processor 1200 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0129] The RAM 1300 may store data required for the operation of the computing system 1000. For example, the RAM 1300 may be implemented as a dynamic random access memory (DRAM), a mobile DRAM, a static RAM (SRAM), a phase change RAM (PRAM), a ferroelectric RAM (FRAM), a resistive RAM (RRAM), and / or a magnetic RAM (MRAM).

[0130] The input / output device 1400 may include components for input, such as a keyboard, a keypad, and a mouse, etc., and components for output, such as a printer, a display, etc. The power supply 1500 may provide a dynamic voltage required for the operation of the computing system 1000 .

[0131] Exemplary embodiments have been described in the accompanying drawings and throughout the specification. Although the inventive concepts of the present disclosure have been specifically shown and described with reference to their embodiments, these embodiments are considered to be descriptive rather than limiting. It will be readily appreciated by those skilled in the art that various modifications and other equivalent embodiments are possible. Therefore, the true technical scope of the inventive concepts described herein is limited by the technical spirit of the appended claims.

Claims

1. A storage device, comprising: A memory cell array, comprising a plurality of memory cells; a plurality of bit lines, wherein each of the plurality of bit lines is connected to at least one of the plurality of memory cells, and a predetermined voltage is applied to a selection bit line connected to a selection memory cell among the plurality of bit lines; a compensation circuit including a sampling circuit and a holding circuit, the sampling circuit generating a sampled value by sensing a leakage current applied to an unselected memory cell among a plurality of memory cells, and the holding circuit compensating a voltage applied to a selected bit line based on the sampled value; and A control logic circuit outputs a sampling enable signal for controlling the enablement of the sampling circuit and a holding enable signal for controlling the enablement of the holding circuit; in: The control logic circuit also outputs a row address of the memory cell array based on an address received from outside the memory device, The sampling circuit also includes a first resistor and a second resistor connected in series with each other, and The resistance of the second resistor is changed based on the row address.

2. The storage device according to claim 1, wherein: The compensation circuit further includes a switch, one end of the switch is connected to the sampling circuit, the other end of the switch is connected to the holding circuit, and the switch is controlled to be turned on or off based on the sampling enable signal.

3. The storage device according to claim 2, wherein: The switch is turned on when the sampling circuit is enabled in response to the sampling enable signal.

4. The storage device according to claim 1, wherein: Each of the plurality of bit lines includes a global bit line and at least one local bit line, the local bit line being electrically connected to the global bit line via a local selection transistor, The global bit line is electrically connected to the sampling circuit via a global selection transistor, and at least one local bit line is electrically connected to at least one of the plurality of memory cells.

5. The storage device according to claim 4, wherein: The first resistor includes a resistance substantially equal to a sum of a resistance of the global bit line, a resistance of the local select transistor, and a resistance of the global select transistor.

6. The storage device according to claim 4, wherein: The sampling circuit includes: A first transistor having one terminal to which a power supply voltage is applied and another terminal to which a first signal is applied; a second transistor connected to the first transistor via the node and having one end electrically connected to the first resistor and the second resistor; and The amplifier has a positive input terminal to which a predetermined voltage is applied, a negative input terminal connected to the second resistor, and an output terminal connected to the gate terminal of the second transistor.

7. The storage device according to claim 6, wherein: The first transistor is turned on when the first signal is activated, and when the first transistor is turned on, the sampling circuit transmits the sampled value to the holding circuit.

8. The storage device according to claim 6, wherein: The holding circuit includes: a third transistor having one terminal to which the power supply voltage is applied and a gate terminal to which the hold enable signal is applied; and A fourth transistor is connected to the third transistor via a node, a gate terminal of the fourth transistor is connected to one end of a switch, the other end of the switch is connected to the output terminal of the amplifier, and one end of the fourth transistor is electrically connected to the first resistor and the second resistor.

9. The storage device according to claim 4, wherein: The sampling circuit includes a first transistor having one end to which a power supply voltage is applied and the other end electrically connected to a first resistor and a second resistor.

10. The storage device according to claim 9, wherein: The holding circuit includes: A third transistor includes one end to which a power supply voltage is applied, a gate end, and the other end connected to the gate end, wherein the gate end is connected to one end of the first switch, and the other end of the first switch is connected to the gate end of the first transistor; a fourth transistor having one terminal connected to the gate terminal of the third transistor; an amplifier having a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal being connected to one terminal of a second switch, the second switch having the other terminal to which a predetermined voltage is applied, the negative input terminal being connected to the other terminal of a fourth transistor, and the output terminal being connected to a gate terminal of the fourth transistor; and The boost capacitor is connected between one end of the third switch and the positive input terminal of the amplifier, and the other end of the third switch is electrically connected to the first resistor and the second resistor.

11. The storage device according to claim 4, wherein: The sampling circuit includes: a first transistor having one end to which a power supply voltage is applied and the other end connected to a first resistor; and The first amplifier has a positive input terminal connected to the other end of the first transistor, a negative input terminal to which a ground voltage is applied, and an output terminal connected to the holding circuit.

12. The storage device according to claim 11, wherein: The holding circuit includes: A third transistor includes one end to which a power supply voltage is applied, a gate end, and the other end connected to the gate end, wherein the gate end is connected to one end of the first switch, and the other end of the first switch is connected to the gate end of the first transistor; a fourth transistor having one terminal connected to the gate terminal of the third transistor, and a gate terminal of the fourth transistor connected to the output terminal of the first amplifier; and The second amplifier has a positive input terminal to which a predetermined voltage is applied, a negative input terminal connected to the other terminal of the fourth transistor, and an output terminal connected to the gate terminal of the fourth transistor.

13. A resistive memory device comprising: A memory cell array, comprising a plurality of word lines, a plurality of bit lines and a plurality of memory cells; a control logic circuit that outputs a row address of a plurality of word lines based on an address received from an external device; as well as a compensation circuit including a sampling circuit, a holding circuit, and a switch, the sampling circuit generating a sampled value by sensing a leakage current applied to a bit line connected to a selected memory cell on which a storage operation is performed among a plurality of memory cells, the holding circuit holding the sampled value and compensating a voltage applied to the bit line connected to the selected memory cell based on the sampled value, and the switch having one end connected to the sampling circuit and the other end connected to the holding circuit; in: The sampling circuit further includes a first resistor and a second resistor connected in series with each other, and The second resistor has a resistance that changes based on a row address.

14. The resistive memory device according to claim 13, wherein: The control logic circuit also outputs a sampling enable signal that controls the enablement of the sampling circuit, and The switch is turned on or off based on the sample enable signal.

15. The resistive memory device according to claim 13, wherein: Each of the plurality of bit lines includes a global bit line and at least one local bit line electrically connected to the global bit line via a local selection transistor, and The global bit line is electrically connected to the compensation circuit via a global selection transistor, and at least one local bit line is connected to at least one of the plurality of memory cells.

16. The resistive memory device according to claim 15, wherein: The first resistor has a resistance substantially equal to a sum of a resistance of the global bit line, a resistance of the local selection transistor, and a resistance of the global selection transistor.

17. A resistive memory device, comprising: A memory cell array comprising a plurality of memory cells arranged in rows and columns; bit lines, including a plurality of local bit lines respectively connected to the plurality of memory cells and a plurality of global bit lines connected to at least one of the plurality of local bit lines via local selection transistors; as well as a compensation circuit including a sampling circuit and a holding circuit, the sampling circuit generating a sampling value by sensing a leakage current applied to a bit line connected to a selected memory cell on which a storage operation is performed, and the holding circuit compensating a voltage applied to the bit line connected to the selected memory cell based on the sampling value, in: A plurality of global bit lines, each electrically connected to a sampling circuit through a global selection transistor, The sampling circuit also includes a first resistor having a resistance substantially equal to a sum of a resistance of a global bit line included in a bit line connected to the selected memory cell, a resistance of the local selection transistor, and a resistance of the global selection transistor.

18. The resistive memory device according to claim 17, in, The sampled value includes at least one of information on the leakage current and information on the resistance value of the first resistor.

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