semiconductor devices

Abstract

A semiconductor device is provided. The semiconductor device includes: a first fin pattern and a second fin pattern separated by a first isolation trench and extending in a first direction; a third fin pattern spaced apart from the first fin pattern in a second direction intersecting the first direction and extending in the first direction; a fourth fin pattern separated from the third fin pattern by a second isolation trench; a first gate structure intersecting the first fin pattern and having a portion extending along an upper surface of the first fin pattern; a second gate structure intersecting the second fin pattern and having a portion extending along an upper surface of the second fin pattern; and a first element isolation structure filling the second isolation trench and facing a short side of the first gate structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0068000 filed on June 14, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices. Background Art

[0004] As one of the scaling technologies to increase the density of semiconductor devices, multi-gate transistors have been proposed. A multi-gate transistor can be obtained by forming a fin-shaped or nanowire-shaped multi-channel active pattern (or silicon body) on a substrate and forming a gate on the surface of the multi-channel active pattern.

[0005] Multi-gate transistors can be easily scaled down because they use a three-dimensional (3D) channel. Furthermore, the current control capability of a multi-gate transistor can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. Summary of the Invention

[0006] Aspects of the present disclosure provide a semiconductor device having increased element integration density and improved reliability and performance.

[0007] However, aspects of the present disclosure are not limited to the contents set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to some embodiments of the present disclosure, a semiconductor device is provided, including: a first fin pattern and a second fin pattern, which are separated by a first isolation trench and extend in a first direction; a third fin pattern, which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction; a fourth fin pattern, which is separated from the third fin pattern by a second isolation trench; a first gate structure, which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern; a second gate structure, which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern; and a first element isolation structure, which fills the second isolation trench and faces a short side of the first gate structure.

[0009] According to some embodiments of the present disclosure, a semiconductor device is provided, including: a first fin pattern and a second fin pattern, which are aligned in a first direction serving as a longitudinal direction; a third fin pattern, which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction; a fourth fin pattern, which is separated from the third fin pattern by a first isolation trench; a first gate structure, which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern; a second gate structure, which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern; a third gate structure, which intersects the first fin pattern and the third fin pattern; and a first element isolation structure, which fills the first isolation trench, wherein the upper surface of the first element isolation structure is higher than the upper surface of the third fin pattern.

[0010] According to some embodiments of the present disclosure, a semiconductor device is provided, including: a first fin pattern and a second fin pattern, which are arranged in an n-type metal oxide semiconductor (NMOS) region and aligned in a first direction as a longitudinal direction; a third fin pattern, which is arranged in a p-type metal oxide semiconductor (PMOS) region, is spaced apart from the first fin pattern in a second direction intersecting the first direction, and extends in the first direction; a fourth fin pattern, which is separated from the third fin pattern by a first isolation trench; a first gate structure, which intersects the first fin pattern and has a portion extending along the upper surface of the first fin pattern; a second gate structure, which intersects the second fin pattern and has a portion extending along the upper surface of the second fin pattern; a first element isolation structure, which fills the first isolation trench; and a gate insulating support, which is formed between the first gate structure and the first element isolation structure to contact the first gate structure and the first element isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] These and / or other aspects will become clearer and more readily understood through the following description of the embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 is a schematic plan view of a semiconductor device according to an embodiment;

[0013] Figure 2 It is along Figure 1 A cross-sectional view taken along line AA;

[0014] Figure 3 It is along Figure 1 A cross-sectional view taken along line BB;

[0015] Figure 4 It is along Figure 1 A cross-sectional view taken along line CC;

[0016] Figure 5 It is along Figure 1 A cross-sectional view taken along line DD;

[0017] Figure 6 It is along Figure 1 A cross-sectional view taken along line EE of FIG.

[0018] Figure 7 A semiconductor device according to an embodiment is shown;

[0019] Figure 8 A semiconductor device according to an embodiment is shown;

[0020] Figure 9 A semiconductor device according to an embodiment is shown;

[0021] Figure 10 A semiconductor device according to an embodiment is shown;

[0022] Figure 11 A semiconductor device according to an embodiment is shown;

[0023] Figure 12 and Figure 13 A semiconductor device according to an embodiment is shown;

[0024] Figure 14 and Figure 15 A semiconductor device according to an embodiment is shown;

[0025] Figure 16 A semiconductor device according to an embodiment is shown;

[0026] Figure 17 and Figure 18 A semiconductor device according to an embodiment is shown;

[0027] Figure 19 is a schematic plan view of a semiconductor device according to an embodiment;

[0028] Figure 20 It is along Figure 19 A cross-sectional view taken along line DD;

[0029] Figure 21 is a schematic plan view of a semiconductor device according to an embodiment;

[0030] Figure 22 It is along Figure 21 A cross-sectional view taken along line BB;

[0031] Figure 23 It is along Figure 21 A cross-sectional view taken along line DD;

[0032] Figure 24 It is along Figure 21 A cross-sectional view taken along line FF;

[0033] Figure 25A semiconductor device according to an embodiment is shown;

[0034] Figure 26 A semiconductor device according to an embodiment is shown;

[0035] Figure 27 is a schematic plan view of a semiconductor device according to an embodiment;

[0036] Figure 28 It is along Figure 27 A cross-sectional view taken along line BB;

[0037] Figure 29 is a schematic plan view of a semiconductor device according to an embodiment;

[0038] Figure 30 It is along Figure 29 a cross-sectional view taken along line CC of ; and

[0039] Figures 31 to 34 are views showing some steps of a method of manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0040] In the drawings relating to semiconductor devices according to embodiments, a fin field effect transistor (FinFET) including a channel region having a fin pattern shape is shown as an example. However, embodiments are not limited to FinFETs. Semiconductor devices according to embodiments may also include tunneling FETs, transistors including nanowires, transistors including nanosheets, or three-dimensional (3D) transistors. In addition, semiconductor devices according to embodiments may include bipolar junction transistors, lateral double diffused transistors (LDMOS), and the like.

[0041] Figure 1 is a schematic plan view of a semiconductor device according to an embodiment. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA. Figure 3 It is along Figure 1 A cross-sectional view taken along line BB. Figure 4 It is along Figure 1 A cross-sectional view taken along line CC. Figure 5 It is along Figure 1 A cross-sectional view taken along line DD. Figure 6 It is along Figure 1 For ease of description, Figure 1 The lower interlayer insulating film 191 and the upper interlayer insulating film 192 are not shown.

[0042] It should be understood that although the terms "first", "second", "third" etc. can be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. Unless the context indicates otherwise, these terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part, for example as a naming convention. Therefore, the first element, component, region, layer or part discussed below in one part of the specification can be named as the second element, component, region, layer or part in another part of the claim or specification without departing from the teachings of the present invention. In addition, in some cases, even if "first", "second" etc. are not used to describe a term in the specification, the term can still be referred to as "first" or "second" in the claim to distinguish the different elements claimed for protection from each other.

[0043] Reference Figures 1 to 6 The semiconductor device according to the embodiment includes a first fin pattern 110, a second fin pattern 210, a third fin pattern 310 and a fourth fin pattern 410, a first gate structure 120, a second gate structure 220, a third gate structure 320 and a fourth gate structure 420, a gate insulating support 160 and a first element isolation structure 180.

[0044] The substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may be, but is not limited to, a silicon substrate or a substrate made of other materials such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0045] Each of the first to fourth fin patterns 110, 210, 310, and 410 may protrude from the substrate 100. Each of the first to fourth fin patterns 110, 210, 310, and 410 may extend along a first direction X on the substrate 100. For example, each of the first to fourth fin patterns 110, 210, 310, and 410 may include a long side extending in the first direction X and a short side extending in a second direction Y perpendicular to the first direction X. Each of the first to fourth fin patterns 110, 210, 310, and 410 may be defined by a fin trench FT. For example, each of the long sides 110a, 210a, 310a, and 410a of the first to fourth fin patterns 110, 210, 310, and 410 may be defined by a fin trench FT.

[0046] The first fin pattern 110 and the second fin pattern 210 may be aligned in a first direction X as a longitudinal direction. The first fin pattern 110 and the second fin pattern 210 may be spaced apart in the first direction X. Short sides 110 b of the first fin pattern 110 and short sides 210 b of the second fin pattern 210 may face each other. The first fin pattern 110 and the second fin pattern 210 may be separated by a fin cutting trench ST.

[0047] The third fin pattern 310 and the fourth fin pattern 410 may be aligned in a first direction X, which is a longitudinal direction. The third fin pattern 310 and the fourth fin pattern 410 may be spaced apart in the first direction X. The short side 310b of the third fin pattern 310 and the short side 410b of the fourth fin pattern 410 may face each other. The third fin pattern 310 and the fourth fin pattern 410 may be separated by a first isolation trench 180t. For example, based on the upper surfaces of the first to fourth fin patterns 110, 210, 310, and 410, the width W11 of the fin cutting trench ST in the first direction X is greater than the width W12 of the first isolation trench 180t in the first direction X.

[0048] The third and fourth fin patterns 310 and 410 may be spaced apart from the first fin pattern 110 in the second direction Y. A long side 310a of the third fin pattern 310 may face a long side 110a of the first fin pattern 110, and a long side 410a of the fourth fin pattern 410 may face a long side 210a of the second fin pattern 210. Although each of the first to fourth fin patterns 110, 210, 310, and 410 is shown in plural, embodiments are not limited thereto.

[0049] When the first and second fin patterns 110 and 210 are formed in the first region and the third and fourth fin patterns 310 and 410 are formed in the second region, the first and second regions may be regions where transistors of the same conductivity type are formed, or may be regions where transistors of different conductivity types are formed.

[0050] In the following description, it is assumed that the first and second fin patterns 110 and 210 are formed in an n-type metal oxide semiconductor (NMOS) region, and the third and fourth fin patterns 310 and 410 are formed in a p-type metal oxide semiconductor (PMOS) region.

[0051] Each of the first to fourth fin patterns 110, 210, 310, and 410 may be part of the substrate 100 or may include an epitaxial layer grown from the substrate 100. Each of the first to fourth fin patterns 110, 210, 310, and 410 may include an elemental semiconductor material such as silicon or germanium. Additionally, each of the first to fourth fin patterns 110, 210, 310, and 410 may include a compound semiconductor such as a Group IV-IV compound semiconductor or a Group III-V compound semiconductor. Group IV-IV compound semiconductors may be, for example, binary or ternary compounds including two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds obtained by doping the binary or ternary compounds with Group IV elements. Group III-V compound semiconductors may be, for example, binary, ternary, or quaternary compounds composed of at least one of aluminum (Al), gallium (Ga), and indium (In) (i.e., Group III elements) combined with at least one of phosphorus (P), arsenic (As), and antimony (Sb) (i.e., Group V elements).

[0052] A field insulating layer 105 may be formed on the substrate 100 . The field insulating layer 105 may at least partially fill the fin cutting trench ST and the fin trench FT. The field insulating layer 105 may be disposed on a portion of a sidewall of each of the first to fourth fin patterns 110 , 210 , 310 , and 410 .

[0053] The upper surfaces of the first to fourth fin patterns 110, 210, 310, and 410 may protrude above the upper surface of the field insulating layer 105. The field insulating layer 105 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. In the semiconductor device according to the embodiment, the field insulating layer 105 may fill a portion of the fin cutting trench ST.

[0054] Each of the first to fourth gate structures 120, 220, 320, and 420 may extend along the second direction Y on the field insulation layer 105. The first gate structure 120 may be disposed on the first fin pattern 110 to intersect the first fin pattern 110. The first gate structure 120 may overlap an end portion of the first fin pattern 110, including a short side 110b of the first fin pattern 110. A portion of the first gate structure 120 may extend along an upper surface of each first fin pattern 110.

[0055] The second gate structure 220 may be disposed on the second fin pattern 210 and the fourth fin pattern 410 to intersect the second fin pattern 210 and the fourth fin pattern 410. The second gate structure 220 may overlap an end portion of the second fin pattern 210 including a short side 210 b of the second fin pattern 210. A portion of the second gate structure 220 may extend along an upper surface of each second fin pattern 210.

[0056] The third gate structure 320 may be disposed on the first and third fin patterns 110 and 310 to intersect the first and third fin patterns 110 and 310. The fourth gate structure 420 may be disposed on the second and fourth fin patterns 210 and 410 to intersect the second and fourth fin patterns 210 and 410. The third and fourth gate structures 320 and 420 do not overlap with ends of the first and second fin patterns 110 and 210, respectively.

[0057] In the semiconductor device according to the embodiment, the first gate structure 120 may cover an end portion of the first fin pattern 110, and the second gate structure 220 may cover an end portion of the second fin pattern 210. The first gate structure 120 may cover a sidewall of the first fin pattern 110 defining a short side 110 b of the first fin pattern 110. The second gate structure 220 may cover a sidewall of the second fin pattern 210 defining a short side 210 b of the second fin pattern 210.

[0058] The first to fourth gate structures 120, 220, 320 and 420 may respectively include first to fourth gate electrodes 130, 230, 330 and 430, first to fourth gate insulating layers 135, 235, 335 and 435, first to fourth gate spacers 140, 240, 340 and 440, first to fourth gate trenches 140t, 240t, 340t and 440t defined by the first to fourth gate spacers 140, 240, 340 and 440, and first to fourth capping patterns 145, 245, 345 and 445.

[0059] The first to fourth gate insulating layers 135, 235, 335, and 435 may extend along sidewalls and bottom surfaces of the first to fourth gate trenches 140t, 240t, 340t, and 440t, respectively. Each of the first to fourth gate insulating layers 135, 235, 335, and 435 may include a high dielectric constant insulating layer.

[0060] The high-k dielectric layer may include a high-k dielectric material having a higher dielectric constant than the silicon oxide layer. Each of the first to fourth gate insulating layers 135, 235, 335, and 435 may include one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0061] The first to fourth gate electrodes 130, 230, 330, and 430 may be respectively disposed on the first to fourth gate insulating layers 135, 235, 335, and 435. The first to fourth gate electrodes 130, 230, 330, and 430 may respectively at least partially fill the first to fourth gate trenches 140t, 240t, 340t, and 440t.

[0062] Each of the first to fourth gate electrodes 130, 230, 330, and 430 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), or the like. , tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and at least one of the following:

[0063] First to fourth gate spacers 140, 240, 340, and 440 may be respectively formed on sidewalls of the first to fourth gate electrodes 130, 230, 330, and 430. Each of the first to fourth gate spacers 140, 240, 340, and 440 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), and silicon oxycarbonitride (SiOCN).

[0064] First to fourth capping patterns 145 , 245 , 345 , and 445 may be formed on the first to fourth gate electrodes 130 , 230 , 330 , and 430 and the first to fourth gate spacers 140 , 240 , 340 , and 440 , respectively.

[0065] Each of the first to fourth capping patterns 145 , 245 , 345 and 445 may include, for example, at least one of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon oxycarbonitride (SiOCN).

[0066] exist Figure 2 、 Figure 3 and Figure 5 , the first to fourth capping patterns 145, 245, 345, and 445 are shown as not filling a portion of the first to fourth gate trenches 140t, 240t, 340t, and 440t, respectively. However, this is merely an example used for convenience of description, and embodiments are not limited to this example.

[0067] A first epitaxial pattern 150 may be formed on each first fin pattern 110. A second epitaxial pattern 250 may be formed on each second fin pattern 210. A third epitaxial pattern 350 may be formed on each third fin pattern 310. A fourth epitaxial pattern 450 may be formed on each fourth fin pattern 410.

[0068] The first epitaxial pattern 150 may be included in the source / drain of a transistor using the first fin pattern 110 as a channel region. The second epitaxial pattern 250 may be included in the source / drain of a transistor using the second fin pattern 210 as a channel region. The third epitaxial pattern 350 may be included in the source / drain of a transistor using the third fin pattern 310 as a channel region. The fourth epitaxial pattern 450 may be included in the source / drain of a transistor using the fourth fin pattern 410 as a channel region.

[0069] A lower interlayer insulating film 191 may be formed on the field insulating layer 105 and may cover the first to fourth epitaxial patterns 150, 250, 350, and 450. The lower interlayer insulating film 191 may be formed around the first to fourth gate structures 120, 220, 320, and 420. The lower interlayer insulating film 191 may at least partially cover sidewalls of the first to fourth gate structures 120, 220, 320, and 420.

[0070] The upper surface of the lower interlayer insulating film 191 may be located in the same plane as the upper surface of each of the first to fourth capping patterns 145, 245, 345, and 445. The lower surface of the lower interlayer insulating film 191 may be located below the lower surface of each of the first to fourth capping patterns 145, 245, 345, and 445.

[0071] Although not shown, the lower interlayer insulating film 191 may further include an etch-stop layer extending along upper surfaces of the first to fourth epitaxial patterns 150 , 250 , 350 , and 450 .

[0072] The first element isolation structure 180 may be disposed between the third fin pattern 310 and the fourth fin pattern 410. The first element isolation structure 180 may be disposed between the short side 310b of the third fin pattern 310 and the short side 410b of the fourth fin pattern 410. The first element isolation structure 180 may separate the third fin pattern 310 from the fourth fin pattern 410. The first element isolation structure 180 may be disposed between the second gate structure 220 and the third gate structure 320.

[0073] The first element isolation structure 180 includes a first side 180 a extending in the first direction X and a second side 180 b extending in the second direction Y. The first side 180 a of the first element isolation structure 180 may face the short side 120 b of the first gate structure 120. The second side 180 b of the first element isolation structure 180 may face the short side 310 b of the third fin pattern 310 and the short side 410 b of the fourth fin pattern 410.

[0074] The first element isolation structure 180 and the first gate structure 120 may be aligned in the second direction Y. The first element isolation structure 180 is disposed on an extension line of the first gate structure 120 extending along the second direction Y.

[0075] The first element isolation structure 180 may be provided in a first isolation trench 180 t included in the lower interlayer insulating film 191 . The first element isolation structure 180 may fill the first isolation trench 180 t . The first isolation trench 180 t may be formed between the third epitaxial pattern 350 and the fourth epitaxial pattern 450 .

[0076] Sidewalls of the first isolation trench 180 t extending in the second direction Y between the third and fourth epitaxial patterns 350 and 450 may be defined by the first dummy spacer 185 , the lower interlayer insulating film 191 , and the third and fourth fin patterns 310 and 410 .

[0077] The upper surface of the first element isolation structure 180 is higher than the upper surfaces of the third fin pattern 310 and the fourth fin pattern 410. For example, the upper surface of the first element isolation structure 180 may be located in the same plane as the upper surface of the lower interlayer insulating film 191. The upper surface of the first element isolation structure 180 may be located in the same plane as the upper surfaces of the second to fourth gate structures 220, 320, and 420.

[0078] exist Figure 3, the width between the sidewalls of the first isolation trench 180t defined by the third fin pattern 310 and the fourth fin pattern 410 increases as the distance from the substrate 100 increases. For example, the width of the first isolation trench 180t between the sidewalls of the first isolation trench 180t defined by the third fin pattern 310 and the fourth fin pattern 410 in the first direction X may gradually increase in an upward direction away from the upper surface of the substrate 100. However, embodiments are not limited to this. For example, according to alternative embodiments, the width between the sidewalls of the first isolation trench 180t defined by the third fin pattern 310 and the fourth fin pattern 410 may not change as the distance from the substrate 100 increases.

[0079] exist Figure 4 In the embodiment, a portion of a sidewall of the first isolation trench 180 t extending in the first direction X may be defined by the field insulation layer 105 . A portion of the first isolation trench 180 t may, but is not necessarily, recessed into the field insulation layer 105 .

[0080] The bottom surface of the first isolation trench 180t may be defined by the field insulation layer 105, the substrate 100, and the remaining fin RF. The remaining fin RF may be a portion remaining after the fin pattern portion is removed in the etching process for forming the first isolation trench 180t. Unlike the drawings, the remaining fin RF may not exist.

[0081] The first element isolation structure 180 may include, for example, at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon carbon oxynitride, and aluminum oxide. Although the first element isolation structure 180 is shown as a single layer, this is merely an example used for ease of description, and the first element isolation structure 180 is not limited to a single layer.

[0082] The first dummy spacer 185 and the first gate spacer 140 may have the same material composition. Unlike the drawings, the first dummy spacer 185 may not be disposed on the sidewall of the first element isolation structure 180 .

[0083] The gate insulating supporter 160 may be disposed on the field insulating layer 105 between the first and third fin patterns 110 and 310. The gate insulating supporter 160 may be spaced apart from the first and third fin patterns 110 and 310 in the second direction Y.

[0084] The gate insulating supporter 160 may be disposed between the first gate structure 120 and the first element isolation structure 180. The gate insulating supporter 160 may be disposed on the field insulating layer 105 between the first gate structure 120 and the first element isolation structure 180.

[0085] The gate insulating support 160 may separate the first gate structure 120 and the first element isolation structure 180. The gate insulating support 160 may pass between the first gate structure 120 and the first element isolation structure 180. The first gate structure 120 and the first element isolation structure 180 may be arranged along the second direction Y, with the gate insulating support 160 interposed between the first gate structure 120 and the first element isolation structure 180.

[0086] The gate insulating supporter 160 contacts the first gate structure 120 and the first element isolation structure 180 .

[0087] It will be understood that when an element is referred to as “contacting” or “being in contact with” another element, there are no intervening elements present at the point of contact.

[0088] The gate insulating supporter 160 includes a first side 160 a extending in the first direction X and a second side 160 b extending in the second direction Y. The first gate structure 120 and the first element isolation structure 180 contact the first side 160 a of the gate insulating supporter 160 .

[0089] In the semiconductor device according to the embodiment, the width W22 of the gate insulating support 160 in the first direction X (see Figure 5 ) may be greater than or equal to the width W21 of the first gate structure 120 in the first direction X (see Figure 2 ).

[0090] exist Figure 1 and Figure 5 In the embodiment, a width W22 of the gate insulating supporter 160 in the first direction X is greater than a width W21 of the first gate structure 120 in the first direction X.

[0091] In addition, Figure 1 and Figure 5 In the embodiment, the gate insulating supporter 160 does not contact the second gate structure 220 and the third gate structure 320. However, the embodiment is not limited to this case.

[0092] The gate insulating supporter 160 may be disposed in the insulating trench 160t included in the lower interlayer insulating film 191. The gate insulating supporter 160 may fill the insulating trench 160t. Figure 4 and Figure 5 In the embodiment, a portion of the sidewall of the insulating trench 160t may be recessed into the field insulating layer 105 and defined by the field insulating layer 105. However, the embodiment is not limited to this case.

[0093] exist Figure 4 , a bottom surface of the first isolation trench 180t defined by the field insulation layer 105 is shown to be closer to the substrate 100 than a bottom surface of the isolation trench 160t. However, embodiments are not limited to this case.

[0094] The gate insulating supporter 160 may include, for example, at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, and aluminum oxide. Figure 4 and Figure 5 The gate insulating supporter 160 is shown as a single layer in FIG. 1 , but this is merely an example used for convenience of description, and the gate insulating supporter 160 is not limited to a single layer.

[0095] exist Figure 4 In the embodiment, the first gate insulating layer 135 does not extend along the sidewalls of the gate insulating support 160. The first gate electrode 130 may contact the gate insulating support 160. For example, the sidewalls of the first gate electrode 130 extending in the first direction X may contact the sidewalls of the gate insulating support 160 extending in the first direction X. Figure 5 In the embodiment, the upper surface of the gate insulating supporter 160 may be located in the same plane as the upper surface of the lower interlayer insulating film 191. The upper surface of the gate insulating supporter 160 may be located in the same plane as the upper surfaces of the second to fourth gate structures 220, 320, and 420.

[0096] An upper interlayer insulating film 192 is formed on the lower interlayer insulating film 191 , the gate insulating supporter 160 , the first element isolation structure 180 , and the first to fourth gate structures 120 , 220 , 320 , and 420 . The interlayer insulating film 190 includes the lower interlayer insulating film 191 and the upper interlayer insulating film 192 . Each of the lower interlayer insulating film 191 and the upper interlayer insulating film 192 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, flowable oxide (FOX), Ton-burning silazane (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), carbon-doped silicon oxide (CDO), dry gel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer materials, or combinations thereof.

[0097] Figure 7 A semiconductor device according to an embodiment is shown. Figure 8 A semiconductor device according to an embodiment is shown. Figure 9 For the convenience of description, the following embodiments are mainly described with reference to Figures 1 to 6 The differences between the elements and features described.

[0098] Reference Figure 7In the semiconductor device according to the embodiment, the first gate insulating layer 135 includes a portion extending along the sidewall of the gate insulating supporter 160 in the first direction X.

[0099] The first gate insulating layer 135 may extend between the first gate electrode 130 and the gate insulating supporter 160 .

[0100] Reference Figure 8 In the semiconductor device according to the embodiment, the first to fourth gate electrodes 130 , 230 , 330 , and 430 may partially fill the first to fourth gate trenches 140 t , 240 t , 340 t , and 440 t , respectively.

[0101] The first to fourth capping patterns 145, 245, 345, and 445 may respectively fill the first to fourth gate trenches 140 t, 240 t, 340 t, and 440 t remaining after forming the first to fourth gate electrodes 130, 230, 330, and 430. The upper surfaces of the first to fourth gate spacers 140, 240, 340, and 440 may be located in the same plane as the upper surfaces of the first to fourth capping patterns 145, 245, 345, and 445.

[0102] Although the first to fourth gate insulating layers 135 , 235 , 335 , and 435 are illustrated as not extending between the first to fourth capping patterns 145 , 245 , 345 , and 445 and the first to fourth gate spacers 140 , 240 , 340 , and 440 in the drawings, embodiments are not limited thereto.

[0103] Reference Figure 9 In the semiconductor device according to the embodiment, upper surfaces of the first to fourth gate electrodes 130 , 230 , 330 , and 430 may be located in the same plane as an upper surface of the lower interlayer insulating film 191 .

[0104] The upper surfaces of the first to fourth gate electrodes 130, 230, 330, and 430 may be aligned with the gate insulating supporter 160 (see Figure 5 ) and the upper surface of the first element isolation structure 180 (see Figure 3 ) are located in the same plane. The first to fourth gate structures 120, 220, 320, and 420 may not include the capping patterns 145, 245, 345, and 445, respectively.

[0105] Figure 10 A semiconductor device according to an embodiment is shown. Figure 11 For the convenience of description, the following embodiments are mainly described with reference to Figures 1 to 6The differences between the elements and features described.

[0106] Reference Figure 10 The semiconductor device according to the embodiment may further include a connection spacer 120 cs protruding from the upper surface of the field insulation layer 105 between the gate insulation supporter 160 and the field insulation layer 105 .

[0107] The connection spacer 120cs may be recessed into the gate insulating supporter 160. For example, the vertical height of the connection spacer 120cs may be smaller than the vertical heights of the second to fourth gate spacers 240 to 440. The bottom surface of the connection spacer 120cs and the bottom surfaces of the second to fourth gate spacers 240, 340, and 440 may contact the field insulating layer 105. Therefore, the upper surfaces of the second to fourth gate spacers 240, 340, and 440 are higher than the upper surface of the connection spacer 120cs.

[0108] In addition, the connection spacer 120cs is directly connected to the first gate structure 120. The connection spacer 120cs is directly connected to the first dummy spacer 185 provided on the sidewall of the first element isolation structure 180. The connection spacer 120cs contacts the first gate structure 120. The material composition of the connection spacer 120cs and the first gate spacer 140 may be the same.

[0109] A bottom surface of the gate insulating supporter 160 may be defined by the field insulating layer 105 and the connection spacers 120 cs.

[0110] Reference Figure 11 In the semiconductor device according to the embodiment, a portion of the lower interlayer insulating film 191 may be interposed between the gate insulating supporter 160 and the field insulating layer 105 .

[0111] The bottom surface of the gate insulating supporter 160 includes a first portion defined by the field insulating layer 105 and a second portion defined by the lower interlayer insulating film 191. The second portion of the gate insulating supporter 160 may be disposed along the first direction X with the first portion of the gate insulating supporter 160 interposed therebetween.

[0112] The gate insulating supporter 160 , whose bottom surface is defined by the field insulating layer 105 , may contact the field insulating layer 105 . The gate insulating supporter 160 , whose bottom surface is defined by the lower interlayer insulating film 191 , may not contact the field insulating layer 105 .

[0113] Figure 12 and Figure 13 A semiconductor device according to an embodiment is shown. Figure 14 and Figure 15 For the convenience of description, the following embodiments are mainly described with reference to Figures 1 to 6 The differences between the elements and features described.

[0114] Reference Figure 12 and Figure 13 , a deep trench DT may be formed in the substrate 100 between the first fin pattern 110 and the third fin pattern 310 .

[0115] The deep trench DT may be longer than the long side 110a (see Figure 1 ) and the long side 310a of the third fin pattern 310 (see Figure 1 The field insulating layer 105 fills the deep trench DT.

[0116] The gate insulating supporter 160 may be formed on the field insulating layer 105 filling the deep trench DT.

[0117] Reference Figure 14 and Figure 15 , the semiconductor device according to the embodiment may further include a protrusion pattern FP protruding from the substrate 100 between the first fin pattern 110 and the third fin pattern 310 .

[0118] The height of the protrusion pattern FP is smaller than the height of the first fin pattern 110 and the height of the third fin pattern 310 . The height of the protrusion pattern FP is smaller than the height of a portion of the field insulation layer 105 overlapping the first gate electrode 130 .

[0119] For example, the upper surface of the protruding pattern FP may be covered by the field insulating layer 105. The protruding pattern FP may extend in the first direction X, but need not necessarily do so (see FIG. Figure 1 ).

[0120] Although the bottom surface of the gate insulating support 160 is shown as being higher than the upper surface of the protruding pattern FP, the embodiment is not limited to this case. The gate insulating support 160 may also contact the protruding pattern FP. In this case, the upper surface of the protruding pattern FP is not covered by the field insulating layer 105.

[0121] Figure 16 A semiconductor device according to an embodiment is shown. Figure 17 and Figure 18 For the convenience of description, the following embodiments are mainly described with reference to Figures 1 to 6 The differences between the elements and features described.

[0122] Reference Figure 16 , the semiconductor device according to the embodiment may include a contact portion 195 penetrating the interlayer insulating film 190 .

[0123] Contacts 195 may be respectively connected to the first and second epitaxial patterns 150 and 250. Although contacts 195 are shown as not contacting the first to fourth gate structures 120, 220, 320, and 420, embodiments are not limited thereto.

[0124] Although each contact portion 195 is shown as a single structure, the embodiment is not limited to this case. Each contact portion 195 may also include a plurality of structures arranged in the thickness direction of the substrate 100.

[0125] The contact portion 195 may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten carbonitride (WCN), tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu), and doped polysilicon. Unlike in the figure, a silicide layer may be formed between the contact portion 195 and the epitaxial patterns 150 and 250.

[0126] Reference Figure 17 and Figure 18 In the semiconductor device according to the embodiment, the upper surface of the field insulation layer 105 filling the fin-cut trench ST may be at the same height as or higher than the upper surfaces of the first and second fin patterns 110 and 210 .

[0127] Sidewalls of the first fin pattern 110 defining the short sides 110 b of the first fin pattern 110 and sidewalls of the second fin pattern 210 defining the short sides 210 b of the second fin pattern 210 may be covered by the field insulating layer 105 .

[0128] For example, the first gate structure 120 does not cover the short side 110b defining the first fin pattern 110 (see Figure 1 ) of the sidewall of the first fin pattern 110. The second gate structure 220 does not cover the short side 210b defining the second fin pattern 210 (see Figure 1 ) of the sidewall of the second fin pattern 210.

[0129] Figure 19 is a schematic plan view of a semiconductor device according to an embodiment. Figure 20 It is along Figure 19 For the convenience of description, the following embodiments are mainly described with reference to the above embodiment. Figures 1 to 6 The differences between the elements and features described.

[0130] Reference Figure 19 and Figure 20 In the semiconductor device according to the embodiment, the width of the gate insulating supporter 160 in the first direction X may be less than or equal to the width of the first gate structure 120 in the first direction X.

[0131] The gate insulating supporter 160 may be formed between the first dummy spacers 185. The first dummy spacers 185 may be disposed on sidewalls of the gate insulating supporter 160. The first dummy spacers 185 may extend along sidewalls of the gate insulating supporter 160 and sidewalls of the first element isolation structure 180.

[0132] The insulating trench 160t may be aligned with the first dummy spacer 185. In a semiconductor device manufacturing process, the insulating trench 160t may be formed using the first dummy spacer 185 as a mask.

[0133] Figure 21 is a schematic plan view of a semiconductor device according to an embodiment. Figure 22 It is along Figure 21 A cross-sectional view taken along line BB. Figure 23 It is along Figure 21 A cross-sectional view taken along line DD. Figure 24 It is along Figure 21 For ease of description, the following embodiments are mainly described with reference to the above embodiment. Figures 1 to 6 The differences between the elements and features described.

[0134] Reference Figures 21 to 24 The semiconductor device according to the embodiment may further include a fifth fin pattern 510 , a second element isolation structure 181 , and a connection isolation structure 182 .

[0135] The fifth fin pattern 510 may protrude from the substrate 100. The fifth fin pattern 510 may extend in the first direction X on the substrate 100. The fifth fin pattern 510 may include long sides 510a extending in the first direction X and short sides 510b extending in the second direction Y.

[0136] The fifth fin pattern 510 may be aligned with the third fin pattern 310 and the fourth fin pattern 410 in the first direction X as a longitudinal direction. The third to fifth fin patterns 310 to 510 may be sequentially arranged in the first direction X. The fourth fin pattern 410 may be disposed between the third fin pattern 310 and the fifth fin pattern 510. The fourth fin pattern 410 and the fifth fin pattern 510 may be separated by a second isolation trench 181t. The third to fifth fin patterns 310 to 510 are disposed in a region where transistors of the same conductivity type are formed.

[0137] The second gate structure 220 may intersect the second fin pattern 210, but may not intersect the fourth fin pattern 410 and the fifth fin pattern 510. The second gate structure 220 may extend up to the gate insulating supporter 160. The fourth gate structure 420 may be disposed on the second fin pattern 210 and the fifth fin pattern 510 to intersect the second fin pattern 210 and the fifth fin pattern 510.

[0138] A fourth epitaxial pattern 450 may be formed on each fourth fin pattern 410 . A fifth epitaxial pattern 550 may be formed on each fifth fin pattern 510 .

[0139] The second element isolation structure 181 may be disposed between the fourth fin pattern 410 and the fifth fin pattern 510. The fourth fin pattern 410 may be disposed between the first element isolation structure 180 and the second element isolation structure 181. The second element isolation structure 181 may be disposed between short sides of the fourth fin pattern 410 and the fifth fin pattern 510.

[0140] The second element isolation structure 181 may separate the fourth fin pattern 410 and the fifth fin pattern 510 . The first element isolation structure 180 and the second element isolation structure 181 may be disposed between the third gate structure 320 and the fourth gate structure 420 .

[0141] The second element isolation structure 181 includes a first side 181 a extending in the first direction X and a second side 181 b extending in the second direction Y. The first side 181 a of the second element isolation structure 181 may face the short side 220 b of the second gate structure 220. The second side 181 b of the second element isolation structure 181 may face the short sides of the fourth fin pattern 410 and the fifth fin pattern 510.

[0142] The second element isolation structure 181 and the second gate structure 220 may be aligned in the second direction Y. The second element isolation structure 181 is disposed on an extension line of the second gate structure 220 extending along the second direction Y.

[0143] The second element isolation structure 181 may be provided in the second isolation trench 181t included in the lower interlayer insulating film 191. The second element isolation structure 181 may fill the second isolation trench 181t.

[0144] The second isolation trench 181t may be formed between the fourth epitaxial pattern 450 and the fifth epitaxial pattern 550. Sidewalls of the second isolation trench 181t extending in the second direction Y between the fourth epitaxial pattern 450 and the fifth epitaxial pattern 550 may be defined by the second dummy spacer 186, the lower interlayer insulating film 191, and the fourth and fifth fin patterns 410 and 510.

[0145] The upper surface of the second element isolation structure 181 is higher than the upper surfaces of the fourth fin pattern 410 and the fifth fin pattern 510. For example, the upper surface of the second element isolation structure 181 may be located in the same plane as the upper surface of the lower interlayer insulating film 191.

[0146] An upper surface of the second element isolation structure 181 may be located in the same plane as upper surfaces of the third gate structure 320 and the fourth gate structure 420 .

[0147] exist Figure 22 , the width between the sidewalls of the second isolation trench 181t defined by the fourth fin pattern 410 and the fifth fin pattern 510 increases as the distance from the substrate 100 increases. For example, the width between the sidewalls of the second isolation trench 181t defined by the fourth fin pattern 410 and the fifth fin pattern 510 in the first direction X gradually increases as the distance from the substrate 100 increases. However, embodiments are not limited to this. For example, the width between the sidewalls of the second isolation trench 181t defined by the fourth fin pattern 410 and the fifth fin pattern 510 in the first direction X may remain the same as the distance from the substrate 100 increases.

[0148] exist Figure 24 In the embodiment, a portion of a sidewall of the second isolation trench 181 t extending in the first direction X may be defined by the field insulation layer 105 . A portion of the second isolation trench 181 t may, but is not necessarily, recessed into the field insulation layer 105 .

[0149] The bottom surface of the second isolation trench 181t may be defined by the field insulation layer 105, the substrate 100, and the remaining fin RF. The remaining fin RF may be a portion remaining after the fin pattern portion is removed in the etching process for forming the second isolation trench 181t. Unlike the drawings, the remaining fin RF may not exist.

[0150] exist Figure 24 , a bottom surface of the second isolation trench 181t defined by the field insulation layer 105 is shown to be closer to the substrate 100 than a bottom surface of the isolation trench 160t. However, embodiments are not limited to this case.

[0151] The second element isolation structure 181 may include, for example, at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon carbon oxynitride, and aluminum oxide. Although the second element isolation structure 181 is shown as a single layer, this is merely an example used for ease of description, and the second element isolation structure 181 is not limited to a single layer.

[0152] The second dummy spacer 186 and the second gate spacer 240 may have the same material composition. Unlike the drawings, the second dummy spacer 186 may not be disposed on the sidewall of the second element isolation structure 181 .

[0153] Connection isolation structure 182 may be provided between first element isolation structure 180 and second element isolation structure 181. Connection isolation structure 182 may connect first element isolation structure 180 and second element isolation structure 181. Second element isolation structure 181 may be connected to first element isolation structure 180 through connection isolation structure 182.

[0154] Connection isolation structure 182 may connect an upper portion of first element isolation structure 180 and an upper portion of second element isolation structure 181. An upper surface of connection isolation structure 182 may be located in the same plane as upper surfaces of first element isolation structure 180 and second element isolation structure 181.

[0155] The connection isolation structure 182 may cover the fourth fin pattern 410 and the fourth epitaxial pattern 450 . A portion of the lower interlayer insulating film 191 may be disposed between the connection isolation structure 182 and each of the fourth fin patterns 410 .

[0156] For example, a portion of the lower interlayer insulating film 191 may be provided between the connection isolation structure 182 and each of the fourth epitaxial patterns 450. For example, based on the bottom surfaces of the first element isolation structure 180 and the second element isolation structure 181, the lower surface of the connection isolation structure 182 is higher than the upper surface of the fourth fin pattern 410 and the upper surface of the fourth epitaxial pattern 450.

[0157] The first and second element isolation structures 180 and 181 and the connection isolation structure 182 may be included in the overall isolation structure 180ST. For example, the first and second element isolation structures 180 and 181 and the connection isolation structure 182 may be formed in the same process to produce an overall structure.

[0158] The connection isolation structure 182 may include, for example, at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, and aluminum oxide.

[0159] The gate insulating supporter 160 may be disposed between the first gate structure 120 and the first element isolation structure 180 and between the second gate structure 220 and the second element isolation structure 181. The gate insulating supporter 160 may be disposed on the field insulating layer 105 between the first gate structure 120 and the first element isolation structure 180 and between the second gate structure 220 and the second element isolation structure 181.

[0160] The gate insulating support 160 may separate the second gate structure 220 and the second element isolation structure 181. The gate insulating support 160 may pass between the second gate structure 220 and the second element isolation structure 181. The second gate structure 220 and the second element isolation structure 181 may be arranged along the second direction Y, with the gate insulating support 160 interposed between the second gate structure 220 and the second element isolation structure 181.

[0161] The gate insulating supporter 160 contacts the second gate structure 220 and the second element isolation structure 181. The gate insulating supporter 160 may contact the connection isolation structure 182.

[0162] The gate insulating support 160 includes a first side 160 a extending in the first direction X and a second side 160 b extending in the second direction Y. The second gate structure 220 and the second element isolation structure 181 contact the first side 160 a of the gate insulating support 160. The connection isolation structure 182 may contact the first side 160 a of the gate insulating support 160.

[0163] In the semiconductor device according to the embodiment, the width of the gate insulating supporter 160 in the first direction X is greater than the width of the first gate structure 120 in the first direction X and the width of the second gate structure 220 in the first direction X. Figure 23 The middle gate insulating supporter 160 is shown not to contact the third gate structure 320 and the fourth gate structure 420 , but the embodiment is not limited to this case.

[0164] Figure 25 A semiconductor device according to an embodiment is shown. Figure 26 For the convenience of description, the following embodiments are mainly described with reference to Figures 21 to 24 The differences between the elements and features described.

[0165] Reference Figure 25 In the semiconductor device according to the embodiment, the connection isolation structure 182 may contact the fourth epitaxial pattern 450 .

[0166] In the etching process for forming the connection isolation structure 182 , the upper surface of the fourth epitaxial pattern 450 may be exposed. The connection isolation structure 182 may be formed on the exposed fourth epitaxial pattern 450 .

[0167] Reference Figure 26 In the semiconductor device according to the embodiment, a portion of the connection isolation structure 182 may be recessed into the fourth epitaxial pattern 450 .

[0168] In the etching process for forming the connection isolation structure 182, a portion of the fourth epitaxial pattern 450 may be etched. The connection isolation structure 182 may be formed on the partially etched fourth epitaxial pattern 450.

[0169] Figure 27 is a schematic plan view of a semiconductor device according to an embodiment. Figure 28 It is along Figure 27 For the convenience of description, the following embodiments are mainly described with reference to the above embodiment. Figures 21 to 24 The differences between the elements and features described.

[0170] Reference Figure 27 and Figure 28 , in the semiconductor device according to the embodiment, the first element isolation structure 180 is separated from the second element isolation structure 181 .

[0171] A connection isolation structure for connecting the first element isolation structure 180 and the second element isolation structure 181 is not provided between the first element isolation structure 180 and the second element isolation structure 181 .

[0172] A connection isolation structure for connecting the first element isolation structure 180 and the second element isolation structure 181 is not disposed on the fourth fin pattern 410 and the fourth epitaxial pattern 450 .

[0173] Figure 29 is a schematic plan view of a semiconductor device according to an embodiment. Figure 30 It is along Figure 29 For ease of description, the following embodiments are mainly described with reference to the above embodiment. Figures 1 to 6 The differences between the elements and features described.

[0174] Reference Figure 29 and Figure 30 In the semiconductor device according to the embodiment, the first gate structure 120 may contact the first element isolation structure 180 .

[0175] The short side 120b of the first gate structure 120 may contact the first side 180a of the first element isolation structure 180. The first gate structure 120 and the first element isolation structure 180 contacting each other may be arranged in a row along the second direction Y.

[0176] The first gate electrode 130 , the first gate insulation layer 135 , and the first capping pattern 145 may make contact with the first element isolation structure 180 .

[0177] Figures 31 to 34 are views showing some steps of a method of manufacturing a semiconductor device according to an embodiment.

[0178] Reference Figure 31 , a first fin pattern 110 and a second fin pattern 210 are formed that are aligned in the first direction X. The first fin pattern 110 and the second fin pattern 210 are spaced apart from each other in the first direction X.

[0179] A pre-fin F1 extending in the first direction X is formed. The pre-fin F1 is spaced apart from the first and second fin patterns 110 and 210 in the second direction Y.

[0180] Reference Figure 32 , a pre-gate structure 120G and a third gate structure 320 are formed on the first fin pattern 110 and the pre-fin F1 .

[0181] Each of the pre-gate structure 120G and the third gate structure 320 intersects the first fin pattern 110 and the pre-fin F1. The pre-gate structure 120G overlaps an end portion of the first fin pattern 110 including a short side 110b thereof. The third gate structure 320 does not overlap an end portion of the first fin pattern 110.

[0182] A second gate structure 220 and a fourth gate structure 420 are formed on the second fin pattern 210 and the pre-fin F1 .

[0183] Each of the second gate structure 220 and the fourth gate structure 420 intersects the second fin pattern 210 and the pre-fin F1. The second gate structure 220 overlaps an end portion of the second fin pattern 210 including a short side 210b of the second fin pattern 210. The fourth gate structure 420 does not overlap an end portion of the second fin pattern 210.

[0184] In an example, the pre-gate structure 120G may include a gate electrode formed by a replacement metal gate (RMG) process. In another example, the pre-gate structure 120G may include a dummy mold gate before the RMG process.

[0185] In the method of fabricating a semiconductor device according to an embodiment, the pre-gate structure 120G is described as including a gate electrode formed by the RMG process.

[0186] Reference Figure 33 , forming a gate insulating support member 160 for cutting the pre-gate structure 120G.

[0187] The gate insulating supporter 160 may divide the pre-gate structure 120G into the first gate structure 120 and the fifth gate structure 120RG.

[0188] The first gate structure 120 may intersect the first fin pattern 110. The fifth gate structure 120RG intersects the pre-fin F1.

[0189] Reference Figure 34, the fifth gate structure 120RG and the pre-fin F1 may be partially removed.

[0190] As a result of the partial removal of the pre-fin F1 , the pre-fin F1 may be divided into a third fin pattern 310 and a fourth fin pattern 410 .

[0191] The first element isolation structure 180 may be formed at a location where the fifth gate structure 120RG and the pre-fin F1 have been removed.

[0192] The gate insulating supporter 160 may contact the first element isolation structure 180 and the first gate structure 120 .

[0193] While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as defined in the appended claims. It is therefore intended that these embodiments be considered in all respects as illustrative and not restrictive, with reference to the appended claims, rather than the foregoing description, indicating the scope of the invention.

Claims

1. A semiconductor device comprising: a first fin pattern and a second fin pattern, the first fin pattern and the second fin pattern being separated by a first isolation trench and extending in a first direction, wherein the short side of the first fin pattern and the short side of the second fin pattern are spaced apart from each other in the first direction and face each other in the first direction; a third fin pattern spaced apart from the first fin pattern in a second direction intersecting the first direction and extending in the first direction; a fourth fin pattern, the fourth fin pattern being separated from the third fin pattern by a second isolation trench, wherein the short side of the third fin pattern and the short side of the fourth fin pattern are spaced apart from each other in the first direction and face each other in the first direction, and Wherein, the second isolation trench extends in the second direction; a first gate structure intersecting the first fin pattern and having a portion extending along an upper surface of the first fin pattern; a second gate structure intersecting the second fin pattern and having a portion extending along an upper surface of the second fin pattern; and a first element isolation structure, wherein the first element isolation structure fills the second isolation trench; wherein the first element isolation structure extends in the second direction, Wherein, in a top view, the short side of the first element isolation structure and the short side of the first gate structure are spaced apart from each other in the second direction and face each other in the second direction, The top surface of the first element isolation structure is at the same height as the top surface of the first gate structure, and The first gate structure covers a sidewall of an end portion of the first fin pattern including the short side of the first fin pattern.

2. The semiconductor device according to claim 1, further comprising: a field insulating layer disposed between the first fin pattern and the third fin pattern; as well as A gate insulating support member is formed on the upper surface of the field insulating layer, and in a top view, the gate insulating support member is arranged between the first element isolation structure and the first gate structure to contact the short side of the first element isolation structure and the short side of the first gate structure.

3. The semiconductor device according to claim 2, wherein A width of the gate insulating support in the first direction is greater than a width of the first gate structure in the first direction.

4. The semiconductor device according to claim 2, wherein The first gate structure includes a high dielectric constant insulating layer extending along the upper surface of the field insulating layer and a gate electrode disposed on the high dielectric constant insulating layer, wherein the high dielectric constant insulating layer does not extend along the sidewall of the gate insulating supporter. The semiconductor device according to claim 1 , wherein The first element isolation structure contacts the first gate structure, and the first element isolation structure and the first gate structure are aligned in the second direction.

6. The semiconductor device according to claim 1, further comprising: a fifth fin pattern, the fifth fin pattern being separated from the fourth fin pattern by a third isolation trench; as well as A second element isolation structure fills the third isolation trench.

7. The semiconductor device according to claim 6, further comprising: A connecting isolation structure connects an upper portion of the first element isolation structure and an upper portion of the second element isolation structure.

8. The semiconductor device according to claim 7, further comprising: An interlayer insulating film is disposed between the connection isolation structure and the fourth fin pattern.

9. The semiconductor device according to claim 6, further comprising: An epitaxial pattern is disposed on the fourth fin pattern.

10. The semiconductor device according to claim 1, wherein The second gate structure intersects the fourth fin pattern.

11. The semiconductor device according to claim 1, wherein An upper surface of the first element isolation structure is at the same height as an upper surface of the first gate structure.

12. A semiconductor device comprising: a first fin pattern and a second fin pattern, the first fin pattern and the second fin pattern being aligned in a first direction being a longitudinal direction; a third fin pattern spaced apart from the first fin pattern in a second direction intersecting the first direction and extending in the first direction; a fourth fin pattern, the fourth fin pattern being separated from the third fin pattern by a first isolation trench; a first gate structure intersecting the first fin pattern and having a portion extending along an upper surface of the first fin pattern; a second gate structure intersecting the second fin pattern and having a portion extending along an upper surface of the second fin pattern; a third gate structure, the third gate structure intersecting the first fin pattern and the third fin pattern; as well as a first element isolation structure, wherein the first element isolation structure fills the first isolation trench; The upper surface of the first element isolation structure is higher than the upper surface of the third fin pattern. The top surface of the first element isolation structure is at the same height as the top surface of the first gate structure, and The first gate structure covers a sidewall of an end portion of the first fin pattern including a short side of the first fin pattern.

13. The semiconductor device according to claim 12, further comprising: A gate insulating support member, in a top view, the gate insulating support member is formed between the short side of the first element isolation structure and the short side of the first gate structure to contact the short side of the first element isolation structure and the short side of the first gate structure, wherein the width of the gate insulating support member in the first direction is greater than the width of the first gate structure in the first direction.

14. The semiconductor device according to claim 12, wherein The second gate structure intersects the fourth fin pattern.

15. The semiconductor device according to claim 12, further comprising: a fifth fin pattern, the fifth fin pattern being separated from the fourth fin pattern by a second isolation trench; as well as A second element isolation structure fills the second isolation trench and is connected to the first element isolation structure.

16. A semiconductor device comprising: a first fin pattern and a second fin pattern, the first fin pattern and the second fin pattern being disposed in an n-type metal oxide semiconductor (NMOS) region and aligned in a first direction as a longitudinal direction; a third fin pattern, the third fin pattern being disposed in a p-type metal oxide semiconductor (PMOS) region, spaced apart from the first fin pattern in a second direction intersecting the first direction, and extending in the first direction; a fourth fin pattern, the fourth fin pattern being separated from the third fin pattern by a first isolation trench; a first gate structure intersecting the first fin pattern and having a portion extending along an upper surface of the first fin pattern; a second gate structure intersecting the second fin pattern and having a portion extending along an upper surface of the second fin pattern; a first element isolation structure filling the first isolation trench, wherein in a top view, the first element isolation structure and the first gate structure are spaced apart from each other in the second direction; and a gate insulating support member, which is disposed between the first gate structure and the first element isolation structure in a top view so as to contact a short side of the first gate structure and a short side of the first element isolation structure; The top surface of the first element isolation structure is at the same height as the top surface of the first gate structure, and The first gate structure covers a sidewall of an end portion of the first fin pattern including a short side of the first fin pattern.

17. The semiconductor device according to claim 16, wherein A width of the gate insulating support in the first direction is greater than a width of the first gate structure in the first direction.

18. The semiconductor device according to claim 16, further comprising: a fifth fin pattern, the fifth fin pattern being separated from the fourth fin pattern by a second isolation trench; as well as A second element isolation structure fills the second isolation trench.

19. The semiconductor device according to claim 18, further comprising: A connecting isolation structure connects an upper portion of the first element isolation structure and an upper portion of the second element isolation structure.

20. The semiconductor device according to claim 18, wherein The gate insulating support member passes between the second element isolation structure and the second gate structure.

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