Organic light emitting diode display device

Abstract

An organic light emitting diode display is disclosed. The organic light emitting diode display includes a driving transistor and a compensation transistor. The driving transistor includes a first gate electrode, a polycrystalline semiconductor layer, and a second gate electrode, the first gate electrode is arranged on a substrate, the polycrystalline semiconductor layer is arranged on the first gate electrode of the driving transistor and includes a first electrode, a second electrode, and a channel, and the second gate electrode is arranged on the polycrystalline semiconductor layer of the driving transistor. The compensation transistor includes a polycrystalline semiconductor layer and a gate electrode, the polycrystalline semiconductor layer includes a first electrode, a second electrode, and a channel, and the gate electrode is arranged on the polycrystalline semiconductor layer of the compensation transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0074950 filed on June 28, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to an organic light emitting diode display. Background Art

[0004] Organic light emitting diode displays have self-luminous properties. Since organic light emitting diode displays do not require a separate light source, they can have a relatively small thickness and weight, unlike liquid crystal displays. In addition, organic light emitting diode displays exhibit high quality properties such as low power consumption, high brightness, high response speed, etc.

[0005] Generally, an organic light emitting diode display includes a substrate, a plurality of thin film transistors positioned on the substrate, a plurality of insulating layers arranged between wirings constituting the thin film transistors, and an organic light emitting element connected to the thin film transistors. Summary of the invention

[0006] The exemplary embodiments of the present invention reduce the thickness of the display device and improve the display device by, for example, removing or reducing a momentary afterimage despite the presence of a protrusion formed in a polycrystalline semiconductor layer of the display device.

[0007] According to an exemplary embodiment, an organic light emitting diode display includes a substrate, a pixel arranged on the substrate, a scan line, a data line, a driving voltage line, and an initialization voltage line. The scan line, the data line, the driving voltage line, and the initialization voltage line are connected to the pixel. The pixel includes an organic light emitting element, a first switching transistor connected to the scan line, a driving transistor that applies a current to the organic light emitting element, and a compensation transistor that compensates for the operation of the driving transistor. The driving transistor includes a first gate electrode and a polycrystalline semiconductor layer, the first gate electrode is arranged on the substrate, and the polycrystalline semiconductor layer is arranged on the first gate electrode and includes a first electrode, a second electrode, and a channel. The compensation transistor includes a polycrystalline semiconductor layer and a first gate electrode, the polycrystalline semiconductor layer includes a first electrode, a second electrode, and a channel, and the first gate electrode is arranged on the polycrystalline semiconductor layer of the compensation transistor.

[0008] In an exemplary embodiment, the driving transistor further includes a second gate electrode disposed on the polycrystalline semiconductor layer of the driving transistor.

[0009] In an exemplary embodiment, the second gate electrode of the driving transistor receives a driving voltage flowing to the driving voltage line.

[0010] In an exemplary embodiment, the driving transistor further includes an overlapping layer disposed between the substrate and the first gate electrode of the driving transistor.

[0011] In an exemplary embodiment, the driving voltage flowing to the driving voltage line is applied to the overlapping layer.

[0012] In an exemplary embodiment, the organic light emitting diode display further includes a driving voltage applying part that applies a driving voltage to the overlapping layer and the second gate electrode of the driving transistor.

[0013] In an exemplary embodiment, the organic light emitting diode display further includes a second switching transistor. The first switching transistor is connected to the scan line and the data line, and the second switching transistor is connected to the scan line and the first gate electrode of the driving transistor.

[0014] In an exemplary embodiment, the first switching transistor includes a polycrystalline semiconductor layer and a first gate electrode, the polycrystalline semiconductor layer includes a first electrode, a second electrode, and a channel, and the first gate electrode is disposed on the polycrystalline semiconductor layer of the first switching transistor.

[0015] In an exemplary embodiment, the first switch transistor further includes a second gate electrode disposed below the polycrystalline semiconductor layer of the first switch transistor. A driving voltage flowing to the driving voltage line is applied to the second gate electrode of the first switch transistor.

[0016] In an exemplary embodiment, the first switching transistor includes a gate electrode and a polycrystalline semiconductor layer, the gate electrode is disposed on a substrate, and the polycrystalline semiconductor layer is disposed on the gate electrode of the first switching transistor and includes a first electrode, a second electrode, and a channel.

[0017] In an exemplary embodiment, the second switching transistor includes a polycrystalline semiconductor layer and a first gate electrode, the polycrystalline semiconductor layer includes a first electrode, a second electrode, and a channel, and the first gate electrode is disposed on the polycrystalline semiconductor layer of the second switching transistor.

[0018] In an exemplary embodiment, the second switch transistor further includes a second gate electrode disposed below the polycrystalline semiconductor layer of the second switch transistor. The second gate electrode of the second switch transistor receives a driving voltage flowing to the driving voltage line.

[0019] In an exemplary embodiment, the first switching transistor includes a polycrystalline semiconductor layer and a first gate electrode, the polycrystalline semiconductor layer includes a first electrode, a second electrode, and a channel, and the first gate electrode is disposed on the polycrystalline semiconductor layer of the first switching transistor.

[0020] In an exemplary embodiment, the first switch transistor further includes a second gate electrode disposed below the polycrystalline semiconductor layer of the first switch transistor. The second gate electrode of the first switch transistor receives a driving voltage flowing to the driving voltage line.

[0021] In an exemplary embodiment, the driving transistor further includes an overlapping layer disposed between the substrate and the first gate electrode of the driving transistor. The overlapping layer receives a driving voltage and is electrically connected to the second gate electrode of the second switching transistor so that the driving voltage is applied to the second gate electrode of the second switching transistor.

[0022] In an exemplary embodiment, the organic light emitting diode display further includes a driving voltage applying unit. The driving transistor further includes a second gate electrode disposed on the polycrystalline semiconductor layer of the driving transistor, and the driving voltage applying unit applies the driving voltage to the overlapping layer and the second gate electrode of the driving transistor.

[0023] In an exemplary embodiment, the second switching transistor includes a gate electrode and a polycrystalline semiconductor layer, the gate electrode is disposed on a substrate, and the polycrystalline semiconductor layer is disposed on the gate electrode of the second switching transistor and includes a first electrode, a second electrode, and a channel.

[0024] In an exemplary embodiment, the compensation transistor initializes the first gate electrode of the driving transistor.

[0025] In an exemplary embodiment, the compensation transistor further includes a second gate electrode disposed below the polycrystalline semiconductor layer of the compensation transistor. The second gate electrode of the compensation transistor receives a driving voltage flowing to the driving voltage line.

[0026] According to an exemplary embodiment, an organic light emitting diode display includes a substrate, a pixel arranged on the substrate, a scan line, a data line, a driving voltage line, and an initialization voltage line. The scan line, the data line, the driving voltage line, and the initialization voltage line are connected to the pixel. The pixel includes an organic light emitting element, a first switching transistor connected to the scan line, a driving transistor that applies a current to the organic light emitting element, and a compensation transistor that compensates for the operation of the driving transistor. The driving transistor includes a first gate electrode, a polycrystalline semiconductor layer, and a second gate electrode, the first gate electrode is arranged on the substrate, the polycrystalline semiconductor layer is arranged on the first gate electrode and includes a first electrode, a second electrode, and a channel, and the second gate electrode is arranged on the polycrystalline semiconductor layer of the driving transistor. The compensation transistor includes a polycrystalline semiconductor layer and a first gate electrode, the polycrystalline semiconductor layer includes a first electrode, a second electrode, and a channel, and the first gate electrode is arranged on the polycrystalline semiconductor layer of the compensation transistor. The compensation transistor does not include a second gate electrode arranged below the polycrystalline semiconductor layer of the compensation transistor.

[0027] According to an exemplary embodiment of the present invention, although the protrusion may be formed in the polycrystalline semiconductor layer, since the gate electrode of the driving transistor is arranged below the polycrystalline semiconductor layer, the thickness of the gate insulating layer may be reduced and the thickness of the display device may be reduced. Furthermore, since the gate electrode of the driving transistor is arranged below the polycrystalline semiconductor layer, if the thickness of the gate insulating layer is reduced, the characteristic (hysteresis) of the driving transistor is reduced so that an instantaneous afterimage is not generated in the displayed image. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0029] Figure 1 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0030] Figure 2 is a timing diagram of signals applied to one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0031] Figure 3 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0032] Figure 4 is a view schematically showing the structure of an upper cladding layer due to a protrusion generated in a polycrystalline semiconductor layer.

[0033] Figure 5 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0034] Figure 6 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0035] Figure 7 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0036] Figure 8 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0037] Fig. 9 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0038] Fig.10is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0039] Fig.11 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0040] Fig.12 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0041] Fig.13 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0042] Fig.14 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0043] Fig.15 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment. DETAILED DESCRIPTION

[0044] Hereinafter, exemplary embodiments of the present invention will be described more fully with reference to the accompanying drawings. Throughout the drawings, like reference numerals represent like elements.

[0045] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.

[0046] Spatially relative terms such as "beneath", "below", "lower", "under", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the drawings. For example, if the device in the figure is turned over, the elements described as being "below", "beneath" or "under" other elements or features will then be oriented to be "above" other elements or features. Therefore, the exemplary terms "below" and "under" can include both orientations of above and below.

[0047] It should be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and these elements are not limited by these terms. Therefore, the "first" element in an exemplary embodiment may be described as the "second" element in another exemplary embodiment.

[0048] Descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

[0049] Reference Figures 1 to 3 An organic light emitting diode display according to an exemplary embodiment is described.

[0050] Figure 1 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment. Figure 2 is a timing diagram of signals applied to one pixel of an organic light emitting diode display according to an exemplary embodiment. Figure 3 According to an exemplary embodiment (e.g., Figure 1 A cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment shown in FIG.

[0051] Reference Figure 1 , a pixel PX of the organic light emitting diode display includes a plurality of transistors T1, T2, T3, T4, T5, T6 and T7 connected to signal lines 127, 151, 152, 153, 158, 171, 172 and 741, a storage capacitor Cst and an organic light emitting diode OLED.

[0052] Reference Figure 3 , the driving transistor T1 includes a gate electrode G1 (referred to as a driving gate electrode) disposed below the polycrystalline semiconductor layer. The polycrystalline semiconductor layer includes a first electrode S1, a second electrode D1, and a channel disposed therebetween. In contrast, in the other transistors T2 to T7, the gate electrodes G2, G3, G4, G5, G6, and G7 are disposed on the polycrystalline semiconductor layer. Figure 3, G4, G5, G6, and G7 are shown as G, S4, S5, S6, and S7 are shown as S, and D4, D5, D6, and D7 are shown as D. In the driving transistor T1, unlike the gate electrodes G2, G3, G4, G5, G6, and G7 of the other transistors T2 to T7 that may be affected by the protrusion of the polycrystalline semiconductor layer, the gate electrode G1 is not affected by the protrusion of the polycrystalline semiconductor layer. In an exemplary embodiment, the driving transistor T1 is used to complete the main function of supplying current to the organic light emitting diode OLED, and the other transistors T2 to T7 only perform the function of preparing or initializing the operation of the driving transistor T1. As a result, the influence on the display quality caused by the protrusion of the polycrystalline semiconductor layer can be reduced.

[0053] Reference Figure 1 and Figure 3 , the driving transistor T1 for providing current to the organic light emitting diode OLED further includes an overlapping layer M1 and a second gate electrode G1-2 overlapping the overlapping layer M1. For the convenience of explanation, Figure 1 The overlapping layer M1 is not shown in the figure. According to an exemplary embodiment, the overlapping layer M1 may be omitted. The second gate electrode G1-2 is arranged on a side opposite to the gate electrode G1 of the driving transistor T1, wherein a semiconductor layer forming a channel of the driving transistor T1 is arranged between them. The overlapping layer M1 is arranged below the gate electrode G1 of the driving transistor T1. The second gate electrode G1-2 and the overlapping layer M1 are electrically connected to each other, and a driving voltage ELVDD is applied thereto. A predetermined voltage (driving voltage ELVDD) is applied to the second gate electrode G1-2 so that the second gate electrode G1-2 does not serve as a gate electrode of the transistor. As Figure 3 As shown in FIG. 1 , the second gate electrode G1 - 2 is disposed on a channel of a polycrystalline semiconductor layer including a first electrode S1 , a second electrode D1 , and a channel disposed therebetween.

[0054] The pixel PX according to the exemplary embodiment includes a total of seven transistors T1 to T7 .

[0055] The seven transistors T1 to T7 include a driving transistor T1 that supplies current to the organic light emitting diode OLED, and also include a second transistor T2 that is connected to the scan line 151 and the data line 171 and provides a data voltage Dm in the pixel PX. The third transistor T3 is also connected to the scan line 151. The second transistor T2 and the third transistor T3 connected to the scan line 151 may each be referred to as a switching transistor. Other transistors for operating the organic light emitting diode OLED may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and each of these transistors may be referred to as a compensation transistor.

[0056] The plurality of signal lines 127, 151, 152, 153, 158, 171, 172, and 741 may include a scan line 151, a previous scan line 152, a light emission control line 153, a bypass control line 158, a data line 171, a driving voltage line 172, an initialization voltage line 127, and a common voltage line 741. The bypass control line 158 may be a part of the previous scan line 152 or may be electrically connected to the previous scan line 152.

[0057] The scan line 151 is connected to the gate driver and transmits the scan signal Sn to the second transistor T2 and the third transistor T3. The previous scan line 152 is connected to the gate driver and transmits the previous scan signal Sn-1 applied to the pixel PX arranged at the previous stage to the fourth transistor T4. The light emission control line 153 is connected to the light emission controller and transmits the light emission control signal EM controlling the time when the organic light emitting diode OLED emits to the fifth transistor T5 and the sixth transistor T6. The bypass control line 158 transmits the bypass signal GB to the seventh transistor T7, and according to an exemplary embodiment, may transmit the same signal as the previous scan signal Sn-1.

[0058] The data line 171 is a wiring for transmitting a data voltage Dm generated from a data driver. The brightness emitted by the organic light emitting diode OLED (also referred to as an organic light emitting device) changes according to the data voltage Dm. The driving voltage line 172 applies a driving voltage ELVDD, the initialization voltage line 127 transmits an initialization voltage Vint for initializing the driving transistor T1, and the common voltage line 741 applies a common voltage ELVSS. The voltages applied to the driving voltage line 172, the initialization voltage line 127, and the common voltage line 741 may be predetermined voltages, respectively.

[0059] Next, a plurality of transistors are described in detail.

[0060] The driving transistor T1 controls the magnitude of the output current according to the applied data voltage Dm, and the output driving current Id is applied to the organic light emitting diode OLED. As a result, the brightness of the organic light emitting diode OLED is controlled according to the data voltage Dm. For this purpose, the first electrode S1 (also referred to as the input terminal) of the driving transistor T1 is arranged to receive the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5. The first electrode S1 of the driving transistor T1 is also connected to the second electrode D2 of the second transistor T2, thereby also receiving the data voltage Dm. The second electrode D1 (also referred to as the output terminal) is arranged to output current toward the organic light emitting diode OLED and is connected to the anode of the organic light emitting diode OLED via the sixth transistor T6. The gate electrode G1 is connected to one electrode (the second storage electrode E2) of the storage capacitor Cst. Accordingly, the voltage of the gate electrode G1 changes according to the voltage stored in the storage capacitor Cst, and as a result, the driving current Id output by the driving transistor T1 changes. The gate electrode G1 is arranged between the polycrystalline semiconductor layer and the substrate, thereby being arranged below the polycrystalline semiconductor layer. Moreover, the second gate electrode G1-2 is arranged on the polycrystalline semiconductor layer and directly receives the driving voltage ELVDD. The driving voltage ELVDD is also applied to the overlapping layer M1 electrically connected to the second gate electrode G1-2, and the overlapping layer M1 is arranged between the gate electrode G1 and the substrate. The second gate electrode G1-2 drifts the characteristics (threshold voltage value) of the driving transistor T1 due to the driving voltage ELVDD in the channel region (region between the second electrode D1 and the first electrode S1) of the polycrystalline semiconductor layer, so that the characteristics of the driving transistor T1 are improved.

[0061] The second transistor T2 receives the data voltage Dm in the pixel PX. The gate electrode G2 is connected to the scan line 151, and the first electrode S2 is connected to the data line 171. The second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the first electrode S1 of the driving transistor T1. The gate electrode G2 is arranged on the polycrystalline semiconductor layer where the channel of the second transistor T2 is arranged.

[0062] The third transistor T3 transmits the compensation voltage (voltage Dm+Vth) of the data voltage Dm changed by the driving transistor T1 to the second storage electrode E2 of the storage capacitor Cst. The gate electrode G3 of the third transistor T3 is connected to the scan line 151. The first electrode S3 of the third transistor T3 is connected to the second electrode D1 of the driving transistor T1, and the second electrode D3 of the third transistor T3 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. The third transistor T3 is turned on according to the scan signal Sn transmitted through the scan line 151. When turned on, the third transistor T3 connects the gate electrode G1 and the second electrode D1 of the driving transistor T1, and connects the second electrode D1 of the driving transistor T1 with the second storage electrode E2 of the storage capacitor Cst. The gate electrode G3 is arranged on the polycrystalline semiconductor layer where the channel of the third transistor T3 is arranged.

[0063] The fourth transistor T4 has a function of initializing the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G4 of the fourth transistor T4 is connected to the previous scan line 152, and the first electrode S4 is connected to the initialization voltage line 127. The second electrode D4 of the fourth transistor T4 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 via the second electrode D3 of the third transistor T3. The fourth transistor T4 transmits the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst according to the previous scan signal Sn-1 transmitted through the previous scan line 152. Accordingly, the gate voltage of the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint may be a voltage capable of turning on the driving transistor T1 by having a low voltage value. The gate electrode G4 is arranged on the polycrystalline semiconductor layer where the channel of the fourth transistor T4 is arranged.

[0064] The fifth transistor T5 has a function of transmitting the driving voltage ELVDD to the driving transistor T1. The gate electrode G5 is connected to the light emission control line 153, and the first electrode S5 is connected to the driving voltage line 172. The second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1. The gate electrode G5 is arranged on the polycrystalline semiconductor layer where the channel of the fifth transistor T5 is arranged.

[0065] The sixth transistor T6 has a function of transmitting the driving current Id output from the driving transistor T1 to the organic light emitting diode OLED. The gate electrode G6 is connected to the light emitting control line 153, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1. The second electrode D6 of the sixth transistor T6 is connected to the anode of the organic light emitting diode OLED. The gate electrode G6 is arranged on the polycrystalline semiconductor layer where the channel of the sixth transistor T6 is arranged.

[0066] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light emission control signal EM transmitted through the light emission control line 153. When the driving voltage ELVDD is transmitted to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, the driving transistor T1 outputs the driving current Id according to the voltage of the gate electrode G1 of the driving transistor T1 (for example, the voltage of the second storage electrode E2 of the storage capacitor Cst). The output driving current Id is transmitted to the organic light emitting diode OLED through the sixth transistor T6. When the current Ioled flows to the organic light emitting diode OLED, the organic light emitting diode OLED emits light.

[0067] The seventh transistor T7 has a function of initializing the anode of the organic light emitting diode OLED. The gate electrode G7 is connected to the bypass control line 158, the first electrode S7 is connected to the anode of the organic light emitting diode OLED, and the second electrode D7 is connected to the initialization voltage line 127. The bypass control line 158 may be connected to the previous scan line 152, and the bypass signal GB is applied with a signal having the same timing as the previous scan signal Sn-1. In an exemplary embodiment, the bypass control line 158 is not connected to the previous scan line 152, and a signal independent of the previous scan signal Sn-1 may be transmitted. When the seventh transistor T7 is turned on according to the bypass signal GB, the initialization voltage Vint is applied to the anode of the organic light emitting diode OLED for initialization. The gate electrode G7 is arranged on the polycrystalline semiconductor layer where the channel of the seventh transistor T7 is arranged.

[0068] The pixel PX further includes a storage capacitor Cst. The data voltage Dm passes through the driving transistor T1 and is applied to the storage capacitor Cst to be stored.

[0069] The first storage electrode E1 of the storage capacitor Cst is connected to the driving voltage line 172, and the second storage electrode E2 is connected to the gate electrode G1 of the driving transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. As a result, the second storage electrode E2 determines the voltage of the gate electrode G1 of the driving transistor T1 (the gate-source voltage Vgs of the driving transistor T1), the data voltage Dm is applied to the second storage electrode E2 through the second electrode D3 of the third transistor T3, and the initialization voltage Vint is applied to the second storage electrode E2 through the second electrode D4 of the fourth transistor T4.

[0070] The pixel PX further includes an organic light emitting diode OLED having an anode connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7 and a cathode connected to a common voltage line 741 transmitting a common voltage ELVSS.

[0071] exist Figure 1 In the exemplary embodiment of the present invention, the pixel circuit includes seven transistors T1 to T7 and one capacitor Cst. However, the pixel circuit is not limited thereto. For example, according to the exemplary embodiment, the number of transistors, the number of capacitors, and their connections may be variously changed.

[0072] The organic light emitting diode display includes a display area displaying an image, and pixels PX are arranged in the display area in various forms such as a matrix.

[0073] Now refer to Figure 1 and Figure 2 The operation of one pixel of the organic light emitting diode display according to the exemplary embodiment is described.

[0074] During the initialization period, the previous scan signal Sn-1 of a low level is supplied to the pixel PX through the previous scan line 152. Therefore, the fourth transistor T4 receiving the previous scan signal Sn-1 is turned on, and the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst through the fourth transistor T4. As a result, the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint is a low voltage so that the driving transistor T1 can be turned on.

[0075] During the initialization period, the bypass signal GB of the low level is also applied to the seventh transistor T7. Therefore, the seventh transistor T7 receiving the bypass signal GB is turned on so that the initialization voltage Vint is applied to the anode of the organic light emitting diode OLED through the seventh transistor T7. As a result, the anode of the organic light emitting diode OLED is also initialized.

[0076] Next, during a data writing period (hereinafter referred to as a writing period), a low-level scan signal Sn is supplied to the pixel PX through the scan line 151. The second transistor T2 and the third transistor T3 are turned on by the low-level scan signal Sn.

[0077] When the second transistor T2 is turned on, the data voltage Dm is input to the first electrode S1 of the driving transistor T1 after passing through the second transistor T2.

[0078] Moreover, during the data write period, the third transistor T3 is turned on, and as a result, the second electrode D1 of the driving transistor T1 is electrically connected to the gate electrode G1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G1 of the driving transistor T1 and the second electrode D1 are connected in a diode connection. In addition, a low voltage (initialization voltage Vint) is applied to the gate electrode G1 of the driving transistor T1 during the initialization period so that the driving transistor T1 is in a conducting state. As a result, the data voltage Dm input to the first electrode S1 of the driving transistor T1 passes through the channel of the driving transistor T1 and is output from the second electrode D1, and is then stored in the second storage electrode E2 of the storage capacitor Cst through the third transistor T3. In this case, the voltage applied to the second storage electrode E2 changes according to the threshold voltage Vth of the driving transistor T1, and when the data voltage Dm is applied to the first electrode S1 of the driving transistor T1 and the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1, the voltage output to the second electrode D1 may have a value (Vgs+Vth). Here, the voltage Vgs is the difference between the voltages applied to the gate electrode G1 and the first electrode S1 of the driving transistor T1, and thus has a value (Dm-Vint). Therefore, the voltage output from the second electrode D1 and stored in the second storage electrode E2 may have a value (Dm-Vint+Vth).

[0079] Next, during the light emission period, the light emission control signal EM supplied from the light emission control line 153 has a value of a low level so that the fifth transistor T5 and the sixth transistor T6 are turned on.

[0080] Since the fifth transistor T5 and the sixth transistor T6 are turned on, the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1, and the second electrode D1 of the driving transistor T1 is connected to the organic light emitting diode OLED. The driving current Id is generated according to the voltage difference between the voltage of the gate electrode G1 of the driving transistor T1 and the voltage of the first electrode S1 (for example, the driving voltage ELVDD). The driving current Id of the driving transistor T1 may have a value proportional to the square of the value (Vgs-Vth). Here, the value Vgs is the same as the voltage difference applied to the two terminals of the storage capacitor Cst, and the value Vgs is (Vg-Vs), thereby having a value (Dm-Vint+Vth-ELVDD). Here, when the value (Vgs-Vth) is obtained by subtracting the value Vth, the value (Dm-Vint-ELVDD) is obtained. That is, the driving current Id of the driving transistor T1 has a value that is independent of the threshold voltage Vth of the driving transistor T1.

[0081] Therefore, although the driving transistor T1 disposed in each pixel PX has a different threshold voltage Vth due to process distribution, the output current of each driving transistor T1 may be constant, thereby improving its non-uniformity characteristics.

[0082] In the driving transistor T1, the gate electrode G1 is formed below the polycrystalline semiconductor layer. As a result, even if a protrusion is formed in the polycrystalline semiconductor layer, the driving transistor T1 can operate correctly regardless of the protrusion (for example, the protrusion does not have a negative impact on the driving transistor T1), and obtain constant characteristics. As a result, the display device can get rid of display defects such as instantaneous afterimages.

[0083] In the above equation, in the case of a P-type transistor using a polycrystalline semiconductor layer, the value Vth may have a value slightly greater than 0 or a negative value. Moreover, the expression of + and - may change according to the direction of the calculated voltage. However, one point that does not change is that the drive current Id as the output current of the drive transistor T1 may have a value that does not depend on the threshold voltage Vth.

[0084] When the above-mentioned lighting period ends, the initialization period starts again and the same operation is repeated from the beginning.

[0085] For the first and second electrodes of the plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 , one may be a source electrode S and the other may be a drain electrode D according to an applied direction of a voltage or a current.

[0086] According to an exemplary embodiment, when the seventh transistor T7 in the initialization period initializes the anode of the organic light emitting diode OLED, a small amount of leakage current from the driving transistor T1 can also be prevented from flowing toward the organic light emitting diode OLED. In this case, a small amount of current is discharged to the initialization voltage Vint terminal through the seventh transistor T7 as a bypass current Ibp. As a result, since the organic light emitting diode OLED does not emit unnecessary light, black and gray can be displayed more clearly and the contrast can also be improved. In this case, the bypass signal GB may be a signal with a different timing from the timing of the previous scan signal Sn-1. According to an exemplary embodiment, the seventh transistor T7 may be omitted.

[0087] Furthermore, in the pixel PX operated as described above, when the driving voltage ELVDD is applied to the second gate electrode G1 - 2 of the driving transistor T1 , the characteristic (threshold voltage) of the driving transistor T1 shifts, so that the display quality is improved.

[0088] Next, refer to Figure 3 A cross-sectional structure of a transistor included in an organic light emitting diode display is described.

[0089] Figure 3 A cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display is shown. From left to right, a driving transistor T1, a third transistor T3, and a second transistor T2 are shown, followed by a fourth transistor T4 to a seventh transistor T7. The cross-sections of the fourth transistor T4 to the seventh transistor T7 are the same. Therefore, for the convenience of explanation, these cross-sections are combined and shown as one. In this regard, Figure 3 , G corresponds to G4 to G7, D corresponds to D4 to D7, and S corresponds to S4 to S7.

[0090] According to an exemplary embodiment, the organic light emitting diode display includes substrates 110 and 110-1 including, for example, plastic or polyimide (PI), and barrier layers 111 and 111-1 disposed on the substrates 110 and 110-1, respectively. The substrates 110 and 110-1 may be collectively referred to as a substrate, and the barrier layers 111 and 111-1 may be collectively referred to as a barrier layer. According to an exemplary embodiment, the substrate and the barrier layer may be formed to have the same number and be the same as Figure 3 Unlike those shown in , they may include only one pair, or may form three or more pairs. The barrier layers 111 and 111 - 1 may be formed to reduce the influence applied to the flexible substrates 110 and 110 - 1 when forming the upper cladding layer.

[0091] Now, a cross section of the driving transistor T1 is described.

[0092] The overlapping layer M1 is disposed on the upper barrier layer 111, and the overlapping layer M1 is covered by the buffer layer 112. The gate electrode G1 is formed on the buffer layer 112, and the gate electrode G1 is covered by the first gate insulating layer 141. The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S1, a second electrode D1, and a channel disposed therebetween.

[0093] The polycrystalline semiconductor layer is covered with a second gate insulating layer 142, and a second gate electrode G1-2 is formed on the second gate insulating layer 142. The second gate electrode G1-2 is covered with an interlayer insulating layer 160.

[0094] A data conductor is formed on the interlayer insulating layer 160. The data conductor includes a data line 171 and a driving voltage line 172 transmitting a driving voltage ELVDD.

[0095] The driving voltage line 172 includes a driving voltage applying portion C-1 connected to the second gate electrode G1-2 and the overlapping layer M1 through an opening that exposes the second gate electrode G1-2 and the overlapping layer M1, respectively. The driving voltage applying portion C-1 may be a portion of the driving voltage line 172 that extends or is only electrically connected.

[0096] The gate electrode G1 and the second gate electrode G1-2 are arranged above and below the channel of the driving transistor T1. In an exemplary embodiment, the gate electrode G1 and the second gate electrode G1-2 may have a width corresponding to (eg, substantially equal to) the width of the channel. However, in an exemplary embodiment, as shown in FIG. Figure 3 As shown in FIG. 1 , it is shown that the gate electrode G1 is directed toward the third transistor T3 (eg, Figure 3 In an exemplary embodiment, the gate electrode G1 has a width corresponding to (eg, substantially equal to) the width of the channel of the driving transistor T1 except for the extension portion so that the gate electrode G1 disposed below the channel is connected to the second electrode D3 of the third transistor T3.

[0097] When doping the polycrystalline semiconductor layer, the second gate electrode G1-2 may be used as a mask. As a result, the width of the second gate electrode G1-2 may conform to the width of the channel. According to an exemplary embodiment, since the driving transistor T1 includes the second gate electrode G1-2 and the overlapping layer M1 as a portion receiving the driving voltage ELVDD, the overlapping layer M1 may be omitted.

[0098] The driving transistor T1 has a bottom gate (eg, the second gate electrode G1-2), and the driving voltage ELVDD is applied to the second gate electrode G1-2, thereby drifting the characteristics of the channel. As a result, according to exemplary embodiments, the protrusions (see Figure 4 ) and the defects caused by it.

[0099] Next, a cross section of the third transistor T3 is described.

[0100] The buffer layer 112 is disposed on the upper barrier layer 111 , and the first gate insulating layer 141 is disposed on the buffer layer 112 .

[0101] The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S3, a second electrode D3, and a channel disposed therebetween.

[0102] The polycrystalline semiconductor layer is covered with the second gate insulating layer 142, and the gate electrode G3 (151) is formed on the second gate insulating layer 142. The gate electrode G3 (151) is covered with the interlayer insulating layer 160.

[0103] A connection portion 71 is formed on the interlayer insulating layer 160. The connection portion 71 electrically connects the second electrode D3 of the third transistor T3 and the gate electrode G1 of the driving transistor T1 through an opening that exposes the second electrode D3 of the third transistor T3 and the gate electrode G1 of the driving transistor T1, respectively. Since the output of the driving transistor T1 changes according to the voltage of the gate electrode G1, the voltage output to the second electrode D3 of the third transistor T3 affects the output of the driving transistor T1.

[0104] The gate electrode G3 (151) is disposed on the channel of the third transistor T3 and has a width corresponding to (eg, substantially equal to) the width of the channel. The gate electrode G3 (151) may be used as a mask when doping the polycrystalline semiconductor layer.

[0105] As described above, unlike the driving transistor T1, in the exemplary embodiment, the third transistor T3 has a top gate and does not include a bottom gate. Therefore, unlike the driving transistor T1, in the exemplary embodiment, the third transistor T3 does not include a structure that shifts the characteristics of the channel.

[0106] Next, a cross section of the second transistor T2 is described.

[0107] The buffer layer 112 is disposed on the upper barrier layer 111 , and the first gate insulating layer 141 is disposed on the buffer layer 112 .

[0108] The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S2, a second electrode D2, and a channel disposed therebetween.

[0109] The polycrystalline semiconductor layer is covered with the second gate insulating layer 142, and the gate electrode G2 (151) is formed on the second gate insulating layer 142. The gate electrode G2 (151) is covered with the interlayer insulating layer 160.

[0110] The data line 171 is formed on the interlayer insulating layer 160. The data line 171 is connected to the first electrode S2 of the second transistor T2 through an opening exposing the first electrode S2 of the second transistor T2. When the second transistor T2 is turned on, the data voltage Dm is input to the corresponding pixel PX.

[0111] The gate electrode G2 (151) is disposed on the channel of the second transistor T2 and has a width corresponding to (eg, substantially equal to) the width of the channel. The gate electrode G2 (151) may be used as a mask when doping the polycrystalline semiconductor layer.

[0112] As described above, in the exemplary embodiment, unlike the driving transistor T1, the second transistor T2 has a top gate and does not include a bottom gate. Therefore, in the exemplary embodiment, the second transistor T2 does not include a structure that shifts the characteristics of the channel.

[0113] Hereinafter, the fourth to seventh transistors T4 to T7 included in the pixel PX are grouped and described. A first electrode of each of the fourth to seventh transistors T4 to T7 is indicated by S, a second electrode thereof is indicated by D, and a gate electrode thereof is indicated by G.

[0114] The buffer layer 112 is disposed on the upper barrier layer 111, and the first gate insulating layer 141 is disposed on the buffer layer 112. The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S, a second electrode D, and a channel disposed therebetween.

[0115] The polycrystalline semiconductor layer is covered with a second gate insulating layer 142, and a gate electrode G is formed on the second gate insulating layer 142. The gate electrode G is covered with an interlayer insulating layer 160.

[0116] The fourth transistor T4 to the seventh transistor T7 have Figure 1 The connection relationship shown in , and arranged in the pixel PX.

[0117] The gate electrode G is disposed on channels of the fourth to seventh transistors T4 to T7 and has a width corresponding to (eg, substantially equal to) a width of the channel. The gate electrode G may be used as a mask when doping the polycrystalline semiconductor layer.

[0118] As described above, in the exemplary embodiment, the fourth to seventh transistors T4 to T7 also have top gates and do not include bottom gates. As a result, in the exemplary embodiment, the fourth to seventh transistors T4 to T7 do not include a structure that shifts the characteristics of a channel.

[0119] In the organic light emitting diode display having the above structure, only the driving transistor T1 performing the main operation in the pixel PX has a bottom gate (a gate electrode arranged below the polycrystalline semiconductor layer), and the remaining transistors have a top gate (a gate electrode arranged on the polycrystalline semiconductor layer) and do not have a bottom gate.

[0120] The polycrystalline semiconductor layer is formed by forming a semiconductor layer of amorphous silicon and irradiating laser light onto the semiconductor layer to crystallize it. A protrusion may be formed in the polycrystalline semiconductor layer during the crystallization step, and referring to Figure 4 An extended cross section in a structure using a top gate is described.

[0121] Figure 4 is a view schematically showing the structure of an upper cladding layer due to a protrusion generated in a polycrystalline semiconductor layer.

[0122] Figure 4The cross-sectional view in FIG. 1 shows a structure using a top gate in the driving transistor T1. Two gate layers GL1 and GL2 are formed on the polycrystalline semiconductor layer Poly.

[0123] A polycrystalline semiconductor layer Poly having a protrusion is arranged on a substrate 110. The protrusion formed in the polycrystalline semiconductor layer Poly is formed to form a protruding protrusion in the first gate insulating layer 141 and the second gate insulating layer 142 and the two gate layers GL1 and GL2 arranged thereon. As a result, charges are accumulated on the protrusions of the gate layers GL1 and GL2, and the thickness of the first gate insulating layer 141 and the second gate insulating layer 142 becomes thinner, so that the insulation aspect may be destroyed. In order to prevent insulation breakdown, the thickness of the first gate insulating layer 141 and the second gate insulating layer 142 should be thick enough, and as a result, there is a limit on the reduction of the thickness of the display device.

[0124] However, in the exemplary embodiment according to the present invention, the gate electrode G1 of the driving transistor T1 is formed under the protrusion of the polycrystalline semiconductor layer (bottom gate), and as a result, the influence of the protrusion is reduced or eliminated. That is, even if the thickness of the first gate insulating layer 141 is thinned, sufficient insulation characteristics can be obtained.

[0125] Unlike the driving transistor T1, the second transistor T2 to the seventh transistor T7 have a top gate structure (e.g., they do not include a bottom gate), and the gate electrode is arranged on the polycrystalline semiconductor layer including the protrusion. However, the second transistor T2 to the seventh transistor T7 do not play a major role in providing current to the organic light emitting diode OLED, and therefore, the display quality is not particularly affected by the protrusion corresponding to the second transistor T2 to the seventh transistor T7. However, in an exemplary embodiment, at least some of the second transistor T2 to the seventh transistor T7 may have a bottom gate structure to further improve the display characteristics.

[0126] exist Figures 1 to 3 In the exemplary embodiment of the present invention, the characteristics of the driving transistor T1 are drifted by forming the second gate electrode G1-2 receiving the driving voltage ELVDD only in the driving transistor T1. However, the exemplary embodiment of the present invention is not limited thereto. For example, according to the exemplary embodiment, at least some of the second transistor T2 to the seventh transistor T7 may include a second gate electrode receiving the driving voltage ELVDD. Compared with using the second gate electrode G1-2 only in the driving transistor T1, using the second gate electrode in some of the second transistor T2 to the seventh transistor T7 may increase the complexity and cost of the display device, but may further improve the display characteristics.

[0127] Next, refer to Figure 5 and Figure 6An exemplary embodiment further including the second gate electrode G2 - 2 receiving the driving voltage ELVDD applied to the second transistor T2 is described.

[0128] Figure 5 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment. Figure 6 According to an exemplary embodiment (e.g., Figure 5 A cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment shown in FIG.

[0129] and Figure 1 Compared with the circuit diagram, Figure 5 In the circuit diagram of , the second transistor T2 further includes a second gate electrode G2-2, and the second gate electrode G2-2 is connected to the driving voltage line 172. Therefore, the second gate electrode G2-2 receives the driving voltage ELVDD, and as a result, in addition to the channel characteristics of the driving transistor T1, the channel characteristics of the second transistor T2 also drift.

[0130] and Figure 3 Compared with the cross-sectional diagram, Figure 6 In the cross-sectional view of FIG. 1 , the second transistor T2 further includes a second gate electrode G2 - 2 , and further includes a driving voltage applying part C- 2 for applying the driving voltage ELVDD to the second gate electrode G2 - 2 .

[0131] Reference Figure 5 and Figure 6 , for convenience of explanation, further description of previously described elements may be omitted.

[0132] A cross section of the second transistor T2 will now be described in detail.

[0133] The buffer layer 112 is disposed on the upper barrier layer 111, and the second gate electrode G2-2 is disposed on the buffer layer 112. The second gate electrode G2-2 is covered by the first gate insulating layer 141.

[0134] The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S2, a second electrode D2, and a channel disposed therebetween.

[0135] The polycrystalline semiconductor layer is covered with the second gate insulating layer 142, and the gate electrode G2 (151) is formed on the second gate insulating layer 142. The gate electrode G2 (151) is covered with the interlayer insulating layer 160.

[0136] The data line 171 and the driving voltage applying part C-2 are formed on the interlayer insulating layer 160. The data line 171 is connected to the first electrode S2 of the second transistor T2 through the opening exposing the first electrode S2 of the second transistor T2. When the second transistor T2 is turned on, the data voltage Dm is input to the corresponding pixel PX. The driving voltage applying part C-2 is connected to the second gate electrode G2-2 of the second transistor T2 through the opening exposing the second gate electrode G2-2. The driving voltage applying part C-2 applies the driving voltage ELVDD to the second gate electrode G2-2. As a result, the channel characteristics of the second transistor T2 drift.

[0137] The gate electrode G2 (151) is disposed on the channel of the second transistor T2 and has a width corresponding to (eg, substantially equal to) the width of the channel. The gate electrode G2 (151) may be used as a mask when doping the polycrystalline semiconductor layer.

[0138] As described above, the second transistor T2 includes a top gate. Figure 5 and Figure 6 In the exemplary embodiment of , a second gate electrode G2 - 2 receiving the driving voltage ELVDD is additionally included so that the channel characteristics of the second transistor T2 also shift.

[0139] However, the structure of the second transistor T2 is not limited thereto, and according to an exemplary embodiment, the second transistor T2 may be formed with a bottom gate, and the second gate electrode G2-2 may be formed as a top gate. In this case, the gate electrode G2 (151) may be formed under the polycrystalline semiconductor layer so that it is connected to the scan line 151, and the second gate electrode G2-2 may be formed on the polycrystalline semiconductor layer so that the driving voltage ELVDD is applied.

[0140] Next, refer to Figure 7 and Figure 8 An exemplary embodiment further including the second gate electrode G3 - 2 receiving the driving voltage ELVDD applied to the third transistor T3 is described.

[0141] Figure 7 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment. Figure 8 According to an exemplary embodiment (e.g., Figure 7 A cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment shown in FIG.

[0142] and Figure 1 Compared with the circuit diagram, Figure 7In the circuit diagram of , the third transistor T3 further includes a second gate electrode G3-2, and the second gate electrode G3-2 is connected to the driving voltage line 172. Therefore, the second gate electrode G3-2 receives the driving voltage ELVDD, and as a result, in addition to the channel characteristics of the driving transistor T1, the channel characteristics of the third transistor T3 also drift.

[0143] and Figure 1 Compared with the cross-sectional diagram, Figure 8 In the cross-sectional view of FIG. 1 , the third transistor T3 further includes a second gate electrode G3 - 2 , and further includes a driving voltage applying part C- 3 for applying the driving voltage ELVDD to the second gate electrode G3 - 2 .

[0144] Reference Figure 7 and Figure 8 , for convenience of explanation, further description of previously described elements may be omitted.

[0145] A cross section of the third transistor T3 will now be described in detail.

[0146] The buffer layer 112 is disposed on the upper barrier layer 111, and the second gate electrode G3-2 is disposed on the buffer layer 112. The second gate electrode G3-2 is covered by the first gate insulating layer 141.

[0147] The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S3, a second electrode D3, and a channel disposed therebetween.

[0148] The polycrystalline semiconductor layer is covered with the second gate insulating layer 142, and the gate electrode G3 (151) is formed on the second gate insulating layer 142. The gate electrode G3 (151) is covered with the interlayer insulating layer 160.

[0149] The connection portion 71 and the driving voltage applying portion C- 3 are formed on the interlayer insulating layer 160 .

[0150] The connection portion 71 electrically connects the second electrode D3 of the third transistor T3 and the gate electrode G1 of the driving transistor T1 through an opening that exposes the second electrode D3 of the third transistor T3 and the gate electrode G1 of the driving transistor T1, respectively. Since the output of the driving transistor T1 changes according to the voltage of the gate electrode G1, the voltage output to the second electrode D3 of the third transistor T3 affects the output of the driving transistor T1.

[0151] The driving voltage applying part C-3 is connected to the second gate electrode G3-2 of the third transistor T3 through the opening exposing the second gate electrode G3-2. The driving voltage applying part C-3 applies the driving voltage ELVDD to the second gate electrode G3-2. As a result, the channel characteristics of the third transistor T3 drift.

[0152] The gate electrode G3 (151) is disposed on the channel of the third transistor T3 and has a width corresponding to (eg, substantially equal to) the width of the channel. The gate electrode G3 (151) may be used as a mask when doping the polycrystalline semiconductor layer.

[0153] As described above, the third transistor T3 includes a top gate. Figure 7 and Figure 8 In the exemplary embodiment of FIG. 1 , a second gate electrode G3 - 2 receiving the driving voltage ELVDD is additionally included so that the channel characteristic of the third transistor T3 also shifts.

[0154] However, the structure of the third transistor T3 is not limited thereto, and according to an exemplary embodiment, the third transistor T3 may be formed with a bottom gate, and the second gate electrode G3-2 may be formed as a top gate. In this case, the gate electrode G3 (151) is formed under the polycrystalline semiconductor layer so that it is connected to the scan line 151, and the second gate electrode G3-2 is formed on the polycrystalline semiconductor layer to receive the driving voltage ELVDD.

[0155] Next, refer to Fig. 9 A method for applying the driving voltage ELVDD to the second gate electrode G3 - 2 of the third transistor T3 is described.

[0156] Fig. 9 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0157] Fig. 9 The cross-sectional structure of each of the transistors T1 to T7 is Figure 8 The cross-sectional structure is basically the same as Figure 8 Unlike the exemplary embodiment shown in Fig. 9 In the exemplary embodiment shown in , the driving voltage applying part C- 3 that applies the driving voltage ELVDD to the second gate electrode G3 - 2 of the third transistor T3 is omitted.

[0158] On the contrary, Fig. 9 In the exemplary embodiment shown in , the second gate electrode G3 - 2 of the third transistor T3 receives the driving voltage ELVDD from the overlapping layer M1 disposed below the driving transistor T1 .

[0159] For example, in Fig. 9, the overlapping layer M1 is arranged under the driving transistor T1 and also includes a portion M1-1 extending under the third transistor T3. The overlapping layer M1 is directly connected to the second gate electrode G3-2 of the third transistor T3 through an opening exposing the extended portion M1-1 of the overlapping layer M1. Since the overlapping layer M1 receives the driving voltage ELVDD through the driving voltage applying part C-1, the driving voltage ELVDD is also applied to the second gate electrode G3-2 of the third transistor T3.

[0160] and Figure 8 Compared to the exemplary embodiment shown in Fig. 9 In the exemplary embodiment shown in , the structure on the interlayer insulating layer 160 is simplified, and the structure below the polycrystalline semiconductor layer (for example, below the gate electrode G1 of the driving transistor T1) is more complicated. A transistor using a polycrystalline semiconductor layer generally uses a top gate type and generally has a more complicated structure when an organic light emitting diode OLED made of a pixel electrode, an organic emission layer, and a common electrode is arranged on the transistor.

[0161] Accordingly, in Fig. 9 In the exemplary embodiment shown in , the relatively simple structure below the polycrystalline semiconductor layer (eg, below the gate electrode G1 of the driving transistor T1 ) becomes more complex, and the structure of the upper region (on the interlayer insulating layer 160 ) is simplified.

[0162] Since the area of ​​the pixel PX becomes smaller at high resolution, Fig. 9 A simple structure on the interlayer insulating layer 160 as in FIG. 1 may be advantageous in some cases.

[0163] Next, refer to Fig.10 and Fig.11 Combination Figures 5 to 8 An exemplary embodiment of an exemplary embodiment of the present invention is described.

[0164] Fig.10 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment. Fig.11 According to an exemplary embodiment (e.g., Fig.10 A cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0165] Reference Fig.10 and Fig.11 , for convenience of explanation, further description of previously described elements may be omitted.

[0166] Fig.10 and Fig.11The exemplary embodiment further includes a second gate electrode G2-2 (eg, a second gate electrode G2-2 receiving a driving voltage ELVDD applied to the second transistor T2) Figure 5 and Figure 6 ), and further comprising a second gate electrode G3-2 (such as the exemplary embodiment of the present invention) receiving the driving voltage ELVDD applied to the third transistor T3 Figure 7 and Figure 8 ).

[0167] and Figure 1 Compared with the circuit diagram, Fig.10 In the circuit diagram of , the second transistor T2 further includes a second gate electrode G2-2, and the third transistor T3 further includes a second gate electrode G3-2. As a result, the second gate electrode G2-2 of the second transistor T2 is connected to the driving voltage line 172, and the second gate electrode G3-2 of the third transistor T3 is also connected to the driving voltage line 172. This structure causes the channel characteristics of the second transistor T2 and the channel characteristics of the third transistor T3 to drift.

[0168] exist Fig.11 In the cross-sectional diagram, Figure 6 and Figure 8 The features of are shown together. For example, Figure 3 Compared with the cross-sectional view of FIG. 1 , the second transistor T2 further includes a second gate electrode G2-2, and the third transistor T3 further includes a second gate electrode G3-2. In addition, a driving voltage applying unit C-2 for applying the driving voltage ELVDD to the second gate electrode G2-2 of the second transistor T2 and a driving voltage applying unit C-3 for applying the driving voltage ELVDD to the second gate electrode G3-2 of the third transistor T3 are also included.

[0169] Fig.11 The exemplary embodiment has a structure in which the two driving voltage applying parts C-2 and C-3 are directly connected. According to the exemplary embodiment, the two driving voltage applying parts C-2 and C-3 may be electrically connected only through the connecting part.

[0170] As described above, the second transistor T2 and the third transistor T3 include a top gate. However, according to an exemplary embodiment, the second transistor T2 and the third transistor T3 may also be formed with a bottom gate, and the second gate electrodes G2-2 and G3-2 may be formed as a top gate. In this case, the gate electrodes G2 and G3 may be formed below the polycrystalline semiconductor layer to be connected to the scan line 151, and the second gate electrodes G2-2 and G3-2 may be formed on the polycrystalline semiconductor layer to receive the driving voltage ELVDD.

[0171] Next, refer to Fig.12 and Fig.13An exemplary embodiment further including the second gate electrode G4 - 2 receiving the driving voltage ELVDD applied to the fourth transistor T4 is described.

[0172] Fig.12 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment. Fig.13 According to an exemplary embodiment (e.g., Fig.12 A cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment shown in FIG.

[0173] Reference Fig.12 and Fig.13 , for convenience of explanation, further description of previously described elements may be omitted.

[0174] and Figure 1 Compared with the circuit diagram, Fig.12 In the circuit diagram of , the fourth transistor T4 further includes a second gate electrode G4-2, and the second gate electrode G4-2 is connected to the driving voltage line 172. Therefore, the second gate electrode G4-2 receives the driving voltage ELVDD, and as a result, the channel characteristics of the fourth transistor T4 drift.

[0175] and Figure 3 Compared with the cross-sectional diagram, Fig.13 In the cross-sectional view of FIG. 4 , the fourth transistor T4 further includes a second gate electrode G4 - 2 , and further includes a driving voltage applying part C- 4 for applying the driving voltage ELVDD to the second gate electrode G4 - 2 .

[0176] A cross section of the fourth transistor T4 will now be described in detail.

[0177] The buffer layer 112 is disposed on the upper barrier layer 111, and the second gate electrode G4-2 is disposed on the buffer layer 112. The second gate electrode G4-2 is covered by the first gate insulating layer 141.

[0178] The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S4, a second electrode D4, and a channel disposed therebetween.

[0179] The polycrystalline semiconductor layer is covered with a second gate insulating layer 142, and a gate electrode G4 is formed on the second gate insulating layer 142. The gate electrode G4 is covered with an interlayer insulating layer 160.

[0180] The driving voltage applying part C-4 is formed on the interlayer insulating layer 160. The driving voltage applying part C-4 is connected to the second gate electrode G4-2 of the second transistor T4 through the opening exposing the second gate electrode G4-2. The driving voltage applying part C-4 applies the driving voltage ELVDD to the second gate electrode G4-2. As a result, the channel characteristics of the fourth transistor T4 drift.

[0181] The gate electrode G4 is disposed on the channel of the fourth transistor T4 and has a width corresponding to (eg, substantially equal to) the width of the channel. The gate electrode G4 may be used as a mask when doping the polycrystalline semiconductor layer.

[0182] As described above, the fourth transistor T4 includes a top gate. However, in an exemplary embodiment, a second gate electrode G4-2 receiving the driving voltage ELVDD is additionally formed so that the channel characteristics of the fourth transistor T4 also shift.

[0183] However, the structure of the fourth transistor T4 is not limited thereto, and according to an exemplary embodiment, the fourth transistor T4 may include a bottom gate, and the second gate electrode G4-2 may be formed as a top gate. In this case, the gate electrode G4 may be formed under the polycrystalline semiconductor layer, and the second gate electrode G4-2 may be formed on the polycrystalline semiconductor layer to receive the driving voltage ELVDD.

[0184] It is possible to provide the features of the exemplary embodiment described above together with Fig.12 and Fig.13 The exemplary embodiment of the exemplary embodiment also includes the characteristics of the exemplary embodiment of the ... Fig.12 and Fig.13 In addition to the exemplary embodiment of the present invention, the second transistor T2 may further include a second gate electrode G2-2 receiving the driving voltage ELVDD, or the third transistor T3 may further include a second gate electrode G3-2 receiving the driving voltage ELVDD. Moreover, the second gate electrodes G2-2 and G3-2 receiving the driving voltage ELVDD may be included in both the second transistor T2 and the third transistor T3.

[0185] In exemplary embodiments, the fifth to seventh transistors T5 to T7 may also include a second gate electrode receiving the driving voltage ELVDD.

[0186] In the above exemplary embodiment, only the driving transistor T1 uses a bottom gate structure (gate electrode arranged below the polycrystalline semiconductor layer), and the other transistors T2 to T7 use a top gate structure (gate electrode arranged on the polycrystalline semiconductor layer).

[0187] However, according to example embodiments, a bottom gate structure may be used in transistors other than the driving transistor T1 so that the influence of characteristics of transistors other than the driving transistor T1 due to the protrusion of the polycrystalline semiconductor layer may be reduced.

[0188] Next, refer to Fig.14 An exemplary embodiment in which the second transistor T2 and the third transistor T3 have a bottom gate structure is described.

[0189] Fig.14 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0190] exist Fig.14 In an exemplary embodiment, Figure 3 Different from the exemplary embodiment of the present invention, the second transistor T2 and the third transistor T3 use a bottom gate structure. Next, the structures of the second transistor T2 and the third transistor T3 are described in detail.

[0191] First, a cross section of the second transistor T2 will be described.

[0192] The buffer layer 112 is disposed on the upper barrier layer 111, and the gate electrode G2 (151) is disposed on the buffer layer 112. The gate electrode G2 (151) is covered by the first gate insulating layer 141.

[0193] The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S2, a second electrode D2, and a channel disposed therebetween.

[0194] The polycrystalline semiconductor layer is covered with the second gate insulating layer 142 , and an interlayer insulating layer 160 is formed on the second gate insulating layer 142 .

[0195] The data line 171 is formed on the interlayer insulating layer 160. The data line 171 is connected to the first electrode S2 of the second transistor T2 through an opening exposing the first electrode S2 of the second transistor T2. When the second transistor T2 is turned on, the data voltage Dm is input to the corresponding pixel PX.

[0196] The gate electrode G2 of the second transistor T2 is arranged below the polycrystalline semiconductor layer so that it has a bottom gate structure, and the gate electrode G2 has a width corresponding to (e.g., substantially equal to) the width of the channel. Moreover, since the gate electrode G2 is arranged below the polycrystalline semiconductor layer, a mask can be used separately when doping the polycrystalline semiconductor layer.

[0197] exist Fig.14In the exemplary embodiment, the second transistor T2 does not separately include a structure for shifting channel characteristics, and according to the exemplary embodiment, may receive a driving voltage ELVDD and may be formed with a second gate electrode disposed on the polycrystalline semiconductor layer.

[0198] Next, a cross section of the third transistor T3 is described.

[0199] The buffer layer 112 is disposed on the upper barrier layer 111, and the gate electrode G3 (151) is disposed on the buffer layer 112. The gate electrode G3 (151) is covered by the first gate insulating layer 141.

[0200] The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S3, a second electrode D3, and a channel disposed therebetween.

[0201] The polycrystalline semiconductor layer is covered with the second gate insulating layer 142 , and an interlayer insulating layer 160 is formed on the second gate insulating layer 142 .

[0202] The connection portion 71 is formed on the interlayer insulating layer 160. The connection portion 71 electrically connects the second electrode D3 of the third transistor T3 and the gate electrode G1 of the driving transistor T1 through an opening that exposes the second electrode D3 of the third transistor T3 and the gate electrode G1 of the driving transistor T1, respectively. Since the output of the driving transistor T1 changes according to the voltage of the gate electrode G1, the voltage output to the second electrode D3 of the third transistor T3 affects the output of the driving transistor T1.

[0203] The gate electrode G3 of the third transistor T3 is arranged below the polycrystalline semiconductor layer so that it has a bottom gate structure, and the gate electrode G3 has a width corresponding to (e.g., substantially equal to) the width of the channel. Since the gate electrode G3 is arranged below the polycrystalline semiconductor layer, a mask can be used separately when doping the polycrystalline semiconductor layer.

[0204] exist Fig.14 In the exemplary embodiment, the third transistor T3 does not separately include a structure to shift the channel characteristics, and according to the exemplary embodiment, may receive the driving voltage ELVDD and may be formed with a second gate electrode disposed on the polycrystalline semiconductor layer.

[0205] and Fig.14 Unlike the exemplary embodiment of the present invention, only one of the second transistor T2 and the third transistor T3 includes a bottom gate structure. Also, in the exemplary embodiment, one transistor among the fourth to seventh transistors T4 to T7 may have a bottom gate structure.

[0206] In addition to this structure, at least one transistor among the second to seventh transistors T2 to T7 may further include a second gate electrode receiving the driving voltage ELVDD.

[0207] In the above exemplary embodiment, the driving transistor T1 has a bottom gate structure and further includes a second gate electrode G1-2 on the polycrystalline semiconductor layer. However, according to the exemplary embodiment, the second gate electrode G1-2 may be omitted. Referring now to Fig.15 This structure is described.

[0208] Fig.15 is a cross-sectional view of a plurality of transistors included in one pixel of an organic light emitting diode display according to an exemplary embodiment.

[0209] and Figure 1 The exemplary embodiments are different, in accordance with Fig.15 In the driving transistor T1 of the exemplary embodiment, the second gate electrode G1 - 2 is omitted.

[0210] Now according to Fig.15 A cross section of a driving transistor T1 according to an exemplary embodiment will be described.

[0211] The overlapping layer M1 is disposed on the upper barrier layer 111, and the overlapping layer M1 is covered by the buffer layer 112. The gate electrode G1 is formed on the buffer layer 112, and the gate electrode G1 is covered by the first gate insulating layer 141. The polycrystalline semiconductor layer is disposed on the first gate insulating layer 141. The polycrystalline semiconductor layer includes a first electrode S1, a second electrode D1, and a channel disposed therebetween.

[0212] The polycrystalline semiconductor layer is covered with the second gate insulating layer 142 , and the interlayer insulating layer 160 is disposed on the second gate insulating layer 142 .

[0213] The driving voltage applying part C-1 is formed on the interlayer insulating layer 160. The driving voltage applying part C-1 is connected to the overlapping layer M1 through the opening exposing the overlapping layer M1. Moreover, the driving voltage applying part C-1 is connected to the driving voltage line 172 so that the driving voltage ELVDD flows. As a result, the driving voltage ELVDD is also applied to the overlapping layer M1. The driving voltage applying part C-1 may be a portion extending from the driving voltage line 172 or a portion that is only electrically connected.

[0214] The gate electrode G1 is disposed under the channel of the driving transistor T1 , and has a width corresponding to (eg, substantially equal to) the width of the channel. Fig.15 A structure is shown in which the gate electrode G1 is extended rightward to be connected to the second electrode D3 of the third transistor T3, and its width corresponds to (eg, is substantially equal to) the width of the channel except for the extended portion.

[0215] exist Fig.15 In the driving transistor T1, the second gate electrode is not formed on the polycrystalline semiconductor layer so that a mask can be used separately when doping the polycrystalline semiconductor layer. According to an exemplary embodiment, the structure of the driving voltage applying part C-1 can be formed in a shape covering the channel of the driving transistor T1 so that an exemplary embodiment without using a mask can be implemented.

[0216] According to exemplary embodiments, the overlapping layer M1 may be omitted.

[0217] In each exemplary embodiment described herein, the wiring and the electrode arranged at the same layer may be formed of the same material. The layer arranged on the second gate insulating layer 142 may be formed of the same material and may be formed by using one mask. Moreover, each layer arranged on the upper barrier layer 111, arranged on the buffer layer 112, arranged on the first gate insulating layer 141, and arranged on the interlayer insulating layer 160 may be formed of the same material.

[0218] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope and spirit of the invention as defined in the following claims.

Claims

1. Organic light emitting diode display, comprising: substrate; Pixels, the pixels are arranged on the substrate; Scan line; Data cable; driving voltage line; as well as Initialize the voltage line, The scan line, the data line, the drive voltage line and the initialization voltage line are connected to the pixel. Wherein, the pixels include: Organic light emitting element; a first switch transistor, the first switch transistor being connected to the scan line; a driving transistor that applies current to the organic light emitting element; a compensation transistor that compensates for the operation of the drive transistor; and The second switching transistor, Wherein, the driving transistor comprises: a first gate electrode disposed on the substrate; and a semiconductor layer, the semiconductor layer being arranged on the first gate electrode, and includes a first electrode, a second electrode and a channel, Wherein, the compensation transistor comprises: a semiconductor layer, the semiconductor layer comprising a first electrode, a second electrode, and a channel; and a first gate electrode, the first gate electrode being arranged on the semiconductor layer of the compensation transistor, Wherein, the first switch transistor is connected to the scan line and the data line, wherein the second switch transistor is connected to the first gate electrode of the drive transistor, and Wherein, the second switch transistor comprises: A semiconductor layer, the semiconductor layer comprising a first electrode, a second electrode and a channel; a first gate electrode disposed on the semiconductor layer of the second switching transistor; and A second gate electrode is disposed below the semiconductor layer of the second switching transistor.

2. The organic light emitting diode display according to claim 1, wherein: The driving transistor further comprises: a second gate electrode, the second gate electrode being arranged on the semiconductor layer of the driving transistor, The second gate electrode of the driving transistor receives the driving voltage flowing to the driving voltage line.

3. The organic light emitting diode display according to claim 2, wherein: The driving transistor further comprises: an overlapping layer, the overlapping layer being arranged between the substrate and the first gate electrode of the driving transistor, Wherein, the driving voltage flowing to the driving voltage line is applied to the overlapping layer.

4. The organic light emitting diode display according to claim 1, wherein: The first switch transistor comprises: A semiconductor layer, the semiconductor layer comprising a first electrode, a second electrode and a channel; a first gate electrode disposed on the semiconductor layer of the first switching transistor; and a second gate electrode, the second gate electrode being arranged below the semiconductor layer of the first switching transistor, The driving voltage flowing to the driving voltage line is applied to the second gate electrode of the first switching transistor.

5. The organic light emitting diode display according to claim 1, wherein: The first switch transistor comprises: a gate electrode disposed on the substrate; and A semiconductor layer is disposed on the gate electrode of the first switching transistor and includes a first electrode, a second electrode, and a channel.

6. The organic light emitting diode display according to claim 1, wherein: The second gate electrode of the second switching transistor receives a driving voltage flowing to the driving voltage line.

7. The organic light emitting diode display according to claim 1, wherein: The first switch transistor comprises: A semiconductor layer, the semiconductor layer comprising a first electrode, a second electrode and a channel; a first gate electrode disposed on the semiconductor layer of the first switching transistor; and a second gate electrode, the second gate electrode being arranged below the semiconductor layer of the first switching transistor, The second gate electrode of the first switch transistor receives the driving voltage flowing to the driving voltage line.

8. The organic light emitting diode display according to claim 1, further comprising: a driving voltage applying unit, Wherein, the driving transistor further comprises: An overlapping layer is arranged between the substrate and the driving transistor Between the first gate electrodes, wherein the overlapping layer receives the driving voltage, the overlapping layer is electrically connected to the second gate electrode of the second switching transistor, so that the driving voltage is applied to the second gate electrode of the second switching transistor, and Wherein, the driving transistor further comprises: a second gate electrode disposed on the semiconductor layer of the driving transistor, and The driving voltage applying section applies the driving voltage to the overlapping layer and the second gate electrode of the driving transistor.

9. The organic light emitting diode display according to claim 1, wherein: The compensation transistor further includes a second gate electrode disposed below the semiconductor layer of the compensation transistor.

10. Organic light emitting diode displays, comprising: substrate; Pixels, the pixels are arranged on the substrate; Scan line; Data cable; driving voltage line; as well as Initialize the voltage line, The scan line, the data line, the drive voltage line and the initialization voltage line are connected to the pixel. Wherein, the pixels include: Organic light emitting element; a first switch transistor, the first switch transistor being connected to the scan line; a driving transistor that applies current to the organic light emitting element; a compensation transistor that compensates for the operation of the drive transistor; and The second switching transistor, Wherein, the driving transistor comprises: a first gate electrode disposed on the substrate; and a semiconductor layer, the semiconductor layer being arranged on the first gate electrode, and includes a first electrode, a second electrode and a channel, Wherein, the compensation transistor comprises: a semiconductor layer, the semiconductor layer comprising a first electrode, a second electrode, and a channel; and a first gate electrode, the first gate electrode being arranged on the semiconductor layer of the compensation transistor, Wherein, the first switch transistor is connected to the scan line and the data line, wherein the second switch transistor is connected to the first gate electrode of the drive transistor, and Wherein, the second switch transistor comprises: a gate electrode disposed on the substrate; and A semiconductor layer is disposed on the gate electrode of the second switching transistor and includes a first electrode, a second electrode, and a channel.

Images