Semiconductor Structure and Method for Forming the Same

Abstract

A method includes forming a metal gate structure, the metal gate structure including a gate dielectric layer and a gate electrode. A surface treatment is performed on a top surface of the metal gate structure, the surface treatment transforming a top portion of the gate electrode into an oxide layer. A conductive layer is formed over the gate electrode, the formation of the conductive layer including substituting a metal element for oxygen in the oxide layer. A plug component is formed over the metal gate structure, the plug component being in direct contact with the conductive layer.

Description

Technical Field

[0001] An embodiment of the present invention relates to a method for forming a semiconductor structure, and particularly to a method for forming a metal plug on a metal gate. Background Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. The progress of integrated circuit materials and design technologies has led to the emergence of generations of integrated circuits, with each generation of circuits being smaller and more complex than the previous one. During the development of integrated circuits, the functional density (i.e., the number of devices interconnected per chip area) is usually increased, while the geometric dimensions (i.e., the smallest elements or lines that can be fabricated in the process) are reduced. The benefits brought about by the size reduction generally include improved production efficiency and reduced related costs.

[0003] Such a size reduction also increases the complexity of processing and manufacturing integrated circuits, and for these advancements to be achieved, similar developments in integrated circuit processing and manufacturing are required. For example, polysilicon gates have been replaced by metal gates to facilitate the improvement of device performance by reducing the feature size. However, during the manufacturing of devices, there are challenges in the process of forming contact features on the metal gates. In one example, the interface between the contact feature and the metal gate may encounter high resistance that is difficult to control due to the reduction of the feature size. A possible improvement is to form a low-resistance conductive layer between the contact feature and the metal gate to reduce the resistance between the contact feature and the metal gate. At the same time, it is necessary to maintain the electrical stability of the metal gate without being disturbed by the overlying low-resistance conductive layer. Therefore, there is a need to further improve this field. Summary of the Invention

[0004] An embodiment of the present invention provides a method. The method includes forming a metal gate structure, the metal gate structure including a gate dielectric layer and a gate electrode. Performing a surface treatment on the top surface of the metal gate structure, the surface treatment transforming the top of the gate electrode into an oxide layer. Forming a conductive layer above the gate electrode, the formation of the conductive layer including replacing oxygen in the oxide layer with a metal element. Forming a plug component above the metal gate structure, the plug component being in direct contact with the conductive layer.

[0005] Another embodiment of the present invention provides a method for forming a semiconductor structure. The method includes forming a metal gate structure, the metal gate structure includes a gate dielectric layer and a gate electrode, the gate electrode includes a first metal layer and a second metal layer, the first metal layer includes a first metal element, and the second metal layer includes a second metal element, and the top surface of the first metal layer is coplanar with the top surface of the second metal layer. The top surface of the first metal layer and the top surface of the second metal layer are passivated, and the passivation treatment forms a compound on the gate electrode, and the compound includes the first metal element and the second metal element. A third metal element is deposited above the metal gate structure to form a conductive layer, and the deposition of the third metal element converts the compound into an alloy including the first metal element, the second metal element and the third metal element. A plug component is formed above the metal gate structure, and the plug component is in direct contact with the conductive layer.

[0006] Another embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes a metal gate structure, the metal gate structure includes a gate dielectric layer and a gate electrode, the gate electrode includes at least one metal. A conductive layer is formed above the gate electrode, the conductive layer includes an alloy layer, the alloy layer includes the at least one metal and a second metal, and the alloy layer extends above the top surface of the metal gate structure. A plug component is disposed above the metal gate structure, and the plug component is in direct contact with the top surface of the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A , Figure 4A , Figure 5A , Figure 5B , Figure 6A , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F , Figure 7G , Figure 7H , Figure 8A , Figure 9A and Figure 10A A partial cross-sectional schematic diagram of a device according to an embodiment of various aspects of the present invention is shown.

[0008] Figure 1B , Figure 4B , Figure 6B , Figure 8B , Figure 9B and Figure 10B Shown respectively as Figure 1A , Figure 4A , Figure 6A , Figure 8A , Figure 9A and Figure 10A A top plan view of a device according to an embodiment of the present invention is shown.

[0009] Figure 2 is a three-dimensional perspective view showing a device according to an embodiment in various aspects of the present invention.

[0010] Figure 3A and Figure 3B is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment in various aspects of the present invention.

[0011] Figure 11 shows a comparison of the oxidation rates of different materials under the same oxidation surface treatment.

[0012] List of Reference Numerals

[0013] 100, 200 Semiconductor Structures

[0014] 102, 202 Semiconductor Substrates

[0015] 106, 208 Source / Drain Components

[0016] 108 Channel Region

[0017] 110, 210 First Interlayer Dielectric (ILD) Layers

[0018] 120, 220 High-K Metal Gate (HK MG) Structures

[0019] 122, 222 Gate Dielectric Layers

[0020] 124, 224 Gate Electrodes

[0021] 126, 226 Conductive Layers

[0022] 128, 228 Gate Spacers

[0023] 130, 230 Second ILD Layers

[0024] 132, 232 Plug Components

[0025] 136 Top Surface

[0026] 138 Bottom Surface

[0027] 140 Capping Layer

[0028] 150, 152, 154 Metal Layers

[0029] 204 Fin Structure

[0030] 206 Isolation Structure

[0031] 300 Method

[0032] Steps 302, 304, 306, 308, 310, 312, 314, 316, 318, 320, 322

[0033] 502 Plasma

[0034] 504 Passivation layer

[0035] 600 Region

[0036] 602 ALD process

[0037] 700 Alloy

[0038] 702 First metal

[0039] 704 Second metal

[0040] 706 Third metal

[0041] 708 Fourth metal

[0042] 710 Metal film

[0043] 712 Residue

[0044] 720, 810 Opening

[0045] 750 Side region

[0046] 752 Intermediate region

[0047] 754 Central region

[0048] Hg Gate height

[0049] Lg Gate length Detailed implementation manners

[0050] Many different embodiments or examples are provided below for implementing different features of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are only examples and not restrictive. For example, forming the first component on or above the second component in the subsequent description may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where additional components are formed between the first and second components such that the first and second components may not be in direct contact.

[0051] In addition, embodiments of the present invention may repeat reference numerals and / or letters in various examples. These repeated symbols or words are for the purposes of simplicity and clarity and are not intended to limit the relationship between various embodiments and / or the configurations described. Furthermore, when the following description of the present invention states that one component is formed on, connected to, and / or coupled to another component, it may include embodiments in which the above-mentioned components formed are in direct contact, and may also include embodiments in which additional components are formed between the above-mentioned components such that the above-mentioned components may not be in direct contact. In addition, for the convenience of describing the relationship between one component and another component in the present invention, spatially relative terms may be used, such as "lower", "upper", "horizontal", "longitudinal", "above", "on...", "below", "under...", "up", "down", "top", "bottom", etc. and derivative terms thereof (e.g., "horizontally", "longitudinally", "downwardly", etc.). Spatially relative terms are used to cover different orientations of devices including multiple components. Furthermore, unless otherwise specified, when a number or a range of numbers is described using terms such as "about", "approximate", or similar terms, such terms are intended to include numbers within a range of + / - 10% of the said number. For example, the term "about 5 nm" includes a size range from 4.5 nm to 5.5 nm.

[0052] Embodiments of the present invention generally relate to a method for manufacturing a semiconductor device, and particularly to a method for forming a plug component on a metal gate structure. When forming a metal gate structure in a device, a plug component is formed on the top surface of the metal gate structure for further manufacturing of the device. However, as the feature size continues to shrink, many challenges arise at this stage of the manufacturing process. In one example, multiple work function metal (WFM) layers included in the metal gate electrode may generate a high-resistance interface with the plug component, thereby limiting the overall performance of the device. Furthermore, the reduced feature size makes it difficult to control the electrical properties of the interface between the conductive component and the top surface of the metal gate electrode. Therefore, the present invention provides a structure for reducing the contact resistance of the interface between the metal gate structure and the plug component while maintaining the stability of the electrical properties (e.g., critical voltage, gate resistance-capacitance delay, etc.) of the metal gate electrode. In some embodiments of the present invention, a conductive layer is formed between the metal gate structure and the plug component to reduce the high resistance of the interface between the metal gate structure and the plug component caused by the presence of one or more work function metal layers in the metal gate structure. In various embodiments, the reduction in resistance can exceed 50%. The semiconductor device disclosed herein may be, for example, a complementary metal oxide semiconductor (CMOS) device including P-type metal oxide semiconductor (PMOS) devices and N-type metal oxide semiconductor (NMOS) devices. In terms of structure, the above-mentioned device may be a two-dimensional planar MOS field effect transistor (MOSFET) device (Figure 1A and Figure 1B ) or a three-dimensional non-planar fin field-effect transistor (FinFET) device ( Figure 2 ). However, it should be understood that the present invention should not be limited to a specific type of device.

[0053] Figure 1A is a schematic cross-sectional view of a semiconductor structure (i.e., a device or a semiconductor device) 100 along the cut line AA' in a plan view of the plane of the semiconductor structure 100 as shown in Figure 1B . In some embodiments, Figure 1A and Figure 1B are a part of a two-dimensional planar device, such as a PMOS device, an NMOS device, or a CMOS device, while Figure 2 is a three-dimensional PMOS or NMOS FinFET device. Figure 3A and Figure 3B are flowcharts showing a method 300 of forming a semiconductor structure 100 and a semiconductor structure (i.e., a FinFET device or a semiconductor device) 200 according to various embodiments of the present invention. The method 300 is only illustrative as an example and is not intended to limit the present invention beyond what is explicitly recited in the claims. Additional steps may be provided before, during, and after the process methods described herein, and in other embodiments of the present invention, certain of the steps may be replaced, omitted, or varied.

[0054] Please refer to Figure 3A, in step 302 of method 300, a semiconductor substrate 102 is provided. The semiconductor substrate (or substrate) 102 comprises an elemental semiconductor (such as silicon) having a crystalline structure. Optionally or alternatively, the substrate 102 comprises another elemental semiconductor (such as germanium), a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), an alloy semiconductor (including silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and gallium indium arsenide phosphide), or a combination of the foregoing. Alternatively, the substrate 102 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be fabricated by a separation by implantation of oxygen (SIMOX) process, wafer bonding and / or other suitable methods. The substrate 102 may also comprise other components, such as a buried layer and / or an epitaxial semiconductor layer grown thereon. In some embodiments, depending on the nature of the desired device, the substrate 102 may comprise doped regions, such as n-type well regions and p-type well regions. Doping of the substrate 102 can be carried out by an ion implantation process, a diffusion process, an in-situ doping process, or a combination of the foregoing.

[0055] In step 304 of method 300, an isolation component (not shown) is formed on the substrate 102 to define the active regions of the semiconductor structure 100. The isolation component may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, other suitable dielectric materials, or a combination of the foregoing. The isolation component may comprise, for example, a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure and / or a local oxidation of silicon (LOCOS) structure.

[0056] In step 306 of method 300, a dummy gate structure (not shown) is formed on substrate 102, and the dummy gate structure is a part that will be replaced in subsequent steps. The dummy gate structure may include a dummy interface layer and a dummy gate electrode. The dummy interface layer includes silicon oxide or silicon oxynitride, and the dummy gate electrode includes polysilicon. The dummy gate structure can be formed through a series of deposition and patterning processes. After that, please refer to Figure 1A and Figure 4A , in step 306, gate spacers 128 are formed along the sidewalls of the dummy gate structure. The gate spacers 128 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other dielectric materials, or a combination of the foregoing, and can be formed by a deposition process followed by an anisotropic etching process.

[0057] Please continue to refer to Figure 1A and Figure 4A , method 300 then proceeds to step 308 to form source / drain components 106 adjacent to the dummy gate structure, and then a channel region 108 is formed between the dummy gate structure and the source / drain components 106. The source / drain components 106 can be n-type components for forming NMOS devices or p-type components for forming PMOS devices. In some embodiments, depending on the nature of the desired device, the source / drain regions adjacent to the dummy gate structure in substrate 102 can be doped with one or more n-type dopants or p-type dopants by a method such as ion implantation to form the source / drain components 106. In other embodiments, in step 308, the source / drain components 106 are formed by epitaxially growing a doped semiconductor material layer inside and outside the source / drain regions, thereby forming raised source / drain components 106. In other embodiments, in step 308, the source / drain regions are first locally recessed by etching to form trenches, and then a semiconductor layer is epitaxially grown in the trenches to form the source / drain components 106. The above epitaxially grown semiconductor material can be the same as or different from the semiconductor material of substrate 102. For example, for p-type FETs, the above epitaxially grown semiconductor material is silicon germanium, and for n-type FETs, the above epitaxially grown semiconductor material is silicon or silicon carbide. In some embodiments, dopants are introduced into the source / drain components 106 by in-situ doping. Specifically, the precursor for epitaxial growth further contains a chemical substance containing dopants.

[0058] After that, in step 310 of method 300, between the source / drain components 106 and the isolation components ( Figure 1A and Figure 4A)A first interlayer dielectric (ILD) layer 110 is formed thereon. The first ILD layer 110 may include any suitable dielectric material, such as tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped siliconglass (BSG)), low-k dielectric material, and / or other suitable dielectric materials. The first ILD layer 110 may include a multilayer structure or a single-layer structure with multiple dielectric materials. For example, the first ILD layer 110 may include a thin etch stop layer (e.g., silicon nitride) and a low-k dielectric material layer. In step 310, the first ILD layer 110 is formed by a deposition process, such as a spin coating process, a chemical vapor deposition (CVD) process, other suitable methods, or a combination of the foregoing. Step 310 also includes a planarization process, such as a chemical-mechanical polishing / planarization (CMP) process, after depositing the first ILD layer 110 to remove excess ILD material from the top surface of the semiconductor structure 100.

[0059] In step 312 of method 300, a high-k (HK) metal gate (MG) (HK MG) structure 120 ( Figure 1A , Figure 4A and Figure 4B ) replaces the dummy gate structure. In step 312, the local dummy gate structure is removed to form a gate trench (not shown), and then the HK MG structure 120 is formed in the gate trench by a deposition process. The gate material layer thus formed is U-shaped. Thereafter, a planarization process, such as CMP, is performed to remove excess metal gate material from the surface of the semiconductor structure 100. In some embodiments, the HK MG structure 120 has a gate height Hg in the range of about 10 nm to about 35 nm and a gate length Lg in the range of about 13 nm to about 28 nm.

[0060] Please refer to Figure 1A , Figure 4A and Figure 4B, the HK MG structure 120 includes a gate dielectric (or gate dielectric) layer 122 of high dielectric constant (HK), a capping layer 140 covering the gate dielectric layer 122, and a gate electrode 124, and the multi-layer metal layers 150, 152, and 154 together form the gate electrode 124. In some embodiments, the gate electrode 124 may include additional metal layers. In other embodiments, the HK MG structure 120 may include additional material layers (not shown), such as an interface layer, a capping layer, a diffusion layer, a barrier layer, or a combination of the foregoing. For example, the HK MG structure 120 may include an interface layer disposed between the channel region 108 and the gate dielectric layer 122. The material layers of the HK MG structure 120 may be formed by one or more suitable methods, such as CVD, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, electroplating process, other suitable methods, or a combination of the foregoing. In some embodiments, one or more deposition methods are performed to separately form the U-shaped gate dielectric layer 122, the capping layer 140, the metal layers 150, 152, and 154 constituting the gate electrode 124, and any other material layers disposed between the above-mentioned film layers, such that the above-mentioned material layers have a top surface coplanar with the top surface 136 of the HK MG structure 120.

[0061] The gate dielectric layer 122 of high dielectric constant may include a dielectric material containing one or more high dielectric constants (or one or more layers of high dielectric constant dielectric materials), such as hafnium silicon oxide (HfSiO), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), or a combination of the foregoing. CVD, ALD, and / or other suitable methods may be used to deposit the gate dielectric layer 122.

[0062] In various embodiments, the capping layer 140 includes one or more of the following materials: HfSiON, HfTaO, HfTiO, HfAlON, HfZrO, or other suitable materials. In a particular embodiment, the capping layer 140 includes titanium silicon nitride (TiSiN). Thus, step 312 may further include, after forming the gate dielectric layer 122, co-sputtering the capping layer 140 on the gate dielectric layer 122 by a method such as rapid thermal anneal (RTA) in nitrogen. In many embodiments, the capping layer 140 provides improved thermal stability for the HK MG 120 and is used to prevent metal impurities from diffusing from the gate electrode 124 into the gate dielectric layer 122.

[0063] The gate electrode 124 may include one or more metal layers, such as a (multi-layer) work function metal (WFM) layer, a (multi-layer) conductive isolation layer, and a (multi-layer) bulk conductive layer. In one example, the gate electrode 124 includes two different work function metal layers 150 and 152, and a metal layer (bulk conductive layer) 154 as a metal filler in the center. The metal layer (bulk conductive layer) 154 may include tungsten. In another example, the gate electrode 124 includes three different work function metal layers 150, 152, and 154. In some other examples, the gate electrode 124 may include additional work function metal layers and bulk conductive layers.

[0064] Depending on the type of device required (PMOS or NMOS), the work function metal layer can be a p-type or n-type work function layer. The p-type WFM layer includes metals with a sufficiently large effective work function and may include one or more of the following materials: titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), other suitable metals, or combinations thereof. For example, the metal layer 150, the metal layer 152, and the metal layer 154 can be three different p-type work function metal layers. In a specific example, the metal layer 150, the metal layer 152, and the metal layer 154 respectively include a tantalum nitride (TaN) layer, a titanium nitride (TiN) layer, and a titanium aluminum (TiAl) layer. The TaN layer, the TiN layer, and the TiAl layer can be arranged in any order within the work function metal layer. For example, the TaN layer is in the center, the TiN layer is in the middle layer position, and the TiAl layer is on the side of the gate electrode 124. In some other embodiments, the metal layer 150, the metal layer 152, and the metal layer 154 can be three different n-type work function metal layers. The n-type work function metal layer includes metals with a sufficiently low effective work function and may include one or more of the following materials: tantalum (Ta), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), other suitable metals, or combinations thereof. Alternatively, the metal layer 150 and the metal layer 152 can be two different work function metal layers, and the metal layer 154 can be a bulk conductive layer. The bulk conductive layer may include aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), platinum (Pt), molybdenum (Mo), cobalt (Co), silver (Ag), manganese (Mn), zirconium (Zr), ruthenium (Ru), and / or other suitable materials. The gate electrode 124 may include multiple work function metal layers, or optionally may include multiple work function metal layers and bulk conductive metal layers. The gate electrode 124 can be formed by one or more deposition methods, such as CVD, PVD, ALD, electroplating, and / or other suitable methods.

[0065] Please refer toFigure 3A , Figure 5A and Figure 5B , Method 300 proceeds to step 314 to perform a surface treatment on the top surface 136 of the HK MG structure 120 to transform the top of the gate electrode 124 into a passivation layer 504. In one embodiment, the surface treatment includes an oxidation process, and the passivation layer 504 includes a metal oxide. In another embodiment, the surface treatment includes a nitridation process, and the passivation layer 504 includes a metal nitride and / or a metal oxynitride. The surface treatment can include any suitable technique, such as a thermal growth process and a plasma treatment. In some embodiments, as Figure 5A shown, the top surface 136 of the HK MG structure 120 is treated with a plasma 502, and the plasma 502 includes a gas selected from oxygen (O2), a mixture of oxygen (O2) and nitrogen (N2), and ammonia (NH3). The gas flow used in the plasma treatment can be in the range of about 100 sccm to about 10,000 sccm. The plasma can be applied with a bias voltage of about 50 W to about 5,000 W at an operating temperature between about 150 degrees Celsius and 350 degrees Celsius and at a process pressure between about 50 mTorr and about 4,000 mTorr. In one embodiment, the time of the surface treatment is about 10 seconds to about 50 seconds.

[0066] In the illustrated embodiment, step 314 is an oxidation surface treatment by applying an O2 plasma to the top surface 136 of the HK MG structure 120. The O2 plasma treatment is performed at a gas flow between about 8,000 sccm and about 10,000 sccm, with a bias voltage applied between about 3,000 W and about 5,000 W, at a temperature of about 200 degrees Celsius and a process pressure of about 1,100 mTorr. The oxidation surface treatment process can be performed for about 30 seconds. Before performing the oxidation surface treatment, the top surfaces of the work function metal layer 150, the work function metal layer 152, and the work function metal layer 154 may each include a native oxide of the respective work function metal layer. Such native oxides can be discontinuous and non-uniform. The oxidation surface treatment is used to oxidize the top surfaces of the work function metal layer 150, the work function metal layer 152, and the work function metal layer 154 and form a uniform passivation layer 504 (i.e., an oxide layer), as Figure 5BAs shown. The passivation layer 504 (i.e., the oxide layer) has a regular boundary, such as a smooth bottom surface 138 where the passivation layer 504 (i.e., the oxide layer) is connected to the underlying gate electrode 124. As shown in subsequent steps, the passivation layer 504 (i.e., the oxide layer) will be transformed into a low-resistance conductive layer. The low-resistance conductive layer will be confined within the smooth bottom surface 138 and will not further protrude into the work function metal layer of the gate electrode 124, which helps to maintain the stability of the electrical properties (e.g., threshold voltage, gate resistance-capacitance delay, etc.) of the gate electrode 124. The passivation layer 504 (i.e., the oxide layer) may have a top portion located approximately 1 nm to approximately 3 nm above the top surface 136 of the gate electrode 124 and a bottom portion located approximately 2 nm to approximately 8 nm below the top surface 136 of the gate electrode 124. The height of the top portion and the height of the bottom portion may have a ratio of approximately 1:8 to approximately 1.5:1. In one embodiment, the metal layer 154 exhibits a faster oxidation rate than the metal layers 152 and 150, and the top portion of the passivation layer 504 (i.e., the oxide layer) has a convex shape with a central region higher than the peripheral region. In another embodiment, the metal layer 154 exhibits a slower oxidation rate than the metal layers 152 and 150, and the top portion of the passivation layer 504 (i.e., the oxide layer) has a concave shape with a central region lower than the peripheral region.

[0067] In some other embodiments, step 314 is a nitriding surface treatment, and the plasma contains a mixture of O2 and N2. Accordingly, the passivation layer 504 is a nitride layer and contains a mixture of oxides and nitrides. In yet another embodiment, step 314 is a hydrogenation surface treatment, and the plasma contains NH3. Thus, the passivation layer 504 is a hydrogenated layer and contains hydrogen. Advantageously, the surface treatment performed during step 314 can be carried out in the same process equipment as that for forming the conductive layer 126 and the plug component 132 in subsequent steps.

[0068] Please refer to Figure 3B , in step 316 of method 300, a conductive layer 126 is grown on the top surface of the HK MG structure 120. Step 316 may include a deposition process, such as an ALD process, a CVD process, other suitable methods, or a combination of the foregoing. As Figure 6AAs shown, in some embodiments, an ALD process 602 is performed using a gaseous precursor in step 316, the gaseous precursor including a conductive element such as W, Co, Ti, Al, Cu, Au, or a combination of the foregoing. The inventors have observed that by selecting certain precursor compositions and adjusting appropriate process conditions, a substitution reaction occurs between the deposited conductive element and non-conductive elements (e.g., oxygen and nitrogen) within the passivation layer 504. Without being bound by theory, the inventors have observed that this substitution reaction generally transforms the compound of the passivation layer 504 into an alloy including the conductive element introduced from the gaseous precursor and those original metal elements from within the work function metal layer. During the deposition process, additional conductive elements can be further deposited over the alloy as a metal film. The alloy that is the main part of the conductive layer 126 extends from a position below the top surface 136 of the HK MG structure 120 to a position above the top surface 136. In this way, the low-resistance conductive layer 126 replaces the high-resistance passivation layer 504 with a regular boundary (e.g., a smooth bottom surface 138 connected to the gate electrode 124 below it). As shown in subsequent steps, a plug component will be formed directly over the conductive layer 126. In the case of direct contact, due to the presence of the interfaces of multiple high-resistance work function metal layers, the contact resistance at the interface between the plug component and the conductive layer 126 is generally lower than the contact resistance between the plug component and the top surface of the gate electrode 124. In various embodiments, this reduction in resistance can exceed 50%.

[0069] Please refer to Figure 6A and Figure 6B, in some embodiments, the deposition process performed in step 316 is a selective deposition process such that the conductive layer 126 is selectively formed on and self-aligned with the metal layers 150, 152, and 154 of the gate electrode 124 and is not formed over the gate dielectric layer 122 or the capping layer 140. In the illustrated embodiment, step 316 first performs an ALD process 602 that sequentially exposes the top surface of the HKMG structure 120 to two different gaseous precursors in a cyclic manner, i.e., alternately applying a first gaseous precursor and a second gaseous precursor to the top surface of the HKMG structure 120. The first gaseous precursor may include a compound containing a conductive element (e.g., W, Co, Ti, Al, Cu, Au, or a combination of the foregoing) and a halogen (e.g., chlorine (Cl) or fluorine (F)). In one embodiment, the first gaseous precursor may be tungsten chloride (WCl5), tungsten fluoride (WF6), titanium chloride (TiCl4), or other suitable materials. The second gaseous precursor includes elements such as silicon (Si) and hydrogen (H). Examples of the second gaseous precursor include hydrogen (H2) and silane (SiH4). In a particular embodiment, the first gaseous precursor contains WCl5 and the second gaseous precursor contains H2. In another particular embodiment, the first gaseous precursor contains WF6 and the second gaseous precursor contains SiH4. Step 316 performs the deposition process at a temperature between about 400 degrees Celsius and about 520 degrees Celsius and a process pressure between about 5 Torr and about 50 Torr. In some embodiments, the deposition process may be performed for about 10 minutes to about 120 minutes.

[0070] An enlarged region 600 surrounding the conductive layer 126 is shown in Figures 7A to 7F . The work function metal layers 150, 152, and 154 may include different metal elements, denoted as a first metal 702, a second metal 704, and a third metal 706, respectively. For example, the first metal 702, the second metal 704, and the third metal 706 may be tantalum (Ta), titanium (Ti), and aluminum (Al), respectively. Refer to Figure 7A, the conductive layer 126 includes an alloy 700, which is a compound of a first metal 702, a second metal 704, a third metal 706, and a fourth metal 708 that is substituted into the compound during step 316. The alloy 700 is self-aligned with the work function metal layer 150, the work function metal layer 152, and the work function metal layer 154, and does not form over the gate dielectric layer 122 or the capping layer 140. Based on the spatial relationship with the work function metal layer located directly below, the alloy 700 can be divided into several regions, such as a side region 750 directly above the work function metal layer 150, an intermediate region 752 directly above the work function metal layer 152, and a central region 754 directly above the work function metal layer 154. The side region 750 is rich in the first metal 702 (i.e., there is more of the first metal 702 than the second metal 704 or the third metal 706), the intermediate region 752 is rich in the second metal 704, and the central region 754 is rich in the third metal 706, where all regions have the fourth metal 708. In some embodiments, there is no distinct boundary between two adjacent side regions 750, intermediate regions 752, or central regions 754 because the respective metals of each region may diffuse into the adjacent regions around the boundary. In some other embodiments, the first metal 702, the second metal 704, the third metal 706, and the fourth metal 708 further diffuse into each region. For example, due to the optional heating or annealing treatment in step 316, each region has a substantially the same metal alloy composition without any particular metal being in excess. The conductive layer 126 may have a top that is approximately 1 nm to approximately 3 nm above the top surface 136 of the gate electrode 124, and a bottom that is approximately 2 nm to approximately 8 nm below the top surface 136 of the gate electrode 124. The height of the top and the height of the bottom may have a ratio of approximately 1:8 to approximately 1.5:1.

[0071] Please refer to Figure 7BAs shown, in some embodiments, the conductive layer 126 further includes a metal film 710 covering the alloy 700. The metal film 710 includes a fourth metal 708. In some embodiments, the metal film 710 does not contain the first metal 702, the second metal 704, and the third metal 706. For example, the metal film 710 can be a tungsten (W) layer. In various other embodiments, the metal film 710 contains a metal selected from tungsten (W), cobalt (Co), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), other suitable metals, or combinations of the foregoing. The metal film 710 is formed by increasing the deposition time of the first gaseous precursor and the second gaseous precursor (e.g., WCl5 / H2 precursor or WF6 / SiH4 precursor) in a cyclic manner during step 316 after the alloy 700 is formed. The deposition of the metal film 710 on the surface of the alloy 700 can include a chemical reaction called "electron exchange", which helps to form a more uniform and low-resistance metal film 710. In some embodiments, the metal film 710 can have a thickness of about 1 nm to about 20 nm.

[0072] Please refer to Figure 7C , in some embodiments, the conductive layer 126 may further include residues 712 from the passivation layer 504. For clarity of illustration, the illustrations of the first metal 702, the second metal 704, the third metal 706, and the fourth metal 708 are omitted here. Depending on the material composition of the passivation layer 504, the residues 712 can be metal oxides, metal nitrides, or metal oxynitrides, and the residues 712 are not completely replaced by the fourth metal 708 during step 316. Near the bottom of the conductive layer 126, the chance of the residues 712 being replaced is higher. Therefore, the bottom of the conductive layer 126 can be considered as a result of the molecular intermixing between the alloy 700 and the non-metallic residues 712 (e.g., metal oxides), and the concentration of the residues 712 increases along the direction towards the underlying gate electrode 124. In yet another embodiment, the residues 712 accumulate at the interface between the conductive layer 126 and the gate electrode 124, while the main body of the conductive layer 126 is substantially free of the residues 712, as Figure 7D schematically shown in. The residues 712 may not be formed continuously along the interface between the conductive layer 126 and the gate electrode 124, and sufficient openings 720 are left such that the conductive layer 126 can be in sufficient direct contact with the gate electrode 124.

[0073] Please refer to Figure 7E, in some embodiments, a portion of the conductive layer 126 may extend laterally to contact the top surface of the capping layer 140. The capping layer 140 may include material components that may undergo a passivation reaction in step 314. For example, the capping layer 140 may comprise titanium silicon nitride (TiSiN), and the capping layer 140 containing titanium silicon nitride may be oxidized during the oxidation surface treatment in step 314. Even though the oxidation rate of the capping layer 140 may be much slower than that of the work function metal layer of the gate electrode 124, the extended oxidation time will cause the passivation layer 504 to extend laterally to the top of the capping layer 140. Thereafter, as described above, in step 316, the passivation layer 504 is converted into a part of the conductive layer 126, and the top of the capping layer 140 including it will also be converted into a part of the conductive layer 126.

[0074] Please refer to Figure 7F , in some embodiments, the top surface of the conductive layer 126 may have a concave shape, where the points in the central region are lower than some points in the peripheral region. When the work function metal layer 154 exhibits a faster oxidation rate than the metal layers 152 and 150, the top of the passivation layer 504 (i.e., the oxide layer) will have a convex shape, where the central region is higher than the peripheral region. Thereafter, the alloy 700 and the metal film 710 will also exhibit a convex shape. However, when the metal layer 154 exhibits a slower oxidation rate than the metal layers 152 and 150, the top of the passivation layer 504 (i.e., the oxide layer) has a concave shape, where the central region is lower than the peripheral region. Thereafter, the alloy 700 and the metal film 710 will also exhibit a concave shape. Similarly, the bottom surface of the conductive layer 126 may also exhibit a concave shape, where the points in the central region are higher than some points in the peripheral region.

[0075] In a specific embodiment, the capping layer 140 comprises titanium silicon nitride (TiSiN), while the work function metal layer 150, the work function metal layer 152, and the work function metal layer 154 comprise a tantalum nitride (TaN) layer, a titanium nitride (TiN) layer, and a titanium aluminum (TiAl) layer, respectively. Figure 11 Shows a comparison of the oxidation rates among four materials under a specific oxidation surface treatment. TiAl exhibits the highest oxidation rate compared to other materials. Accordingly, the alloy 700 will have the highest point above the work function metal layer 154. It is worth noting that under this specific oxidation surface treatment, the material TiSiN of the capping layer 140 exhibits a higher oxidation rate than the material TaN of the work function metal layer. Therefore, the alloy 700 also extends above the capping layer 140, as Figure 7G shown. At the same time, the alloy 700 above the capping layer 140 may be higher than the part above the work function metal layer 150.

[0076] In yet another specific embodiment, the capping layer 140 includes titanium silicon nitride (TiSiN), while the work function metal layer 150, the work function metal layer 152, and the work function metal layer 154 respectively include a tantalum nitride (TaN) layer, a titanium aluminum (TiAl) layer, and a titanium nitride (TiN) layer. Please refer again to the Figure 11 oxidation rate comparison table shown. TiAl exhibits the highest oxidation rate compared to other materials. Accordingly, the alloy 700 will have a highest point located above the work function metal layer 152 and form a recessed shape above the center of the metal gate electrode, as shown in Figure 7H . Meanwhile, the oxidation rate of the material TiSiN of the capping layer 140 allows the alloy 700 to continuously extend above the capping layer 140. As shown in Figure 7H , since the oxidation rate of TiSiN is higher than that of TaN in a specific oxidation surface treatment, the alloy 700 above the capping layer 140 can be higher than the portion above the work function metal layer 150.

[0077] Please refer to Figure 8A and Figure 8B . In step 318 of method 300, a second ILD layer 130 is formed on the conductive layer 126, a portion of the HK MG structure 120, and the first ILD layer 110. The second ILD layer 130 may include the same or different materials as the first ILD layer 110 and may be, for example, TEOS, undoped silicate glass, BPSG, FSG, PSG, BSG, a low dielectric constant dielectric material, and / or other suitable dielectric materials. In step 318, the second ILD layer 110 is formed by a deposition process, such as a spin coating process, CVD, other suitable methods, or a combination of the foregoing. Step 318 may also include performing a CMP process to remove excess ILD material from the top surface of the semiconductor structure 100.

[0078] Method 300 proceeds to step 320 to form the plug member 132. Step 320 may include multiple steps, such as patterning, deposition, and CMP. First, in step 320, a patterning process (including a lithography process and etching) is performed to form (i.e., pattern) an opening 810 in the second ILD layer 130. The opening 810 corresponds to the planar shape of the plug member 132 when viewed from a top view ( Figure 8B ). In the illustrated embodiment, the plug member 132 is formed to have a rectangular shape with rounded corners. In many other embodiments, the plug member 132 is configured to be circular (e.g., Figure 2The plug component 232 (FinFET device) 200 in the semiconductor structure is square, rectangular, or of other planar shapes. In the illustrated embodiment, the opening 810 is directly formed above the top surface of the gate electrode 124 (i.e., the metal layers 150, 152, and 154). The patterning process may include forming a patterned resist layer (not shown) on a hard mask layer (not shown) through photoresist coating, exposure, post-exposure baking, and development processes. The hard mask layer may include a material different from that of the second ILD layer 130, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or other suitable materials, and may be formed by a suitable method (e.g., thermal oxidation, CVD, PVD, ALD, other suitable methods, or a combination of the foregoing). Thereafter, the hard mask layer is etched using the patterned photoresist as an etching mask to form the opening 810 in the second ILD layer 130. The etching process may include wet etching, dry etching, reactive ion etching, or other suitable etching methods.

[0079] Next, please refer to Figure 9A and Figure 9B , and a plug component 132 is formed in the opening 810 of the second ILD layer 130 through a deposition process. In some embodiments, the plug component 132 includes tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), platinum (Pt), molybdenum (Mo), silver (Ag), manganese (Mn), zirconium (Zr), ruthenium (Ru), other suitable conductive materials, or a combination of the foregoing. The plug component 132 may include the same or different material as the metal film 710 of the conductive layer 126. For example, if the metal film 710 of the conductive layer 126 includes metal tungsten, the plug component 132 may include metal tungsten, metal cobalt, and / or metal aluminum. In some embodiments, in step 320, the plug component 132 is formed through a deposition process (e.g., CVD, PVD, ALD, electroplating, other suitable methods, or a combination of the foregoing). In an exemplary embodiment, the plug component 132 is formed through a CVD process different from the ALD process. In the illustrated embodiment, the plug component 132 is formed using a continuous deposition technique, and a single gaseous substance is used to complete the deposition process during the use of the continuous deposition technique. Advantageously, the contact resistance at the interface between the plug component 132 and the conductive layer 126 is generally lower than the contact resistance at the interface between the plug component 132 and the top surface of the gate electrode 124 (including the metal layers 150, 152, and 154), thereby reducing the impact of the high-resistance interface between the multiple work function metal layers of the HK MG structure 120 and the plug component 132. Thereafter, one or more planarization processes, such as CMP, may be performed to remove any excess material from the top surface of the semiconductor structure 100.

[0080] Furthermore, please refer to Figure 10Aand Figure 10B In the illustrated embodiment, the plug member 132 (i.e., the opening formed in the second ILD layer 130) is offset from the center of the gate electrode by a certain distance, which indicates that misalignment occurred during the patterning process. A portion of the plug member 132 may fall on the capping layer 140 or may also fall on the gate dielectric layer 122. Due to the low resistivity of the conductive layer 126 as described above, a low-resistance interface can still be established between the plug member 132 and the conductive layer 126 despite the misalignment.

[0081] In step 322 of method 300, further subsequent steps are performed to complete the fabrication of the semiconductor structure (i.e., semiconductor device) 100. The semiconductor structure 100 may be disposed in a microprocessor, a memory, and / or other integrated circuit devices. In some embodiments, the semiconductor structure 100 may be a part of an IC chip, a system on chip (SoC), or a part of an SoC. The semiconductor structure 100 includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), CMOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable elements, or combinations of the foregoing. Other components may be added to the semiconductor structure 100 through subsequent process steps. For example, various vertical interconnect components (e.g., plugs and / or vias) and / or horizontal interconnect components (e.g., lines) configured to connect various components or structures of the semiconductor structure 100, as well as multi-level interconnect components (e.g., metal layers and interlayer dielectric layers), may be formed on the substrate 102.

[0082] Embodiments of method 300 may also be applied to form three-dimensional non-planar devices, such as Figure 2The semiconductor structure (i.e., FinFET device) 200 shown. In some embodiments, according to method 300, a semiconductor substrate 202 is provided, and fin structures 204 isolated by isolation structures 206 are formed. According to method 300, a dummy gate structure (not shown) and gate spacers 228 are formed over the fin structures 204 and isolation structures 206. Thereafter, method 300 forms source / drain components 208 on the fin structures 204, and then deposits a first ILD layer 210 over the isolation components 206 and source / drain components 208. Then, according to method 300, the dummy gate structure is replaced with a high-k metal gate (HK MG) structure 220. The components of the semiconductor structure 200 may include components similar in composition to the corresponding components in the semiconductor structure 100 and may be fabricated using methods similar to the corresponding components in the semiconductor structure 100. For example, similar to the HK MG structure 120, the HK MG structure 220 includes a high-k gate dielectric layer 222 and a gate electrode 224, and the gate electrode 224 may further include multiple layers of conductive material layers. The metal gate structure 220 may also include other material layers (not shown), such as an interface layer, a capping layer, a diffusion layer, a barrier layer, or a combination of the foregoing. According to method 300, a conductive layer 226 similar to the conductive layer 126 of the semiconductor structure 100 is further formed on the top surface of the HK MG structure 220. Thereafter, a second ILD layer 230 similar to the second ILD layer 130 of the semiconductor structure 100 is deposited over the conductive layer 226, a portion of the HK MG structure 220, and the first ILD layer 210, and via components 232 are formed within the second ILD layer 230 in a manner similar to the above-described method of forming via components 132.

[0083] Although not limited, one or more embodiments of the present invention provide improvements to semiconductor structures and methods of manufacturing the same. For example, embodiments of the present invention provide a conductive layer formed between a metal gate structure and a via component to reduce the high resistance at the interface between the metal gate structure and the via component due to the presence of one or more work function metal layers within the metal gate structure. This conductive layer is confined within smooth boundaries and does not intrude into the underlying gate electrode, which would otherwise affect the electrical stability of the metal gate structure. Furthermore, the formation of this conductive layer can be easily integrated into existing semiconductor manufacturing processes.

[0084] As can be seen from the above, the present invention provides many different embodiments for manufacturing semiconductor structures. One embodiment of the present invention relates to a method. This method includes forming a metal gate structure, where the metal gate structure includes a gate dielectric layer and a gate electrode. A surface treatment is performed on the top surface of the metal gate structure, and the surface treatment transforms the top of the gate electrode into an oxide layer. A conductive layer is formed above the gate electrode, and the formation of the conductive layer includes replacing oxygen in the oxide layer with a metal element. A plug component is formed above the metal gate structure, and the plug component is in direct contact with the conductive layer. In some embodiments, the surface treatment includes applying a plasma to the top surface of the metal gate structure. In some embodiments, the plasma is applied in-situ and the conductive layer is formed. In some embodiments, the plasma includes oxygen. In some embodiments, the formation of the conductive layer includes using a cyclic deposition technique with two gaseous precursors. In some embodiments, one of the two gaseous precursors includes the above metal element and a halogen element. In some embodiments, the above metal element is selected from the group consisting of tungsten, cobalt, titanium, aluminum, gold, and copper. In some embodiments, the conductive layer extends from a position below the top surface of the metal gate structure to another position above the top surface of the metal gate structure. In some embodiments, the conductive layer further includes a metal oxide, and the concentration of the metal oxide in the conductive layer increases along the direction towards the gate electrode. In some embodiments, the conductive layer is self-aligned with the top surface of the gate electrode but not with the top surface of the gate dielectric layer.

[0085] In another embodiment, the present invention relates to a method of forming a semiconductor structure. This method includes forming a metal gate structure, the metal gate structure including a gate dielectric layer and a gate electrode, the gate electrode including a first metal layer and a second metal layer, the first metal layer including a first metal element, and the second metal layer including a second metal element, the top surface of the first metal layer being coplanar with the top surface of the second metal layer. A passivation treatment is performed on the top surface of the first metal layer and the top surface of the second metal layer, and the passivation treatment forms a compound on the gate electrode, the compound including the first metal element and the second metal element. A third metal element is deposited above the metal gate structure to form a conductive layer, and the deposition of the third metal element transforms the compound into an alloy including the first metal element, the second metal element, and the third metal element. A plug component is formed above the metal gate structure, and the plug component is in direct contact with the conductive layer. In some embodiments, the conductive layer includes a metal film covering the above alloy, the metal film including the third metal element and not including the first metal element and the second metal element. In some embodiments, the passivation treatment includes a plasma treatment using a gas selected from oxygen and nitrogen. In some embodiments, the above compound includes an oxide of the first metal element and an oxide of the second metal element. In some embodiments, the conductive layer includes tungsten and the plug component includes cobalt.

[0086] In yet another embodiment, the present invention relates to a semiconductor structure. The semiconductor structure includes a metal gate structure, which includes a gate dielectric layer and a gate electrode, and the gate electrode includes at least one metal. A conductive layer is formed above the gate electrode, and the conductive layer includes an alloy layer, which includes the above-mentioned at least one metal and a second metal, and the alloy layer extends above the top surface of the metal gate structure. A plug component is disposed above the metal gate structure, and the plug component is in direct contact with the top surface of the conductive layer. In some embodiments, the conductive layer further includes a metal layer located on the alloy layer, and the metal layer includes the above-mentioned second metal. In some embodiments, the above-mentioned at least one metal is selected from the group consisting of tantalum, titanium, and aluminum, and the above-mentioned second metal is selected from the group consisting of tungsten, cobalt, gold, and copper. In some embodiments, the conductive layer further includes a metal oxide, and the concentration of the metal oxide in the conductive layer increases along the direction towards the gate electrode. In some embodiments, the contact resistance of the interface between the plug component and the conductive layer is lower than the contact resistance of the interface between the plug component and the metal gate structure.

[0087] The features of several embodiments are outlined above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that the present invention can be easily used as a basis for designing or changing other processes and structures to achieve the same purposes as the embodiments disclosed herein and / or obtain the same advantages. Those skilled in the art can also understand that the equivalent structures or processes do not depart from the concept and protection scope of the embodiments of the present invention, and various changes, substitutions, and modifications can be made without departing from the concept and scope of the embodiments of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising: forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment on a top surface of the metal gate structure, wherein the surface treatment transforms a top portion of the gate electrode into an oxide layer; forming a conductive layer over the gate electrode, wherein the formation of the conductive layer includes replacing oxygen in the oxide layer with a metal element; and forming a plug component over the metal gate structure, wherein the plug component is in direct contact with the conductive layer.

2. The method for forming a semiconductor structure according to claim 1, wherein the surface treatment includes applying plasma to the top surface of the metal gate structure.

3. The method for forming a semiconductor structure according to claim 2, wherein the plasma is applied in-situ and the conductive layer is formed.

4. The method for forming a semiconductor structure according to claim 2, wherein the plasma includes oxygen.

5. The method for forming a semiconductor structure according to claim 1, wherein the formation of the conductive layer includes using two gaseous precursors for a cyclic deposition technique.

6. The method for forming a semiconductor structure according to claim 5, wherein one of the two gaseous precursors includes the metal element and a halogen element.

7. The method for forming a semiconductor structure according to claim 6, wherein the metal element is selected from the group consisting of tungsten, cobalt, titanium, aluminum, gold, and copper.

8. The method for forming a semiconductor structure according to claim 1, wherein the conductive layer extends from a position below the top surface of the metal gate structure to another position above the top surface of the metal gate structure.

9. The method for forming a semiconductor structure according to claim 1, wherein the conductive layer further includes a metal oxide, and wherein the concentration of the metal oxide in the conductive layer increases along a direction toward the gate electrode.

10. The method for forming a semiconductor structure according to claim 1, wherein the conductive layer is self-aligned with a top surface of the gate electrode, but not with a top surface of the gate dielectric layer.

11. A method for forming a semiconductor structure, comprising: forming a metal gate structure, the metal gate structure including a gate dielectric layer and a gate electrode, wherein the gate electrode includes a first metal layer and a second metal layer, the first metal layer includes a first metal element, and the second metal layer includes a second metal element, and a top surface of the first metal layer is coplanar with a top surface of the second metal layer; performing a passivation treatment on the top surface of the first metal layer and the top surface of the second metal layer, wherein the passivation treatment forms a compound on the gate electrode, the compound including the first metal element and the second metal element; forming a conductive layer by depositing a third metal element over the metal gate structure, wherein the deposition of the third metal element transforms the compound into an alloy including the first metal element, the second metal element, and the third metal element; and forming a plug component over the metal gate structure, wherein the plug component is in direct contact with the conductive layer.

12. The method for forming a semiconductor structure as claimed in claim 11, wherein the conductive layer includes a metal film covering the alloy, and the metal film includes the third metal element and does not include the first metal element and the second metal element.

13. The method for forming a semiconductor structure as claimed in claim 11, wherein the passivation treatment includes plasma treatment using a gas selected from oxygen and nitrogen.

14. The method for forming a semiconductor structure as claimed in claim 11, wherein the compound includes a first metal element oxide and a second metal element oxide.

15. The method for forming a semiconductor structure as claimed in claim 11, wherein the conductive layer includes tungsten and the plug component includes cobalt.

16. A method for forming a semiconductor structure, comprising: forming a metal gate stack including a first metal element and a second metal element; transforming a top portion of the metal gate stack into an alloy, wherein the transformation of the top portion of the metal gate stack includes introducing a third metal element into the top portion of the metal gate stack, the third metal element being different from the first metal element and the second metal element; and forming a gate plug component on the alloy.

17. The method for forming a semiconductor structure as claimed in claim 16, wherein the transformation of the top portion of the metal gate stack also includes performing a passivation process on the top portion of the metal gate stack.

18. The method for forming a semiconductor structure as claimed in claim 17, wherein the passivation process is an oxidation treatment or a nitridation treatment.

19. The method for forming a semiconductor structure as claimed in claim 16, wherein a top surface of the alloy has a concave shape.

20. The method for forming a semiconductor structure as claimed in claim 16, wherein the metal gate stack includes a capping layer and a metal gate surrounded by the capping layer, and a portion of the alloy is directly above the capping layer.

21. A semiconductor structure, comprising: a metal gate structure including a gate dielectric layer and a gate electrode, in a cross-sectional schematic view in a longitudinal direction perpendicular to the metal gate structure, the metal gate structure includes a first sidewall and a second sidewall opposite to the first sidewall, and the gate electrode includes at least one first metal; a conductive layer formed above the gate electrode, the conductive layer includes an alloy layer including at least the first metal and a second metal different from the first metal, the alloy layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure, wherein in the cross-sectional schematic view, the conductive layer is laterally entirely located between the first sidewall and the second sidewall of the metal gate structure; and a plug component disposed above the metal gate structure, wherein the plug component is in direct contact with a top surface of the conductive layer, and the plug component is located above a topmost surface of the conductive layer.

22. The semiconductor structure as claimed in claim 21, wherein the conductive layer further includes a metal film of the second metal disposed above the alloy layer.

23. The semiconductor structure as claimed in claim 21, wherein the first metal is selected from the group consisting of tantalum, titanium and aluminum, and the second metal is selected from the group consisting of tungsten, cobalt, gold and copper.

24. The semiconductor structure as claimed in claim 21, wherein the conductive layer further comprises a metal oxide, and the concentration of the metal oxide in the conductive layer increases along a direction towards the gate electrode.

25. The semiconductor structure as claimed in claim 21, wherein the conductive layer does not contain a composite of a metal oxide, a metal nitride or a metal oxynitride.

26. The semiconductor structure as claimed in claim 21, wherein the contact resistance of the interface between the plug member and the conductive layer is lower than the contact resistance of the interface between the plug member and the metal gate structure.

27. The semiconductor structure as claimed in claim 21, wherein the gate electrode further comprises a third metal different from the first metal or the second metal, and the alloy layer comprises a central portion rich in the first metal and a side portion rich in the third metal.

28. The semiconductor structure as claimed in claim 21, wherein the conductive layer is self-aligned with the gate electrode.

29. The semiconductor structure as claimed in claim 21, wherein the conductive layer comprises a top and a bottom, the top of the conductive layer is above the top surface of the metal gate structure, and the bottom of the conductive layer is below the top surface of the metal gate structure, wherein the ratio of the thickness of the top to the bottom is from 1:8 to 1.5:

1.

30. A semiconductor structure, comprising: a metal gate structure, in a cross-sectional schematic view perpendicular to the longitudinal direction of the metal gate structure, the metal gate structure comprises a first sidewall and a second sidewall opposite to the first sidewall; an alloy layer deposited on the metal gate structure, the alloy layer extends from a position below the top surface of the metal gate structure to a position above the top surface of the metal gate structure, the alloy layer comprises at least a first metal element and a second metal element, wherein in the cross-sectional schematic view, the alloy layer is laterally entirely located between the first sidewall and the second sidewall of the metal gate structure; a metal film of the second metal element deposited on the alloy layer and above a topmost surface of the alloy layer; and a gate plug landing on the metal film.

31. The semiconductor structure as claimed in claim 30, wherein the metal gate structure comprises the first metal element and is substantially free of the second metal element.

32. The semiconductor structure as claimed in claim 30, wherein the metal film has a concave top surface.

33. The semiconductor structure as claimed in claim 30, wherein the metal film has a convex top surface.

34. The semiconductor structure as claimed in claim 30, wherein the first metal element is selected from the group consisting of tantalum, titanium and aluminum, and the second metal element is selected from the group consisting of tungsten, cobalt, gold and copper.

35. The semiconductor structure as claimed in claim 30, wherein the metal gate structure includes a gate dielectric layer, a capping layer on the gate dielectric layer, and a gate electrode on the capping layer, and wherein the boundary of the alloy layer is aligned with the boundary of the gate electrode.

36. The semiconductor structure as claimed in claim 30, wherein the metal gate structure includes a gate dielectric layer, a capping layer on the gate dielectric layer, and a gate electrode on the capping layer, and wherein the boundary of the alloy layer is aligned with the boundary of the capping layer.

37. A semiconductor structure, comprising: a metal gate structure including a gate dielectric layer and a gate electrode layer. In a cross-sectional view perpendicular to the longitudinal direction of the metal gate structure, the metal gate structure includes a first sidewall and a second sidewall opposite to the first sidewall; a conductive layer deposited on and in contact with the gate electrode layer, wherein the gate dielectric layer laterally confines the conductive layer, and wherein in the cross-sectional view, the conductive layer is laterally entirely located between the first sidewall and the second sidewall of the metal gate structure; and a gate plug landing on the conductive layer and located above a topmost surface of the conductive layer.

38. The semiconductor structure as claimed in claim 37, wherein the gate electrode layer includes a first metal and a second metal different from the first metal, and the conductive layer includes the first metal, the second metal, and a third metal different from the first metal or the second metal.

39. The semiconductor structure as claimed in claim 37, wherein the conductive layer extends vertically from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure.

40. The semiconductor structure as claimed in claim 39, wherein a thickness of a portion of the conductive layer below the top surface of the metal gate structure is less than 8 nm.

Images