Charge pump, high voltage generator having the charge pump, and flash memory device

Abstract

A charge pump, a high voltage generator and a flash memory device having the charge pump are provided. The charge pump includes: a first pumping capacitor configured to pump a first voltage of a first node in response to a first clock signal; a gate pumping capacitor configured to pump a second voltage of a second node in response to a second clock signal; a charge transfer transistor including a first source connected to one of a first node and a third node, a first gate connected to the second node, and a first drain connected to the other of the first node and the third node; a gate control transistor including a second source connected to the one of the first node and the third node, a second gate connected to the other of the first node and the third node, and a second drain connected to the second node; and a gate discharge or charge unit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2018-0088948, filed on Jul. 31, 2018, and Korean Patent Application No. 10-2018-0167133, filed on Dec. 21, 2018, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Apparatuses and devices consistent with example embodiments relate to a charge pump, and a high voltage generator and a flash memory device including the charge pump. Background Art

[0004] In a flash memory device, a positive high voltage and a negative high voltage that are higher or lower than a voltage applied from the outside may be required. In this way, the flash memory device may include a positive high voltage generator that generates a positive high voltage by pumping an applied voltage and a negative high voltage generator that generates a negative high voltage by pumping an applied voltage. Therefore, the circuit configuration of the flash memory device may be complex. Summary of the invention

[0005] According to an example embodiment, a charge pump is provided, which includes: a first pumping capacitor configured to pump a voltage of a first node in response to a first clock signal; a gate pumping capacitor configured to pump a second voltage of a second node in response to a second clock signal; a charge transfer transistor including a first source connected to one of a first node and a third node, a first gate connected to the second node, and a first drain connected to the other of the first node and the third node; a gate control transistor including a second source connected to one of the first node and the third node, a second gate connected to the other of the first node and the third node, and a second drain connected to the second node; and a gate discharge or charge unit configured to discharge or charge the charge of the second node.

[0006] According to an example embodiment, a high voltage generator is provided, the high voltage generator including: a first predetermined number of boost or buck pumps configured to output a positive or negative intermediate high voltage through a first output terminal by pumping an input voltage applied through an input terminal, the first predetermined number of boost or buck pumps being connected in series between the input terminal and the first output terminal; and a second predetermined number of boost or buck pumps configured to output a positive or negative final high voltage through a second output terminal by pumping the positive or negative intermediate high voltage, the second predetermined number of boost or buck pumps being connected in series between the first output terminal and the second output terminal. Each of the first predetermined number of boost or buck pumps and the second predetermined number of boost or buck pumps includes: a pumping capacitor configured to pump a first voltage of a first node in response to a first clock signal or a third clock signal; a gate pumping capacitor configured to pump a second voltage of a second node in response to a second clock signal or a fourth clock signal; and a charge transfer transistor including a first source connected to one of the first node and the third node, a first gate connected to the second node, and a first drain connected to the other of the first node and the third node. Each of the first predetermined number of boost or buck pumps and the second predetermined number of boost or buck pumps also includes: a gate control transistor including a second source connected to one of the first node and the third node, a second gate connected to the other of the first node and the third node, and a second drain connected to the second node; and a gate discharge or charge unit constructed to discharge or charge the charge of the second node.

[0007] According to an example embodiment, a high voltage generator is provided, the high voltage generator comprising: a predetermined number of boost and buck pumps configured to output a positive high voltage through an output terminal by boosting an input voltage applied through an input terminal, and output a negative high voltage through an input terminal by bucking an output voltage applied through an output terminal. The predetermined number of boost and buck pumps are connected in series between an input terminal and an output terminal. Each of the predetermined number of boost and buck pumps comprises: a first pumping capacitor configured to pump a first voltage of a first node in response to a first clock signal; a second pumping capacitor configured to pump a third voltage of a third node in response to a third clock signal; and a gate pumping capacitor configured to pump a second voltage of a second node in response to a second clock signal or a fourth clock signal. Each of the predetermined number of step-up and step-down pumps also includes a charge transfer transistor including a first source connected to a third node, a first gate connected to the second node, and a first drain connected to the first node, a gate control transistor including a second source connected to the third node, a second gate connected to the first node, and a second drain connected to the second node, and a gate discharge or charge unit configured to discharge or charge the charge of the second node.

[0008] According to example embodiments, there is provided a flash memory device, the flash memory device including a flash memory cell array including a plurality of flash memory cells, and a first high voltage generator including a first charge pump including a first predetermined number of first boost pumps connected in series, the first high voltage generator being configured to output an intermediate high voltage through a first output terminal by boosting an input voltage applied through a first input terminal during a programming operation, and output a first positive high voltage through a second output terminal by boosting an input voltage applied through the first input terminal during an erase operation. The flash memory device also includes a second high voltage generator including a second charge pump including a second predetermined number of second boost and buck pumps connected in series, the second high voltage generator being configured to output a second positive high voltage through a third output terminal by boosting an input voltage applied through the second input terminal during a programming operation, and output a negative high voltage through the second input terminal by bucking an output voltage applied through the third output terminal during an erase operation. The flash memory device also includes a row driver configured to apply an intermediate high voltage and a second positive high voltage to the flash memory cell array during a program operation and to apply a first positive high voltage and a negative high voltage to the flash memory cell array during an erase operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a circuit diagram illustrating a charge pump according to example embodiments.

[0010] Figure 2 is shown applied to Figure 1 FIG. 1 is a timing diagram of the first clock signal CLK1 to the fourth clock signal CLK4 of the charge pump.

[0011] Figure 3 is a diagram illustrating a high voltage generator according to example embodiments.

[0012] Figure 4 It is shown that the Figure 3 A block diagram of a charge pump in a high voltage generator is shown.

[0013] Figure 5 is a diagram illustrating a high voltage generator according to example embodiments.

[0014] Figure 6 It is shown that the Figure 5 A block diagram of a charge pump in a high voltage generator is shown.

[0015] Figure 7 is a diagram illustrating a high voltage generator according to example embodiments.

[0016] Figure 8is a diagram illustrating a high voltage generator according to example embodiments.

[0017] Fig. 9 is a diagram illustrating a high voltage generator according to example embodiments.

[0018] Fig.10 is a cross-sectional view of a first body control transistor of a charge pump of a high voltage generator according to example embodiments.

[0019] Fig.11 is a block diagram illustrating a flash memory device according to example embodiments.

[0020] Fig.12 is a diagram showing a method according to an example embodiment Fig.11 A circuit diagram of the structure of a flash memory cell array is shown. DETAILED DESCRIPTION

[0021] Example embodiments of the inventive concept are directed to providing a charge pump that generates different positive (negative) high voltages or a positive high voltage or a negative high voltage, and a high voltage generator and a flash memory device including the charge pump.

[0022] Hereinafter, a charge pump, and a high voltage generator and a flash memory device including the charge pump according to example embodiments of the inventive concept will be described below with reference to the accompanying drawings.

[0023] Figure 1 is a circuit diagram showing a charge pump according to an example embodiment, Figure 2 is shown applied to Figure 1 FIG. 1 is a timing diagram of the first clock signal CLK1 to the fourth clock signal CLK4 of the charge pump.

[0024] Reference Figure 1 The charge pump 10 may include first and second boost pumps PU1 and PU2 , first and second buck pumps PD1 and PD2 , and first and second switches SW1 and SW2 .

[0025] The first boost pump PU1 may include a first pump capacitor Cp1, a first gate pump capacitor Cb1, a first charge transfer transistor CT1, a first gate control transistor GC1, a first body control transistor BC1 and a second body control transistor BC2, and a first gate discharge or charge transistor DT1 and a second gate discharge or charge transistor DT2. Excluding the first pump capacitor Cp1 of the first boost pump PU1, the second buck pump PD2 may also include a third pump capacitor Cp3 and a first switch SW1. The first gate discharge or charge transistor DT1 and the second gate discharge or charge transistor DT2 may be embodiments of a gate discharge or charge unit. Different from what is shown in the figure, the first gate discharge or charge transistor DT1 and the second gate discharge or charge transistor DT2 may include one gate discharge or charge transistor or may include at least three gate discharge or charge transistors connected in series. That is, the first gate discharge or charge transistor DT1 and the second gate discharge or charge transistor DT2 may include at least one discharge or charge transistor.

[0026] The second boost pump PU2 may include a second pump capacitor Cp2, a second gate pump capacitor Cb2, a second charge transfer transistor CT2, a second gate control transistor GC2, a third body control transistor BC3 and a fourth body control transistor BC4, a third gate discharge or charge transistor DT3 and a fourth gate discharge or charge transistor DT4, and a second switch SW2. Excluding the second pump capacitor Cp2 of the second boost pump PU2 and the switch SW2, the first buck pump PD1 may also include a first pump capacitor Cp1 of the first boost pump PU1. The third gate discharge or charge transistor DT3 and the fourth gate discharge or charge transistor DT4 may be embodiments of a gate discharge or charge unit. Different from what is shown in the figure, the third gate discharge or charge transistor DT3 and the fourth gate discharge or charge transistor DT4 may include one gate discharge or charge transistor or may include at least three gate discharge or charge transistors connected in series. That is, the third gate discharge or charge transistor DT3 and the fourth gate discharge or charge transistor DT4 may include at least one gate discharge or charge transistor.

[0027] Each of the first charge transfer transistor CT1, the first gate control transistor GC1, the first and second body control transistors BC1 and BC2, the second charge transfer transistor CT2, the second gate control transistor GC2, and the third and fourth body control transistors BC3 and BC4 may be an n-type metal oxide semiconductor (NMOS) transistor.

[0028] Reference Figure 1 and Figure 2, when the mode signal M is at a "low" level, the first switch SW1 may be turned off and the second switch SW2 may be turned on. When the second clock signal CLK2 is at a "low" level (e.g., the ground voltage VSS), the first clock signal CLK1 may be at a "high" level (e.g., the power supply voltage VDD or the voltage 2VDD), and when the first clock signal CLK1 is at a "low" level, the second clock signal CLK2 may be at a "high" level. Similarly, when the fourth clock signal CLK4 is at a "low" level, the third clock signal CLK3 may be at a "high" level, and when the third clock signal CLK3 may be at a "low" level, the fourth clock signal CLK4 may be at a "high" level. The first boost pump PU1 and the second boost pump PU2 can respond to the first clock signal CLK1 to the fourth clock signal CLK4 by boosting the voltage (for example, the power supply voltage VDD) supplied through the input / output terminal VIN / VOUT to perform a boost operation to generate a positive high voltage (for example, voltage 3VDD) through the output / input terminal VOUT / VIN.

[0029] On the contrary, when the mode signal M is at a "high" level, the first switch SW1 may be turned on and the second switch SW2 may be turned off. The first buck pump PD1 and the second buck pump PD2 may perform a step-down operation of generating a negative high voltage (e.g., -2VDD) through the input / output terminal VIN / VOUT by stepping down a voltage (e.g., a ground voltage VSS) supplied through the output / input terminal VOUT / VIN in response to the first to fourth clock signals CLK1 to CLK4.

[0030] The following will describe Figure 1 Functions of the components shown.

[0031] The first pumping capacitor Cp1 may be connected to the first node n11 and may pump a first voltage of the first node n11 in response to the first clock signal CLK1 .

[0032] The first gate pumping capacitor Cb1 may be connected to the second node n12 and may pump a second voltage of the second node n12 in response to the second clock signal CLK2 .

[0033] The first charge transfer transistor CT1 may include a first source connected to the third node n13, a first gate connected to the second node n12, a first drain connected to the first node n11, and a first body connected to the fourth node n14, and may be turned on in response to a second voltage at the second node n12 to transfer charge from the third node n13 serving as an input terminal to the first node n11.

[0034] The first gate control transistor GC1 may include a second gate connected to the first node n11, a second source connected to the third node n13, a second drain connected to the second node n12, and a second body connected to the fourth node n14, and may be turned on in response to a first voltage of the first node n11 to transfer charges from the third node n13 to the second node n12.

[0035] The first body control transistor BC1 may include a fourth source connected to the third node n13, a fourth gate connected to the first node n11, and a fourth drain and a fourth body connected to the fourth node n14, and may be turned on in response to a third voltage of the third node n13 to transfer charges from the third node n13 to the fourth node n14 connected to the fourth body.

[0036] The second body control transistor BC2 may include a fifth source connected to the first node n11, a fifth gate connected to the third node n13, and a fifth drain and a fifth body connected to the fourth node n14, and may be turned on in response to a third voltage of the third node n13 to transfer charges from the first node n13 to the fourth node n14.

[0037] The third pumping capacitor Cp3 may be connected to the third node n13 and may pump a third voltage of the third node n13 in response to the third clock signal CLK3 .

[0038] The first gate discharge or charge transistor DT1 and the second gate discharge or charge transistor DT2 may be connected in series between the second node n12 and the first node n11, and each may include a third body connected to the fourth node n14. For example, the first gate discharge or charge transistor DT1 may include a third gate and a third source connected to the second node n12, and the second gate discharge or charge transistor DT2 may include a third drain connected to the first node n11. The first gate discharge or charge transistor DT1 and the second gate discharge or charge transistor DT2 may have a diode configuration, and may discharge or charge the charge of the second node n12. During a discharge operation or a charge operation, a second voltage of the second node n12 may be equal to the sum of the first voltage of the first node n11 and 2Vth (here, Vth may represent a threshold voltage of each of the first gate discharge or charge transistor DT1 and the second gate discharge or charge transistor DT2). Unless the first voltage of the first node n11 is 2Vth higher than the voltage of the second node n12, the first gate discharge or charge transistor DT1 and the second gate discharge or charge transistor DT2 may not be operated. That is, the first gate discharge or charge transistor DT1 and the second gate discharge or charge transistor DT2 may be operated only during the discharge operation or the charge operation after the pumping operation (boost operation or buck operation), and may be operated during the pumping operation. Unlike what is shown in the figure, three or more gate discharge and charge transistors may be connected between the second node n12 and the first node n11.

[0039] In summary, the first boost pump PU1 can perform a boost operation in response to the first clock signal CLK1 and the second clock signal CLK2, and output the boost voltage to the first node n11, and the second buck pump PD2 can perform a buck operation in response to the third clock signal CLK3 and the second clock signal CLK2, and output the buck voltage to the third node n13.

[0040] The second boost pump PU2 may be configured to be the same as the first boost pump PU1 between the first node n11, the fifth node n15, the sixth node n16, and the seventh node n17. Similarly, the first buck pump PD1 may be configured to be the same as the second buck pump PD2 between the first node n11, the fifth node n15, the sixth node n16, and the seventh node n17. The operation of the second pumping capacitor Cp2, the second gate pumping capacitor Cb2, the second charge transfer transistor CT2, the second gate control transistor GC2, the third body control transistor BC3 and the fourth body control transistor BC4, the third gate discharge or charge transistor DT3 and the fourth gate discharge or charge transistor DT4, and the first pumping capacitor Cp1 may correspond to the operation of the above-mentioned first pumping capacitor Cp1, the first gate pumping capacitor Cb1, the second charge transfer transistor CT1, the second gate control transistor GC1, the first body control transistor BC1 and the second body control transistor BC2, the first gate discharge or charge transistor DT1 and the second gate discharge or charge transistor DT2, and the third pumping capacitor Cp3.

[0041] In summary, the second boost pump PU2 can perform a boost operation in response to the third clock signal CLK3 and the fourth clock signal CLK4 and generate a boost voltage to the fifth node n15, and the first buck pump PD1 can perform a buck operation in response to the first clock signal CLK1 and the fourth clock signal CLK4 and generate a buck voltage to the first node n11.

[0042] The following will refer to Figure 1 and Figure 2 The boost operation performed by the charge pump 10 according to an embodiment of the inventive concept is described. In the second period T2, when the first clock signal CLK1 is at a "high" level and the second clock signal CLK2 is at a "low" level, the first pumping capacitor Cp1 may perform a pumping operation to pump the first node n11 (previously charged to the power supply voltage VDD) to a voltage of 2VDD, and the first gate pumping capacitor Cb1 may provide 0V for the second node n12. The first gate control transistor GC1 may be turned on to transfer the charge of the power supply voltage VDD to the second node n12. The first charge transfer transistor CT1 may be turned off.

[0043] In this case, the first voltage of the first node n11 may be higher than the voltage of the third node n13. Therefore, the first body control transistor BC1 may be turned on, and thus the fourth node n14 connected to its fourth body may be biased by the power supply voltage VDD. Therefore, it is possible to prevent the threshold voltage Vth from being undesirably increased due to the body effect of the first gate control transistor GC1.

[0044] In addition, in the second period T2, when the third clock signal CLK3 is at a "low" level and the fourth clock signal CLK4 is at a "high" level, the second gate pumping capacitor Cb2 may perform a pumping operation to pump the sixth node n16 (previously charged to a voltage of 2VDD) to a voltage of 3VDD. Therefore, the second charge transfer transistor CT2 may be turned on to transfer charges from the first node n11 to the fifth node n15. Therefore, the second gate control transistor GC2 may be turned off.

[0045] In this case, the first voltage of the first node n11 may be higher than the voltage of the fifth node n15. Therefore, the fourth body control transistor BC4 may be turned on, and thus the seventh node n17 may be biased by the voltage 2VDD. Therefore, it is possible to prevent the threshold voltage from being undesirably increased due to the body effect of the second charge transfer transistor CT2.

[0046] In the third period T3, when the first clock signal CLK1 is at a "low" level and the second clock signal CLK2 is at a "high" level, the first gate pumping capacitor Cb1 may perform a pumping operation to pump the second node n12 (previously charged to the power supply voltage VDD) to a voltage of 2VDD. The first charge transfer transistor CT1 may be turned on to transfer charges from the third node n13 to the first node n11. Therefore, the first gate control transistor GC1 may be turned off.

[0047] In this case, the third voltage of the third node n13 may be higher than the first voltage of the first node n11. Therefore, the second body control transistor BC2 may be turned on, and thus the fourth node n14 may be biased by the power supply voltage VDD. Therefore, it is possible to prevent the threshold voltage from being undesirably increased due to the effect of the first body of the first charge transfer transistor CT1.

[0048] In addition, in the third period T3, when the third clock signal CLK3 is at a "high" level and the fourth clock signal CLK4 is at a "low" level, the second pumping capacitor Cp2 may perform a pumping operation to pump the fifth node n15 (previously charged to a voltage of 2VDD) to a voltage of 3VDD, and the second gate pumping capacitor Cb2 may provide 0V to the sixth node n16. The second charge transfer transistor CT2 may be turned off. The second gate control transistor GC2 may be turned on to provide a voltage of 2VDD to the sixth node n16.

[0049] In this case, the voltage of the fifth node n15 may be higher than the voltage of the first node n12. Therefore, the third body control transistor BC3 may be turned on, and thus the seventh node n17 may be biased by the voltage 2VDD. Therefore, it is possible to prevent the threshold voltage from being undesirably increased due to the body effect of the second gate control transistor GC2.

[0050] The first and second boost pumps PU1 and PU2 may repeatedly perform boosting operations to boost a first voltage of the first node n11 to a voltage of 2VDD and a voltage of the fifth node n15 to a voltage of 3VDD in response to the first to fourth clock signals CLK1 to CLK4 .

[0051] The following will refer to Figure 1 and Figure 2 A voltage step-down operation performed by the charge pump 10 according to an embodiment of the inventive concept is described.

[0052] In the second period T2, when the first clock signal CLK1 is at a "high" level and the fourth clock signal CLK4 is at a "high" level, the second gate pumping capacitor Cb2 may provide 0V to the sixth node n16 (previously discharged to the voltage -VDD). The second charge transfer transistor CT2 may be turned on to transfer the charge from the first node n11 to the fifth node n15. The first pumping capacitor Cp1 may perform a pumping operation to pump the first node n11 to the voltage -VDD. In this case, the second gate control transistor GC2 may be turned on to transfer the charge of the voltage -VDD to the sixth node n16. The second charge transfer transistor CT2 may be turned off.

[0053] In this case, the voltage of the fifth node n11 may be higher than the voltage of the first node n15. Therefore, the third body control transistor BC3 may be turned on, and thus the seventh node n17 may be biased by the voltage -VDD. Therefore, it is possible to prevent the threshold voltage from being undesirably increased due to the body effect of the second gate control transistor GC2.

[0054] Furthermore, in the second period T2 , when the second clock signal CLK2 is at a “high” level and the third clock signal CLK3 is at a “low” level, the third pumping capacitor Cp3 and the first gate pumping capacitor Cb1 may not perform a pumping operation.

[0055] In the third period T3 , when the first clock signal CLK1 is at a “low” level and the fourth clock signal CLK4 is at a “low” level, the first pumping capacitor Cp1 and the second gate pumping capacitor Cb2 may not perform a pumping operation.

[0056] In addition, in the third period T3, when the second clock signal CLK2 is at a "high" level and the third clock signal CLK3 is at a "high" level, the first gate pumping capacitor Cb1 may perform a pumping operation to pump the second node n12 (previously discharged to a voltage of -2VDD) to a voltage of -VDD. The first charge transfer transistor CT1 may be turned on to transfer charge from the third node n13 to the first node n11. The third pumping capacitor Cp3 may perform a pumping operation to pump the third node n13 (previously discharged to a voltage of -VDD) to a voltage of -2VDD. In this case, the first gate control transistor GC1 may be turned on to transfer the voltage of -2VDD to the second node n12. The first charge transfer transistor CT1 may be turned off.

[0057] In this case, the third voltage of the third node n13 may be higher than the first voltage of the first node n11. Therefore, the first body control transistor BC1 may be turned on, and thus the fourth node n14 may be biased by the voltage -2VDD. Therefore, it is possible to prevent the threshold voltage from being undesirably increased due to the body effect of the first gate control transistor GC1.

[0058] The first and second step-down pumps PD1 and PD2 may repeatedly perform step-down operations in response to the first to fourth clock signals CLK1 to CLK4 and provide a voltage of −2VDD to the third node n13 .

[0059] After the boost operation or the buck operation, the charge pump 10 may perform a discharge operation or a charge operation. During the discharge operation or the charge operation, charges may be discharged or charged from the input / output terminal VIN / VOUT to the output / input terminal VOUT / VIN via the first charge transfer transistor CT1 and the second charge transfer transistor CT2.

[0060] During the discharge operation, as the voltages of the first node n11 and the fifth node n15 decrease, the voltages of the second node n12 and the sixth node n16 may be decreased by the first gate discharge or charge transistor DT1 and the second gate discharge or charge transistor DT2 and the third gate discharge or charge transistor DT3 and the fourth gate discharge or charge transistor DT4. For example, when the voltage of the first node n11 and the voltage of the fifth node n15 decrease to 1V, the voltage of the second node n12 and the voltage of the sixth node n16 may decrease to a voltage of 1V+2Vth. During the charging operation, as the voltage of the first node n11 and the voltage of the fifth node n15 increase, the voltage of the second node n12 and the voltage of the sixth node n16 may be increased by the first gate discharge or charge transistor DT1 and the second gate discharge or charge transistor DT2 and the third gate discharge or charge transistor DT3 and the fourth gate discharge or charge transistor DT4. For example, when the voltage of the first node n11 and the voltage of the fifth node n15 increase to 1V, the voltage of the second node n12 and the voltage of the sixth node n16 may increase to a voltage of 1V+2Vth.

[0061] Therefore, in the charge pump 10 according to an embodiment of the present invention, during the discharge operation after the boost operation and during the charging operation after the buck operation, not only the first node n11 and the fifth node n15 but also the second node n12 and the sixth node n16 are discharged or charged, thereby accurately performing the boost operation and the buck operation.

[0062] Although the present inventive concept is illustrated and described above by distinguishing the charge pump from the boost pump and the buck pump for convenience of explanation, in practice, the charge pump according to an embodiment of the present inventive concept may have a structure in which a plurality of boost pumps are connected in series.

[0063] Although the above Figure 1 The charge pump 10 is shown as including two-stage boost pumps PU1 and PU2 and two-stage buck pumps PD1 and PD2, but Figure 1 Different from the above, the charge pump according to the embodiment of the inventive concept may include a primary boost pump PU1, a primary buck pump PD1, or both a primary boost pump PU1 and a primary buck pump PD2. Figure 1 When the charge pump 10 includes a first-stage boost pump PU1 and a first-stage buck pump PD2, the first node n11 can be used as an output / input terminal VOUT / VIN. Figure 1 When the charge pump 10 includes a first-stage boost pump PU1 and a first-stage buck pump PD2, it can respond to Figure 2 The first clock signal CLK1 at a "high" level and the second clock signal CLK2 at a "low" level perform a voltage boost operation, and can respond to Figure 2The third clock signal CLK3 at the "high" level and the second clock signal CLK2 at the "high" level are shown to perform a step-down operation, which is clear from the above-mentioned step-up operation and step-down operation.

[0064] In addition, the above Figure 1 The charge pump 10 includes a first body control transistor BC1, a second body control transistor BC2, a third body control transistor BC3, and a fourth body control transistor BC4, but unlike Figure 1 Different from what is shown, the first to fourth body control transistors BC1 to BC4 may be omitted.

[0065] Figure 3 is a diagram illustrating a high voltage generator according to an example embodiment, Figure 4 It is shown that the Figure 3 A block diagram of a charge pump in a high voltage generator is shown.

[0066] Reference Figure 3 , the high voltage generator 100 may include a charge pump 10', a clock generator 12, a first comparator 14, a first regulator 16, and a high voltage discharger 18. The first regulator 16 may include first and second resistors R1 and R2 and a third switch SW3.

[0067] The following will describe Figure 3 Functionality of the blocks shown.

[0068] The charge pump 10' may output a positive high voltage through an output terminal VOUT by pumping a voltage (eg, a power supply voltage VDD) applied through an input terminal VIN in response to first to fourth clock signals CLK1 to CLK4. The charge pump 10' may include Figure 1 The first boost pump PU1 and the second boost pump PU2 are shown, but the second switch SW2 may not be included, and the second pumping capacitor Cp2 may be directly connected to the fifth node n15.

[0069] like Figure 4 As shown, the charge pump 10' may have a structure in which the first boost pump PU1 to the nth boost pump PUn are connected in series. In this case, each of the odd-numbered boost pumps from the first boost pump PU1 to the nth boost pump PUn may perform a boost operation in response to the first clock signal CLK1 and the second clock signal CLK2, and each of the other even-numbered boost pumps may perform a boost operation in response to the third clock signal CLK3 and the fourth clock signal CLK4, so that when the power supply voltage VDD is applied via the input terminal VIN, the positive high voltage (n+1) VDD may be output via the output terminal VOUT. For example, when n is ten, the charge pump 10' may generate a positive high voltage 11VDD.

[0070] Refer to Figure 3 , the clock generator 12 can generate a clock signal such as Figure 2 The first clock signal CLK1 to the fourth clock signal CLK4 are shown.

[0071] The first comparator 14 may compare the voltage of the eighth node n18 with the first reference voltage Vref1, and may activate the first enable signal EN1 when the voltage of the eighth node n18 is lower than the first reference voltage Vref1, and may deactivate the first enable signal EN1 when the voltage of the eighth node n18 is equal to or greater than the first reference voltage Vref1.

[0072] When the third switch SW3 is turned on in response to the first regulator enable signal REN1 , the first regulator 16 may be enabled to divide the voltage of the output terminal VOUT through the first resistor R1 and the second resistor R2 and generate a divided voltage through the eighth node n18 .

[0073] The high voltage discharger 18 may discharge the voltage of the output terminal VOUT. For example, after the voltage of the output terminal VOUT reaches the target positive high voltage VPP, when the third switch SW3 is turned off in response to the first regulator enable signal REN1, the positive high voltage VPP may be discharged to the output terminal VOUT.

[0074] Figure 5 is a diagram illustrating a high voltage generator according to an example embodiment, and Figure 6 It is shown that the Figure 5 A block diagram of a charge pump in a high voltage generator is shown.

[0075] Reference Figure 5 , the high voltage generator 200 may include a charge pump 10 ″, a clock generator 12 ′, a second comparator 20 , a second regulator 22 , and a high voltage charger 24 . The second regulator 22 may include a fourth switch SW4 and third and fourth resistors R3 and R4 .

[0076] The following will describe Figure 5 Functionality of the blocks shown.

[0077] The charge pump 10 ″ may generate a negative high voltage through an output terminal VOUT by pumping a voltage (eg, a ground voltage VSS) applied through an input terminal VIN in response to the first to fourth clock signals CLK1 to CLK4. The charge pump 10 ″ may include Figure 1 The first and second buck pumps PD1 and PD2 are shown without including the second switch SW2 , and the third pumping capacitor Cp3 may be connected to the third node n13 .

[0078] like Figure 6As shown, the charge pump 10" may have a structure in which the first buck pump PD1 to the kth buck pump PDk are connected in series. In this case, each of the odd-numbered buck pumps from the first buck pump PD1 to the kth buck pump PDk may perform a buck operation in response to the first clock signal CLK1 and the fourth clock signal CLK4, and each of the other even-numbered buck pumps may perform a buck operation in response to the third clock signal CLK3 and the second clock signal CLK2, so that when the ground voltage VSS is applied through the input terminal VIN, a negative high voltage -kVDD may be output through the output terminal VOUT. For example, when k is ten, the charge pump 10" may generate a negative high voltage -10VDD.

[0079] Refer to Figure 5 , the clock generator 12 can generate the first clock signal CLK1 to the fourth clock signal CLK4 in response to the second enable signal EN2. Figure 2 shown.

[0080] The second comparator 20 can compare the voltage of the ninth node n19 with the second reference voltage Vref2, and can activate the second enable signal EN2 when the voltage of the ninth node n19 is higher than the second reference voltage Vref2, and can deactivate the second enable signal EN2 when the voltage of the ninth node n19 is less than or equal to the second reference voltage Vref2.

[0081] When the fourth switch SW4 is turned on in response to the second regulator enable signal REN2 , the second regulator 22 may be enabled to divide the voltage of the input terminal VIN through the third resistor R3 and the fourth resistor R4 and output the divided voltage through the ninth node n19 .

[0082] The high voltage charger 24 can charge the input terminal VIN with a negative high voltage. For example, after the voltage of the input terminal VIN reaches a target negative high voltage, when the fourth switch SW4 is turned off in response to the second regulator enable signal REN2, the input terminal VIN can be charged to the negative high voltage.

[0083] Figure 7 is a diagram illustrating a high voltage generator according to example embodiments.

[0084] Reference Figure 7 , the high voltage generator 300 may include first and second high voltage generators 310 and 320 and a switch unit 330. The switch unit 330 may include fifth to eighth switches SW5 to SW8.

[0085] The following will describe Figure 7 Functionality of the blocks shown.

[0086] The first high voltage generator 310 may generate the intermediate high voltage VM by pumping an input voltage (eg, a power supply voltage VDD) applied through an input terminal IN.

[0087] The second high voltage generator 320 may generate the final high voltage VP by pumping the input voltage IN or the intermediate high voltage VM applied through the fifth switch SW5 .

[0088] Each of the first high voltage generator 310 and the second high voltage generator 320 may have Figure 3 The high voltage generator 100 or Figure 5 The high voltage generator 200 has the same structure.

[0089] The fifth switch SW5 may output the voltage of the input terminal IN to the second high voltage generator 320 when the mode signal M is at a “low” level, and may output the intermediate high voltage VM to the second high voltage generator 320 when the mode signal M is at a “high” level.

[0090] When the mode signal M is at a “low” level, the sixth switch SW6 may be turned on to output the intermediate high voltage VM through the first output terminal OUT1 .

[0091] When the mode signal M is at a “low” level, the seventh switch SW7 may be turned on to output the intermediate high voltage VM through the first output terminal OUT1 .

[0092] When the mode signal M is at a “high” level, the eighth switch SW8 may be turned on to output the final high voltage VP through the second output terminal OUT2 .

[0093] That is to say, Figure 7 The high voltage generator 300 may output the intermediate high voltage VM output from the first high voltage generator 310 and the second high voltage generator 320 through the first output terminal OUT1 when the mode signal M is at a “low” level, and may output the final high voltage VP output from the first high voltage generator 310 and the second high voltage generator 320 through the second output terminal OUT2 when the mode signal M is at a “high” level.

[0094] Figure 7 The high voltage generator 300 may generate two different positive high voltages or two different negative high voltages according to the mode signal M. For example, the intermediate high voltage VM may be 5VDD, and the final high voltage VP may be 10VDD. Alternatively, the intermediate high voltage VM may be -5VDD, and the final high voltage VP may be -10VDD.

[0095] Figure 7The high voltage generator 300 may have a structure in which a first high voltage generator 310 and a second high voltage generator 320 generating the same intermediate high voltage VM are connected in parallel to generate the intermediate high voltage VM. Figure 7 Unlike shown, one of the first high voltage generator 310 and the second high voltage generator 320 may be configured to generate the intermediate high voltage VM by pumping the voltage of the input terminal IN.

[0096] Figure 8 is a diagram illustrating a high voltage generator according to example embodiments.

[0097] Reference Figure 8 ,remove Figure 3 In addition to the configuration of the high voltage generator 100 shown in the figure, the high voltage generator 400 may also include Figure 5 A second comparator 20 , a second regulator 22 and a high voltage charger 24 are shown.

[0098] By reference Figure 3 and Figure 5 The above functions of the blocks shown will be easily understood Figure 8 The functions of the blocks shown are not described, and thus their description will be omitted.

[0099] When the mode signal M is at a “low” level, the charge pump 10 may output a positive high voltage through the output terminal VOUT by boosting an input voltage (eg, power supply voltage VDD) applied through the input terminal VIN in response to the first to fourth clock signals CLK1 to CLK4 .

[0100] In contrast, when the mode signal M is at a "high" level, the charge pump 10 may output a negative high voltage through the input terminal VIN by stepping down an input voltage (eg, ground voltage VSS) applied through the output terminal VOUT in response to the first to fourth clock signals CLK1 to CLK4.

[0101] The charge pump 10 may be Figure 1 The structure shown may be Figure 1 The structure shown is that different i pressure boosting pumps PU1 to PUi or i pressure reducing pumps PD1 to PDi are connected in series.

[0102] The clock generator 12 may generate the first to fourth clock signals CLK1 to CLK4 in response to the first enable signal EN1 when the mode signal M is at a "high" level, and may generate the first to fourth clock signals CLK1 to CLK4 in response to the second enable signal EN2 when the mode signal M is at a "low" level. Figure 2 The first clock signal CLK1 to the fourth clock signal CLK4 are generated as shown.

[0103] When the mode signal M is at a “low” level, the first comparator 14, the first regulator 16 and the high voltage discharger 18 may perform the above-mentioned Figure 3 The operation described.

[0104] When the mode signal M is at a “high” level, the second comparator 20, the second regulator 22 and the high voltage charger 24 may perform the above-mentioned Figure 5 The operation described.

[0105] That is, when the mode signal M is at a "low" level, Figure 8 The high voltage generator 400 can output a positive high voltage through the output terminal VOUT by boosting the input voltage (e.g., the power supply voltage VDD) applied through the input terminal VIN. When the mode signal M is at a "high" level, the high voltage generator 400 can output a negative high voltage through the input terminal VIN by stepping down the input voltage (e.g., the ground voltage VSS) applied through the output terminal VOUT.

[0106] Fig. 9 is a diagram illustrating a high voltage generator according to example embodiments.

[0107] Reference Fig. 9 , the high voltage generator 500 may include a high voltage generator 510 and a switch unit 520. The switch unit 520 may include ninth to twelfth switches SW9 to SW12.

[0108] The following will describe Fig. 9 Functionality of the blocks shown.

[0109] When the mode signal M is at a "low" level, the high voltage generator 510 can generate a positive high voltage by pumping a first input voltage (e.g., a power supply voltage VDD) applied via the first input terminal IN1. When the mode signal M is at a "high" level, the high voltage generator 510 can generate a negative high voltage by pumping a second input voltage (e.g., a ground voltage VSS).

[0110] When the mode signal M is at a “low” level, the ninth switch SW9 may be turned on to transfer the first input voltage to the high voltage generator 510 .

[0111] When the mode signal M is at a “high” level, the tenth switch SW10 may be turned on to transfer the negative high voltage output from the high voltage generator 510 to the second output terminal OUT2 .

[0112] When the mode signal M is at a “low” level, the eleventh switch SW11 may be turned on to transfer the positive high voltage output from the high voltage generator 510 to the first output terminal OUT1 .

[0113] When the mode signal M is at a “high” level, the twelfth switch SW12 may be turned on to transfer the second input voltage IN2 applied through the second input terminal IN2 to the high voltage generator 510 .

[0114] That is to say, Fig. 9 The high voltage generator 500 can output a positive high voltage through the first output terminal OUT1 by boosting the first input voltage IN1 when the mode signal M is at a “low” level, and can output a negative high voltage through the second output terminal OUT2 by bucking the second input voltage when the mode signal M is at a “high” level.

[0115] Fig.10 is a cross-sectional view of a first body control transistor of a charge pump of a high voltage generator according to example embodiments.

[0116] Reference Fig.10 , the first body control transistor BC1 may be formed in a P+ well having a triple well structure including an N+ well formed in a P-type substrate PSUB and a P+ well formed in an N+ well. The first body control transistor BC1 may include an n+ source S and an n+ drain D formed in the P+ well, a gate G formed on an upper portion of the P+ well between the n+ source S and the n+ drain D, and a p+ body B1. The p+ body B1 may be connected to a first body node, for example, a fourth node n14 or a seventh node n17. The n+ body B2 formed in the N+ well may be connected to a terminal generating the highest voltage (for example, an output terminal VOUT or an input terminal VIN). A ground voltage may be applied to the p+ body B3 formed in the P-type substrate PSUB.

[0117] Although not shown, the first gate control transistor GC1, the first charge transfer transistor CT1, and the second body control transistor BC2 included in a boost pump or a buck pump as a charge pump may be formed in a triple-well structure similar to the first body control transistor BC1. That is, the NMOS transistor of each of the boost pump or the buck pump of the charge pump may be formed in a P+ well having the same triple-well structure.

[0118] Although not shown, the first gate control transistor GC1, the first charge transfer transistor CT1, the first body control transistor BC1 and the second body control transistor BC2, the second charge transfer transistor CT2, the second gate control transistor GC2, and the third body control transistor BC3 and the fourth body control transistor BC4 may be implemented as p-type metal oxide semiconductor (PMOS) transistors. In this case, Fig.10In the triple-well structure, the P-type substrate, N+ well and P+ well can be replaced by N-type substrate, P+ well and N+ well, respectively. The n+ source S, n+ drain D, and p+ body B1 formed in the P+ well can be replaced by p+ drain, p+ source and n+ body, respectively. The n+ body B2 formed in the N+ well can be replaced by p+ body, and the p+ body B3 formed in the N-type substrate can be replaced by n+ body.

[0119] Fig.11 is a block diagram illustrating a flash memory device according to example embodiments.

[0120] Reference Fig.11 , the flash memory device 600 may include a row decoder 60, a row driver 62, a driving voltage generator 64, a control logic unit 66, a flash memory cell array 68, a column decoder 70, and a page buffer 72. The row driver 62 may include an erase line driver 62-2, a source line driver 62-4, a coupling line driver 62-6, and a word line driver 62-8. The driving voltage generator 64 may include a first high voltage generator 64-2, a second high voltage generator 64-4, and a voltage generator 64-6.

[0121] The following will describe Fig.11 Functionality of the blocks shown.

[0122] The row decoder 60 may decode the row address RA to generate a row selection signal rl for selecting a row line. Although not shown, the row line may include a word line, a coupling line, a source line, and an erase line.

[0123] The erase line driver 62-2 may generate an erase line selection signal e1 in response to a row selection signal r1.

[0124] The source line driver 62-4 may generate a source line selection signal sl in response to a row selection signal r1.

[0125] The coupling line driver 62-6 may generate a coupling line selection signal cl in response to a row selection signal r1.

[0126] The word line driver 62-8 may generate a word line selection signal wl in response to a row selection signal r1.

[0127] The first high voltage generator 64-2 may generate the intermediate high voltage VM by boosting the power supply voltage VDD in response to the program command PGM, and may generate the first positive high voltage VP1 by boosting the power supply voltage VDD in response to the erase command ERS. The first high voltage generator 64-2 may be implemented as Figure 7 For example, the first high voltage generator 64-2 may respond to the program command PGM (when Figure 7The mode signal M shown in FIG. 1 is at a “low” level) generates an intermediate high voltage VM of 5V, and can respond to an erase command ERS (when Figure 7 When the mode signal M is at a “high” level, a first positive high voltage VP1 of 10V is generated.

[0128] The second high voltage generator 64-4 may generate a second positive high voltage VP2 by boosting the power supply voltage VDD in response to the program command PGM, and may generate a negative high voltage VN by boosting the ground voltage VSS in response to the erase command ERS. Fig. 9 The mode signal M is at a "low" level) generates a second positive high voltage VP2, and can respond to the erase command ERS (when Fig. 9 When the mode signal M is at a "high" level, a negative high voltage VN of -8V is generated.

[0129] The voltage generator 64 - 6 may receive the power supply voltage VDD and generate the word line selection voltage VH in response to the program command PGM, and may receive and generate the ground voltage VSS in response to the erase command ERS.

[0130] The control logic unit 66 may generate a program command PGM and an erase command ERS by decoding the command signal COM. Although not shown, the control logic unit 66 may also generate a read command by decoding the command signal COM. In addition, the control logic unit 66 may receive an address signal ADD and generate a row address RA and a column address CA.

[0131] The flash memory cell array 68 can program data in memory cells selected by the word line selection signal wl, the coupling line selection signal cl, the source line selection signal sl, the erase line selection signal el and the column selection signal csl in response to the program command PGM, and can erase the programmed data in all memory cells in response to the erase command ERS.

[0132] The column decoder 70 may generate a column selection signal csl by decoding the column address CA.

[0133] The page buffer 72 may temporarily store data in response to a program command PGM, and may transmit the data DATA via a data line DL to a selected memory cell of the flash memory cell array 68. In addition, the page buffer 72 may temporarily store data output from a selected memory cell of the flash memory cell array 68 via a data line DL, and may output the data DATA in response to a read command (not shown).

[0134] Fig.12 is a diagram showing a method according to an example embodiment Fig.11FIG. 6 is a circuit diagram of a structure of a flash memory cell array 68. The flash memory cell array 68 may include (x×y) unit memory cells UM11 to UMxy arranged in a matrix form. Each of the unit memory cells UM11 to UMxy may include two memory cells.

[0135] Reference Fig.12 , each of the unit memory cells UM11 to UMxy may include a first word gate transistor WT1, a first coupling gate transistor CT1, an erase gate transistor ET, a second coupling gate transistor CT2, and a second word gate transistor WT2. The first word gate transistor WT1 may include a gate connected to the corresponding word line WL1, WL2, ... or WLx and a drain connected to the corresponding bit line BL1, BL2, ... or BLy. The second word gate transistor WT2 may include a gate connected to the corresponding word line WL1', WL2', ... or WLx' and a drain connected to the corresponding bit line BL1, BL2, ... or BLy. The erase gate transistor ET may include a gate connected to the corresponding erase line EG1, EG2, ... or EGx and a source and a drain connected to the corresponding source line SL1, SL2, ... or SLx. The first coupling gate transistor CT1 may be a floating gate transistor connected between the corresponding first word gate transistor WT1 and the corresponding source line SL1, SL2, ... or SLx. The second coupling-gate transistor CT2 may be a floating-gate transistor connected between the corresponding second word-gate transistor WT2 and the corresponding source line SL1 , SL2 , . . . , or SLx.

[0136] The following will refer to Fig.11 and Fig.12 A programming operation of a flash memory device is described.

[0137] The word line WL1, the coupling line CG1, the erase line EG1, and the source line SL1 may be selected in response to the row selection signal rl. In this case, a word line selection voltage VH (e.g., 0.7V) may be applied to the word line WL1 in response to the program command PGM, a second positive high voltage VP2 (e.g., 10V) may be applied to the coupling line CL1, and an intermediate high voltage VM (e.g., 5V) may be applied to the erase line EG1 and the source line SL1. In response to the column selection signal csl, j bit lines BL1 to BL16 (e.g., j represents a number less than y and may be 16 (i.e., one word)) may be selected, and a specific voltage (e.g., 0.3V) may be applied via the bit lines BL1 to BL16. In this case, a specific voltage (e.g., 0V) may be provided to unselected word lines, coupling lines, erase lines, and source lines. In this case, a programming operation may be performed in the floating gate of the first coupling gate transistor CT1 of the unit memory cells UM11 to UM16 by hot carrier injection (HCI). That is, data (eg, “0”) may be programmed in the first coupling gate transistors CT1 of the unit memory cells UM11 to UM16 .

[0138] The following will refer to Fig.11 and Fig.12 An erase operation of a flash memory device is described.

[0139] A ground voltage (0V) may be applied to the word lines WL1 to WLx and WL1' to WLx' and the source lines SL1 to SLx, a negative high voltage VN (e.g., -8V) may be applied to the coupling lines CG1 to CGx and CG1' to CGx', and a first positive high voltage VP1 (e.g., 10V) may be applied to the erase lines EG1 to EGx. A ground voltage (0V) may be applied to the bit lines BL1 to Bly. In this case, electrons in the floating gates of the first coupling gate transistors CT1 and the second coupling gate transistors CT2 of all unit memory cells UM11 to UMxy may be lost due to the Fowler-Nordheim tunneling effect. Therefore, data of all unit memory cells UM11 to UMxy may be erased. That is, data of the first coupling gate transistors CT1 and the second coupling gate transistors CT2 of all unit memory cells UM11 to UMxy may be erased (i.e., data (e.g., "1") may be programmed therein).

[0140] As described above, for programming operations and erasing operations, in a flash memory device according to an embodiment of the inventive concept, two first high voltage generators 64-2 and second high voltage generators 64-4 may be used to generate an intermediate high voltage VM, a first positive high voltage VP1 and a second positive high voltage VP2, and a negative high voltage VN.

[0141] The first high voltage generator or the second high voltage generator according to the embodiment of the present invention can be applied to other types of flash memory devices. The first high voltage generator or the second high voltage generator can be applied not only to flash memory devices, but also to other devices or electronic devices that use different positive high voltages or use positive high voltages or negative high voltages according to operation modes.

[0142] According to an exemplary embodiment of the inventive concept, the high voltage generator can generate different positive (negative) high voltages or generate a positive high voltage or a negative high voltage according to a mode. In this case, the charge pump of the high voltage generator can discharge and charge the charge of the gate of the charge transfer transistor after the boost operation or the buck operation, thereby accurately performing the buck operation after the boost operation or performing the boost operation after the buck operation.

[0143] According to example embodiments of the inventive concepts, a flash memory device can generate different positive high voltages or generate a positive high voltage and a negative high voltage in a program operation and an erase operation by using one high voltage generator, thereby simplifying a circuit structure.

[0144] Although the embodiments of the present invention have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the present invention and without changing its main features. Therefore, the above embodiments should be considered only as descriptive meanings, and not for the purpose of limitation.

Claims

1. A charge pump, comprising: a first pumping capacitor configured to pump a voltage of the first node in response to a first clock signal; a gate pumping capacitor configured to pump a second voltage of the second node in response to a second clock signal; a charge transfer transistor including a first source connected to one of a first node and a third node, a first gate connected to the second node, a first drain connected to the other of the first node and the third node, and a first body connected to a fourth node; a gate-controlled transistor including a second source connected to the one of the first node and a third node, a second gate connected to the other of the first node and the third node, a second drain connected to the second node, and a second body connected to the fourth node; a gate discharge or charge unit configured to discharge or charge the electric charge of the second node and including at least one gate discharge or charge transistor including a third gate and a third source connected to the second node, a third drain connected to the other of the first node and the third node, and a third body connected to the fourth node, and A first body control transistor includes a fourth source connected to the one of the first node and the third node, a fourth gate connected to the other of the first node and the third node, and a fourth drain and a fourth body connected to the fourth node.

2. The charge pump according to claim 1 , further comprising: A second body control transistor includes a fifth source connected to the other of the first node and the third node, a fifth gate connected to the one of the first node and the third node, and a fifth drain and a fifth body connected to the fourth node.

3. The charge pump according to claim 2, wherein: Each of the gate control transistor, the charge transfer transistor, the first body control transistor, the second body control transistor, and the at least one gate discharge or charge transistor has a triple well structure.

4. The charge pump according to claim 1 , further comprising a second pumping capacitor configured to pump a voltage of the third node in response to a third clock signal, in, In a boost operation, a boosted voltage higher than a voltage of the one of the first node and the third node is output to the other of the first node and the third node, and In the step-down operation, a step-down voltage lower than a voltage of the other of the first node and the third node is output to the one of the first node and the third node.

5. The charge pump according to claim 4, wherein: In the boost operation: In a first period, when the first clock signal is at a low level, the second clock signal is at a high level; and In the second period, when the second clock signal is at a low level, the first clock signal is at a high level, and Wherein, in the step-down operation: In the first period, when the third clock signal is at a high level, the second clock signal is at a high level; and In the second period, when the third clock signal is at a low level, the second clock signal is at a low level.

6. A high voltage generator, comprising: a first predetermined number of step-up or step-down pumps configured to output a positive or negative intermediate high voltage via a first output terminal by pumping an input voltage applied via an input terminal, the first predetermined number of step-up or step-down pumps being connected in series between the input terminal and the first output terminal; as well as a second predetermined number of step-up or step-down pumps configured to output a positive or negative final high voltage via a second output terminal by pumping the positive or negative intermediate high voltage, the second predetermined number of step-up or step-down pumps being connected in series between the first output terminal and the second output terminal; and Wherein, each of the first predetermined number of boost or depressurization pumps and the second predetermined number of boost or depressurization pumps comprises: a pumping capacitor configured to pump a first voltage of the first node in response to the first clock signal or the third clock signal; a gate pumping capacitor configured to pump a second voltage of the second node in response to the second clock signal or the fourth clock signal; a charge transfer transistor including a first source connected to one of the first node and a third node, a first gate connected to the second node, a first drain connected to the other of the first node and the third node, and a first body connected to a fourth node; a gate-controlled transistor including a second source connected to the one of the first node and the third node, a second gate connected to the other of the first node and the third node, a second drain connected to the second node, and a second body connected to the fourth node; a gate discharge or charge unit configured to discharge or charge the electric charge of the second node and including at least one gate discharge or charge transistor including a third gate and a third source connected to the second node, a third drain connected to the other of the first node and the third node, and a third body connected to the fourth node, and A first body control transistor includes a fourth source connected to the one of the first node and the third node, a fourth gate connected to the other of the first node and the third node, and a fourth drain and a fourth body connected to the fourth node.

7. The high voltage generator according to claim 6, wherein: Each of the first predetermined number of boost or buck pumps and the second predetermined number of boost or buck pumps also includes: a second body control transistor, which includes a fifth source connected to the other of the first node and the third node, a fifth gate connected to the one of the first node and the third node, and a fifth drain and a fifth body connected to the fourth node.

8. The high voltage generator according to claim 7, wherein: The gate control transistor, the charge transfer transistor, the first body control transistor, the second body control transistor and the at least one gate discharge or charge transistor included in each of the first predetermined number of boost or buck pumps and the second predetermined number of boost or buck pumps are formed according to a triple well structure.

9. The high voltage generator according to claim 6, wherein: The pumping capacitor of each of the odd-numbered boost or buck pumps in the first predetermined number of boost or buck pumps and the second predetermined number of boost or buck pumps is further configured to pump a first voltage of the first node in response to the first clock signal. wherein the gate pump capacitor of each of the odd-numbered step-up or step-down pumps is further configured to pump the second voltage of the second node in response to the second clock signal, wherein the pumping capacitor of each of the even-numbered boost or buck pumps in the first predetermined number of boost or buck pumps is further configured to pump the first voltage of the first node in response to the third clock signal, and The gate pumping capacitor of each of the odd-numbered step-up or step-down pumps is further configured to pump the second voltage of the second node in response to the fourth clock signal.

10. The high voltage generator according to claim 6, further comprising: a clock generator configured to generate the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal in response to a first enable signal or a second enable signal during a first step-up or step-down operation or a second step-up or step-down operation; a first regulator configured to generate a first divided voltage by dividing the positive or negative intermediate high voltage of the first output terminal in response to a first regulator enable signal during the first step-up or step-down operation; a first comparator configured to generate the first enable signal by comparing the first divided voltage with a first reference voltage; a first high voltage discharging or charging unit configured to discharge or charge the positive or negative intermediate high voltage during a discharging or charging operation after the first voltage step-up or step-down operation; a second regulator configured to generate a second divided voltage by dividing the positive or negative final high voltage of the second output terminal in response to a second regulator enable signal during the second step-up or step-down operation; a second comparator configured to generate the second enable signal by comparing the second divided voltage with a second reference voltage; as well as A second high voltage discharging or charging unit is configured to discharge or charge the positive or negative final high voltage during a discharging or charging operation after the second voltage step-up or step-down operation.

11. A high voltage generator, comprising: A predetermined number of pressure-increasing and pressure-reducing pumps configured to: By boosting the input voltage applied through the input terminal, a positive high voltage is output through the output terminal; as well as By stepping down the output voltage applied through the output terminal, a negative high voltage is output through the input terminal. wherein the predetermined number of boost and buck pumps are connected in series between the input terminal and the output terminal, Wherein, each of the predetermined number of boost and depressurization pumps comprises: a first pumping capacitor configured to pump a first voltage of a first node in response to a first clock signal; a second pumping capacitor configured to pump a third voltage of a third node in response to a third clock signal; a gate pumping capacitor configured to pump a second voltage of the second node in response to the second clock signal or the fourth clock signal; a charge transfer transistor including a first source connected to the third node, a first gate connected to the second node, and a first drain connected to the first node; a gate control transistor including a second source connected to the third node, a second gate connected to the first node, and a second drain connected to the second node; and a gate discharging or charging unit configured to discharge or charge the electric charge of the second node; a clock generator configured to generate the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal in response to a first enable signal during a boost operation; a first regulator configured to generate a first divided voltage by dividing the positive high voltage of the output terminal in response to a first regulator enable signal during the boost operation; a first comparator configured to generate the first enable signal by comparing the first divided voltage with a first reference voltage; and A high voltage discharge unit is configured to discharge the positive high voltage during a discharge operation after the boosting operation.

12. The high voltage generator according to claim 11, wherein: The gate discharge or charge unit includes at least one gate discharge or charge transistor including a third gate and a third source connected to the second node and a third drain connected to the first node.

13. The high voltage generator according to claim 12, wherein: The charge transfer transistor includes a first body connected to a fourth node, wherein the gate control transistor comprises a second body connected to the fourth node, wherein the at least one gate discharge or charge transistor comprises a third body connected to the fourth node, and Wherein, each of the predetermined number of boost and depressurization pumps further comprises: a first body control transistor including a fourth source connected to the third node, a fourth gate connected to the first node, and a fourth drain and a fourth body connected to the fourth node; and A second body control transistor includes a fifth source connected to the first node, a fifth gate connected to the third node, and a fifth drain and a fifth body connected to the fourth node.

14. The high voltage generator according to claim 13, wherein: The gate control transistor, the charge transfer transistor, the first body control transistor, the second body control transistor, and the at least one gate discharge or charge transistor in each of the predetermined number of step-up and step-down pumps are formed in a triple-well structure.

15. The high voltage generator according to claim 11, wherein: The first pumping capacitor of each of the odd-numbered boost and buck pumps of the predetermined number of boost and buck pumps is further configured to pump a first voltage of the first node in response to the first clock signal. wherein the gate pump capacitor of each of the odd-numbered step-up and step-down pumps is further configured to pump the second voltage of the second node in response to the second clock signal, wherein the first pumping capacitor of each of the even-numbered boost and buck pumps of the predetermined number of boost and buck pumps is further configured to pump the first voltage of the first node in response to the third clock signal, and The gate pumping capacitor of each of the odd-numbered step-up and step-down pumps is further configured to pump the second voltage of the second node in response to the fourth clock signal.

16. The high voltage generator according to claim 11, wherein: The clock generator is further configured to: generate the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal in response to a second enable signal during a step-down operation; and Wherein, the high voltage generator further comprises: a second regulator configured to generate a second divided voltage by dividing the negative high voltage of the input terminal in response to a second regulator enable signal during the step-down operation; a second comparator configured to generate the second enable signal by comparing the second divided voltage with a second reference voltage; and A high voltage charging unit is configured to charge the negative high voltage during a charging operation after the voltage step-down operation.

17. A flash memory device comprising: a flash memory cell array comprising a plurality of flash memory cells; A first high voltage generator, comprising a first charge pump, wherein the first charge pump comprises a first predetermined number of first boost pumps connected in series, and the first high voltage generator is configured as follows: During a programming operation, outputting an intermediate high voltage through a first output terminal by boosting an input voltage applied through a first input terminal; as well as During an erase operation, outputting a first positive high voltage through a second output terminal by boosting an input voltage applied through the first input terminal; A second high voltage generator, comprising a second charge pump, the second charge pump comprising a second predetermined number of second step-up and step-down pumps connected in series, the second high voltage generator being configured as follows: During the programming operation, outputting a second positive high voltage through a third output terminal by boosting an input voltage applied through the second input terminal; and During the erase operation, a negative high voltage is output through the second input terminal by stepping down an output voltage applied through the third output terminal; and a row driver configured to: applying the intermediate high voltage and the second positive high voltage to the flash memory cell array during the programming operation; as well as During the erase operation, the first positive high voltage and the negative high voltage are applied to the flash memory cell array.

18. The flash memory device according to claim 17, wherein: The flash memory cell array includes a plurality of unit memory cells, and Wherein, each of the plurality of unit memory cells comprises: a first word-gate transistor including a gate connected to a corresponding first word line and a drain connected to a corresponding bit line; a second word-gate transistor including a gate connected to a corresponding second word line and a drain connected to the corresponding bit line; an erase gate transistor including a gate connected to a corresponding erase line and a drain and a source connected to a corresponding source line; a first coupling-gate transistor including a gate connected to a corresponding first coupling line, a source connected to a source of the first word-gate transistor, and a drain connected to a corresponding source line; and A second coupling-gate transistor includes a gate connected to a corresponding second coupling line, a source connected to a source of the second word-gate transistor, and a drain connected to the corresponding source line.

19. The flash memory device according to claim 17, wherein: Each of the first predetermined number of first booster pumps comprises: a pumping capacitor configured to pump a first voltage of the first node in response to the first clock signal or the third clock signal; a gate pumping capacitor configured to pump a second voltage of the second node in response to the second clock signal or the fourth clock signal; a charge transfer transistor including a first source connected to a third node, a first gate connected to the second node, and a first drain connected to the first node; a gate control transistor including a second source connected to the third node, a second gate connected to the first node, and a second drain connected to the second node; and A gate discharger is configured to discharge the charge of the second node.

20. The flash memory device according to claim 19, wherein: The gate discharger includes at least one gate discharge transistor including a third gate and a third source connected to the second node and a third drain connected to the first node.

21. The flash memory device according to claim 20, wherein: The charge transfer transistor includes a first body connected to a fourth node, wherein the gate control transistor comprises a second body connected to the fourth node, wherein the at least one gate discharge transistor comprises a third body connected to the fourth node, and Wherein, each of the first predetermined number of first booster pumps further comprises: a first body control transistor including a fourth source connected to the third node, a fourth gate connected to the first node, and a fourth drain and a fourth body connected to the fourth node; and A second body control transistor includes a fifth source connected to the first node, a fifth gate connected to the third node, and a fifth drain and a fifth body connected to the fourth node.

22. The flash memory device according to claim 21, wherein: The gate control transistor, the charge transfer transistor, the first body control transistor, the second body control transistor, and the at least one gate discharge transistor included in each of the first predetermined number of first boost pumps are formed in a triple well structure.

23. The flash memory device according to claim 17, wherein: Each of the second predetermined number of second boost and depressurization pumps comprises: a first pumping capacitor configured to pump a first voltage of a first node in response to a first clock signal; a second pumping capacitor configured to pump a third voltage of a third node in response to a third clock signal; a gate pumping capacitor configured to pump a second voltage of the second node in response to the second clock signal or the fourth clock signal; a charge transfer transistor including a first source connected to the third node, a first gate connected to the second node, and a first drain connected to the first node; a gate control transistor including a second source connected to the third node, a second gate connected to the first node, and a second drain connected to the second node; and A gate discharging or charging unit is configured to discharge or charge the electric charge of the second node.

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