Loss of lock detector

Abstract

The present application discloses a loss-of-lock detector. A loss-of-lock detection circuit includes a detection circuit (201) and a pulse accumulation circuit (220). The detection circuit includes a first flip-flop (202), a second flip-flop (204) and a third flip-flop (218). The first flip-flop (208) is configured to synchronize a data stream (110) to a first edge of a clock signal (112). The second flip-flop (204) is configured to synchronize a data stream (110) to a second edge of the clock signal (112). The third flip-flop (218) is clocked by the data stream (110) and is configured to store a combined output of the first flip-flop (202) and the second flip-flop (202) at an edge of the data stream (110). The pulse accumulation circuit (220) is coupled to the detection circuit (201). The pulse accumulation circuit (220) is configured to collect pulses generated by the third flip-flop (218).

Description

Background Art

[0001] In many communication systems, data is sent from one device to another without an accompanying clock signal. During transmission, the signal carrying the data may become jittery and difficult to decipher and process by the receiving device. Therefore, many systems utilize clock and data recovery (CDR) circuits to retime the incoming signal and send the retimed signal to the receiving device. This requires the CDR circuit to generate a clock that is locked to the frequency of the transmitted data. In many systems, the CDR circuit detects the frequency of the incoming signal and phase-aligns the clock signal to the incoming signal. The incoming signal is then retimed with the clean clock that the CDR circuit has generated. The retimed signal can then be output to the receiving device for further processing. Summary of the invention

[0002] A loss-of-lock detection circuit for use with a half-rate clock and data recovery circuit is disclosed herein. In one example, the loss-of-lock detection circuit includes a detection circuit and a pulse accumulation circuit. The detection circuit includes a first flip-flop, a second flip-flop, and a third flip-flop. The first flip-flop is configured to synchronize a data stream to a first edge of a clock signal. The second flip-flop is configured to synchronize a data stream to a second edge of the clock signal. The third flip-flop is clocked / controlled by the data stream and is configured to store a combined output of the first flip-flop and the second flip-flop at an edge of the data stream. The pulse accumulation circuit is coupled to the detection circuit. The pulse accumulation circuit is configured to collect pulses generated by the third flip-flop.

[0003] In another example, a method for detecting loss of lock includes synchronizing a data stream to a rising edge of a clock to produce a first half-rate data stream, and synchronizing the data stream to a falling edge of a clock to produce a second half-rate data stream. The first half-rate data stream and the second half-rate data stream are combined. The combined first half-rate data stream and the second half-rate data stream are clocked into a flip-flop. Output pulses of the flip-flop are accumulated to detect loss of lock.

[0004] In another example, a lock-out detection circuit includes a first trigger, a second trigger, an XOR gate, and a third trigger. The first trigger includes a data input terminal and an output terminal. The second trigger includes a data input terminal and an output terminal. The XOR gate includes a first input, a second input, and an output terminal. The first input is coupled to the output terminal of the first trigger. The second input is coupled to the output terminal of the second trigger. The third trigger includes a data input terminal, a clock input terminal, and an output terminal. The data input terminal of the third trigger is coupled to the output of the XOR gate. The clock input terminal of the third trigger is coupled to the data input terminal of the first trigger and the data input terminal of the second trigger. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] For a detailed description of various examples, reference will now be made to the accompanying drawings, in which:

[0006] Figure 1 A block diagram showing a half-rate clock and data recovery (CDR) system according to the present disclosure;

[0007] Figure 2 A schematic diagram showing an example of a loss-of-lock detection circuit applicable to a half-rate CDR circuit according to the present disclosure;

[0008] Figure 3 and Figure 4 An example of a pulse accumulation circuit applicable to an out-of-lock detection circuit according to the present invention is shown;

[0009] Figure 5 and Figure 6 An example of a timing diagram illustrating the operation of the loss-of-lock detection circuit according to the present invention; and

[0010] Figure 7 A flow chart showing an example of a method for detecting loss of lock in a half-rate CDR circuit according to the present disclosure. DETAILED DESCRIPTION

[0011] Certain terms are used throughout the specification and claims to refer to specific system components. As will be appreciated by those skilled in the art, different parties may refer to components by different names. This document is not intended to distinguish between components that have different names but the same function. In this disclosure and claims, the terms "including and comprising" are used in an open-ended manner and should therefore be interpreted to mean "including but not limited to...". In addition, the term "coupled" is intended to mean an indirect or direct wired or wireless connection. Thus, if a first device is coupled to a second device, the connection may be through a direct connection or through an indirect connection via other devices and connections. The statement "based on" is intended to mean "based at least in part on". Thus, if X is based on Y, then X can be a function of Y and any number of other factors.

[0012] A clock and data recovery (CDR) circuit uses a phase and frequency detector to recover a frequency and phase aligned clock to a clock embedded in received data. A frequency acquisition loop includes a frequency detector that acquires a frequency close to the frequency of the embedded clock, and a phase tracking loop includes a phase detector that phase aligns the recovered clock to the frequency aligned embedded clock. In some embodiments, frequency and phase detection are performed in a single loop. The recovered clock is used to generate recovered data from the received data.

[0013] In some applications, the CDR circuit includes a reference clock in the frequency acquisition loop, while for other applications, the CDR circuit is reference-less and only the location of the data edges is known. Particularly (but not exclusively) for reference-less CDR circuits, a mechanism for detecting an out-of-lock condition (including a false lock) is advantageous. For example, in a CDR circuit, the frequency detector may be turned off after initial frequency acquisition to save power. An out-of-lock detection circuit may detect / identify an out-of-lock condition and enable the CDR to take corrective action, which may include powering up the frequency detector and restarting frequency acquisition.

[0014] Loss of lock detection circuits designed for full-rate CDR circuits are not suitable for use with half-rate CDR circuits. Loss of lock detection circuits disclosed herein detect loss of lock and false lock in half-rate CDR circuits. Implementations of the disclosed loss of lock detection circuits determine whether half-rate retimed data includes transitions that correspond to transitions in the original data. Missing transitions in the half-rate retimed data may be due to the clock frequency being less than or greater than half the data rate, resulting in missing transitions due to undersampling or sample / hold time violations. The disclosed loss of lock detection circuits are applicable to a variety of half-rate phase / frequency detectors and do not require the use of a reference clock.

[0015] Figure 1 A block diagram of a half-rate CDR system 100 according to the present disclosure is shown. The half-rate CDR system 100 includes a CDR circuit 102 and a lock-out detection circuit 108. The CDR circuit 102 recovers a clock signal from received data and retimes the received data using the recovered clock signal. The CDR circuit 102 includes a data recovery circuit 104 and a clock recovery circuit 106. The clock recovery circuit 106 may include a frequency detection circuit and a phase detection circuit to generate a recovered clock signal 112 based on the transition of the original data stream 110. The frequency and phase of the recovered clock signal 112 align the recovered clock signal 112 with the bit timing of the original data stream 110. The data recovery circuit 104 applies the recovered clock signal 112 to retime (i.e., reclock) the original data stream 110. The data recovery circuit 104 generates two retimed data streams 114 and 116 from the original data stream 110. Each of the retimed data streams 114 and 116 is half the bit rate of the original data stream 110. For example, the retimed data stream 114 includes only the odd bits of the original data stream 110 , and the retimed data stream 114 includes only the even bits of the original data stream 110 .

[0016] The loss-of-lock detection circuit 108 monitors the relationship between the recovered clock signal 112 and the original data stream 110 to determine whether the recovered clock signal 112 is locked to the original data stream 110. If the loss-of-lock detection circuit 108 determines that the recovered clock signal 112 is not locked to the original data stream 110, the loss-of-lock detection circuit 108 generates a loss-of-lock indicator 118. Upon receiving the loss-of-lock indicator 118, the clock recovery circuit 106 may activate a frequency detection circuit and / or a phase detection circuit to resynchronize the recovered clock signal 112 to the original data stream 110.

[0017] Figure 2 A schematic diagram of an example of a loss-of-lock detection circuit 200 suitable for use in a half-rate CDR system 100 is shown. The loss-of-lock detection circuit 200 is an embodiment of 108. The loss-of-lock detection circuit 200 includes a detection circuit 201 and a pulse accumulation circuit 220 coupled to the detection circuit 201. The detection circuit 201 includes a synchronization flip-flop 202, a synchronization flip-flop 204, an XOR gate 214, a delay circuit 216, and a pulse generation flip-flop 218. The original data stream 110 received from the transmitting data source is clocked into the synchronization flip-flop 202 and the synchronization flip-flop 204 using the recovered clock signal 112 derived from the original data stream 110 by the half-rate CDR circuit 102. In some embodiments, the synchronization flip-flop 202 and the synchronization flip-flop 204 can be included in the half-rate CDR circuit 102 (e.g., in the data recovery circuit 104).

[0018] The synchronization flip-flop 202 samples the original data stream 110 at the rising edge of the recovered clock signal 112 to generate a half-rate data stream 210 containing every other data bit (i.e., odd data bits) of the original data stream 110. The synchronization flip-flop 202 includes a data input terminal 236, a clock input terminal 238, and an output terminal 252. The data input terminal 236 receives the original data stream 110. The clock input terminal 238 receives the recovered clock signal 112. The synchronization flip-flop 204 samples the original data stream 110 at the falling edge of the recovered clock signal 112 to generate a half-rate data stream 212 containing every other data bit (i.e., even data bits) of the original data stream 110. The synchronization flip-flop 204 includes a data input terminal 240, a clock input terminal 242, and an output terminal 254. The data input terminal 240 receives the original data stream 110 and is coupled to the data input terminal 236 of the flip-flop 202. The clock input terminal 242 receives the recovered clock signal 112.

[0019] XNOR gate 214 combines half-rate data stream 210 and half-rate data stream 212 to generate a signal indicating whether half-rate data stream 210 and half-rate data stream 212 are the same or different logic values ​​at any time. XNOR gate 214 includes input 248, input 250, and output 246. Input 248 is coupled to output terminal 252 of synchronization flip-flop 202. Input 250 is coupled to output terminal 254 of synchronization flip-flop 204. In some embodiments, an XOR circuit or other circuit that compares two logic level signals can be used instead of XNOR gate 214.

[0020] The delay circuit 216 includes circuitry that delays the original data stream 110 by approximately one bit time of the original data stream 110 to produce a delayed original data stream 224. For example, the delay circuit 216 may include one or more buffer circuits (inverting or non-inverting drivers) through which the original data stream 110 passes to delay the original data stream 110, wherein the drivers and their number are selected to produce a delay of approximately one bit time. The bit time is the shortest time between transitions in the original data 110. For example, in the case of non-return-to-zero data, the bit time is the inverse of the bit transfer rate (e.g., 1 nanosecond bit time for a 1 gigabit per second bit transfer rate). The delay circuit 216 includes an input terminal 230 and an output terminal 232. The input terminal 230 is coupled to an input terminal 236 of the synchronization flip-flop 202 and an input terminal 240 of the synchronization flip-flop 204.

[0021] The pulse generation flip-flop 218 samples the signal 222 on a transition (e.g., a rising edge) of the delayed original data stream 224. Clocking the signal 222 with the delayed original data stream 224 produces a signal 226 indicating that the synchronization flip-flop 202 or the synchronization flip-flop 204 did not transition in response to a transition in the original data stream 110. Missed transitions in the half-rate data stream 210 or the half-rate data stream 212 may be caused by undersampling (i.e., the rate of the recovered clock signal 112 is lower than the rate of the original data stream 110) or setup or hold time violations in the synchronization flip-flop 202 or the synchronization flip-flop 204, which may be caused by an incorrect rate of the recovered clock signal 112. The signal 226 is provided to the pulse accumulation circuit 220. The pulse generation flip-flop 218 includes a data input terminal 244, a clock input terminal 234, and an output terminal 228. The data input terminal 244 is coupled to the output 246 of the exclusive-NOR gate 214. The clock input terminal 234 is coupled to the output terminal 232 of the delay circuit 216.

[0022] In some embodiments of the out-of-lock detection circuit 200, the pulse generation flip-flop 218 includes an edge-triggered set or reset input. In such embodiments, an inverted version of the delayed original data stream 224 can be provided to the edge-triggered set or reset input so that the pulse generation flip-flop 218 is set or reset at each falling edge of the delayed original data stream 224. Thus, the pulse generation flip-flop 218 starts an output pulse at a rising edge of the delayed original data stream 224 and terminates an output pulse at a subsequent falling edge of the delayed original data stream 224.

[0023] The pulse accumulation circuit 220 is coupled to the output terminal of the pulse generation flip-flop 218. The pulse accumulation circuit 220 collects the pulses generated by the pulse generation flip-flop 218 and generates the out-of-lock indicator 118 based on the signal 226. Some embodiments of the pulse accumulation circuit 220 generate the out-of-lock indicator 118 based on generating a predetermined number of pulses on the signal 226 in a fixed time interval. Figure 3 and Figure 4 An example of an implementation of the pulse accumulation circuit 220 is shown. Figure 3 , a digital counter 300 implements the pulse accumulation circuit 220. A clock input of the digital counter is coupled to an output terminal of a pulse generating flip-flop. The pulse provided on the signal 226 increments or decrements the digital counter 300, and when the digital counter 300 increments or decrements to a predetermined value, the digital counter 300 generates an output signal indicating that the recovered clock signal 112 has lost lock with the original data stream 110. In some embodiments, the digital counter 300 may be periodically set to a predetermined value (e.g., set to zero) to initialize the digital counter 300 for loss of lock detection.

[0024] Figure 4Pulse accumulation circuit 400 is shown, which is another embodiment of pulse accumulation circuit 220. Pulse accumulation circuit 400 includes comparator 406 and filter circuit 412. Filter circuit 412 is coupled to the output terminal of pulse generation trigger 218. Filter circuit 412 includes resistor 402 and capacitor 404. A first terminal 414 of capacitor 404 is coupled to the output terminal of pulse generation trigger 218, and a second terminal 420 of capacitor 404 is connected to ground. The pulses on signal 226 charge capacitor 404, so that a voltage 410 across capacitor 404 increases in accordance with the number of pulses on signal 226. Filter circuit 412 is also coupled to comparator 406. A first terminal 414 of capacitor 404 is coupled to an input terminal 422 of comparator 406. Comparator 406 compares voltage 410 with threshold voltage 408. Input terminal 416 of comparator 406 is coupled to threshold voltage source 418 that generates threshold voltage 408. If the voltage 410 exceeds the threshold voltage 408, the comparator 406 drives the out-of-lock indicator 118 to indicate that the recovered clock signal 112 has lost lock with the original data stream 110. Embodiments of the pulse accumulation circuit 400 may also include circuitry to periodically discharge the capacitor 404 to initialize the pulse accumulation circuit 400 for out-of-lock detection. Some embodiments of the pulse accumulator circuit 400 may include a pulse generator 424, such as a monostable multivibrator circuit, that generates pulses of a defined width to charge the capacitor 304 in response to transitions on the signal 226.

[0025] Figure 5 An example timing diagram of the operation of the lock-out detection circuit 200 according to the present disclosure is shown. The original data stream 110 is sampled by the synchronization flip-flop 202 on the rising edge of the recovered clock signal 112 to capture the odd data bits B, D, F, etc. The original data stream 110 is sampled by the synchronization flip-flop 204 on the falling edge of the recovered clock signal 112 to capture the even data bits A, C, E, etc. The XOR gate 214 combines the half-rate data stream 210 and the half-rate data stream 212 to generate high or low going pulses when the half-rate data stream 210 and the half-rate data stream 212 are different. The delayed original data stream 224 clocks the signal 222 into the pulse generation flip-flop 218. If the signal 222 indicates that the half-rate data stream 210 and the half-rate data stream 212 are not different at the edge of the delayed original data, then the half-rate data stream has missed a transition in the original data stream 110, and the signal 226 transitions to indicate the missing transition. Pulse accumulator 220 accumulates transitions or pulses on loss of lock indicator 118 .

[0026] Figure 6 An example timing diagram of the operation of the out-of-lock detection circuit 200 is shown, wherein transitions on the raw data stream 110 are illustrated. Figure 6 , the original data stream 110 is zero during bit A and is 1 thereafter. At 602, the original data stream 110 transitions from low to high. At 604, the synchronization flip-flop 202 samples the original data stream 110, and the half-rate data stream 210 transitions from low to high. The half-rate data stream 212 is low at 604, and the signal 222 output by the XOR gate 214 indicates that the half-rate data stream 210 and the half-rate data stream 212 are different. At 608, the delayed original data stream 224 transitions from low to high and the pulse generation flip-flop 218 samples the signal 222 to set the signal 226. At 610, the signal 226 indicates that in response to the transition in the original data stream 110 at 602, a transition is detected in the half-rate data stream 210 and the half-rate data stream 212. Thus, the timing of the recovered clock signal 112 produces transitions in the half-rate data stream 210 and the half-rate data stream 212 in response to the transition in the original data stream 110 at 602. If there were no transition in the half-rate data stream 210 at 604, the signal 222 would indicate that there is no difference between the half-rate data stream 210 and the half-rate data stream 212, and at 608, the signal 226 would transition to indicate an error.

[0027] Figure 7 A flow chart of an example of a method 700 for detecting loss of lock in a half-rate CDR circuit according to the present disclosure is shown. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. Additionally, some embodiments may only perform some of the actions shown. The operations of the method 700 may be performed by an embodiment of the loss of lock detection circuit 200. In the method 700, the half-rate CDR circuit 102 generates a recovered clock signal 112 based on the original data stream 110.

[0028] In block 702, the original data stream 110 is sampled and synchronized to the rising edge of the recovered clock signal 112 to produce the half-rate data stream 210. For example, the synchronization flip-flop 202 samples the original data stream 110 on the rising edge of the recovered clock signal 112.

[0029] In block 704, the original data stream 110 is sampled on the falling edge of the recovered clock signal 112 and synchronized to the falling edge of the recovered clock signal 112 to produce the half-rate data stream 212. For example, the synchronization flip-flop 204 samples the original data stream 110 on the falling edge of the recovered clock signal 112.

[0030] In block 706, the results of sampling the original data stream 110 on the rising and falling edges of the recovered clock signal 112 are combined. For example, the XOR gate 214 logically combines the half-rate data stream 210 generated by the synchronization flip-flop 202 and the half-rate data stream 212 generated by the synchronization flip-flop 204. Some embodiments may apply an XOR circuit or other comparison logic for combining the results of sampling the original data stream 110 on the rising and falling edges of the recovered clock signal 112.

[0031] In block 708, the original data stream 110 is delayed by approximately one bit time. For example, the delay circuit 216 delays the original data stream 110 by one bit time.

[0032] In block 710 , the combined rising and falling edge sampled recovered clock signal 112 is sampled (ie, clocked) on the rising edge of the delayed original data stream 224 . For example, the pulse generation flip-flop 218 samples the signal 222 on the rising edge of the delayed original data stream 224 .

[0033] In block 712, pulses generated by sampling signal 222 on rising edges of delayed original data stream 224 are accumulated. For example, counter 300 may count rising edges or falling edges occurring in a predetermined time interval, wherein each rising edge or falling edge indicates a transition in original data stream 110 that is not included (i.e., is lost) in half-rate data stream 210 and half-rate data stream 212.

[0034] In block 714, the number of pulses accumulated in block 712 is compared to a threshold. If the number of pulses accumulated in block 712 exceeds the threshold, a loss of lock indication is generated. In response to the loss of lock indication, the CDR circuit 102 may activate circuitry to resynchronize the recovered clock signal 112 to the original data stream 110. For example, the CDR circuit may activate a frequency detector and / or a phase detector to synchronize the recovered clock signal 112 to the original data stream 110.

[0035] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Once the above disclosure is fully understood, many changes and modifications will become apparent to those skilled in the art. It is intended that the appended claims be interpreted as including all such changes and modifications.

Claims

1. A lock-out detection circuit, comprising: A detection circuit comprising: a first flip-flop configured to synchronize a data stream to a first edge of a clock signal; a second flip-flop configured to synchronize the data stream to a second edge of the clock signal; a third flip-flop clocked by the data stream and configured to store a combined output of the first flip-flop and the second flip-flop at an edge of the data stream; and A pulse accumulation circuit is coupled to the detection circuit, and is configured to collect the pulses generated by the third flip-flop. 2 . The out-of-lock detection circuit of claim 1 , further comprising a delay circuit configured to delay the data stream by a bit time of the data stream. 3 . The out-of-lock detection circuit of claim 2 , wherein a clock input of the third flip-flop is coupled to an output of the delay circuit.

4. The lock-out detection circuit of claim 1 , further comprising an XNOR gate coupled to the first flip-flop, the second flip-flop, and the third flip-flop; wherein the XNOR gate is configured to combine an output of the first flip-flop with an output of the second flip-flop to generate an input to the third flip-flop. 5 . The out-of-lock detection circuit of claim 1 , wherein the pulse accumulation circuit comprises a counter configured to count the pulses generated by the third flip-flop. 6 . The out-of-lock detection circuit of claim 1 , wherein the pulse accumulation circuit comprises a capacitor configured to be charged by the pulse generated by the third flip-flop. 7 . The out-of-lock detection circuit of claim 6 , further comprising a comparator configured to compare the voltage across the capacitor with a threshold voltage.

8. A method for detecting loss of lock, comprising: synchronizing the data stream to a rising edge of the clock to generate a first half-rate data stream; synchronizing the data stream to a falling edge of the clock to produce a second half-rate data stream; combining the first half-rate data stream and the second half-rate data stream; clocking the combined first half-rate data stream and the second half-rate data stream into a flip-flop; as well as The output pulses of the flip-flop are accumulated to detect loss of lock.

9. The method of claim 8, further comprising delaying the data stream by a bit time of the data stream to generate a clock for timing the flip-flop.

10. The method according to claim 8, wherein: The combining includes providing the first half-rate data stream and the second half-rate data stream to an XOR circuit. The method of claim 8 , wherein the accumulating comprises counting pulses generated by the flip-flop.

12. The method of claim 11, further comprising identifying a loss of lock by counting a predetermined number of pulses within a predetermined time interval.

13. The method of claim 8, wherein the accumulating comprises charging a capacitor with a pulse generated by the trigger.

14. The method of claim 13, further comprising identifying a loss of lock by comparing a voltage across the capacitor to a threshold voltage.

15. A lock-out detection circuit, comprising: The first trigger comprises: data input terminal; and Output terminals; The second trigger comprises: a data input terminal coupled to the data input of the first flip-flop; and Output terminals; XOR gate, which includes: a first input coupled to the output terminal of the first flip-flop; a second input coupled to the output terminal of the second flip-flop; and Output terminals; The third trigger includes: a data input terminal coupled to the output of the XOR gate; a clock input terminal coupled to the data input terminal of the first flip-flop and the data input terminal of the second flip-flop; and Output terminal.

16. The lock-out detection circuit according to claim 15, further comprising a delay circuit, wherein the delay circuit comprises: an input terminal coupled to the data input terminal of the first flip-flop and the data input terminal of the second flip-flop; as well as An output terminal is coupled to the clock input terminal of the third flip-flop. 17 . The out-of-lock detection circuit of claim 15 , further comprising a counter coupled to the output terminal of the third flip-flop.

18. The out-of-lock detection circuit of claim 15, further comprising a filter circuit coupled to the output terminal of the third flip-flop.

19. The lock-out detection circuit of claim 18, wherein the filter circuit comprises a capacitor, the capacitor comprising: a first terminal coupled to the output terminal of the third flip-flop; as well as A second terminal is coupled to ground.

20. The lock-out detection circuit of claim 19, wherein the filter circuit comprises a comparator, the comparator comprising: a first input terminal coupled to the first terminal of the capacitor; as well as A second input terminal is coupled to a threshold voltage source.

Images