Display driving device for driving a display panel and display device including the same

Abstract

Disclosed are a display driving device for driving a display panel and a display device including the same. The display driving device includes: a first driving circuit configured to output a first image signal; a second driving circuit configured to output a second image signal; a first switching circuit connected to the first driving circuit, and the first switching circuit is configured to send the first image signal to a portion of a first group of sub-pixels arranged in the display panel based on a first switching signal during a first horizontal time interval; and a second switching circuit connected to the second driving circuit, and the second switching circuit is configured to send the second image signal to a portion of a second group of sub-pixels arranged in the display panel adjacent to the first group of sub-pixels based on a second switching signal during the first horizontal time interval, wherein during the first horizontal time interval, a width of the first switching signal and a width of the second switching signal are different from each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0093726 filed on August 10, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0003] The following description relates to a display driver. The following description also relates to a display device including such a display driver. The following description also relates to a display driver and a display device including such a display driver, which can adjust the timing of a signal used in the display driver. Such adjustment can reduce noise. Background Art

[0004] In recent years, as display driving devices or driving circuits process more data, the amount of current used in the driving devices has gradually increased accordingly. In particular, the increased size of display screens and the improved image quality of panels in flat panel display devices have increased the possibility of generating noise due to electromagnetic interference (EMI) in the panels.

[0005] Due to temporary output of various signals for the display driving device, noise associated with EMI may occur in the panel, thereby causing malfunction of the display driving device. Summary of the invention

[0006] This summary is provided to introduce a series of concepts in a simplified form, which are further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0007] In a general aspect, a display driving device for driving a display panel includes: a first driving circuit, which is configured to output a first image signal; a second driving circuit, which is configured to output a second image signal; a first switching circuit, which is connected to the first driving circuit and configured to send the first image signal to a portion of a first group of sub-pixels arranged in the display panel based on a first switching signal during a first horizontal time interval; and a second switching circuit, which is connected to the second driving circuit and configured to send the second image signal to a portion of a second group of sub-pixels arranged in the display panel adjacent to the first group of sub-pixels based on a second switching signal during the first horizontal time interval, wherein during the first horizontal time interval, a width of the first switching signal and a width of the second switching signal are different from each other.

[0008] During the first horizontal time interval, a falling time point of the first switching signal may be earlier than a falling time point of the second switching signal.

[0009] During the first horizontal time interval, a rising time point of the first switching signal may be the same as a rising time point of the second switching signal.

[0010] The first switching circuit can also be configured to send the first image signal to another part of the first group of sub-pixels based on the third switching signal during a second horizontal time interval after the first horizontal time interval, and the second switching circuit can also be configured to send the second image signal to another part of the second group of sub-pixels based on the fourth switching signal during the second horizontal time interval, and during the second horizontal time interval, the width of the third switching signal and the width of the fourth switching signal can be different from each other.

[0011] The first driving circuit may include a first multiplexer configured to output one of the first pixel data and the second pixel data in response to a first selection signal received during a first horizontal time interval, and the second driving circuit may include a second multiplexer configured to output one of the third pixel data and the fourth pixel data in response to a second selection signal received during the first horizontal time interval, and during the first horizontal time interval, a phase of the first selection signal and a phase of the second selection signal may be different from each other, and a width of the first selection signal and a width of the second selection signal may be the same.

[0012] During the first horizontal time interval, a falling time point of the first selection signal may be earlier than a falling time point of the second selection signal.

[0013] The first driving circuit may further include: a first latch configured to output the first pixel data and the second pixel data to the first multiplexer; and a first source amplifier configured to output a first voltage corresponding to one pixel data output from the first multiplexer as a first image signal to the first group of sub-pixels, and the second driving circuit may further include: a second latch configured to output the third pixel data and the fourth pixel data to the second multiplexer; and a second source amplifier configured to output a second voltage corresponding to one pixel data output from the second multiplexer as a second image signal to the second group of sub-pixels.

[0014] The display driving device may further include a logic circuit configured to adjust a width of the first switching signal and a width of the second switching signal.

[0015] The logic circuit may be further configured to sequentially set the width of the first switching signal during each horizontal period to a reference width, a value smaller than the reference width, the reference width, and a value larger than the reference width based on the four-cycle counter.

[0016] In another general aspect, a display device includes a display panel and a display driving device for driving the display panel, wherein the display panel includes sub-pixels arranged in the display panel, wherein the display driving device includes: a first driving circuit configured to output a first image signal; a second driving circuit configured to output a second image signal; a first switching circuit connected to the first driving circuit, and the first switching circuit is configured to send the first image signal to a portion of a first group of sub-pixels arranged in the display panel based on a first switching signal during a first horizontal time interval; and a second switching circuit connected to the second driving circuit, and the second switching circuit is configured to send the second image signal to a portion of a second group of sub-pixels arranged in the display panel adjacent to the first group of sub-pixels based on a second switching signal during the first horizontal time interval, and wherein, during the first horizontal time interval, a width of the first switching signal and a width of the second switching signal are different from each other.

[0017] During the first horizontal time interval, a falling time point of the first switching signal may be earlier than a falling time point of the second switching signal.

[0018] The first driving circuit may include a first multiplexer configured to output one of the first pixel data and the second pixel data in response to a first selection signal received during a first horizontal time interval, and the second driving circuit may include a second multiplexer configured to output one of the third pixel data and the fourth pixel data in response to a second selection signal received during the first horizontal time interval, during which a phase of the first selection signal and a phase of the second selection signal may be different from each other, and a width of the first selection signal and a width of the second selection signal may be the same.

[0019] The display driving device may also include a logic circuit configured to adjust the width of the first switching signal and the width of the second switching signal. The logic circuit may also be configured to: based on a four-cycle counter, set the width of the first switching signal during each horizontal period to a reference width, a value less than the reference width, the reference width, and a value greater than the reference width in sequence.

[0020] In another general aspect, a display driving device for driving a display panel in which a plurality of pixels are arranged in parallel includes: a first driving circuit unit, which is configured to output a first image signal to odd pixels among the plurality of pixels; a second driving circuit unit, which is configured to output a second image signal to even pixels among the plurality of pixels; a first switching circuit unit, which is interposed between the odd pixels and the first driving circuit unit, and the first switching circuit unit is configured to perform a switching operation for connecting the odd pixels and the first driving circuit unit; and a second switching circuit unit, which is interposed between the even pixels and the second driving circuit unit, and the second switching circuit unit is configured to perform a switching operation for connecting the even pixels and the second driving circuit unit, wherein the switching timing of the first switching circuit unit and the switching timing of the second switching circuit unit may be different from each other.

[0021] The display driving device may further include a plurality of first switching circuit units, and the switching timing of each of the plurality of first switching circuit units may be the same, and the display driving device may further include a plurality of second switching circuit units, and the switching timing of each of the plurality of second switching circuit units may be the same.

[0022] The first switching circuit unit can also be configured to: perform a switching operation for connecting odd pixels and the first driving circuit unit in response to a first switching signal, and the second switching circuit unit can also be configured to: perform a switching operation for connecting even pixels and the second driving circuit unit in response to a second switching signal, wherein the width of the first switching signal and the width of the second switching signal can be different from each other.

[0023] The first driving circuit unit may also be configured to perform a data selection operation for selecting a portion of the input pixel data, the second driving circuit unit may also be configured to perform a data selection operation for selecting a portion of the input pixel data, and the data selection timing of the first driving circuit unit and the data selection timing of the second driving circuit unit may be different from each other.

[0024] In another general aspect, a display device includes a display panel and a display driving device for driving the display panel, wherein the display panel includes a plurality of pixels arranged in the display panel, wherein the display driving device includes: a first driving circuit unit, which is configured to output a first image signal to odd pixels among the plurality of pixels; a second driving circuit unit, which is configured to output a second image signal to even pixels among the plurality of pixels; a first switching circuit unit, which is interposed between the odd pixels and the first driving circuit unit, and the first switching circuit unit is configured to perform a switching operation for connecting the odd pixels and the first driving circuit unit; and a second switching circuit unit, which is interposed between the even pixels and the second driving circuit unit, and the second switching circuit unit is configured to perform a switching operation for connecting the even pixels and the second driving circuit unit, wherein the switching timing of the first switching circuit unit and the switching timing of the second switching circuit unit are different from each other.

[0025] The display driving device may further include a plurality of first switching circuit units, and the switching timing of each of the plurality of first switching circuit units may be the same, and the display driving device may further include a plurality of second switching circuit units, and the switching timing of each of the plurality of second switching circuit units may be the same.

[0026] The first switching circuit unit can also be configured to: perform a switching operation for connecting odd pixels and the first driving circuit unit in response to a first switching signal, and the second switching circuit unit can also be configured to: perform a switching operation for connecting even pixels and the second driving circuit unit in response to a second switching signal, and the width of the first switching signal and the width of the second switching signal can be different from each other.

[0027] The first driving circuit unit may also be configured to perform a data selection operation for selecting a portion of the input pixel data, the second driving circuit unit may also be configured to perform a data selection operation for selecting a portion of the input pixel data, and the data selection timing of the first driving circuit unit and the data selection timing of the second driving circuit unit may be different from each other.

[0028] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a diagram conceptually illustrating a display device according to an example.

[0030] Figure 2 is a diagram conceptually illustrating a display panel and a display driving device according to an example.

[0031] Figure 3is a diagram illustrating switching signals and selection signals used in a display driving device according to an example.

[0032] Figure 4 is a timing chart for explaining the operation of the display driving device according to the example.

[0033] Figures 5 to 8 is a diagram showing the state of the display driving device at each time point.

[0034] Fig. 9 is a timing chart for explaining the operation of the display driving device according to the example.

[0035] Fig.10 is a timing chart for explaining the operation of the display driving device according to the example.

[0036] Fig.11 is a diagram for explaining a timing adjustment operation of a logic circuit according to an example.

[0037] Fig.12 is a diagram for explaining a timing adjustment operation of a logic circuit according to an example.

[0038] Like reference numerals denote like elements throughout the drawings and detailed description. The drawings may not be drawn to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0039] Hereinafter, examples will be described with reference to the accompanying drawings.

[0040] The following detailed description is provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the method, device and / or system described herein will be obvious. For example, except for the operations that must be performed in a certain order, the order of operations described herein is merely an example, and is not limited to those set forth herein, but can be changed as it becomes obvious after understanding the disclosure of the application. In addition, in order to increase clarity and simplicity, the description of features known in the art can be omitted.

[0041] The features described herein may be embodied in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein, which will be apparent after understanding the disclosure of the present application.

[0042] Throughout the specification, when an element such as a layer, a region, or a substrate is described as being “on another element,” “connected to” or “coupled to” another element, it may be directly “on another element,” directly “connected to” or “coupled to” another element, or one or more other elements may be present therebetween. Conversely, when an element is described as being “directly on another element,” “directly connected to” or “directly coupled to” another element, no other elements may be present therebetween.

[0043] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more.

[0044] Although terms such as "first," "second," and "third" may be used herein to describe various components, parts, regions, layers, or portions, these components, parts, regions, layers, or portions are not limited by these terms. Instead, these terms are only used to distinguish one component, part, region, layer, or portion from another component, part, region, layer, or portion. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or portion mentioned in the examples may also be referred to as the second component, part, region, layer, or portion.

[0045] For ease of description, spatially related terms such as "above", "upper", "below" and "lower" may be used herein to describe the relationship of one element to another element as shown in the figures. Such spatially related terms are intended to cover different orientations of the device in use or operation, in addition to the orientations depicted in the drawings. For example, if the device in the drawings is flipped, an element described as being "above" or "upper" relative to another element will be "below" or "lower" relative to another element. Therefore, depending on the spatial orientation of the device, the term "above" includes both the upper orientation and the lower orientation. The device may also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially related terms used herein are to be interpreted accordingly.

[0046] The terms used herein are only used to describe various examples and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the situation where the quantity is not limited is intended to also include plural forms. The terms "comprise", "include" and "have" specify the presence of the features, numbers, operations, components, elements and / or their combinations, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements and / or their combinations.

[0047] Variations in the shapes shown in the drawings may occur due to manufacturing techniques and / or tolerances. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings but include variations in shapes that occur during manufacturing.

[0048] As will be apparent after understanding the disclosure of the present application, the features of the examples described herein can be combined in various ways. In addition, although the examples described herein have various configurations, as will be apparent after understanding the disclosure of the present application, other configurations are also possible.

[0049] In this document, it should be noted that the use of the term "may" with respect to examples or embodiments (e.g., with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment that includes or implements such features, but all examples and embodiments are not limited thereto.

[0050] An object of the present disclosure is to provide a display driving device and a display device including the same, which can adjust the timing of a signal used in the display driving device, thereby reducing noise due to EMI occurring in the display driving device.

[0051] The display driving apparatus according to the example may differently set the timing of the switching signal to differently set the switching timing of the switching circuit unit, thereby reducing noise caused by EMI.

[0052] The display driving apparatus according to an example may differently set the timing of the selection signal to differently set the selection timing of the pixel data, thereby reducing noise caused by EMI.

[0053] Figure 1 FIG. 1 is a diagram conceptually illustrating a display device according to an example. Figure 1 In the example of FIG. 1 , the display device 1000 includes a display panel 100 , a display driving device 200 , a gate driver 300 , and a timing controller 400 .

[0054] According to an example, the display device 1000 may be a device capable of displaying an image or video. For example, the display device 1000 may refer to a smart phone, a tablet personal computer, a mobile phone, a video phone, an e-book reader, a computer, a camera, or a wearable device, etc., but the display device 1000 is not limited thereto.

[0055] The display panel 100 may include a plurality of sub-pixels PX arranged in rows and columns. For example, the display panel 100 may be implemented by a technology selected as one of a light emitting diode (LED) display, an organic LED (OLED) display, an active matrix OLED (AMOLED) display, an electrochromic display (ECD), a digital mirror device (DMD), an actuated mirror device (AMD), a grating light valve (GLV), a plasma display panel (PDP), an electroluminescent display (ELD), and a vacuum fluorescent display (VFD), but the display technology is not limited to these examples, and other display panel technologies may be used in other examples.

[0056] The display panel 100 includes: a plurality of gate lines GL1 to GLn arranged in rows, where n is a natural number; a plurality of data lines DL1 to DLm arranged in columns, where m is a natural number; and sub-pixels PX formed at intersections of the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm. Therefore, the display panel 100 includes a plurality of horizontal lines, and each of the horizontal lines includes a sub-pixel PX connected to one gate line. During one horizontal time interval, the sub-pixels arranged along one horizontal line may be driven, and during the next 1H horizontal time interval, the sub-pixels arranged along another horizontal line may be driven.

[0057] The sub-pixel PX may include a light emitting diode (LED) and a diode driving circuit for independently driving the light emitting diode. The diode driving circuit may be connected to one gate line and one data line, and the light emitting diode may be connected between the diode driving circuit and a power supply voltage (eg, a ground voltage).

[0058] The diode driving circuit may include a switching element, for example, a thin film transistor (TFT) connected to the gate lines GL1 to GLn. When a gate turn-on signal is applied from the gate lines GL1 to GLn to turn on the switching element, the diode driving circuit may provide the light emitting diode with an image signal (also referred to as a pixel signal) received from the data lines DL1 to DLm connected to the diode driving circuit. The light emitting diode may output a light signal corresponding to the image signal.

[0059] Each of the sub-pixels PX may be one of a red element R for outputting red light, a green element G for outputting green light, and a blue element B for outputting blue light. Such pixels corresponding to the red element, the green element, and the blue element may be arranged in the display panel 100 according to various methods. According to these examples, the sub-pixels PX of the display panel 100 may be repeatedly arranged in the order of R, G, B, G or B, G, R, G, etc. However, these are only examples, and other ways of arranging the sub-pixels PX are also possible. For example, the sub-pixels PX of the display panel 100 may be arranged according to an RGB stripe structure or an RGB pentile structure, but are not limited thereto, and other RGB structures are also possible.

[0060] In response to the gate control signal GCS, the gate driver 300 may sequentially provide a gate turn-on signal to the plurality of gate lines GL1 to GLn. For example, the gate control signal GCS may include a gate start pulse for indicating the start of output of the gate turn-on signal, a gate shift clock for controlling the output time point of the gate turn-on signal, and the like.

[0061] When the gate start pulse is applied, the gate driver 300 may sequentially generate a gate turn-on signal, for example, a gate voltage corresponding to a logic high, in response to the gate shift clock, and may sequentially provide the gate turn-on signal to the plurality of gate lines GL1 to GLn. At this time, during a period in which no gate turn-on signal is provided to the plurality of gate lines GL1 to GLn, a gate turn-off signal, for example, a gate voltage corresponding to a logic low is provided to the plurality of gate lines GL1 to GLn.

[0062] In response to the data control signal DCS, the display driving device 200 may convert the digital image data DATA into analog image signals and may provide the converted image signals to the plurality of data lines DL1 to DLm. The display driving device 200 may provide image signals corresponding to one horizontal line to the plurality of data lines DL1 to DLm during a 1H time interval.

[0063] The display driving device 200 may be implemented as one semiconductor chip including a switching circuit unit 210 , a driving circuit unit 230 , and a logic circuit 250 .

[0064] The switching circuit unit 210 may transmit a signal transmitted from the driving circuit unit 230 to the display panel 100. According to an example, the switching circuit unit 210 may connect each of the plurality of channels CH1 to CHk to two data lines among the plurality of data lines DL1 to DLm.

[0065] According to an example, the switch circuit unit 210 may adjust switching timings between data lines of the plurality of channels CH1 to CHk, thereby reducing noise caused by EMI.

[0066] The driving circuit unit 230 may convert the image data DATA into an image signal in response to receiving the data control signal DCS. Therefore, the driving circuit unit 230 may output an image signal as a grayscale voltage corresponding to the image data DATA, and may output such an image signal to a plurality of channels CH1 to CHk, where k is a natural number having a value of m or less. For example, the data control signal DCS may include a source start signal, a source shift clock, a source output enable signal, etc.

[0067] The logic circuit 250 may control the operation of the switch circuit unit 210 and the drive circuit unit 230. According to an example, the logic circuit 250 may control the operation timing of the switch circuit unit 210 and the drive circuit unit 230. For example, as will be further described later, the logic circuit 250 may control various signals (e.g., Figure 3 signal) is generated.

[0068] According to an example, the logic circuit 250 may receive a signal generated by the timing controller 400 and may accordingly control operations of the switching circuit unit 210 and the driving circuit unit 230 based on the received signal.

[0069] The timing controller 400 may receive video image data RGB from an external source and may image-process or convert the video image data RGB to be suitable for the structure of the display panel 100 to generate image data DATA. The timing controller 400 may transmit the image data DATA to the display driving device 200.

[0070] The timing controller 400 may receive a plurality of control signals from an external host device. For example, the control signals may include a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock signal DCLK.

[0071] The timing controller 400 may generate a gate control signal GCS and a data control signal DCS for controlling the gate driver 300 and the display driving device 200 based on the received control signal. The timing controller 400 may control various operation timings of the gate driver 300 and the display driving device 200 based on the gate control signal GCS and the data control signal DCS.

[0072] According to an example, the timing controller 400 may control the gate driver 300 so that the gate driver 300 drives the plurality of gate lines GL1 to GLn based on the gate control signal GCS. The timing controller 400 may control the display driving device 200 so that the display driving device 200 provides image signals to the plurality of data lines DL1 to DLm based on the data control signal DCS.

[0073] Each configuration of the display device 1000 may include a circuit capable of performing a corresponding function.

[0074] Figure 2 FIG. 1 is a diagram conceptually showing a display panel and a display driving device according to an example. Figure 1 and Figure 2 , the display panel 100 may include a plurality of sub-pixels P11 to P14 and P21 to P24 arranged in parallel, and a plurality of data switches DSW11 to DSW14 and DSW21 to DSW24 connected to each of the plurality of sub-pixels P11 to P14 and P21 to P24. Each pair of the plurality of data switches DSW11 to DSW14 and DSW21 to DSW24 may be connected to corresponding channels CH1 to CH4.

[0075] The first group of sub-pixels P11 to P14 and the second group of sub-pixels P21 to P24 may be arranged in parallel or adjacent to each other. For example, the first group of sub-pixels P11 to P14 may be four consecutive sub-pixels, and the second group of sub-pixels P21 to P24 may be the next four consecutive sub-pixels.

[0076] The first group of sub-pixels P11 to P14 may be defined as constituting a first pixel, and the second group of sub-pixels P21 to P24 may be defined as constituting a second pixel. For example, the first pixel may be an odd pixel, and the second pixel may be an even pixel.

[0077] The data switches DSW11 to DSW14 and DSW21 to DSW24 may be switched between the corresponding sub-pixels and channels based on the data switching signals DSSa and DSSb. For example, the data switch DSW11 may connect the first channel CH1 and the sub-pixel P11 based on the first data switching signal DSSa, and the data switch DSW12 may connect the first channel CH1 and the sub-pixel P12 based on the second data switching signal DSSb. For example, when the first data switching signal DSSa is at a first level (e.g., a logic low level), each of the data switches DSW11, DSW13, DSW21, and DSW23 may connect each of the channels CH1, CH3, CH2, and CH4 and each of the pixels P11, P13, P21, and P23 to each other. However, when the second data switching signal DSSb is at a logic low level, each of the data switches DSW12, DSW14, DSW22, and DSW24 may connect each of the channels CH1, CH3, CH2, and CH4 and each of the pixels P12, P14, P22, and P24 to each other.

[0078] According to an example, states (e.g., turned on or off) of adjacent data switches (e.g., DSW11 and DSW12) may be different from each other. That is, when the data switch DSW11 is turned on, the data switch DSW12 may be turned off, and when the data switch DSW12 is turned on, the data switch DSW11 may be turned off. Therefore, the analog image signal transmitted through each of the channels CH1 to CH4 may be selectively provided to any one of the two sub-pixels (e.g., P11 and P12) connected to each of the channels CH1 to CH4 in response to receiving the data switching signal DSSa or DSSb.

[0079] The switch circuit unit 210 may include a first switch SW1 , a second switch SW2 , a third switch SW3 , and a fourth switch SW4 . According to an example, the number of switches included in the switch circuit unit 210 may be the same as the number of channels.

[0080] The first switch circuit unit may include a first switch SW1 and a third switch SW3, and the second switch circuit unit may include a second switch SW2 and a fourth switch SW4. That is, the first switch circuit units SW1 and SW3 may be connected to the first group of sub-pixels P11 to P14, and the second switch circuit units SW2 and SW4 may be connected to the second group of sub-pixels P21 to P24.

[0081] In such an example, each of the switches SW1 to SW4 may perform a switching operation in response to each of the switching signals SS1 to SS4 to connect each of the source amplifiers 231-1 to 231-4 to each of the channels CH1 to CH4. According to an example, the switches SW1 and SW3 may perform switching based on the switching signals SS1 and SS3, and the switches SW2 and SW4 may perform switching based on the switching signals SS2 and SS4.

[0082] According to an example, the first switch SW1 may connect the first source amplifier 231-1 to the first channel CH1 based on the first switching signal SS1, and may connect the first source amplifier 231-1 to the third channel CH3 based on the third switching signal SS3. The third switch SW3 may connect the third source amplifier 231-3 to the third channel CH3 based on the first switching signal SS1, and may connect the third source amplifier 231-3 to the first channel CH1 based on the third switching signal SS3. Similarly, the second switch SW2 may connect the second source amplifier 231-2 to the second channel CH2 based on the second switching signal SS2, and may connect the second source amplifier 231-2 to the fourth channel CH4 based on the fourth switching signal SS4. The fourth switch SW4 may connect the fourth source amplifier 231-4 to the fourth channel CH4 based on the second switching signal SS2, and may connect the fourth source amplifier 231-4 to the second channel CH2 based on the fourth switching signal SS4.

[0083] For example, when the first switching signal SS1 is at a second level (e.g., a logic high level), the first switch SW1 may connect the first source amplifier 231-1 to the first channel CH1, and the third switch SW3 may connect the third source amplifier 231-3 to the third channel CH3. When the third switching signal SS3 is at a logic high level, the first switch SW1 may connect the first source amplifier 231-1 to the third channel CH3, and the third switch SW3 may connect the third source amplifier 231-3 to the first channel CH1. Similarly, when the second switching signal SS2 is at a logic high level, the second switch SW2 may connect the second source amplifier 231-2 to the second channel CH2, and the fourth switch SW4 may connect the fourth source amplifier 231-4 to the fourth channel CH4. When the fourth switching signal SS4 is at a logic high level, the second switch SW2 may connect the second source amplifier 231-2 to the fourth channel CH4, and the fourth switch SW4 may connect the fourth source amplifier 231-4 to the second channel CH2. Thus, based on the switching signal, the source amplifiers and the channels are connected to each other in a manner that is appropriately changed.

[0084] The first and third switching signals SS1 and SS3 may be activated alternately, and the second and fourth switching signals SS2 and SS4 may be activated alternately. For example, a period during which the first and third switching signals SS1 and SS3 are at a logic high level may not overlap each other.

[0085] As further described later, the display driving device 200 according to the example can set the timing of the first switching signal SS1 and the second switching signal SS2 differently from each other, and can set the timing of the third switching signal SS3 and the fourth switching signal SS4 differently from each other. By setting the switching timing between the switches SW1 and SW3 and the switches SW2 and SW4 differently, in this way, noise based on EMI otherwise generated by the switching process can be reduced.

[0086] like Figure 2 As shown in the example of , the driving circuit unit 230 may include source amplifiers 231-1 to 231-4, multiplexers 235-1 to 235-4, and latches 237-1 to 237-4. According to the example, Figure 2 As shown in the example of , the driving circuit unit 230 may further include decoders 233 - 1 to 233 - 4 arranged between the source amplifiers 231 - 1 to 231 - 4 and the multiplexers 235 - 1 to 235 - 4 .

[0087] For convenience, the first source amplifier 231-1, the first decoder 233-1, the first multiplexer 235-1 and the first latch 237-1 are collectively referred to as the first drive circuit. The second drive circuit, the third drive circuit and the fourth drive circuit are also defined in a similar manner with respect to their components. The first drive circuit unit may include the first drive circuit and the third drive circuit, and the second drive circuit unit may include the second drive circuit and the fourth drive circuit.

[0088] The first driving circuit unit may output image signals to the first pixels P11 to P14, and the second driving circuit unit may output image signals to the second pixels P21 to P24. In addition, the first switching circuit units SW1 and SW3 may perform a switching operation to connect the first pixels P11 to P14 and the first driving circuit unit, and the second switching circuit units SW2 and SW4 may perform a switching operation to connect the second pixels P21 to P24 and the second driving circuit unit.

[0089] In addition, the display driving device 200 according to the example may include: an odd driving circuit unit for outputting an image signal to an odd pixel among the pixels arranged in parallel in the display panel 100; and an odd switching circuit unit for performing a switching operation for connecting the odd pixel and the odd driving circuit unit. The display driving device 200 according to the example may also include: an even driving circuit unit for outputting an image signal to an even pixel among the pixels arranged in parallel; and an even switching circuit unit for performing a switching operation for connecting the even pixel and the even driving circuit unit.

[0090] That is, consistent with the above description, the display driving apparatus 200 according to the example may set the switching timing of the odd-numbered switching circuit units and the switching timing of the even-numbered switching circuit units differently from each other, thereby reducing noise caused by EMI generated by the switching process.

[0091] Each of the source amplifiers 231 - 1 to 231 - 4 may output each of the image signals VS1 to VS4 to the display panel 100 through the switching circuit unit 210 .

[0092] Each of the latches 237-1 to 237-4 may store pixel data internally. According to an example, each of the latches 237-1 to 237-4 may store at least one of red pixel data R, green pixel data G, and blue pixel data B internally. For example, the first latch 237-1 may store red pixel data R and green pixel data G internally.

[0093] The latches 237-1 to 237-4 may internally store pixel data corresponding to each of the sub-pixels PX connected to the gate lines GL1 to GLn of the display panel 100. For example, when the sub-pixel PX connected to the first gate line GL1 is driven, the latches 237-1 to 237-4 may internally store pixel data corresponding to light to be output by the sub-pixel PX connected to the first gate line GL1, and when the sub-pixel PX connected to the second gate line GL2 is driven, the latches 237-1 to 237-4 may internally store pixel data corresponding to light to be output by the sub-pixel PX connected to the second gate line GL2.

[0094] The multiplexers 235-1 to 235-4 may select one of the pixel data stored in the corresponding latches 237-1 to 237-4 based on the selection signals SELa and SELb, and may output the selected one of the pixel data to the decoders 233-1 to 233-4 or the source amplifiers 231-1 to 231-4. For example, the first multiplexer 235-1 may select one of the pixel data R and G stored in the first latch 237-1 (e.g., R) based on the first selection signal SELa, and may output the selected pixel data (e.g., R) to the first decoder 233-1 or the first source amplifier 231-1.

[0095] As further described later, the display driving device 200 according to an example may set timings of the first selection signal SELa and the second selection signal SELb differently from each other to differently set selection timings of pixel data at the multiplexers 235 - 1 to 235 - 4 , thereby reducing noise otherwise caused by EMI.

[0096] That is, consistent with the above description, the display driving apparatus 200 according to the example may set the data selection timing of the odd driving circuit unit and the data selection timing of the even driving circuit unit differently from each other, thereby reducing noise based on EMI otherwise generated by the switching process.

[0097] The decoders 233-1 to 233-4 may output a grayscale voltage corresponding to the selected pixel data, and output the grayscale voltage from the multiplexers 235-1 to 235-4 to the source amplifiers 231-1 to 231-4. According to an example, the decoders 233-1 to 233-4 may receive a grayscale voltage corresponding to each of the pixel data, such as an R gamma voltage, a G gamma voltage, and a B gamma voltage, and may output a grayscale voltage corresponding to the selected pixel data, and output the grayscale voltage from the multiplexers 235-1 to 235-4 to the source amplifiers 231-1 to 231-4.

[0098] The source amplifiers 231-1 to 231-4 can convert the pixel data output from the multiplexers 235-1 to 235-4 into image signals VS1 to VS4 using, for example, digital-to-analog (DA) conversion, and can output the converted image signals VS1 to VS4 to channels CH1 to CH4, or can alternatively output the grayscale voltage output from the decoders 233-1 to 233-4, i.e., the gamma voltage corresponding to the pixel data, as the image signals VS1 to VS4 to channels CH1 to CH4.

[0099] According to an example, the source amplifiers 231-1 to 231-4 may output the image signals VS1 to VS4 to the corresponding channels CH1 to CH4 through the connected switches SW1 to SW4. For example, the first source amplifier 231-1 may output the first image signal VS1 to the first channel CH1 or the third channel CH3 through the first switch SW1, the third source amplifier 231-3 may output the third image signal VS3 to the third channel CH3 or the first channel CH1 through the third switch SW3, the second source amplifier 231-2 may output the second image signal VS2 to the second channel CH2 or the fourth channel CH4 through the second switch SW2, and the fourth source amplifier 231-4 may output the fourth image signal VS4 to the fourth channel CH4 or the second channel CH2 through the fourth switch SW4.

[0100] Figure 3 is a diagram showing a switching signal and a selection signal used in a display driving device according to an example. Figure 3 For example, the logic circuit 250 may generate switching signals SS1 to SS4 (collectively referred to as SS) and selection signals SELa and SELb (collectively referred to as SEL).

[0101] According to an example, in one horizontal time interval, the logic circuit 250 can adjust the width of the switching signal SS and can adjust the phase of the selection signal SEL. For example, the logic circuit 250 can adjust the falling time point or the rising time point of the switching signal SS, generate the switching signal SS having the adjusted falling time point or the rising time point, adjust both the rising time point and the falling time point of the selection signal SEL, and generate the selection signal SEL having the adjusted rising time point and the adjusted falling time point.

[0102] For example, the logic circuit 250 may adjust the width of the switching signal SS to a reference width (eg, Figure 3 ), adjust it to be smaller than the reference width (e.g., in the example of “ORIGIN” shown in Figure 3 MINUS example shown), or adjust it to be larger than the reference width (e.g. Figure 3PLUS) shown in the example.

[0103] For example, the logic circuit 250 may adjust the phase of the selection signal SEL to a reference phase (eg, in the ORIGIN example), to be earlier than the reference phase (eg, in the MINUS example), or to be later than the reference phase (eg, in the PLUS example).

[0104] The logic circuit 250 may read a value stored in a register, and may generate a switching signal SS and a selection signal SEL based on the read value read from the register.

[0105] According to an example, the logic circuit 250 may read at least one value from the register, and may adjust a falling time point or a rising time point of the switching signal SS using the at least one value read from the register to adjust the width of the switching signal SS.

[0106] According to an example, the logic circuit 250 may read at least one value from the register, and may adjust the falling time point and the rising time point of the selection signal SEL using the at least one value read from the register to adjust the phase of the selection signal SEL.

[0107] According to an example, the logic circuit 250 can determine whether to adjust the width of the switching signals SS1 to SS4 based on at least one value read from the register, can determine whether to adjust the phases of the selection signals SELa and SELb, can determine the width of the switching signals SS1 to SS4, and can determine the phases of the selection signals SELa and SELb.

[0108] Figure 4 is a timing chart for explaining the operation of the display driving device according to the example, and Figures 5 to 8 is a diagram showing the state of the display driving device at each time point in the example.

[0109] Columns 1H, 2H, 3H, and 4H can be synchronized by the horizontal synchronization signal Hsync. Figures 2 to 4 In the example of , the logic circuit 250 may generate the switching signals SS1 and SS2 so that the width of the switching signals SS1 and SS2 in the first column 1H is the reference width (in the example of ORIGIN), is less than the reference width (in the example of MINUS), or is greater than the reference width (in the example of PLUS). That is, the logic circuit 250 may adjust and / or set the width of the switching signals SS1 and SS2 based on a predetermined reference width.

[0110] In addition, similar to the first column 1H, the logic circuit 250 may generate the switching signals SS3 and SS4 so that the width of the third switching signal SS3 and the width of the fourth switching signal SS4 in the second column 2H become different from each other. According to an example, the logic circuit 250 may generate the switching signals SS3 and SS4 so that the width of the switching signals SS3 and SS4 in the second column 2H is the reference width (in the example of ORIGIN), is smaller than the reference width (in the example of MINUS), or is larger than the reference width (in the example of PLUS).

[0111] According to an example, the logic circuit 250 may adjust or set the widths of the switching signals SS1 to SS4 so that a floating period, which is a period in which both the switching signals SS1 and SS3 or SS2 and SS4 are at a logic low level, exists or does not exist in each horizontal time interval. Figure 4 As shown in the example of , the floating period of the switching signals SS1 and SS3 may exist in the first horizontal time interval 1H. However, the floating period of the switching signals SS1 and SS3 may not exist in the third horizontal time interval 3H.

[0112] As described above, although the logic circuit 250 has been described by way of example as adjusting the switching signals SS1 to SS4 in two columns 1H and 2H, the logic circuit 250 may perform the same adjustment in a series of columns, and thus, such adjustment may occur in similar examples using three or more columns.

[0113] According to the example, the adjustment operation for switching signals SS1 and SS2 in the first column 1H can also be applied to odd columns 3H, 5H, etc. in the same manner, and the adjustment operation for switching signals SS3 and SS4 in the second column 2H can also be applied to even columns 2H, 4H, etc. in the same manner.

[0114] In addition, the logic circuit 250 may generate the selection signals SELa and SELb so that the phase of the first selection signal SELa and the phase of the second selection signal SELb in the first column 1H become different. For example, the logic circuit 250 may generate the selection signals SELa and SELb so that each of the falling time point and the rising time point of the first selection signal SELa in the first column 1H becomes different from each of the falling time point and the rising time point of the second selection signal SELb. At this time, in addition, the widths of the selection signals SELa and SELb may remain the same.

[0115] As described above, although only one column 1H is described by way of example, the techniques used in the examples can also be applied to a series of columns in the same manner. According to these examples, the adjustment operation for the selection signals SELa and SELb in the first column 1H can also be applied to the next consecutive columns 2H, 3H, etc. in the same manner.

[0116] For convenience, the operation of adjusting the widths of the switching signals SS1 to SS4 or adjusting the phases of the selection signals SELa and SELb by the logic circuit 250 according to the example is referred to as a timing adjustment operation.

[0117] Further references Figure 5 An example is described in Figure 4 The operation of the display driving device at the first time point t0 in the example of FIG. Figure 4 and Figure 5 In the example, at the first time point t0, the first multiplexer 235-1 outputs one pixel data, for example, G, of the pixel data stored in the first latch 237-1 based on the first selection signal SELa of a logic low level, and the second multiplexer 235-2 outputs one pixel data, for example, G, of the pixel data stored in the second latch 237-2 based on the second selection signal SELb of a logic low level.

[0118] Similarly, the third multiplexer 235-3 outputs one pixel data, for example, G, from among the pixel data stored in the third latch 237-3 based on the first selection signal SELa of a logic low level; and the fourth multiplexer 235-4 outputs one pixel data, for example, G, from among the pixel data stored in the fourth latch 237-4 based on the second selection signal SELb of a logic low level.

[0119] At the first time point t0, the first switch SW1 connects the first source amplifier 231-1 and the first channel CH1 based on the first switching signal SS1 of the logic high level. Also at the first time point t0, the second switch SW2 connects the second source amplifier 231-2 and the second channel CH2 based on the second switching signal SS2 of the logic high level. Similarly, the third switch SW3 connects the third source amplifier 231-3 and the third channel CH3 based on the first switching signal SS1 of the logic high level, and further, the fourth switch SW4 connects the fourth source amplifier 231-4 and the fourth channel CH4 based on the second switching signal SS2 of the logic high level.

[0120] In addition, at the first time point t0, the switches DSW12, DSW14, DSW22 and DSW24 connect each of the channels CH1, CH3, CH2 and CH4 and each of the pixels P11, P13, P21 and P23 to each other based on the second data selection signal DSSb of a low level.

[0121] Further references Figure 6 Example description Figure 4 The operation of the display driving device at the second time point t1 in the example of FIG. Figure 4 and Figure 6 , at the second time point t1, the first multiplexer 235-1 outputs another pixel data, for example, R, stored in the first latch 237-1 based on the first selection signal SELa of the logic high level. As at the first time point t0, the second multiplexer 235-2 outputs one pixel data, for example, G, stored in the second latch 237-2 based on the second selection signal SELb of the logic low level. That is, the level of only the first selection signal SELa of the selection signals SELa and SELb of the logic low level changes. Therefore, only the selection of the data of the first multiplexer 235-1 changes, for example, from G to R. Similarly, the third multiplexer 235-3 outputs another pixel data, for example, B, stored in the third latch 237-3 based on the first selection signal SELa of the logic high level, and as at the first time point t0, the fourth multiplexer 235-4 outputs one pixel data, for example, G, stored in the fourth latch 237-4 based on the second selection signal SELb of the logic low level.

[0122] Because the phase of the first selection signal SELa and the phase of the second selection signal SELb in the first column 1H are different from each other, the timing of data selection of the multiplexers 235-1 and 235-3 corresponding to the first group of sub-pixels P11 to P14 is changed. That is, the timing of the level change of the selection signal SELa is different from the timing of the data selection change of the other multiplexers 235-2 and 235-4 corresponding to the second group of adjacent sub-pixels P21 to P24. Therefore, compared with the example in which the change timing of data selection of the first multiplexer 235-1 and the third multiplexer 235-3 and the second multiplexer 235-2 and the fourth multiplexer 235-4 is the same, less EMI occurs in the display driving device. Therefore, such a method can reduce noise caused by EMI.

[0123] In addition, at the second time point t1, the first switch SW1 releases the connection between the first source amplifier 231-1 and the first channel CH1 based on the first switching signal SS1 of the logic low level. As at the first time point t0, the second switch SW2 connects the second source amplifier 231-2 and the second channel CH2 based on the second switching signal SS2 of the logic high level. Similarly, the third switch SW3 connects the third source amplifier 231-3 and the third channel CH3 based on the first switching signal SS1 of the logic low level, and the fourth switch SW4 connects the fourth source amplifier 231-4 and the fourth channel CH4 based on the second switching signal SS2 of the logic high level.

[0124] Because the width of the first switching signal SS1 and the width of the second switching signal SS2 are different from each other during the first column 1H, the time point when the first switching signal SS1 enters a logic low level and the time point when the second switching signal SS2 enters a logic low level become different from each other. Therefore, the switching timing of the switches SW1 and SW3 connected to the first group of sub-pixels P11 to P14, that is, the timing of the state change from off to on or from on to off, becomes different from the switching timing of the other switches SW2 and SW4 connected to the second group of adjacent sub-pixels P21 to P24. Therefore, compared with the example in which the switching timing of the switches SW1 to SW4 is the same, less EMI occurs in the display driving device, which can reduce the noise caused by EMI.

[0125] Reference Figure 7 The example further describes Figure 4 Meanwhile, since the operation of the multiplexers 235-1 to 235-4 at the third time point t2 is the same as the operation of the multiplexers 235-1 to 235-4 at the first time point t0, the description of such operation is omitted for the sake of brevity.

[0126] Reference Figure 4 and Figure 7 In the example of, at the third time point t2, the first switch SW1 connects the first source amplifier 231-1 and the third channel CH3 based on the third switching signal SS3 of the logic high level. In addition, the second switch SW2 connects the second source amplifier 231-2 and the fourth channel CH4 based on the fourth switching signal SS4 of the logic high level. Similarly, the third switch SW3 connects the third source amplifier 231-3 and the first channel CH1 based on the third switching signal SS3 of the logic high level, and the fourth switch SW4 connects the fourth source amplifier 231-4 and the second channel CH2 based on the fourth switching signal SS4 of the logic high level.

[0127] Reference Figure 8 The example further describes Figure 4Meanwhile, since the operation of the multiplexers 235-1 to 235-4 at the fourth time point t3 is the same as the operation of the multiplexers 235-1 to 235-4 at the second time point t1, the description of such operation is omitted for the sake of brevity.

[0128] That is, because the phase of the first selection signal SELa and the phase of the second selection signal SELb in the second column 2H are different from each other, the timing of the data selection change of the multiplexers 235-1 and 235-3 corresponding to the first group of sub-pixels P11 to P14, that is, the timing of the level change of the selection signal SELa, becomes different from the timing of the data selection change of the other multiplexers 235-2 and 235-4 corresponding to the second group of adjacent sub-pixels P21 to P24. Therefore, compared with the example in which the change timing of the data selection of the first multiplexer 235-1 and the third multiplexer 235-3 and the second multiplexer 235-2 and the fourth multiplexer 235-4 is the same, less EMI occurs in the display driving device. Therefore, using such a method can reduce noise caused by EMI.

[0129] Reference Figure 4 and Figure 8 , at the fourth time point t3, the first switch SW1 disconnects the first source amplifier 231-1 from the third channel CH3 based on the third switching signal SS3 of the logic low level. As at the first time point t0, the second switch SW2 connects the second source amplifier 231-2 and the fourth channel CH4 based on the fourth switching signal SS4 of the logic high level. Similarly, the third switch SW3 disconnects the third source amplifier 231-3 from the first channel CH1 based on the third switching signal SS3 of the logic low level, and the fourth switch SW4 connects the fourth source amplifier 231-4 to the second channel CH2 based on the fourth switching signal SS4 of the logic high level.

[0130] Because the width of the third switching signal SS3 and the width of the fourth switching signal SS4 are different from each other during the second column 2H, the time point when the third switching signal SS3 enters a logic low level and the time point when the fourth switching signal SS4 enters a logic low level become different from each other. Therefore, the switching timing of the switches SW1 and SW3 connected to the first group of sub-pixels P11 to P14 becomes different from the switching timing of the other switches SW2 and SW4 connected to the second group of adjacent sub-pixels P21 to P24. Therefore, compared with the example in which the switching timing of the switches SW1 to SW4 is the same, less EMI occurs in the display driving device, thereby reducing noise caused by EMI.

[0131] Fig. 92 is a timing diagram for explaining the operation of the display driving apparatus according to an example. As described above, in one horizontal time interval, the logic circuit 250 can adjust the width of the switching signal SS and can adjust the phase of the selection signal SEL.

[0132] and Figure 4 The example is different. Fig. 9 The width of the first switching signal SS1 shown in the example is the same as the reference width, and the width of the second switching signal SS2 is greater than the reference width. That is, according to the example, the display driving device 200 or the logic circuit 250 can adjust the width of the switching signal SS according to various methods, and can adjust the phase of the selection signal SEL.

[0133] Fig.10 2 is a timing chart for explaining the operation of a display driving device according to an example. Fig.10 For example, the logic circuit 250 may adjust the width of each of the switching signals SS1 to SS4 in adjacent odd columns or adjacent even columns differently from each other. Figure 3 and Figure 5 As shown in the example of , the logic circuit 250 may adjust the widths of the first switching signal SS1 in adjacent odd columns differently from each other, and may adjust the widths of the third switching signal SS3 in adjacent even columns differently from each other.

[0134] Similarly, the logic circuit 250 may adjust the phase of each of the selection signals SELa and SELb in adjacent columns differently from each other. Figure 3 and Figure 5 As shown in the example of , the logic circuit 250 may adjust the phases of the first selection signals SELa in adjacent columns differently from each other.

[0135] Therefore, the switching timing of switches SW1 to SW4 in adjacent columns, such as columns 1H and 2H or columns 2H and 3H, etc., or the data selection timing of multiplexers 235-1 to 235-4 become different from each other. That is, the entire cycle of switching or data selection becomes uneven. Therefore, compared with the example with the same timing, less EMI occurs in the display driving device. Therefore, the noise caused by EMI can be reduced.

[0136] Fig.11 and Fig.12 is a diagram for explaining a timing adjustment operation of a logic circuit according to an example. Fig.11 shows the Nth frame FR0 (where N is a natural number) and the (N+1)th frame FR1, and Fig.12 The (N+2)th frame FR2 and the (N+3)th frame FR3 are shown.

[0137] Each block of each frame FR0 to FR3 may correspond to a timing connected to a group of sub-pixels in one horizontal time interval. For example, in each frame FR0 to FR3, block P1 may correspond to the data selection timing of the first multiplexer 235-1 and the third multiplexer 235-3 corresponding to the first group of sub-pixels P11 to P14 in the first horizontal time interval 1H or the switching timing of the first switch SW1 and the third switch SW3. Similarly, in each frame FR0 to FR3, the block set to the right of block P1 may correspond to the data selection timing of the second multiplexer 235-2 and the fourth multiplexer 235-4 corresponding to the second group of sub-pixels P21 to P24 in the first horizontal time interval 1H or the switching timing of the second switch SW2 and the fourth switch SW4.

[0138] Likewise, each column of each of the frames FR0 to FR3 may correspond to a timing connected to a group of sub-pixels in a plurality of horizontal time intervals.

[0139] exist Fig.11 and Fig.12 In the example of FIG. 1 , the sign “+” shown in each block of frames FR0 to FR3 indicates that the corresponding timing is slower than the reference timing. That is, the sign “+” appropriately indicates that the width or phase of the switching signal SS or the selection signal SEL respectively corresponding to the block is a width greater than the reference width or a phase later than the reference phase.

[0140] exist Fig.11 and Fig.12 In the example of FIG. 1 , the symbol “-” shown in each block of frames FR0 to FR3 indicates that the corresponding timing is faster than the reference timing. That is, the symbol “-” appropriately indicates that the width or phase of the switching signal SS or the selection signal SEL respectively corresponding to the block is a smaller width than the reference width or a phase earlier than the reference phase.

[0141] exist Fig.11 and Fig.12 In the example of FIG. 1 , the symbol “0” shown in each block of frames FR0 to FR3 indicates that the corresponding timing is the same as the reference timing. That is, “0” appropriately indicates that the width of the switching signal SS or the phase of the selection signal SEL corresponding to the block is the same as the reference width or the reference phase.

[0142] According to an example, the logic circuit 250 may adjust the widths of the switching signals SS1 to SS4 or the phases of the selection signals SELa and SELb so that the timing differences between the blocks in a certain number of columns become the same. For example, the logic circuit 250 may perform adjustment so that the sum of the width differences between the switching signals SS1 and SS2 or SS3 and SS4 in a column (e.g., four columns as shown in the example) or the sum of the phase differences between the selection signals SELa and SELb becomes 0. Fig.11 and Fig.12As shown in the example of , the number of occurrences of the symbol “-” and the number of occurrences of the symbol “+” can be the same within the range of 1H to 4H.

[0143] Similarly, the logic circuit 250 can adjust the width of the switching signals SS1 to SS4 or the phase of the selection signals SELa and SELb so that the timing differences between the blocks within a certain number of frames become the same. For example, the logic circuit 250 can perform adjustment so that the sum of the width differences between the switching signals SS1 and SS2 or SS3 and SS4 within the frames FR0 to FR3 becomes 0, or similarly, the sum of the phase differences between the selection signals SELa and SELb becomes 0. Fig.11 and Fig.12 As shown in the example of , the number of occurrences of the symbol “-” and the number of occurrences of the symbol “+” in the range of FR0 to FR3 may be the same.

[0144] That is, when a part of the logic circuit 250 belongs to frames different from each other even in the same column, the corresponding switching timing or data selection timing may become different, thereby adjusting the timing so that the deviation of the entire frame becomes 0.

[0145] According to an example, the logic circuit 250 can adjust the width of the switching signal SS and can adjust the phase of the selection signal SEL based on a first counter and a second counter, the first counter operates based on the horizontal synchronization signal Hsync and includes a four-cycle counter or a two-bit counter, and the second counter operates based on the vertical synchronization signal Vsync and also includes a four-cycle counter or a two-bit counter. The counter can be implemented by a hardware counter or a software counter.

[0146] In the present disclosure, a four-cycle counter refers to a counter that periodically generates four count values, such as "00", "01", "10", and "11". That is, when the first counter generates the first count value in the first column 1H, the first count value may be generated again in the fifth column. Similarly, when the second counter generates the first count value in the first vertical time, the first count value may be generated again in the fifth vertical time.

[0147] According to an example, the logic circuit 250 may sequentially adjust the widths of the switching signals SS1 to SS4 according to the count value generated by the first counter, and may also sequentially adjust the phases of the selection signals SELa and SELb to perform a timing adjustment operation for each column.

[0148] For example, when the first counter generates a first count value (for example, "00") in the first column 1H, the logic circuit 250 can set the width of the first switching signal SS1 to be less than the reference width, when the first counter generates a second count value (for example, "01") in the second column 2H, the logic circuit 250 can set the width of the first switching signal SS1 to the reference width, when the first counter generates a third count value (for example, "10") in the third column 3H, the logic circuit 250 can set the width of the first switching signal SS1 to be greater than the reference width, and when the first counter generates a fourth count value (for example, "11") in the fourth column 4H, the logic circuit 250 can set the width of the first switching signal SS1 to the reference width.

[0149] Meanwhile, when adjusting the widths of the other switching signals SS2 to SS4, the logic circuit 250 may use the count value generated by the first counter to shift. For example, when the first counter generates a first count value in the first column 1H, the logic circuit 250 may adjust the width of the second switching signal SS2 based on a value (i.e., a second count value) obtained by shifting the first count value.

[0150] For example, when the first counter generates a first count value (for example, "00"), the logic circuit 250 can set the phase of the first selection signal SELa to be earlier than the reference phase, when the first counter generates a second count value (for example, "01"), the logic circuit 250 can set the phase of the first selection signal SELa to be the reference phase, when the first counter generates a third count value (for example, "10"), the logic circuit 250 can set the phase of the first selection signal SELa to be later than the reference phase, and when the first counter generates a fourth count value (for example, "11"), the logic circuit 250 can set the phase of the first selection signal SELa to the reference phase.

[0151] The logic circuit 250 can adjust the width of the switching signal SS and can adjust the phase of the selection signal SEL according to the sum of the count value generated by the first counter and the value generated by the second counter to perform a timing adjustment operation for each frame. When the frames are different even in the same column, the widths of the switching signals SS1 to SS4 or the phases of the selection signals SELa and SELb can be adjusted accordingly so that the timing difference between the blocks within the frame becomes the same by shifting the count value corresponding to the column.

[0152] For example, Fig.11 and Fig.12 As shown in the example of , the timing of the block P1 in the N-th frame FR0 and the timing of the block P1 in the (N+1)-th frame FR1 may be different from each other.

[0153] Although the present disclosure includes specific examples, it will be apparent after understanding the disclosure of the present application that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered to be descriptive only and not for limiting purposes. The description of the features or aspects in each example is considered to be applicable to similar features or aspects in other examples. Appropriate results may be achieved when the described techniques are performed in different orders and / or the components in the described systems, architectures, devices, or circuits are combined in different ways and / or replaced or supplemented by other components or their equivalents. Therefore, the scope of the present disclosure is not limited by specific embodiments, but by the claims and their equivalents, and all changes within the scope of the claims and their equivalents should be interpreted as included in the present disclosure.

Claims

1. A display driving device for driving a display panel, the display driving device comprising: a first driving circuit configured to output a first image signal; a second driving circuit configured to output a second image signal; a first switch circuit connected to the first drive circuit, and configured to transmit the first image signal to a portion of a first group of sub-pixels arranged in the display panel based on a first switching signal during a first horizontal time interval; as well as a second switch circuit connected to the second drive circuit, and configured to transmit the second image signal to a portion of a second group of sub-pixels arranged in the display panel and adjacent to the first group of sub-pixels based on a second switching signal during the first horizontal time interval, During the first horizontal time interval, the width of the first switching signal and the width of the second switching signal are different from each other, so that the switching timing of the first switching signal and the switching timing of the second switching signal are different from each other.

2. The display driving device according to claim 1, in, During the first horizontal time interval, a falling time point of the first switching signal is earlier than a falling time point of the second switching signal.

3. The display driving device according to claim 2, in, During the first horizontal time interval, a rising time point of the first switching signal is the same as a rising time point of the second switching signal.

4. The display driving device according to claim 1, in, The first switching circuit is further configured to transmit the first image signal to another part of the first group of sub-pixels based on a third switching signal during a second horizontal time interval after the first horizontal time interval, The second switch circuit is further configured to send the second image signal to another part of the second group of sub-pixels based on a fourth switch signal during the second horizontal time interval, and During the second horizontal time interval, a width of the third switching signal and a width of the fourth switching signal are different from each other.

5. The display driving device according to claim 1, in, The first driving circuit comprises: a first multiplexer configured to output one of the first pixel data and the second pixel data in response to a first selection signal received during the first horizontal time interval, Wherein, the second driving circuit comprises: a second multiplexer configured to output one of the third pixel data and the fourth pixel data in response to a second selection signal received during the first horizontal time interval, wherein during the first horizontal time interval, the phase of the first selection signal and the phase of the second selection signal are different from each other, and The width of the first selection signal is the same as the width of the second selection signal.

6. The display driving device according to claim 5, in, During the first horizontal time interval, a falling time point of the first selection signal is earlier than a falling time point of the second selection signal.

7. The display driving device according to claim 5, in, The first driving circuit further includes: a first latch configured to output the first pixel data and the second pixel data to the first multiplexer, and a first source amplifier configured to output a first voltage corresponding to the one pixel data outputted from the first multiplexer as the first image signal to the first group of sub-pixels, and Wherein, the second driving circuit further includes: a second latch configured to output the third pixel data and the fourth pixel data to the second multiplexer, and A second source amplifier is configured to output a second voltage corresponding to the one pixel data output from the second multiplexer to the second group of sub-pixels as the second image signal.

8. The display driving device according to claim 1, in, The display driving device further includes a logic circuit configured to adjust a width of the first switching signal and a width of the second switching signal.

9. The display driving device according to claim 8, in, The logic circuit is further configured to sequentially set the width of the first switching signal during each horizontal period to a reference width, a value smaller than the reference width, the reference width, and a value larger than the reference width based on a four-cycle counter.

10. A display device comprising a display panel and a display driving device for driving the display panel, in, The display panel includes sub-pixels arranged in the display panel; and Wherein, the display driving device comprises: a first driving circuit configured to output a first image signal; a second driving circuit configured to output a second image signal; a first switching circuit connected to the first driving circuit and configured to transmit the first image signal to a portion of a first group of sub-pixels arranged in the display panel based on a first switching signal during a first horizontal time interval; and a second switching circuit connected to the second driving circuit, and configured to transmit the second image signal to a portion of a second group of sub-pixels arranged in the display panel and adjacent to the first group of sub-pixels based on a second switching signal during the first horizontal time interval, and During the first horizontal time interval, the width of the first switching signal and the width of the second switching signal are different from each other, so that the switching timing of the first switching signal and the switching timing of the second switching signal are different from each other.

11. The display device according to claim 10, in, During the first horizontal time interval, a falling time point of the first switching signal is earlier than a falling time point of the second switching signal.

12. The display device according to claim 10, in, The first driving circuit comprises: a first multiplexer configured to output one of the first pixel data and the second pixel data in response to a first selection signal received during the first horizontal time interval, Wherein, the second driving circuit comprises: a second multiplexer configured to output one of the third pixel data and the fourth pixel data in response to a second selection signal received during the first horizontal time interval, wherein during the first horizontal time interval, the phase of the first selection signal and the phase of the second selection signal are different from each other, and The width of the first selection signal is the same as the width of the second selection signal.

13. The display device according to claim 10, in, The display driving device further comprises: a logic circuit configured to adjust a width of the first switching signal and a width of the second switching signal, The logic circuit is further configured to sequentially set the width of the first switching signal during each horizontal period to a reference width, a value less than the reference width, the reference width, and a value greater than the reference width based on a four-cycle counter.

14. A display driving device for driving a display panel, wherein a plurality of pixels are arranged in parallel, the display driving device comprising: a first driving circuit unit configured to output a first image signal to odd-numbered pixels among the plurality of pixels; a second driving circuit unit configured to output a second image signal to even-numbered pixels among the plurality of pixels; a first switch circuit unit interposed between the odd-numbered pixels and the first drive circuit unit, and the first switch circuit unit is configured to perform a switching operation for connecting the odd-numbered pixels and the first drive circuit unit; as well as a second switch circuit unit interposed between the even-numbered pixels and the second drive circuit unit, and the second switch circuit unit is configured to perform a switching operation for connecting the even-numbered pixels and the second drive circuit unit, Wherein, during a horizontal time interval, a switching timing of the first switching circuit unit and a switching timing of the second switching circuit unit are different from each other.

15. The display driving device according to claim 14, It also includes a plurality of first switch circuit units, wherein: The switching timing of each of the plurality of first switching circuit units is the same, and the display driving device further includes a plurality of second switching circuit units, wherein the switching timing of each of the plurality of second switching circuit units is the same.

16. The display driving device according to claim 14, in, The first switch circuit unit is further configured to: perform a switching operation for connecting the odd-numbered pixels and the first driving circuit unit in response to a first switching signal, The second switch circuit unit is further configured to: in response to a second switch signal, perform a switch operation for connecting the even-numbered pixels to the second drive circuit unit, and Wherein, a width of the first switching signal and a width of the second switching signal are different from each other during a horizontal time interval.

17. The display driving device according to claim 14, in, The first driving circuit unit is further configured to perform a data selection operation for selecting a portion of the input pixel data, The second driving circuit unit is further configured to perform a data selection operation for selecting a portion of the input pixel data, and The data selection timing of the first driving circuit unit and the data selection timing of the second driving circuit unit are different from each other.

18. A display device comprising a display panel and a display driving device for driving the display panel, in, The display panel includes a plurality of pixels arranged in the display panel, Wherein, the display driving device comprises: a first driving circuit unit configured to output a first image signal to odd-numbered pixels among the plurality of pixels; a second driving circuit unit configured to output a second image signal to even-numbered pixels among the plurality of pixels; a first switch circuit unit interposed between the odd-numbered pixels and the first drive circuit unit, and configured to perform a switching operation for connecting the odd-numbered pixels and the first drive circuit unit; and a second switch circuit unit interposed between the even-numbered pixels and the second drive circuit unit, and the second switch circuit unit is configured to perform a switching operation for connecting the even-numbered pixels and the second drive circuit unit, Wherein, during a horizontal time interval, a switching timing of the first switching circuit unit and a switching timing of the second switching circuit unit are different from each other.

19. The display device according to claim 18, in, The display driving device further includes a plurality of first switching circuit units, wherein the switching timing of each of the plurality of first switching circuit units is the same, and the display driving device further includes a plurality of second switching circuit units, wherein the switching timing of each of the plurality of second switching circuit units is the same.

20. The display device according to claim 18, in, The first switch circuit unit is further configured to: perform a switching operation for connecting the odd-numbered pixels to the first drive circuit unit in response to a first switching signal, The second switch circuit unit is further configured to: in response to a second switch signal, perform a switch operation for connecting the even-numbered pixels to the second drive circuit unit, and Wherein, a width of the first switching signal and a width of the second switching signal are different from each other during a horizontal time interval.

21. The display device according to claim 18, in, The first driving circuit unit is further configured to perform a data selection operation for selecting a portion of the input pixel data, The second driving circuit unit is further configured to perform a data selection operation for selecting a portion of the input pixel data, and The data selection timing of the first driving circuit unit and the data selection timing of the second driving circuit unit are different from each other.

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