Storage device including non-volatile memory device and operation method thereof

Abstract

A storage device is disclosed, comprising: a non-volatile memory device, comprising a memory block and a memory controller. The memory block comprises a first memory area connected to a first word line and a second memory area connected to a second word line. The memory controller sets a read block voltage based on a first read voltage of the first memory area. The memory controller determines a second read voltage of the second memory area based on change information and the read block voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0094844 filed on August 14, 2018 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various example embodiments of the inventive concepts disclosed herein relate to devices for storing data, and more particularly, to storage devices including nonvolatile memory devices, systems including the storage devices, and / or operating methods thereof. Background Art

[0004] Storage devices (e.g., solid-state drives (SSDs), etc.) include non-volatile memory. Since storage devices retain data stored therein even after power is lost (e.g., the power supply to the storage device is turned off, etc.), it is advantageous to store data on the storage device for a long time. Storage devices are used as main storage in various electronic devices (e.g., computers, smart phones, smart tablets, etc.).

[0005] The non-volatile memory of the storage device degrades over time due to various factors, and the storage device can cope with the degradation in a manner that changes the operating conditions based on the degree of degradation. For example, the storage device can cope with the degradation in a manner that adjusts the level of the read voltage based on the operating conditions of the storage device. Typically, the level of the read voltage can be adjusted for each memory block. However, the read voltage of the memory area connected to different word lines in the memory block may vary differently with degradation. In order to ensure the reliability associated with driving the storage device, it is necessary to adjust the read voltage more finely. Summary of the invention

[0006] Various example embodiments of the inventive concept provide a storage device including a nonvolatile memory device, a system including the storage device, and / or an operating method thereof, which can ensure reliability in consideration of a change in an operating state due to degradation of the nonvolatile memory device.

[0007] According to at least one example embodiment, a storage device includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes at least one memory block, the at least one memory block including at least a first memory area connected to a first word line and a second memory area connected to a second word line. The memory controller is configured to: set a read block voltage corresponding to the memory block based on a first read voltage to be provided to the first memory area; set change information related to the first memory area, the second memory area, and the read block voltage based on a change in the read voltage of the first memory area and a change in the read voltage of the second memory area; and determine a second read voltage to be provided to the second memory area based on the change information.

[0008] According to at least one example embodiment, an operating method of a storage device includes: receiving, using a memory controller, a read request for a memory area connected to a target word line; searching, using the memory controller, in response to the read request, for a read block voltage corresponding to a memory block included in the memory area; setting, using the memory controller, variation information based on a predicted value of a read voltage, the read voltages being respectively provided to a plurality of word lines of the memory area; and determining, using the memory controller, a target read voltage to be provided to the target word line based on the read block voltage and the variation information.

[0009] According to at least one example embodiment, a storage device includes: a nonvolatile memory including at least one memory block; and a memory controller configured to: set a read block voltage for at least one memory block based on a read voltage supplied to a word line corresponding to a successful read operation and position information corresponding to the word line; and determine a target read voltage to be supplied to a target word line based on the read block voltage and position information of a target word line connected to a memory area of ​​a read request. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present inventive concept will become more apparent by describing in detail some exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0011] Figure 1 is a block diagram illustrating a storage device according to at least one example embodiment of the inventive concepts.

[0012] Figure 2 is a diagram showing a method according to at least one example embodiment Figure 1 An example circuit diagram of a memory block is shown.

[0013] Figure 3 is used to describe at least one example embodiment Figure 2 Graph showing changes in threshold voltage distribution of the memory cells shown in FIG.

[0014] Figure 4 is used to describe a method for Figure 2 Graph of changes in threshold voltage distribution of each word line of the memory cells shown in FIG.

[0015] Figure 5 is a diagram showing a method according to at least one example embodiment Figure 1 Block diagram of the read voltage control module.

[0016] Figure 6 is a flowchart illustrating a data reading method of a storage device according to at least one example embodiment of the inventive concepts.

[0017] Figure 7 It shows Figure 6 A flow chart of at least one example embodiment of a data reading method.

[0018] Figure 8 is a diagram for describing a process of classifying tables when change information includes a plurality of tables according to at least one example embodiment.

[0019] Fig. 9 It shows Figure 6 A flow chart of at least one example embodiment of a data reading method.

[0020] Fig.10 is a diagram showing a method according to at least one example embodiment Fig. 9 Figure 14. Processing diagram of the selection change table.

[0021] Fig.11 It shows Figure 6 A flow chart of at least one example embodiment of a data reading method. DETAILED DESCRIPTION

[0022] Hereinafter, various exemplary embodiments of the inventive concept will be described clearly and in detail with reference to the accompanying drawings so that those having ordinary skill in the art can implement the exemplary embodiments of the inventive concept.

[0023] Figure 1 is a block diagram illustrating a storage device according to at least one example embodiment of the inventive concept. Figure 1 The storage device 100 includes a non-volatile memory device 110, a memory controller 120, and / or a buffer memory 130, etc., but example embodiments are not limited thereto. The storage device 100 may be implemented in the form of a solid state drive (SSD), a memory card, an embedded multimedia card (eMMC), and / or a universal flash memory (UFS), etc., but is not limited thereto.

[0024] The non-volatile memory device 110 may perform a write operation, a read operation, an erase operation, etc. under the control of the memory controller 120. The non-volatile memory device 110 may receive a write command, an address, and data, etc. from the memory controller 120, and in response to a write command, may write data to a storage space identified by an address. The non-volatile memory device 110 may receive a read command and an address, etc. from the memory controller 120, may read data from a storage space identified by an address, and may output the read data to the memory controller 120. The non-volatile memory device 110 may receive an erase command and an address from the memory controller 120, and may erase data of the storage space identified by the address.

[0025] The nonvolatile memory device 110 may include a plurality of memory blocks BLK1 to BLKz, but is not limited thereto. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells, but is not limited thereto. The memory cells may form a storage space of the nonvolatile memory device 110. Each of the memory blocks BLK1 to BLKz may also include a selection transistor, so that the memory cells can be selected independently of each other, and / or the memory cells may be selected collectively in groups. The memory blocks BLK1 to BLKz may be distinguished according to the operational characteristics and / or structural characteristics of the nonvolatile memory device 110.

[0026] The nonvolatile memory device 110 may include a flash memory, a phase change random access memory (PRAM), a ferroelectric RAM (FeRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and the like.

[0027] The memory controller 120 may access the nonvolatile memory device 110 and the buffer memory 130, etc. The memory controller 120 may perform a write operation, a read operation, an erase operation, and / or other commands in response to a request of an external host device, a built-in self-test device, at least one internal / integrated processor, etc. The memory controller 120 may write write request data to the nonvolatile memory device 110, and may read read request data from the nonvolatile memory device 110.

[0028] The memory controller 120 may manage the storage device 100 by using the buffer memory 130. For example, the memory controller 120 may temporarily store data to be written to the nonvolatile memory device 110 and / or data read from the nonvolatile memory device 110 in the buffer memory 130. The memory controller 120 may load metadata required and / or necessary for managing the nonvolatile memory device 110 onto the buffer memory 130.

[0029] The memory controller 120 may include at least one central processing unit (hereinafter referred to as “CPU”) 121 , a host interface 124 , a buffer control circuit 125 , a memory interface 126 , and / or a bus 128 , among others.

[0030] The CPU 121 may control the overall operation of the memory controller 120 and may perform logic operations. The CPU 121 may communicate with an external host device through a host interface 124, may communicate with the non-volatile memory device 110 through a memory interface 126, and / or may communicate with the buffer memory 130 through a buffer control circuit 125, but is not limited thereto. The CPU 121 may control the storage device 100 by using the buffer memory 130, but is not limited thereto. The CPU 121 may execute a read voltage (RV) control module 131 loaded onto the buffer memory 130, but example embodiments are not limited thereto, for example, the read voltage control module 131 may be embodied as a separate circuit and / or processing device (e.g., an application specific integrated circuit (ASIC), a system on chip (SoC), a field programmable gate array (FPGA), etc.), etc. In a read operation, when the read voltage control module 131 is executed, the memory controller 120 may determine a read voltage for the non-volatile memory device 110. The CPU 121 may be implemented with a multi-core processor including a plurality of cores, as a multi-processor system, a distributed processing system, a cloud computing system, etc.

[0031] The host interface 124 is configured to communicate with a host device under the control of the CPU 121. The host interface 124 may be configured to send and / or receive communications by using at least one of various communication types, such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), a peripheral component interconnect (PCI), PCI Express (PCIe), a non-volatile memory express (NVMe), a universal flash memory (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and / or a load-reduced DIMM (LRDIMM), etc.

[0032] The buffer control circuit 125 is configured to control the buffer memory 130 under the control of the CPU 121. The buffer control circuit 125 allows the buffer memory 130 to store and / or temporarily store data exchanged between the nonvolatile memory device 110 and the host device.

[0033] The memory interface 126 is configured to communicate with the nonvolatile memory device 110 under the control of the CPU 121. The memory interface 126 may transmit commands, addresses, and / or data, etc. to the nonvolatile memory device 110 through an input / output channel. The memory interface 126 may transmit control signals to the nonvolatile memory device 110 through a control channel.

[0034] The memory interface 126 may include an error correction block 127 (e.g., an error correction circuit, etc.). The error correction block 127 may include an error correction code. The error correction block 127 may perform error correction. The error correction block 127 may perform error correction encoding based on data to be written to the non-volatile memory device 110 through the memory interface 126. The error correction encoded data may be provided to the non-volatile memory device 110 through the memory interface 126. The error correction block 127 may perform error correction decoding on the data received from the non-volatile memory device 110 through the memory interface 126.

[0035] The bus 128 provides a communication channel between components of the memory controller 120. The CPU 121, the host interface 124, the buffer control circuit 125, and / or the memory interface 126, etc. may exchange data with each other through the bus 128. The bus 128 may be configured to support various types of communication formats used in the memory controller 120.

[0036] The buffer memory 130 may store codes and / or computer-readable instructions executed by the CPU 121. The buffer memory 130 may store data processed by the CPU 121. The buffer memory 130 may include a random access memory (RAM). A flash translation layer FTL or various memory management modules may be stored in the buffer memory 130. The flash translation layer FTL may perform address mapping, garbage collection, wear leveling, etc. to provide an interface connection between the non-volatile memory device 110 and the host device, but is not limited thereto.

[0037] The read voltage control module 131 may be stored in the buffer memory 130, but example embodiments are not limited thereto. The read voltage control module 131 may be executed by the CPU 121, but is not limited thereto. When the CPU 121 executes the read voltage control module 131, the memory controller 120 may determine a read voltage in order to cope with (e.g., compensate for, etc.) a change in the read voltage caused by a degradation condition occurring at and / or affecting the nonvolatile memory device 110. When the read voltage control module 131 is executed, the memory controller 120 may set a read block voltage for each of the memory blocks BLK1 to BLKz, and may determine the read voltage of the nonvolatile memory device 110 based on the set read block voltage and variation information. The variation information may be a value obtained by predicting a change in the read voltage due to degradation of the nonvolatile memory device 110. How to determine the read voltage will be described more fully later.

[0038] Figure 2 According to at least one example embodiment Figure 1 , but example embodiments are not limited thereto. Figure 2 , a plurality of cell strings CS are arranged in rows and columns on a substrate SUB. A plurality of cell strings CS may be commonly connected to a common source line CSL formed on (or in) the substrate SUB. The position of the substrate SUB is shown as an example to help understand the structure of the memory block BLKa, but the example embodiments are not limited thereto. At least one example embodiment may include a common source line CSL connected to the lower end of the cell string CS. However, it is sufficient that the common source line CSL is electrically connected to the lower end of the cell string CS, and the example embodiments are not limited to the case where the common source line CSL is physically located at the lower end of the cell CS. At least one example embodiment may include cell strings CS arranged in a 4 by 4 matrix. However, the example embodiments are not limited thereto, and the number of cell strings CS and corresponding circuits in the memory block BLKa may be increased or decreased.

[0039] The cell string of each row may be connected to a corresponding one of the first to fourth ground selection lines GSL1 to GSL4 and a corresponding one of the first to fourth string selection lines SSL1 to SSL4. The cell string of each column may be connected to a corresponding one of the first to fourth bit lines BL1 to BL4. For ease of explanation, the cell strings connected to the second and third ground selection lines GSL2 and GSL3 or the second and third string selection lines SSL2 and SSL3 are depicted as blurred.

[0040] Each cell string CS may include at least one ground selection transistor GST connected to a corresponding ground selection line, a first dummy memory cell DMC1 connected to a first dummy word line DWL1, a plurality of memory cells MC respectively connected to a plurality of word lines WL1 to WL8, a second dummy memory cell DMC2 connected to a second dummy word line DWL2, and / or a string selection transistor SST respectively connected to a string selection line SSL, but example embodiments are not limited thereto. In each cell string CS, the ground selection transistor GST, the first dummy memory cell DMC1, the memory cell MC, the second dummy memory cell DMC2, and / or the string selection transistor SST may be connected in series with each other in a direction perpendicular to the substrate SUB, and may be sequentially stacked in a direction perpendicular to the substrate SUB, but example embodiments are not limited thereto.

[0041] In at least one example embodiment, in each cell string CS, one or more dummy memory cells may be arranged between the ground selection transistor GST and the memory cell MC. In each cell string CS, one or more dummy memory cells may be arranged between the string selection transistor SST and the memory cell MC. In each cell string CS, one or more dummy memory cells may be arranged between the memory cells MC. The dummy memory cell may have the same structure as the memory cell MC, and may not be programmed (e.g., programming is prohibited) or may be programmed differently from the memory cell MC. For example, when the memory cell is programmed to form two or more threshold voltage distributions, the dummy memory cell may be programmed to have a threshold voltage distribution range or a threshold voltage distribution with a number less than the number of threshold voltage distributions of the memory cell MC. However, example embodiments are not limited thereto.

[0042] Memory cells arranged at the same height from the substrate SUB or the ground selection transistor GST in the cell string CS may be electrically connected in common. Memory cells arranged at different heights from the substrate SUB or the ground selection transistor GST in the cell string CS may be electrically separated from each other. Figure 2 At least one example embodiment is established as memory cells of the same height being connected to the same word line. However, example embodiments are not limited thereto, and for example, memory cells of the same height may be directly connected to each other in a plane in which the memory cells are formed, or may be indirectly connected to each other through another layer such as a metal layer.

[0043] The memory cells corresponding to the string (or ground) selection line and the word line can constitute a page. The write operation and the read operation can be performed by page. In each page, each memory cell can store two or more bits. The bits written into the memory cells belonging to a page can form a logical page. For example, the k-th bit in the memory cells of each page can form the k-th logical page.

[0044] The memory block BLKa may be disposed at a three-dimensional (3D) memory array, but example embodiments are not limited thereto. The 3D memory array is monolithically formed in one or more physical levels of an array of memory cells MC having an active region arranged on a silicon substrate and circuits associated with the operation of those memory cells. The circuits associated with the operation of the memory cells MC may be located on or within such a substrate. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the 3D memory array.

[0045] According to at least one example embodiment of the inventive concept, a 3D memory array includes a vertical cell string CS (or NAND string) oriented vertically so that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trapping layer. Each cell string may also include at least one selection transistor located above the memory cell MC. The at least one selection transistor may have the same structure as the memory cell MC and may be formed monolithically with the memory cell MC.

[0046] Figure 3 is used to describe at least one example embodiment Figure 2 , but example embodiments are not limited thereto. Figure 3 is a diagram for describing an example of how threshold voltage distribution varies with specific degradation factors. Figure 3 , the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells. For ease of description, it is assumed that the memory cell is a single-level cell (SLC), but example embodiments are not limited thereto. The single-level cell has an erase state "E" or a program state "P", depending on the desired threshold voltage of the single-level cell. For ease of description, reference will be made to Figure 1 Reference numerals / symbols are used to describe Figure 3 .

[0047] refer to Figure 3(i) to (iii), the solid line indicates the initial state of the threshold voltage distribution. The erased state "E" and the programmed state "P" can be identified by using the initial read voltage Vr. In the initial state, a read margin sufficient to identify the erased state "E" and the programmed state "P" may exist between the erased state "E" and the programmed state "P".

[0048] The dashed lines indicate examples where the desired threshold voltage distribution changes due to degradation and / or defects of the nonvolatile memory device when using the storage device 100. For example, defects may occur at memory cells when manufacturing the storage device 100 and / or through use of the storage device 100. Defects (e.g., voltage and / or current leakage exhibited by one or more memory cells of the storage device 100, etc.) may occur due to degradation of the nonvolatile memory device 110 when using the storage device 100, and the degradation may cause the desired threshold voltage distribution of the memory cells to change.

[0049] refer to Figure 3 , the threshold voltage distribution (e.g., the expected threshold voltage distribution, etc.) may be changed in the direction of decreasing the threshold voltage corresponding to the programming state "P", but is not limited thereto. For example, if the operating temperature of the nonvolatile memory device 110 increases, the trapped charge of the memory cell may leak, and therefore, the threshold voltage of the memory cell having the programming state "P" may decrease. As a result, it is difficult to identify the erase state "E" and the programming state "P" by using the initial read voltage Vr. Therefore, the initial read voltage Vr may be adjusted to the first read voltage Vr1. The operating temperature of the nonvolatile memory device 110 may be a degradation factor that causes the threshold voltage to change and / or the memory device 110 to degrade.

[0050] refer to Figure 3, the threshold voltage distribution may be changed in the direction of increasing the threshold voltage corresponding to the erased state "E", but is not limited thereto. For example, if the number of times the memory cell is read increases, a charge trapping phenomenon may occur at the memory cell in the erased state "E" due to a read disturbance phenomenon, and therefore, the threshold voltage of the memory cell having the erased state "E" may increase. As another example, if the number of times the memory cell is written increases, the tunnel oxide of the memory cell may degrade, and therefore, the threshold voltage of the memory cell having the erased state "E" may increase. As a result, it is difficult to identify the erased state "E" and the programmed state "P" by using the initial read voltage Vr. Therefore, the initial read voltage Vr may be adjusted to the second read voltage Vrm. With respect to the nonvolatile memory device 110, the number of times a read operation is performed (hereinafter referred to as a "read count") and the number of times a write operation is performed (hereinafter referred to as a "write count") may be degradation factors that cause the memory cell to degrade and the threshold voltage of the memory cell to change.

[0051] refer to Figure 3 , the threshold voltage distribution of the erased state "E" and / or the programmed state "P" may change in a direction in which the threshold voltage distribution becomes wider, but example embodiments are not limited thereto. For example, in a case where the number of program / erase cycles of the nonvolatile memory device 110 increases and / or in a case where the retention time increases, the charge trapped in the memory cell may leak, causing the threshold voltage distribution to change. As a result, it is difficult to identify the erased state "E" and the programmed state "P" by using the initial read voltage Vr. Therefore, the initial read voltage Vr may be adjusted to a third read voltage Vrn, etc. With respect to the nonvolatile memory device 110, the number of program / erase cycles and / or the retention time may be degradation factors that cause the nonvolatile memory device 110 to degrade and / or the threshold voltage of the nonvolatile memory device 110 to change.

[0052] According to at least one example embodiment of the inventive concept, the storage device 100 may generate variation information based on a result of predicting a change in a read voltage due to one or more degradation factors (e.g., the degradation factors described above, etc.), and may determine a read voltage of a memory area intended for a read operation based on the variation information. The variation information may be determined by evaluating the nonvolatile memory device 110 for each of the operating conditions associated with one or more degradation factors (e.g., the degradation factors described above, etc.). The variation information will be described in more detail later.

[0053] Figure 4 is used to describe a method for Figure 2 Graph of changes in threshold voltage distribution of each word line of the memory cells shown in FIG. Figure 4 is a graph for describing an example of how the threshold voltage distribution for each word line varies with a specific degradation factor. Figure 4 , the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells. The memory cell may be a multi-level cell (MLC); for ease of description, only threshold voltage distributions corresponding to two programming states Pa and Pb are shown, but example embodiments are not limited thereto. Depending on the threshold voltage of the multi-level cell, the multi-level cell may have a first programming state Pa or a second programming state Pb. For convenience, reference will be made to Figure 1 Reference numerals / symbols are used to describe Figure 4 .

[0054] refer to Figure 4 , showing a threshold voltage distribution of memory cells connected to the first word line WL1, a threshold voltage distribution of memory cells connected to the second word line WL2, and a threshold voltage distribution of memory cells connected to the third word line WL3, but example embodiments are not limited thereto. With respect to the memory cells connected to the first word line WL1, the first programming state Pa and the second programming state Pb can be identified by using the first read voltage Vr1. With respect to the memory cells connected to the second word line WL2, the first programming state Pa and the second programming state Pb can be identified by using the second read voltage Vr2. With respect to the memory cells connected to the third word line WL3, the first programming state Pa and the second programming state Pb can be identified by using the third read voltage Vr3.

[0055] Even if the memory cells are included in the same memory block, the threshold voltage distributions of the memory cells may be different from each other. For example, the threshold voltage distributions corresponding to the first word line WL1 to the third word line WL3, respectively, may be different from each other. In this case, the improved and / or optimal read voltage for identifying the first programming state Pa and the second programming state Pb may vary for each word line. That is, the first read voltage Vr1 to the third read voltage Vr3 may be different from each other. In the case of providing the same read voltage to the memory cells included in the nonvolatile memory device 110, it may be more difficult and / or impossible to identify the first programming state Pa or the second programming state Pb with respect to the memory cells.

[0056] For example, the threshold voltage distribution of the memory cell may vary with and / or based on the location of the memory cell. Figure 2, considering the width of the pillar, the cross section parallel to the upper surface of the substrate SUB becomes smaller as the distance from the substrate SUB decreases. Therefore, when a voltage is provided to a memory cell adjacent to the substrate SUB through a word line, an electric field formed at the memory cell adjacent to the substrate SUB may be greater than an electric field formed at a memory cell far from the substrate SUB. This may have an impact on read interference and may cause different degradation states of each word line.

[0057] In addition, the degree of degradation due to various degradation factors (e.g., retention time, number of program / erase cycles, and / or temperature) may vary with the location of the memory cell, etc. Since the distance from the substrate, the width of adjacent pillars, etc. are almost uniform with respect to the memory cells connected to the same word line, the memory cells may have similar or identical degradation states. In addition, since the length of the word line is uniform or substantially uniform, the memory areas connected to different word lines may have a given correlation depending on the degradation state.

[0058] According to at least one example embodiment of the inventive concept, the storage device 100 may generate variation information based on the result of predicting the difference between the read voltages of the word lines, and may determine the read voltage of the memory area for the purpose of the read operation based on the variation information. The variation information may be determined by evaluating the change in the read voltage associated with various degradation factors for each word line. The variation information will be described in more detail later.

[0059] Figure 5 is a diagram showing a method according to at least one example embodiment Figure 1 The block diagram of the read voltage control module. Figure 5 , the read voltage control module 131 includes a state manager 131_1, an optimal read voltage manager 131_2 and / or a word line change manager 131_3, but the example embodiments are not limited thereto. The read voltage control module 131 can be loaded and executed on the buffer memory 130 under the control of the CPU 121, but the example embodiments are not limited thereto. For example, the read voltage control module 131 can be implemented as a separate circuit and / or processing device (e.g., an application specific integrated circuit (ASIC), a system on a chip (SoC), a field programmable gate array (FPGA), etc.), etc. For example, in the case where the read voltage control module 131 is implemented by firmware, the read voltage control module 131 can be stored in the non-volatile memory device 110. In this case, the read voltage control module 131 can be loaded onto the buffer memory 130 and can be executed by the CPU 121. Additionally, the read voltage control module 131 can be implemented with hardware such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). For ease of description, reference will be made to Figure 1 Reference numerals / symbols are used to describe Figure 5 .

[0060] The state manager 131_1 may predict and / or manage predicted values ​​of read voltages to be provided to a plurality of word lines, respectively, and may determine the predicted values ​​according to degradation (e.g., degradation condition and / or degradation state, etc.) of at least one memory block. The state manager 131_1 may receive state information SI from the buffer memory 130. The state information SI may include a plurality of pieces of state information related to a plurality of memory regions included in the memory block. Here, each of the plurality of memory regions may include memory cells connected to the same word line, but is not limited thereto.

[0061] The state information SI may include information related to the aging state of the non-volatile memory device 110. In addition, the state information SI may also include information related to the result of evaluating the change of the read voltage due to the degradation of the non-volatile memory device 110. The evaluation may be performed in advance (and / or in real time), and the evaluation associated with the change of the read voltage according to various degradation factors (e.g., program / erase count, retention time, and read interference) may be performed in advance and / or in real time for each memory area. For example, the memory controller 120 may not separately manage information related to the aging state and / or information related to the result of pre-evaluating the change of the read voltage. In this case, the memory controller 120 may only store the change information generated based on the state information SI.

[0062] For example, the state information SI may include information related to the state of the memory region based on the current degradation state. In at least one example embodiment, the memory controller 120 may store and update the program / erase count for each memory block of the nonvolatile memory device 110, the read count for each memory region, the temperature, the retention time, etc., which are managed to achieve wear leveling. The information of the current degradation state may be used to calculate the read voltage of the memory region to be read later.

[0063] The optimal read voltage manager 131_2 may set a desired read block voltage for each memory block. In the event of receiving a read request for a memory region included in a particular memory block, the read block voltage may indicate a voltage level to be referenced to calculate a read voltage for the corresponding memory region. The same read block voltage may be used within the same memory block.

[0064] The optimal read voltage manager 131_2 can search for an improved and / or optimal read voltage in order to generate a read block voltage. Here, the improved and / or optimal read voltage can be a set of read voltages that can make all program states identifiable without errors when performing a read operation on a specific memory area. For example, the improved and / or optimal read voltage can be a set of read voltages under which a previous read operation requested for a specific memory block was successful. The optimal read voltage manager 131_2 can generate and store a read block voltage based on the improved and / or optimal read voltage found. Example embodiments associated with generating a read block voltage will be described more fully later.

[0065] After setting the read block voltage, the storage device 100 may receive a read request from the host device. In this case, the optimal read voltage manager 131_2 may receive block information BI, which is information about the memory block corresponding to the read request. The optimal read voltage manager 131_2 may output the read block voltage of the memory block corresponding to the read request to the word line change manager 131_3 based on the block information BI.

[0066] The word line change manager 131_3 may generate and store change information based on a predicted value (e.g., a predicted value) of a read voltage, the predicted value being stored in the state manager 131_1 and corresponding to each memory region. The word line change manager 131_3 may extract correlations between memory regions based on degradation (e.g., degradation states and / or conditions of memory cells / memory regions, etc.), and may generate change information based on the extracted correlations. The change information may be implemented using a table, a relational expression (e.g., an expected relation, etc.), a decision tree, and / or weights of an artificial neural network, etc.

[0067] The word line change manager 131_3 may determine a read voltage of a memory area corresponding to a read request based on the set change information. The word line change manager 131_3 may calculate a read voltage by applying a read block voltage provided from the optimal read voltage manager 131_2 to the change information. To calculate the read voltage, position information of a word line corresponding to a memory area of ​​a read request and position information of a word line for generating a read block voltage may be used.

[0068] For example, the word line change manager 131_3 may calculate the correlation between the word line corresponding to the read block voltage and the word line intended for the read operation through the change information. A correction value of the read block voltage may be calculated based on the correlation. The word line change manager 131_3 may calculate the final read voltage by applying the correction value to the read block voltage. For example, in the case where the state manager 131_1 generates information related to the current degradation state, the word line change manager 131_3 may additionally consider the information generated thereby to calculate the read voltage. In order to provide the calculated read voltage to the relevant word line of the non-volatile memory device 110, the word line change manager 131_3 may provide the word line voltage information WI to the non-volatile memory device 110.

[0069] Figure 6 is a flowchart illustrating a data reading method of a storage device according to at least one example embodiment of the inventive concept. Figure 6 , the data reading method can be Figure 1 The memory controller 120 is executed, but the example embodiment is not limited thereto. For ease of description, reference will be made to Figure 1 Reference numerals / symbols are used to describe Figure 6 .

[0070] In operation S110 , the memory controller 120 may receive a read request from an external host device. The read request may be received through the host interface 124 .

[0071] In operation S120, the memory controller 120 may determine a memory block in the nonvolatile memory device 110 in which the data of the read request is stored. The memory controller 120 may search whether there is a desired and / or optimal read block voltage corresponding to the relevant memory block. For example, before receiving the read request, the desired and / or optimal read block voltage may be set based on the read voltage provided to the word line for which the read operation is successful. In the case where the read block voltage exists, the process proceeds to operation S130; in the case where the read block voltage does not exist, the process proceeds to operation S140.

[0072] In operation S130, the memory controller 120 may calculate a read voltage corresponding to the memory region of the read request based on the read block voltage and / or the variation information. For each memory region, the variation information may be generated based on a variation of the read voltage due to degradation (e.g., degradation state and / or condition, etc.). The memory controller 120 may calculate the read voltage by applying the variation of the read voltage due to degradation of the relevant memory region to the read block voltage.

[0073] In the absence of the read block voltage, the memory controller 120 may determine the read voltage as a desired and / or preset initial voltage in operation S140. Here, the initial voltage may be a default value selected by a user, or the like.

[0074] In operation S150, the memory controller 120 may perform a read operation based on the read voltage determined in operation S130 or operation S140. The memory controller 120 may provide a read command and an address to the nonvolatile memory device 110 so as to read the data of the read request. The nonvolatile memory device 110 may sense the data from the memory cell in response to the read command and the address. The sensed data may be output to the memory controller 120.

[0075] In operation S150, the memory controller 120 may determine whether the read operation performed is successful. For example, the memory controller 120 may determine whether an uncorrectable error correction code (UECC) is generated by detecting and correcting errors of the data read based on the determined read voltage using an error correction technique. The UECC may indicate a state in which an error that is not corrected by the error correction block 127 of the memory controller 120 is included in the read data. The error correction block 127 may detect the UECC while performing error correction decoding on the data received from the nonvolatile memory device 110. In the case where the UECC is detected, the process proceeds to operation S160. In the case where the UECC is not detected, it is determined that the read operation is successful, and thus the read operation is terminated.

[0076] Since the read operation is determined to be unsuccessful based on the detection of the UECC, in operation S160, the memory controller 120 corrects the read voltage in any other method. For example, the memory controller 120 may receive information related to the current degradation state of the nonvolatile memory device 110, and may correct the read voltage based on the current degradation state. For example, the memory controller 120 may perform a prediction mode created by machine learning of the read voltage according to the change in the degradation state, and may predict the read voltage based on the created prediction mode, but example embodiments are not limited thereto. The memory controller 120 may correct a preset read voltage (e.g., a preset read voltage) by using the predicted read voltage. The manner of correcting the read voltage is not limited thereto, and various manners such as decision trees, artificial neural networks, and correction of the read voltage based on empirical data may be used to correct the read voltage. The corrected read voltage may be managed by the memory controller 120 and may be stored in the buffer memory 130. The memory controller 120 may update the read block voltage based on the corrected read voltage.

[0077] Figure 7 It shows Figure 6A flowchart of at least one example embodiment of a data reading method. Figure 7 , the data reading method can be Figure 1 The memory controller 120 is executed, but is not limited thereto. Assume that Figure 1 The memory cell included in the nonvolatile memory device 110 is a multi-level cell, but is not limited thereto. The memory cell may have one of a plurality of programming states, and each of the plurality of programming states may be identified by using a first read voltage RP1 to a third read voltage RP3, etc. For ease of description, reference will be made to Figure 1 Reference numerals / symbols are used to describe Figure 7 .

[0078] In operation S210, a read operation may be performed on a memory region connected to the second word line WL2. Assume that the read operation performed on the memory region connected to the second word line WL2 is successful. Assume that a read voltage Vr2 corresponding to the memory region connected to the second word line WL2 is (aa, bb, cc).

[0079] In operation S220, the memory controller 120 may calculate a read block voltage Vro for a memory block to which the second word line WL2 and the third word line WL3 belong (e.g., the memory controller 120 may calculate a read block voltage Vro for a memory block connected to the second word line WL2 and the third word line WL3). Operation S220 may be performed after a read operation is performed on a memory region connected to the second word line WL2. The read block voltage may be set based on a read voltage provided to a memory region for which the read operation is successful. In other words, a new read block voltage may be set based on a read voltage for a successful read operation.

[0080] A read block voltage Vro may be generated based on the variation information. Figure 7 In the embodiment, the variation information may be managed in the form of a variation offset table Tb, but is not limited thereto. The variation offset table Tb may be created based on a predicted value of a change in a read voltage according to degradation (e.g., degradation state and / or degradation condition, etc.) of a memory block, and the read voltage may be provided to word lines corresponding to the memory blocks, respectively. The predicted value may be evaluated in advance (and / or in real time), and the predicted value may be generated by providing the conditions of various degradation factors (e.g., program / erase count and retention time) to the nonvolatile memory device 110.

[0081] The variation offset table Tb may be created based on the difference between the predicted value of the reference word line and the predicted values ​​of the remaining word lines. For example, assuming that the reference word line is the first word line WL1, the table value corresponding to the first word line WL1 (e.g., the first offset information) may be set to "0". The table value corresponding to the second word line WL2 (e.g., the second offset information) may be the relative difference between the predicted value corresponding to the first word line WL1 and the predicted value corresponding to the second word line WL2. The table value corresponding to the third word line WL3 (e.g., the third offset information) may be the relative difference between the predicted value corresponding to the first word line WL1 and the predicted value corresponding to the third word line WL3, etc. That is, the variation offset table Tb may indicate the relative relationship of the read voltages for the respective word lines according to a specific degradation condition (e.g., a specified range of program / erase counts).

[0082] Returning to operation S220, the read block voltage Vro may be calculated based on the variation offset table Tb. The read block voltage Vro may be calculated by applying the second offset information (e.g., 10, 0, -20) to the value of the read voltage Vr2 associated with the successful read operation (e.g., aa, bb, cc). The read block voltage Vro (e.g., aa-10, bb, cc+20) may be calculated by subtracting the second offset information (e.g., 10, 0, -20) from the read voltage Vr2 (e.g., aa, bb, cc).

[0083] In operation S230, the memory controller 120 may manage and store the calculated read block voltage Vro. The read block voltage Vro may be stored in the buffer memory 130. For example, the memory controller 120 may manage the location information of the word line used to generate the read block voltage Vro and the calculated read block voltage Vro, but example embodiments of the inventive concept are not limited thereto. Figure 7 In at least one example embodiment of the present invention, since the offset value of the variation offset table Tb has been applied to the stored read block voltage Vro, the position information of the word line may not be separately managed, but example embodiments are not limited thereto.

[0084] In operation S240, the memory controller 120 may calculate a read voltage for any other memory region based on the set read block voltage Vro and the variation offset table Tb. Assume that after performing a read operation on the memory region connected to the second word line WL2, a read operation is performed on the memory region connected to the third word line WL3. According to a read request for the memory region connected to the third word line WL3, the memory controller 120 may determine whether the read block voltage Vro exists.

[0085] exist Figure 7In the embodiment, since there is a read block voltage Vro, the memory controller 120 can calculate the read voltage by applying the third offset information (e.g., -5, -10, -5) included in the variation offset table Tb to the read block voltage Vro. The read voltage Vr3 (e.g., aa-15, bb, cc+15) can be calculated by adding the read block voltage Vro (e.g., aa-10, bb, cc+20) to the third offset information (e.g., -5, -10, -5). The memory controller 120 can perform a read operation on the memory area connected to the third word line WL3 based on the calculated read voltage Vr3.

[0086] By using the read block voltage Vro and the variation offset table Tb, not only can the change of the read voltage due to degradation be dealt with for each memory block, but also the change of the read voltage due to degradation can be dealt with for each word line. In addition, when the relative change of the read voltage according to degradation is managed for each word line by using the variation offset table Tb using the offset value, the resources used to control the read voltage can be reduced. In addition, when the read block voltage Vro is set based on the variation offset table Tb, the read voltage can be determined by a simple addition operation in a later and / or subsequent read operation. That is, the operation speed for determining the read voltage can be increased.

[0087] Figure 7 , it is shown that the read voltage is determined by using one variation offset table Tb, but according to at least one example embodiment, a plurality of variation offset tables may be provided to determine the read voltage. The plurality of variation offset tables may respectively correspond to conditions classified with respect to at least one of various degradation factors (e.g., retention time, temperature of the memory device, program / erase count, read count, and / or read disturb, etc.). In the case of using a plurality of variation offset tables, the variation offset table to be used may be selected based on at least one degradation condition, and thus, the accuracy of the read voltage may be increased.

[0088] Figure 8 is a diagram for describing a process of classifying tables when change information includes a plurality of tables according to at least one example embodiment. For example, each of the plurality of change offset tables may be Figure 7The change offset table Tb of the present invention is provided. However, the example embodiments of the present invention are not limited thereto. For example, each of the multiple tables may be associated with a value of a read voltage predicted based on degradation (e.g., degradation condition and / or degradation state, etc.) rather than being associated with a relative offset value for each word line. The process of classifying the tables may be performed at the storage device 100, but the example embodiments of the present invention are not limited thereto. For example, the tables may be classified by a separate test device, etc. In this case, the classification result may be set to the memory controller 120 of the storage device 100 and may be used for a read operation of the storage device 100, etc.

[0089] refer to Figure 8 , the read voltage of the nonvolatile memory device 110 is pre-evaluated according to the degradation, but is not limited thereto. The read voltage of the nonvolatile memory device 110 may be evaluated for each of the various degradation factors. The degradation factors may include, for example, at least one of program / erase count, read count, retention time, temperature, and / or read interference, etc. As a result of the evaluation, read voltage data RD classified according to the degradation condition may be generated. Depending on the programming state to be identified, the read voltage data RD may be divided into a plurality of read voltages RP1, RP2, ..., etc., and may be divided into memory areas corresponding to a plurality of word lines WL1, WL2, WL3 ...

[0090] The read voltage data RD may be classified into a plurality of groups according to the conditions of the degradation factors. First, depending on the conditions of the first degradation factor, etc., the read voltage data RD may be classified into a first read voltage data group RD1 and a second read voltage data group RD2. The number of data groups is for exemplary purposes only, and it may be understood that the number of data groups may be different from "2". In at least one example embodiment, the first degradation factor may be a program / erase count, but is not limited thereto. The read voltage data RD whose program / erase count is a first condition PE1 may be included in the first read voltage data group RD1, and the read voltage data RD whose program / erase count is a second condition PE2 may be included in the second read voltage data group RD2, but is not limited thereto.

[0091] For example, the first condition PE1 of the program / erase count may be a program / erase count less than a reference count, and the first read voltage data group RD1 may include the read voltage data RD evaluated under the first condition PE1. The second condition PE2 of the program / erase count may be a program / erase count not less than (e.g., greater than or equal to) the reference count, and the second read voltage data group RD2 may include the read voltage data RD evaluated under the second condition PE2. The reference count may be set randomly and / or as needed by the designer. Additionally, an improved and / or optimal reference count may be generated by applying clustering to the read voltage data RD. In at least one example embodiment, clustering may be performed by machine learning; in the presence of a large amount of data, a dimensionality reduction process for reducing the amount of data may be performed.

[0092] Depending on and / or based on the condition of a second degradation factor different from the first degradation factor, the first read voltage data RD1 and the second read voltage data group RD2 may be classified into a first read voltage sub-data group RDa to a fourth read voltage sub-data group RDd. The number of sub-data groups is for exemplary purposes only, and it is understood that the number of data groups may be different from "4". In at least one example embodiment, the second degradation factor may be a retention time, but is not limited thereto. In the first read voltage data group RD1, the read voltage data RD whose retention time is the first condition Ret1 may be included in the first read voltage sub-data group RDa, and the read voltage data RD whose retention time is the second condition Ret2 may be included in the second read voltage sub-data group RDb. In the second read voltage data group RD2, the read voltage data RD whose retention time is the first condition Ret1 may be included in the third read voltage sub-data group RDc, and the read voltage data RD whose retention time is the second condition Ret2 may be included in the fourth read voltage sub-data group RDd.

[0093] For example, the first condition Ret1 of the retention time may be a time less than the reference time, and the first read voltage sub-data group RDa and the third read voltage sub-data group RDc may include the read voltage data RD evaluated under the first condition Ret1. The second condition Ret2 of the retention time may be a time not less than (e.g., greater than and / or equal to) the reference time, and the second read voltage sub-data group RDb and the fourth read voltage sub-data group RDd may include the read voltage data RD evaluated under the second condition Ret2, but example embodiments are not limited thereto. The reference time may be randomly set by the designer and / or set as needed. Additionally, an improved and / or optimal reference time may be generated by applying clustering to the read voltage data RD. In at least one example embodiment, clustering may be performed by machine learning, etc., and dimensionality reduction may be performed if needed and / or necessary, but example embodiments are not limited thereto.

[0094] Each of the first read voltage sub-data group RDa to the fourth read voltage sub-data group RDd can be used to create a variation table. For each condition of the degradation factor, the representative value of each of the first read voltage sub-data group RDa to the fourth read voltage sub-data group RDd can be set to a value included in the variation table. Here, the representative value can be an average value, a central value and / or a modulus (i.e., the most frequently occurring value), etc., but the example embodiments of the inventive concept are not limited thereto. For example, various values ​​for selecting a read voltage can be set as representative values. In addition, in the case where the created table is a variation offset table, the predicted value included in the variation offset table can be set by subtracting a value corresponding to a reference word line (e.g., the first word line WL1) from the read voltage data.

[0095] Fig. 9 It shows Figure 6 A flow chart of at least one example embodiment of a data reading method. Fig. 9 Shown in the Figure 8 In the case where the plurality of change tables Tb1 to Tb3 are created by the process of reading data by using the plurality of change tables Tb1 to Tb3, however example embodiments are not limited thereto. Fig. 9 , the data reading method can be Figure 1 The memory controller 120 is executed, but is not limited thereto. Assume that Figure 1 The memory cell included in the nonvolatile memory device 110 is a multi-level cell, but is not limited thereto. The memory cell may have one of a plurality of programming states, and each of the plurality of programming states may be identified by using a plurality of read voltages (eg, a first read voltage RP1 to a third read voltage RP3). For convenience, reference will be made to Figure 1 Reference numerals / symbols are used to describe Fig. 9 .

[0096] In operation S310, a read operation may be performed on a memory region connected to the second word line WL2. Assume that the read operation performed on the memory region connected to the second word line WL2 is successful. Assume that a read voltage Vr2 corresponding to the memory region connected to the second word line WL2 is (e.g., aa, bb, cc).

[0097] In operation S320, the memory controller 120 may set the read block voltage Vro and may select a variation table for performing the following read operation. Figure 8 The process creates multiple variation tables Tb1 to Tb3. The memory controller 120 may compare the read voltage Vr2 corresponding to the memory area connected to the second word line WL2 with the read voltage of the second word line WL2, and the read voltage of the second word line WL2 is included in each of the first variation table Tb1 to the third variation table Tb3. A variation table having the most similar read voltage Vr2 may be selected based on the comparison result. However, the example embodiments of the inventive concept are not limited thereto. For example, the memory controller 120 may receive a current degradation state from the nonvolatile memory device 110, and may select a variation table that satisfies the condition of the current degradation state. In at least one example embodiment, it is assumed that the first variation table Tb1 is selected.

[0098] In operation S330, the memory controller 120 may calculate the read block voltage Vro. The read block voltage Vro may be calculated with reference to the first variation table Tb1 as the selected variation table. Operation S330 is similar to Figure 7 Operation S220 is substantially the same as that of the embodiment, and thus additional description will be omitted to avoid redundancy. The read block voltage Vro (e.g., aa-aa2, bb-bb2, cc-cc2) can be calculated by subtracting information related to the second word line WL2 (e.g., aa2, bb2, cc2) in the first variation table Tb1 from the read voltage Vr2 (e.g., aa, bb, cc).

[0099] In operation S340, the memory controller 120 may manage and store the calculated read block voltage Vro. The read block voltage Vro may be stored in the buffer memory 130. Operation S340 is similar to Figure 7 Operation S230 is substantially the same as that of the embodiment of the present invention, and thus additional description will be omitted to avoid redundancy.

[0100] In operation S350, according to the read request, the memory controller 120 may calculate a read voltage Vr3 of the memory area connected to the third word line WL3 based on the set read block voltage Vro and the selected first variation table Tb1. Operation S350 is similar to Figure 7Operation S240 is substantially the same as that of the first variation table Tb1, and thus additional description will be omitted to avoid redundancy. The read voltage Vr3 (e.g., aa-aa2+aa3, bb-bb2+bb3, cc-cc2+cc3) can be calculated by adding the information related to the third word line WL3 (e.g., aa3, bb3, cc3) in the first variation table Tb1 to the read block voltage Vro (e.g., aa-aa2, bb-bb2, cc-cc2).

[0101] Fig.10 It shows Fig. 9 Figure 1.2.1 shows the processing of the selection change table. Fig.10 , the read voltage Vr2 of the successfully performed read operation and the data in the first to third change tables Tb1 to Tb3 are shown as having numerical values. However, the numerical values ​​may be understood to be set for convenience of description and are not limited thereto. Figure 1 The process of selecting the change table is performed at the memory controller 120.

[0102] The read voltage Vr2 can be compared with the first to third variation tables Tb1 to Tb3, respectively. Figure 8 Since the read voltage Vr2 corresponds to the second word line WL2, the value included in the read voltage Vr2 can be compared with the value of the read voltage corresponding to the second word line WL2, and the value of the read voltage corresponding to the second word line WL2 is included in each of the first change table Tb1 to the third change table Tb3.

[0103] The memory controller 120 may calculate the result based on the comparison. The memory controller 120 may calculate the difference between the value included in the read voltage Vr2 and the value included in each of the first to third change tables Tb1 to Tb3. The difference may be expressed in absolute value. Since, for example, 50-65, 0-10, -30+30 are obtained as the result of comparing the read voltage Vr2 with the first change table Tb1, (for example, 15, 10, 0) may be obtained as the offset value corresponding to the first change table Tb1. Since, for example, 50-80, 0-20, -30+20 are obtained as the result of comparing the read voltage Vr2 with the second change table Tb2, for example, 30, 20, 10 may be obtained as the offset value corresponding to the second change table Tb2. Since, for example, 50-50, 0+10, -30+60 are obtained as the result of comparing the read voltage Vr2 with the third change table Tb3, for example, 0, 10, 30 may be obtained as the offset value corresponding to the third change table Tb1.

[0104] The calculated offset values ​​may be compared for each variation table. As a result of the comparison, a final variation table may be selected so as to calculate a read block voltage and a read voltage according to a following read request. In at least one example embodiment, the memory controller 120 may select a variation table based on a minMax operation, but is not limited thereto. In the case of using a minMax operation, the memory controller 120 may select a maximum value of an offset value in each of the first variation table Tb1, the second variation table Tb2, and the third variation table Tb3, and may select a variation table whose maximum value is the smallest.

[0105] refer to Fig.10 , since the maximum values ​​of the respective change tables Tb1 to Tb3 are 15, 30, and 30, the first change table Tb1 having the minimum maximum value of 15 may be selected. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the change table may be selected in various ways. For example, the final change table may be selected by calculating a cost function for each change table.

[0106] Fig.11 It shows Figure 6 A flow chart of at least one example embodiment of a data reading method. Fig.11 A method of setting a correlation according to a degraded word line by using a relational expression (eg, an expected relationship, etc.) and reading data by using a coefficient model CM for the relational expression is shown. Fig.11 , the data reading method can be Figure 1 The memory controller 120 is executed, but is not limited thereto. Assume that Figure 1 The memory cell included in the nonvolatile memory device 110 is a multi-level cell, but is not limited thereto. The memory cell may have one of a plurality of programming states, and each of the plurality of programming states may be identified by using a plurality of read voltages (eg, a first read voltage RP1 to a third read voltage RP3). For ease of description, reference will be made to Figure 1 Reference numerals / symbols are used to describe Fig.11 .

[0107] In operation S410, a read operation may be performed on a memory region connected to the second word line WL2. Assume that the read operation performed on the memory region connected to the second word line WL2 is successful. Assume that a read voltage Vr2 corresponding to the memory region connected to the second word line WL2 is, for example, aa, bb, cc.

[0108] In operation S420, the memory controller 120 may manage and store the read block voltage Vro. In at least one example embodiment, the read block voltage Vro is shown to be the same as the read voltage Vr2. However, example embodiments of the inventive concept are not limited thereto. For example, in the example Figure 7 or Fig. 9 In the case where an offset reference is provided in the memory controller 120 shown in , the memory controller 120 may calculate the read block voltage Vro by applying the offset reference to the read voltage Vr2, but is not limited thereto.

[0109] In operation S430, the memory controller 120 may calculate a read voltage for any other memory region based on the set read block voltage Vro and the coefficient model CM. For example, in response to a read request for a memory region corresponding to the third word line WL3, the memory controller 120 may calculate a read voltage Vr3 for the requested memory region.

[0110] The coefficient model CM may be created based on the correlation according to the degraded word lines. The correlation according to the degraded word lines may be defined as a relational expression. Fig.11 The case where the relational expression is represented by a linear expression is shown, but the example embodiment is not limited thereto and may be any type of expression (e.g., a geometric expression, etc.). The relational expression may be defined as, for example, "y=ax+b". In the relational expression, "x" may be the read block voltage Vro, "a" may be the slope, "b" may be the intercept, and "y" may be the read voltage Vr3 to be provided according to the read request. The slope and intercept may be set with reference to a coefficient model.

[0111] The memory controller 120 can search for a slope value and an intercept value from the coefficient model CM based on the word line corresponding to the read block voltage Vro and the word line corresponding to the memory area for the purpose of the read operation. For example, since the word line corresponding to the read block voltage Vro is the second word line WL2 and the word line corresponding to the memory area for the purpose of the read operation is the third word line WL3, the memory controller 120 can extract the slope value and the intercept value corresponding to these two word lines. The extracted slope value and the extracted intercept value can be applied to the relational expression. As a result, the read voltage Vr3 can be calculated.

[0112] In the case where the read voltage Vr3 is determined by using the coefficient model CM, the development of the variation of the read voltage can be considered in all degradation cases. Fig.11It is shown that the coefficient model CM includes a model associated with a slope and an intercept corresponding to a relational expression. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, various coefficient models CM may be provided for various conditions of degradation factors. In addition, in the case where the relational expression is a polynomial expression, the coefficient model CM may include more models depending on the number of coefficients of the polynomial expression, etc.

[0113] See also Figure 7 , Fig. 9 and Fig.11 , the change information can be implemented in the form of a change offset table Tb, a plurality of change tables Tb1 to Tb3, a coefficient model CM, etc. Additionally, the change information can be implemented in the form of a prediction model based on a decision tree, an artificial neural network, etc. In this case, the read voltage can be determined by considering the correlation between word lines that are not represented by a relational expression, and the read voltage can be actively determined during operation. In the case of using a decision tree or an artificial neural network, the read block voltage, the position information of the word line for setting the read block voltage, the position information of the word line corresponding to the memory area to be read, etc. can be input to the prediction model. In addition, the current degradation state can also be input to the prediction model.

[0114] According to at least one example embodiment of the inventive concepts, a storage device including a nonvolatile memory device and an operating method thereof may improve a success rate of a read operation by using variation information in which a change in an operating state due to degradation is considered for each word line.

[0115] While the inventive concepts have been described with reference to various example embodiments of the inventive concepts, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concepts as set forth in the following claims.

Claims

1. A storage device, comprising: A nonvolatile memory device comprising at least one memory block, the at least one memory block comprising at least a first memory region connected to a first word line and a second memory region connected to a second word line; as well as The memory controller is configured as: setting a read block voltage corresponding to the memory block based on a first read voltage to be supplied to the first memory area, setting variation information related to the first memory area, the second memory area, and the read block voltage based on a change in the read voltage of the first memory area and a change in the read voltage of the second memory area, and determining a second read voltage to be provided to the second memory region based on the change information, Wherein, the memory block further includes a reference memory area connected to a reference word line; The memory controller is further configured to: setting first offset information based on a difference between a predicted read voltage of the reference memory region and a predicted read voltage of the first memory region, and setting second offset information based on a difference between the predicted read voltage of the reference memory region and the predicted read voltage of the second memory region, The change information includes the first offset information and the second offset information.

2. The storage device according to claim 1, wherein: The memory controller is further configured to calculate the read block voltage based on the first read voltage and the first offset information.

3. The storage device according to claim 1, wherein: The memory controller is further configured to calculate the second read voltage based on the read block voltage and the second offset information.

4. The storage device according to claim 1, wherein: The change information includes a plurality of change tables, the plurality of change tables respectively corresponding to a plurality of conditions classified with respect to at least one degradation factor; as well as Each of the plurality of change tables comprises: first word line information generated based on a read voltage of the first memory area, the read voltage of the first memory area being set according to a corresponding condition for each of the plurality of change tables, and The second word line information is generated based on a read voltage of the second memory area, wherein the read voltage of the second memory area is set according to a corresponding condition for each of the plurality of change tables.

5. The storage device according to claim 4, wherein: The memory controller is further configured to select one of the plurality of variation tables based on the first read voltage and the first word line information included in each of the plurality of variation tables.

6. The storage device according to claim 5, wherein: The memory controller is further configured to: calculating the read block voltage based on the first read voltage and the first word line information included in the selected variation table; and The second read voltage is calculated based on the read block voltage and the second word line information included in the selected variation table.

7. The storage device according to claim 4, wherein: The memory controller is further configured to: detecting a degradation state of the memory block corresponding to the at least one degradation factor; and Based on the degradation state, one of the plurality of variation tables is selected.

8. The storage device according to claim 4, wherein: The at least one degradation factor includes at least one of a program / erase count, a read count, a retention time, a temperature, or a read disturbance of the memory block.

9. The storage device according to claim 1, wherein: the variation information includes coefficient information corresponding to a desired relationship between a read voltage of the first memory region and a read voltage of the second memory region; as well as The memory controller is further configured to calculate the second read voltage based on the expected relationship, the coefficient information, and the read block voltage.

10. The storage device according to claim 1, wherein: The memory controller is further configured to generate prediction model information by training an expected relationship between a read voltage of the second memory region and a read voltage of the first memory region; and The change information includes the generated prediction model information.

11. A method for operating a storage device, the method comprising: receiving, using a memory controller, a read request for a memory region connected to a target word line; searching, using the memory controller, for a read block voltage corresponding to a memory block included in the memory area in response to the read request; using the memory controller to set variation information based on predicted values ​​of read voltages, the read voltages being respectively supplied to a plurality of word lines of the memory region; as well as calculating, using the memory controller, a target read voltage to be provided to the target word line based on the read block voltage and the variation information, The memory block includes a first memory area and a second memory area. The step of using the memory controller to set the change information based on the predicted value of the read voltage includes: setting first offset information based on a difference between a predicted read voltage of a reference memory region and a predicted read voltage of the first memory region, and setting second offset information based on a difference between the predicted read voltage of the reference memory region and the predicted read voltage of the second memory region, The change information includes the first offset information and the second offset information.

12. The operating method according to claim 11, further comprising: Prior to receiving the read request, the read block voltage is set using the memory controller based on a read voltage provided to a word line corresponding to a successful read operation.

13. The operating method according to claim 11, further comprising: setting, using the memory controller, the variation information to include a variation offset table generated based on a difference between a predicted value of a read voltage supplied to a reference word line and predicted values ​​of read voltages respectively supplied to remaining word lines among the plurality of word lines; as well as The read block voltage is set using the memory controller based on the variation offset table and a read voltage provided to a word line corresponding to a successful read operation.

14. The operating method according to claim 11, further comprising: setting the variation information to include a plurality of variation tables respectively corresponding to a plurality of conditions classified with respect to at least one degradation factor using the memory controller; selecting, using the memory controller, one of the plurality of variation tables based on a read voltage supplied to a word line corresponding to a successful read operation; as well as The read block voltage is set based on the read voltage and the selected variation table using the memory controller.

15. The operating method according to claim 11, further comprising: using the memory controller, setting a desired relationship based on a correlation between predicted values ​​of the read voltages; as well as Using the memory controller, the change information is configured to include a coefficient model associated with the expected relationship.

16. The operating method according to claim 11, further comprising: In response to the target read voltage being provided to the target word line, determining, using the memory controller, whether a read operation associated with the memory region is successful.

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