Memory device and method of operating the same

Abstract

A memory device and an operating method thereof are disclosed. The number of consecutive write operations performed on a memory cell array or a portion thereof is monitored. When the number of consecutive write operations reaches a predetermined number, a corresponding check read operation can be performed. If the check read operation indicates that certain portions of the memory have been disturbed by writes, data in these portions can be refreshed to adjust the resistance state of the corresponding memory cells, thereby improving data reliability.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2018-0098075 filed in the Korean Intellectual Property Office on August 22, 2018, and U.S. Patent Application No. 16 / 415,244 filed in the U.S. Patent and Trademark Office on May 17, 2019, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor memory device (eg, a phase change memory device) that checks disturbance of program data, and a method of accessing the phase change memory device. Background Art

[0004] Semiconductor memories include nonvolatile memories, such as phase change memories, ferroelectric memories, magnetic memories, resistive memories, and flash memories (e.g., NAND flash memories). Some nonvolatile memories, such as phase change memories, are configured to change the resistance value of their memory cells through a heating process. When the phase change memory performs a set operation or a reset operation on its phase change memory cells, heat is generated at the corresponding phase change memory cells.

[0005] The heat generated at the phase change memory cell may have an undesirable effect on other phase change memory cells adjacent to the phase change memory cell being programmed. For example, if too much heat is transferred to the phase change memory cells adjacent to the memory cell selected for programming, an undesirable set operation or reset operation may occur, and the resistance values ​​of these adjacent phase change memory cells may be changed (i.e., disturbed). Repeated read operations of one or more rows of memory cells may also cause undesirable disturbances to the memory cells of adjacent rows. Summary of the invention

[0006] Embodiments of the inventive concept provide a semiconductor memory device (eg, a memory module, a controller, and / or a phase change memory device) having improved reliability by checking disturbance of adjacent or neighboring memory cells, a method of accessing the phase change memory device, and a system implementing the same.

[0007] In some examples, a semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of memory cell rows, each memory cell including a variable resistor including a material having a variable resistance; a plurality of word lines, each word line connected to a corresponding memory row; a control logic circuit configured to write data to the memory cell array and read data from the memory cell array; and a checker circuit configured to: in response to a write operation to a first memory cell row, cause a check read operation of a second memory cell row adjacent to the first memory cell row to determine whether a programming state of the second memory cell row indicates write interference to the programming state of the second memory cell row.

[0008] In some examples, the memory device can be a memory module and includes: a printed circuit board; a plurality of nonvolatile memory semiconductor chips, including a first nonvolatile memory semiconductor chip connected to the printed circuit board, each nonvolatile memory semiconductor chip including a memory cell array of nonvolatile memory cells, each nonvolatile memory cell including a variable resistor, the variable resistor including a material having a variable resistance, the nonvolatile memory cells being arranged in a plurality of memory cell rows, and a control logic circuit configured to write data to the memory cell array by changing the resistance of the memory cells in a selected memory cell row, configured to read data from the memory cell array by comparing the resistance of the memory cells in the selected memory cell row with a reference resistance value; and a controller connected to the printed circuit board and connected to the plurality of nonvolatile memory semiconductor chips through one or more buses of the printed circuit board, the controller including a checker circuit.

[0009] The checker circuit can be configured to perform a randomly spaced adjacent check (RINC), which includes, in response to a first write operation to a first memory cell row of a first non-volatile memory chip, performing a check read operation on a second memory cell row in the first non-volatile memory chip that is immediately adjacent to the first memory cell row to determine whether a programming state of the second memory cell row indicates a write disturbance to the programming state of the second memory cell row.

[0010] The checker circuit may be configured to perform a refresh operation on the second row of memory cells in response to determining that the programming state of the second row of memory cells indicates write disturb.

[0011] The disclosed embodiments include a nonvolatile semiconductor chip. For example, a phase change memory (PCM) semiconductor chip includes: a memory cell array, the memory cell array includes a plurality of memory cells arranged in a plurality of memory cell rows, each memory cell includes a phase change material having a variable resistance; a plurality of word lines, each word line connected to a corresponding memory row; a control logic circuit configured to write data into the memory cell array and read data from the memory cell array; and a checker circuit configured to: in response to a write operation to a first memory cell row, cause a check read operation of a second memory cell row immediately adjacent to the first memory cell row to determine whether a programming state of the second memory cell row indicates a write disturbance to the programming state of the second memory cell row.

[0012] A method of operating a memory device is also disclosed. According to one embodiment, a method includes: counting the number of consecutive write operations performed on a memory cell array or a portion of a memory cell array, the memory cell array including a plurality of memory cells arranged in a plurality of memory cell rows, each memory cell including a variable resistor, the variable resistor including a material having a variable resistance; causing a first write operation to a first memory cell row, wherein in response to the first write operation, the count of the number of consecutive write operations provides a counted number of consecutive write operations equal to or greater than a first value stored in a first register; determining whether the counted number of consecutive write operations is greater than or equal to a first value stored in the first register; in response to determining that the counted number of consecutive write operations is greater than or equal to the first value, causing a check read operation of a second memory cell row immediately adjacent to the first memory cell row; and determining whether a programming state of the second memory cell row indicates a write disturbance to the programming state of the second memory cell row based on the check read operation of the second memory cell row. The methods and associated operations described herein may be performed by a nonvolatile memory (e.g., a nonvolatile memory formed as an integrated circuit in a semiconductor chip or semiconductor package), a controller, a memory module, a solid-state memory, and a system employing the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects and features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0014] Figure 1 is a block diagram illustrating a memory module according to an embodiment of the inventive concept.

[0015] Figure 2 is a block diagram illustrating an exemplary nonvolatile memory device.

[0016] Figure 3 is a block diagram illustrating an exemplary memory bank.

[0017] Figure 4 is a block diagram showing a memory cell array.

[0018] Figure 5 is a diagram showing an example of a set pulse and a reset pulse that cause a set operation and a reset operation in a memory cell.

[0019] Figure 6 is a diagram showing an example in which the temperature of a resistance element is changed by a set pulse and a reset pulse.

[0020] Figure 7 is a diagram showing an example of a memory cell (eg, a resistance element of a memory cell).

[0021] Figure 8 is a diagram showing an example of performing a write operation on memory cells in a specific row.

[0022] Fig. 9 is a diagram showing an example of performing a weak reset operation on adjacent neighboring memory cells.

[0023] Fig.10 is a diagram showing an example of disturbance caused by two or more memory cell rows having an influence on a specific memory cell.

[0024] Fig.11 is a flowchart illustrating an exemplary method of operating a semiconductor device.

[0025] Fig.12 is a block diagram illustrating an exemplary controller according to an embodiment of the inventive concept.

[0026] Fig.13 is a diagram showing an example of a method of determining whether an error is caused by write disturbance.

[0027] Fig.14 is a diagram showing an example of performing a check read operation on a memory cell.

[0028] Fig.15 It shows that Fig.14 Figure 1 shows an example of a check read operation performed afterwards.

[0029] Fig.16 is a block diagram illustrating a computing device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0030] Exemplary embodiments of the present invention are described in detail below. However, embodiments may be embodied in many different forms and should not be construed as being limited to the various details of the exemplary embodiments set forth herein. These exemplary embodiments are merely examples, and many different embodiments and variations that do not require the details provided herein are possible. It should also be emphasized that the present disclosure provides the details of alternative examples, but the enumeration of such alternatives is not exhaustive. In addition, any consistency of the details between the exemplary embodiments should not be construed as requiring such details, and it is impractical to list each possible variation of each feature described herein. The language of the claims should be referenced when determining the requirements of the present invention.

[0031] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the inventive concept. Figure 1 The memory device includes a memory module 100, and in some implementations, can be used as a main memory, for example, the main random access memory of a computer or server. In some examples, the memory module 100 can be or form part of a solid-state drive of a computer and / or server (for example, forming a cloud data storage drive). The memory module 100 can be easily removed from the system in which it is implemented, for example, by a physical connector inserted into a corresponding slot of the system (for example, mating with an electrical connector). In some examples, the memory module 100 can be provided in the form of a memory card including a plurality of non-volatile memory devices (for example, memory chips) such as those described herein mounted on a printed circuit board 101 and protected within a resin encapsulation molding (not shown).

[0032] refer to Figure 1 , the memory module 100 includes a controller 110, first nonvolatile memory devices 121 to 129, second nonvolatile memory devices 131 to 139, and data buffers 141 to 149. The controller 110, the first nonvolatile memory devices 121 to 129, the second nonvolatile memory devices 131 to 139, and the data buffers 141 to 149 may each be embodied by one or more semiconductor chips, and may each be implemented with a different semiconductor package, and such semiconductor packages may be mounted on a printed circuit board 101. The printed circuit board 101 may provide signal and power connections (via lines of the printed circuit board 101) between the various semiconductor chips mounted thereon, and between the semiconductor chips of the memory module 100 and sources external to the memory module 100 (e.g., the memory controller 10).

[0033] Each of the first non-volatile memory devices 121 to 129 and the second non-volatile memory devices 131 to 139 may include one or more non-volatile memory semiconductor chips, such as flash memory (e.g., NAND flash memory) memory chips, phase change memory (PCM or PRAM) memory chips, magnetoresistive random access memory (MRAM) memory chips, ferroelectric random access memory (FRAM) memory chips, and / or resistive random access memory (ReRAM) memory chips. Resistive-based memories (e.g., PCM, MRAM, ReRAM, etc.) can program their memory cells to change the resistance of each memory cell (to represent one or more data bits that can be stored in the memory cell), which can then be detected to determine the resistance state of the memory cell, thereby extracting its data.

[0034] The controller 110 may receive an external address ADDRe, an external command CMDe, and an external control signal CTRLe from the memory controller 10 outside the controller 110. The external address ADDRe may be received in the form of an address signal set, and the external command CMDe may be received in the form of a command signal set.

[0035] The controller 110 may be connected to the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139 through the first data buses 151 and 152. The first nonvolatile memory devices 121 to 129 may correspond to the second nonvolatile memory devices 131 to 139, respectively. For example, one (e.g., 121) of the first nonvolatile memory devices 121 to 129 and a corresponding one (e.g., 131) of the second nonvolatile memory devices 131 to 139 may be commonly connected to one or more shared data buses of the first data buses 151 and 152, i.e., the same subset of the data buses. The shared common connections of a subset of the nonvolatile memory devices 121 to 129 and 131 to 139 may be exclusive to those nonvolatile memory devices and not shared by other nonvolatile memory devices 121 to 129 and 131 to 139 (e.g., a shared data bus connecting a first nonvolatile memory device 121 and a second nonvolatile memory device 131 to the controller 110 may be exclusive to the first nonvolatile memory device 121 and the second nonvolatile memory device 131 and not shared by the first nonvolatile memory device 122 to 129 and the second nonvolatile memory device 132 to 139).

[0036] Each of the first data buses 151 and 152 may include two or more data lines (e.g., 8) for transmitting an internal data signal DQi and one or more data strobe lines (e.g., 2) for transmitting an internal data strobe signal DQSi. Such data lines and data strobe lines may be connected to data buffers of the nonvolatile memory devices 121 to 129 and 131 to 139 and the controller 110 to which they are connected, and such data buffers including latches may be configured to latch the transmitted internal data signal DQi at a timing provided by the transmitted internal data strobe signal DQSi.

[0037] The controller 110 may be connected to the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139 through the first control lines 161 and 162. The first control lines 161 and 162 may be commonly connected to the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139.

[0038] The controller 110 may generate an internal address ADDRi according to an external address ADDRe, may generate an internal command CMDi according to an external command CMDe, and may generate an internal control signal CTRLi according to an external control signal CTRLe. The controller 110 may control the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139 by transmitting the internal address ADDRi, the internal command CMDi, and the internal control signal CTRLi via the first control lines 161 and 162 (e.g., as corresponding electrical signals on the first control lines 161 and 162).

[0039] The controller 110 may be connected to the data buffers 141 to 149 through the second data buses 153 and 154. The second data buses 153 and 154 may include a plurality of data lines and one or more data strobe lines to transmit data signals as described with respect to the first data buses 151 and 152. The controller 110 may control the data buffers 141 to 149 through the second control lines 171 and 172. The controller 110 may control the data buffers 141 to 149 by transmitting a buffer command BCOM to the data buffers 141 to 149 via the second control lines 171 and 172 according to the external command CMDe and the external control signal CTRLe. The data buffers 141 to 149 may be embodied as semiconductor chips.

[0040] The controller 110 may perform mutual conversion between the internal data signal DQi and the external data signal DQe. The controller 110 may include a buffer 111 for buffering (e.g., temporarily storing information) between the signals ADDRe, CMDe, CTRLe, and DQe communicated with the memory controller 10 and the signals ADDRi, CMDi, CTRLi, and DQi communicated with the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139.

[0041] The controller 110 may include a checker 112 (also referred to herein as a checker circuit) configured to perform a check read operation on the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139 and supplement integrity of data according to a result of the check read operation.

[0042] For example, the checker 112 may perform a random interval neighbor check RINC. The random interval neighbor check RINC may include an operation of checking the integrity of data stored in memory cells adjacent to the memory cell selected for access. Exemplary details of the random interval neighbor check RINC operation of the checker 112 will be described more fully later.

[0043] In this example, the memory controller 10 is connected to transmit the external address ADDRe, the external command CMDe, and the external control signal CTRLe directly to the controller 110 without using additional buffers interposed therebetween (although these additional buffers may be used in alternative implementations). In this example, the memory controller 10 is connected to transmit the external data signal DQe and the external data strobe signal DQSe to the controller 110 through the data buffers 141 to 149 (although such data buffers 141 to 149 need not be provided in other implementations). The memory controller 10 may act as a host of the memory module 100 and control access operations (e.g., read and write operations) of the memory module 100.

[0044] The memory controller 10 may identify the first nonvolatile memory devices 121 to 129 as one rank (e.g., a first rank), and may identify the second nonvolatile memory devices 131 to 139 as another rank (e.g., a second rank). The memory controller 10 may provide a command to the controller 110 to request the controller 110 to simultaneously access the nonvolatile memory devices belonging to one rank. The controller 110 may support queue-based access according to the request of the memory controller 10.

[0045] For example, when the memory controller 10 requests a write operation or a read operation with respect to the first queue (e.g., via a single command), the controller 110 may perform a write operation or a read operation on all non-volatile memory devices of the first queue (in this example, the first non-volatile memory devices 121 to 129). When the memory controller 10 requests a write operation or a read operation with respect to the second queue (e.g., via a single command), the controller 110 may perform a write operation or a read operation on all non-volatile memory devices of the second queue (in this example, the second non-volatile memory devices 131 to 139). Such queue-based access may be performed simultaneously on multiple (all or a subset) non-volatile memory devices of the corresponding queue (depending on design considerations, such access operations of non-volatile memory devices of the same queue may overlap in time or be initiated simultaneously in an interleaved manner).

[0046] The controller 110 may transfer the external data signal DQe provided for a write operation from the memory controller 10 to the first queue or the second queue as the internal data signal DQi. The controller 110 may transfer the internal data signal DQi read from the first queue or the second queue by a read operation to the memory controller 10 as the external data signal DQe.

[0047] Figure 2 is a block diagram showing a nonvolatile memory device 200 according to an embodiment of the present invention. Each of the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139 can be implemented as one or more nonvolatile memory devices 200 described herein, however, other nonvolatile memory devices can also be used. In an exemplary embodiment, the nonvolatile memory device 200 can be a phase change memory semiconductor integrated circuit chip. However, the nonvolatile memory device 200 is not limited to phase change memory, but can also constitute other types of nonvolatile memory (e.g., NAND flash memory). The nonvolatile memory device 200 in this example includes a memory bank array 210, an input and output buffer 220, an address buffer 230, a command buffer 240, a control logic block 250, a first demultiplexer 260 and a second demultiplexer 270.

[0048] The memory bank array 210 includes first to eighth memory banks 211 to 218. The first to eighth memory banks 211 to 218 each include a memory cell for storing data. The first to eighth memory banks 211 to 218 can perform read and write operations independently of each other, and these read and write operations can be performed simultaneously by some or all of the memory banks. The example shown shows a memory bank array 210 formed by eight memory banks, but the number of memory banks is not limited to 8.

[0049] The input and output buffer 220 may exchange the data signal DQ with a selected one of the first to eighth memory banks 211 to 218. Also, the input and output buffer 220 may exchange the data signal DQ and the data strobe signal DQS with an external device (eg, the controller 110).

[0050] As part of a read operation, the input and output buffer 220 may transmit a data signal DQ provided from a selected memory bank to an external device in synchronization with a data strobe signal DQS (which is generated when transmitting the data signal DQ to an external device and transmitted from the input and output buffer 220). During a write operation, the input and output buffer 220 may latch a data signal DQ provided from an external device in synchronization with a data strobe signal DQS transmitted from the external device, and transmit the latched data signal DQ to the selected memory bank. The operation of the input and output buffer 220 and the timing of such operation may be controlled by a control logic block 250 (a control signal line (not shown) between the control logic block 250 and the input and output buffer 220).

[0051] The nonvolatile memory device 200 may be used in each of the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139 of the memory module 100 described herein. In addition, the nonvolatile memory device 200 may be used in other memory systems, such as the memory systems described herein in which one or more nonvolatile memory devices 200 are directly accessed by the memory controller 10. Therefore, it should be understood that Figure 2 The data signal DQ and the data strobe signal DQS exchanged with the external device (device outside the nonvolatile memory device 200) and the input and output buffer 220 shown in FIG. 2 may constitute a communication method for the nonvolatile memory device 200. Figure 1 The internal data signal DQi and the internal data strobe signal DQSi (when used Figure 2 When the corresponding non-volatile memory device 22 implements the first non-volatile memory devices 121 to 129 and the second non-volatile memory devices 131 to 139), or constitutes Figure 1 The external data signal DQe and the external data strobe signal DQSe are described (when the nonvolatile memory device 200 is implemented in a memory system that provides direct access between one or more nonvolatile memory devices 200 and the memory controller 10). Figure 2 , and the corresponding description generally represent these two of the exemplary implementations as exchanging data signals DQ and data strobe signals DQS with external devices.

[0052] The address buffer 230 may receive an address ADDR from an external device. The address ADDR may include a row address RA, a column address CA, and a bank address BA and / or a bank group address BG. The address buffer 230 may transmit the bank information BG / BA of the received address ADDR to the control logic block 250. The bank information BG / BA may be a bank address (uniquely identifying one bank among the banks 211 to 218), a bank group address (identifying a subgroup of the banks 211 to 218), or a bank address and a bank group address.

[0053] The address buffer 230 may transfer the row address RA in the received address ADDR to the first demultiplexer 260. The address buffer 230 may transfer the column address CA in the received address ADDR to the second demultiplexer 270. The address buffer 230 may operate at appropriate timing under the control of the control logic block 250.

[0054] The command buffer 240 may receive a command CMD from an external device. The command buffer 240 may transfer the received command CMD to the control logic block 250. The command buffer 240 may operate at an appropriate timing under the control of the control logic block 250.

[0055] The control logic block 250 may receive bank information BG / BA from the address buffer 230. The control logic block 250 may receive a command CMD from the command buffer 240. The control logic block 250 may receive a control signal CTRL from an external device. The control logic block 250 may perform an operation in response to the bank information BG / BA, the command CMD, and the control signal CTRL.

[0056] For example, the control logic block 250 may control the timing of the operation of the input and output buffer 220, the address buffer 230, and the command buffer 240. The control logic block 250 may control the first demultiplexer 260 and the second demultiplexer 270 to selectively transmit the received row address RA and column address CA to one or more memory banks as identified by the memory bank information BA / BG. The control logic block 250 may control the operation of the first to eighth memory banks 211 to 218, such as a write operation or a read operation, in response to the received command CMD.

[0057] As described above, each of the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139 of the memory module 100 may be implemented with one or more nonvolatile memory devices 200. In such an exemplary embodiment, the address buffer 230, the command buffer 240, and the control logic block 250 may exchange data with an external device (which constitutes the controller 110 in this example). Figure 1As described above, other embodiments contemplate a memory system described herein in which the nonvolatile memory device 200 can be directly accessed by the memory controller 10. In such exemplary embodiments, the nonvolatile memory device 200 can exchange external addresses ADDRe, external commands CMDe, and external control signals CTRLe with an external device (which constitutes the memory controller 10 in this example). Figure 2 and the corresponding description generally represent these two of the exemplary implementations as exchanging addresses ADDR, commands CMD, and control signals CTRL with external devices.

[0058] The first demultiplexer 260 may receive the row address RA from the address buffer 230. Under the control of the control logic block 250, the first demultiplexer 260 may transmit the row address RA to one of the first to eighth banks 211 to 218 selected by the bank group information BG / BA received together with the command CMD.

[0059] The second demultiplexer 270 may receive the column address CA from the address buffer 230. Under the control of the control logic block 250, the second demultiplexer 270 may transmit the column address CA to one of the first to eighth banks 211 to 218 selected by the bank group information BG / BA received together with the command CMD.

[0060] Figure 3 is a block diagram showing a memory bank 300 according to an embodiment of the inventive concept. The memory bank 300 may be Figure 2 The memory bank 300 may include a memory cell array 310 , a row decoder 320 , a write driver and sense amplifier 330 , a gating block 340 , and a column decoder 350 .

[0061] The memory cell array 310 includes memory cells connected to word lines WL, bit lines BL, and source lines SL. For example, the memory cell array 310 may include memory cells arranged in rows and columns, each row of memory cells being connected to a corresponding word line WL. The memory cells in each column may be connected to a corresponding bit line BL and a corresponding source line SL. The memory cells in the memory cell array 310 may be phase change memory cells.

[0062] The row decoder 320 is connected to the word lines WL and is connected to the memory cell array 310 through the word lines WL. Figure 2When the row address RA is received by the first demultiplexer 260 of the row decoder 320, the row decoder 320 may decode the received row address RA to select one of the word lines WL identified by the received row address RA. The row decoder 320 may activate the selected word line, for example, by applying a selection voltage or a selection current to the selected word line. In general, a word line not identified by the received row address RA is not selected when selecting and activating the selected word line, and the row decoder 320 may apply a non-selection voltage or a non-selection current to each of the non-selected word lines.

[0063] The write driver and sense amplifier 330 are connected to the bit lines BL and the source lines SL, and are connected to the memory cell array 310 through the bit lines BL and the source lines SL. The write driver and sense amplifier 330 may include a plurality of write drivers and a plurality of sense amplifiers. The bit lines BL and the source lines SL may be arranged in pairs so that each bit line / source line pair (BL / SL) is connected to a corresponding one of the write drivers and a corresponding one of the sense amplifiers. In some embodiments, each write driver and each sense amplifier may be shared between two or more bit line / source line pairs (BL / SL) (and selectively connected to the two or more bit line / source line pairs via corresponding demultiplexers).

[0064] During a write operation, the write driver may write data to a selected memory cell connected to a selected word line by applying a voltage or current to a bit line BL or a source line SL. For example, the write driver may perform a set operation or a reset operation on selected memory cells (connected to a selected word line WL) to change the resistance values ​​of these selected memory cells, thereby writing data to the selected memory cells.

[0065] During a read operation, the sense amplifier can read data from a selected memory cell (connected to a selected word line WL) by sensing a voltage or current provided by a bit line BL and a source line SL pair. For example, the sense amplifier can perform a read operation on a selected memory cell to detect a resistance value of the selected memory cell, thereby reading data of the selected memory cell.

[0066] The gating block 340 may be connected to the write driver and sense amplifier 330 via a data line DL. The gating block 340 may be controlled by a column decoder 350. The gating block 340 may include a set of switches (e.g., a set of switches of a multiplexer / demultiplexer) that transmits a data signal DQ between the input and output buffer 220 and a selected one of the write driver and sense amplifier 330. For example, the gating block 340 may connect a selected subset of the write drivers and sense amplifiers 330 to the input and output buffer 220. In response to decoding a received column address CA, the column decoder 350 may select a subset of these write drivers and sense amplifiers.

[0067] The column decoder 350 may receive the column address CA from the second demultiplexer 270. The column decoder 350 may control the gating block 340 according to the column address CA. For example, according to the column address CA, the gating block 340 may select a write driver subset and a sense amplifier subset identified by the received column address CA to connect the write driver subset and the sense amplifier subset to the input and output buffer 220 via the gating block 340.

[0068] In some embodiments, the gating block 340 may be shared by adjacent memory banks. For example, the first to fourth memory banks 211 to 214 may share the first gating block 340, and the fifth to eighth memory banks 215 to 218 may share the second gating block 340. For memory banks that share the same gating block 340, the gating block 340 may select the same subset of write drivers and sense amplifiers 330 in those memory banks according to the received column address CA.

[0069] Figure 4 It shows Figure 3 FIG. 3 is a diagram of exemplary details of aspects of the memory cell array 310. Figure 4 , the memory cell array 310 includes a plurality of memory cells MC arranged in rows and columns. The 1st to nth row memory cells MC are connected to word lines WL1 to WLn, respectively. The 1st to mth column memory cells are connected to first to mth bit lines BL1 to BLm, respectively, and to first to mth source lines SL1 to SLm, respectively.

[0070] In this example, the memory cell MC is connected to one word line WL, one bit line BL, and one source line SL. Each memory cell MC includes a selection element SE and a resistance element RE. The selection element SE may be a switch and controlled by the corresponding word line, and may electrically connect the resistance element RE between the corresponding bit line BL and the corresponding source line SL. In this example, the selection element SE is a transistor controlled by the voltage of the word line to selectively connect the corresponding resistance element RE between the corresponding bit line BL and the corresponding source line SL.

[0071] The resistance element RE is a variable resistor and may have a resistance value that changes by a set operation or a reset operation. The resistance element RE may be connected between the corresponding bit line BL and the corresponding source line SL together with the selection element SE. The resistance element RE may include a phase change material (e.g., a chalcogenide such as GST) having a resistance value that changes according to the phase state of the phase change material.

[0072] In other embodiments, a diode may be used as the selection element SE instead of a transistor. In this case, the selection element SE and the resistance element RE of the memory cell MC may be connected in series between the corresponding word line and the corresponding bit line, and the source line SL may be omitted. As another example, the selection element SE may be omitted, and the resistance element RE of the memory cell MC may be connected between the corresponding word line and the corresponding bit line, and the source line may be omitted.

[0073] Figure 5 are diagrams showing the memory cells MC (eg, Figure 4 FIG. 10 is a diagram of examples of set pulses and reset pulses for set operations and reset operations in those described in the specification. Figure 5 In the figure, the horizontal axis represents time "T" and the vertical axis represents current "I".

[0074] refer to Figure 4 and Figure 5 , when a set operation is performed on the memory cell MC, a set pulse SP may be applied to the resistance element RE. When a reset operation is performed, a reset pulse RSP may be applied to the resistance element RE. The set pulse SP may be applied for a shorter duration than the reset pulse RSP. The amount of current applied to and flowing through the memory cell MC subjected to the set operation may be greater than the amount of current of the reset pulse RSP applied to and flowing through the memory cell MC subjected to the reset operation. It should be understood that although Figure 5A sequence of set pulses SP and reset pulses RSP generated over time is shown, but this is for illustrative purposes. Typically, each memory cell MC in a selected row of memory cells MC (connected to a selected word line WL) may be subjected to the application of a set pulse SP and a reset pulse RSP in the same write operation. For example, some of the selected memory cells in the selected row of memory cells MC may have corresponding set pulses SP applied thereto, while other memory cells in the selected memory cells MC (which may be all of the remaining memory cells in the selected memory cells or some of the remaining memory cells) may have corresponding reset pulses RSP applied thereto. Similarly, it should also be understood that Figure 6 The sequence of temperature changes of the memory cells MC shown in is for convenience of description.

[0075] Figure 6 is a diagram showing an example in which the temperature of the resistance element RE of the memory cell MC is changed by the set pulse SP and the reset pulse RSP. Figure 6 In FIG. 1 , the horizontal axis represents time “T” and the vertical axis represents temperature. The first line L1 indicates the temperature obtained by the resistance element RE of the memory cell MC due to the application of the set pulse SP, and the second line L2 indicates the temperature reached by the resistance element RE of the memory cell MC due to the application of the reset pulse RSP.

[0076] When the set pulse SP is applied, a large current flows through the resistance element RE for a relatively short duration. Therefore, during the relatively short duration, the temperature of the resistance element RE increases sharply. After the relatively short duration, the temperature of the resistance element RE drops sharply. Due to this temperature fluctuation caused by the set pulse SP, the phase change material of the resistance element RE is set to an amorphous state having a relatively high resistance value (compared with its crystalline state).

[0077] When the reset pulse RSP is applied, a small current flows through the resistance element RE for a relatively long duration (i.e., longer than the duration of the set pulse SP). Therefore, the temperature of the resistance element RE increases slowly and remains at a relatively low temperature (compared to the peak temperature reached during the application of the position pulse SP) for a relatively long duration. After the reset pulse RSP is applied, the temperature of the resistance element RE can be reduced relatively slowly. Due to this temperature fluctuation caused by the reset pulse RSP, the phase change material of the resistance element RE is set to a crystalline state with a relatively low resistance value (compared to its amorphous state). The maximum temperature of the resistance element RE obtained when the reset pulse RSP is applied is lower than the maximum temperature of the resistance element RE obtained when the set pulse SP is applied.

[0078] As described above, the set operation or reset operation of the memory cell MC is performed by generating a relatively high temperature by the memory cell MC during a relatively short duration or generating a relatively low temperature by the memory cell MC during a relatively long duration. Both the set operation and the reset operation generate a temperature higher than room temperature. When the set operation or the reset operation is performed by a specific memory cell, the temperature of the memory cells adjacent to the specific memory cell may also increase due to the heat generated at the specific memory cell.

[0079] In some cases, the temperature of the neighboring memory cell increases to such an extent that an undesired set operation or reset operation is caused, thereby interfering with the data stored in the neighboring memory cell. Specifically, the resistance of the resistance element RE of the neighboring memory cell may change from the resistance that was previously programmed via a write operation to the resistance element RE, and this changed resistance value may no longer represent the data (e.g., one or more data bits) stored by the neighboring memory cell via the write operation. Interference may reduce the integrity of the data stored in the neighboring memory cell. According to an embodiment of the inventive concept, the checker 112 (e.g., see Figure 1 ) can check the integrity of the data by performing a check read operation on adjacent (or neighboring) memory cells.

[0080] If the integrity of data stored in adjacent (or neighboring) memory cells is degraded, the checker 112 may perform subsequent operations to improve the integrity of the data. Thus, the reliability of the memory module 100 or the nonvolatile memory device 200 is improved.

[0081] Figure 7 1 is a diagram showing an example of the distribution of the resistance value "R" of the memory cell MC in the memory cell row. The resistance value "R" may be, for example, Figure 3 and Figure 4 ) is the resistance value of the resistance element RE of the memory cell MC in the memory cell MC row described above. Figure 7 In FIG. 5 , the horizontal axis represents the resistance value “R” of the memory cell MC, and the vertical axis represents the number of the memory cells MC.

[0082] like Figure 7 As shown, the memory cell MC in the memory cell MC row may have a first state S1 or a second state S2. When the memory cell MC is reset using a reset pulse RSP, the resistance element RE of the memory cell MC may obtain its crystalline state. The crystalline state may correspond to the first state S1 having a relatively low resistance value.

[0083] When a set operation is performed on a memory cell MC using a set pulse SP, the resistance element RE of the memory cell MC may be placed in its amorphous state. The amorphous state may correspond to a second state S2 having a relatively high resistance value.

[0084] The row decoder 320 can select a row of memory cells MC, such as a word line. Each write driver can selectively perform one of a set operation or a reset operation (depending on the data to be stored) by applying a set pulse SP or a reset pulse RSP to the memory cells connected to the write driver (e.g., via a bit line / source line BL / SL pair) in the selected memory cell row (connected to the selected word line WL), respectively.

[0085] By selectively performing a set operation or a reset operation on the memory cells MC in the selected row, the nonvolatile memory device 200 can adjust the resistance value “R” of each memory cell MC in the selected row to the first state S1 or the second state S2 , thereby storing data in the memory cells MC in the selected row.

[0086] The row decoder 320 may select a row to read data stored in the memory cells MC. The sense amplifiers may each apply a read voltage or a read current to corresponding memory cells MC connected to the sense amplifier (through corresponding bit line / source line BL / SL pairs) in the selected row.

[0087] The sense amplifier can measure the resistance value "R" of each memory cell MC by detecting a cell current or a cell voltage generated by a read voltage or a read current. When the resistance value "R" of the memory cell MC is lower than the reference resistance value RR, the sense amplifier can determine that these memory cells MC have the first state S1. The reference resistance value RR may be the resistance value RR used during a normal read operation of the memory cell MC (e.g., providing read data to the controller 110 in response to a request from a host such as the controller 10). Different reference resistance values ​​may be provided as different voltages, and the comparison of the resistance value "R" of the memory cell MC with the reference resistance value may be a comparison of a voltage in response to the resistance of the memory cell with a voltage representing the reference resistance value. Alternatively, current values ​​may be compared in a similar manner.

[0088] When the resistance value "R" of the memory cells MC is equal to or greater than the reference resistance value RR, the sense amplifier may determine that the memory cells MC have the second state S2. Figure 7The two states of the nonvolatile memory cell MC are represented by the first state, the memory cell MC having the first state can be associated with and represent a first binary value (i.e., "0" or "1"), and the memory cell MC having the second state can be associated with and represent a second binary value (i.e., other "0" or "1" independent of the first state). It should be understood that the nonvolatile memory cell can be programmed into more than two states to represent more than one bit of data. For example, a memory cell array (e.g., Figure 3 and Figure 4 310 in ) can form a multi-level cell array, which can be programmed to store two, three, four or more bits of data. It should be understood that the present invention is also applicable to non-volatile memory devices and systems implemented with such multi-level memory cells, and related methods.

[0089] Figure 8 3 is a diagram showing an example of writing data to a selected row of memory cells MC, wherein a set operation or a reset operation is performed on each memory cell MC in the selected row. In this example, the row decoder 320 has selected and activated the fifth word line WL5. Each write driver can perform a set operation or a reset operation on the corresponding memory cell MC of the fifth word line WL5.

[0090] As reference Figure 6 As described above, when the set pulse SP or the reset pulse RSP is applied to the memory cell MC of the fifth word line WL5, heat may be generated. The heat generated at the memory cell MC of the fifth word line WL5 may be transferred to the memory cells of the fourth word line WL4 and the sixth word line WL6 adjacent to (or adjacent to) the fifth word line WL5.

[0091] When heat is transferred to the memory cells MC of the fourth word line WL4 and the sixth word line WL6 , a weak reset operation may be performed on the memory cells MC of the fourth word line WL4 and the sixth word line WL6 .

[0092] Fig. 9 1 is a diagram showing an example of performing a weak reset operation on memory cells adjacent to memory cells programmed via a write operation (which may be referred to herein as "adjacent memory cells" for short, and may include memory cell rows immediately adjacent to a programmed memory cell row). Fig. 9 , the memory cells MC may be repeatedly weakly reset, and the resistance values ​​"R" of the memory cells MC may decrease from the second state S2 to the third state S3 and then to the fourth state S4. When the resistance values ​​"R" of the memory cells MC initially programmed to the second state S2 become lower than the reference resistance value RR, a read error may occur when data is read from a row including these memory cells MC.

[0093] In some examples, a weak set operation may be performed on adjacent neighboring memory cells. When the memory cells MC repeatedly undergo the weak set operation, the resistance value "R" of the memory cells MC increases. When the resistance value "R" of the memory cells MC initially programmed to the first state S1 becomes higher than the reference resistance value RR, a read error may occur when data is read from a row including these memory cells MC.

[0094] As described above, due to the non-volatile memory device 200 (reference Figure 2 ) performs a set operation or a reset operation on a specific memory cell MC, so interference with the state of the resistance value "R" of the adjacent adjacent memory cell MC may occur. If the interference accumulates to a certain level, a read error with respect to the data stored in the memory cell MC may occur, and the integrity of the data may deteriorate.

[0095] The above-mentioned interference that occurs when a set operation or a reset operation is performed on an adjacent word line during a write operation has been described. Therefore, the above-mentioned interference can be referred to as "write interference". However, the inventive concept is not limited to only write interference, and is applicable to memory cells MC interfered by other mechanisms. For example, the present invention can be directed to "read interference" (caused by reading data).

[0096] Fig.10 is a diagram showing an example of disturbance to a particular set of memory cells caused by other memory cells of two or more rows. Fig.10 , a first write operation including a first set operation and / or a first reset operation may be performed on the memory cells MC of the fifth word line WL5. The first write operation may cause write disturbance affecting the memory cells MC of the fourth word line WL4 and the sixth word line WL6.

[0097] A second write operation including a second set operation and / or a second reset operation may be performed on the memory cells MC of the third word line WL3. The second write operation may cause write disturbance affecting the memory cells MC of the second word line WL2 and the memory cells MC of the fourth word line WL4.

[0098] A third write operation including a third set operation and / or a third reset operation may be performed on the memory cells MC of the seventh word line WL7. The third write operation may cause write disturbance affecting the memory cells MC of the sixth word line WL6 and the memory cells MC of the eighth word line WL8.

[0099] As described above, the write operation of the third word line WL3 or the fifth word line WL5 may cause write disturbance affecting the memory cell MC of the fourth word line WL4. When the data stored in the memory cell MC of the fourth word line WL4 is damaged by the write disturbance, the write disturbance may be mainly attributed to the write operation on the third word line WL3 or mainly attributed to the write operation on the fifth word line WL5.

[0100] In this example, it is assumed that the write disturbance affecting the memory cell MC of the fourth word line WL4 can be attributed to the write operation of the third word line WL3. In this case, it can be expected that the data stored in the memory cells MC of both the second word line WL2 and the fourth word line WL4 are damaged by the write disturbance caused by the write operation on the third word line WL3.

[0101] The checker 112 may be configured to check the accumulated write disturbance of the memory cells MC of the adjacent word lines adjacent to the word line subjected to the write operation. For example, when the write operation is performed on the fifth word line WL5, the checker 112 may check the accumulated write disturbance of the memory cells MC of the fourth word line WL4 and the sixth word line WL6, each adjacent to the fifth word line WL5.

[0102] In this example, we assume that as a result of the check operation, the checker 112 can detect that the data stored in the memory cell MC of the fourth word line WL4 is damaged by the write disturbance. However, if the checker 112 only checks the memory cells of the word line immediately adjacent to the word line subjected to the write operation (in this example, WL5 is subjected to the write operation), the checker 112 will not be able to detect that the data stored in the memory cell MC of the second word line WL2 is damaged by the write operation.

[0103] The data stored in the memory cells MC of the second word line WL2 may be left alone in a damaged state and may continue to be damaged to such an extent that recovery based on error correction is no longer possible. Therefore, a portion of the data written to the nonvolatile memory device 200 may be permanently damaged.

[0104] In order to solve the above-mentioned problem, according to an embodiment conceived by the present invention, the checker 112 can be configured to perform a check read operation on the memory cells MC of the adjacent word line WL adjacent to the word line performing the check operation (for example, the adjacent word line of the second order) and the adjacent word line WL adjacent to the word line performing the write operation (for example, the adjacent word line of the first order).

[0105] According to an embodiment of the inventive concept, the checker 112 may be configured to perform a check-read operation on neighboring word lines including an n-th order neighboring word line (n is a positive integer) when a condition for performing the check-read operation is satisfied.

[0106] Fig.11 1 is a flowchart illustrating an operation method according to an embodiment of the present invention. The method may be implemented by a memory system (e.g., the memory module 100 described herein), or may be implemented by a semiconductor memory device (e.g., the memory module 100 and / or the non-volatile memory device 200 described herein). Figure 1 The following describes the memory module 100 and the non-volatile memory device 200, but it is also applicable to other implementations. Figures 1 to 4 and Fig.11 In operation S111, the controller 110 may perform a write operation including a set operation and / or a reset operation on the memory cells MC connected to the selected word line.

[0107] For example, the controller 110 can simultaneously perform set operations and reset operations on memory rows connected to the same word line (e.g., word lines identified by the same row address) at a selected storage body of the first nonvolatile memory devices 121 to 129 or at a selected storage body of the second nonvolatile memory devices 131 to 139.

[0108] In operation S112, the checker 112 of the controller 110 may determine whether a check condition is satisfied. For example, when the number of write operations performed on any specific memory bank of any one of the first nonvolatile memory devices 121 to 129 or the second nonvolatile memory devices 131 to 139 reaches a specific value, the checker 112 may determine that the check condition for checking the specific memory bank is satisfied.

[0109] When the check condition is not satisfied, the checker 112 does not perform the check read operation. Therefore, the write operation ends without performing the check read operation. When the check condition is satisfied, operation S113 is performed. In operation S113, the checker 112 may cause the controller 110 to perform a check read operation on the memory cells MC connected to at least one adjacent word line adjacent to the selected word line (selected during the write operation of step S111).

[0110] For example, the check read operation may be the same as a normal read operation. The controller 110 may perform the check read operation with respect to a specific memory bank of each of the first nonvolatile memory devices 121 to 129 or the second nonvolatile memory devices 131 to 139. The controller 110 may receive data read from the first nonvolatile memory devices 121 to 129 or the second nonvolatile memory devices 131 to 139.

[0111] In operation S114, the controller 110 may determine whether the number of bit errors of the received data is equal to or greater than a threshold value. When each nonvolatile memory device provides data having a number of bit errors less than the threshold value, the check read operation ends.

[0112] For example, the controller 110 may determine that the result of the check read operation indicates that the reliability of the data is high. Since the reliability of the data is high, the controller 110 may terminate the check read operation without performing subsequent operations to improve the reliability. When the number of bit errors of the data is high (e.g., the number of bit errors received from any non-volatile memory device is equal to or greater than a threshold), operation S115 is performed. In addition, when the number of bit errors of the data is identified as high in step S114, the memory cell row storing the data is identified as requiring a refresh operation (step S116). Note that in Fig.11 In the method of step S115 and step S116, the order of the refresh operation can be switched. In addition, as described below, the refresh operation in step S116 for each row identified as requiring a refresh operation in step S114 can be delayed and performed simultaneously. Fig.11 The remaining steps of the method (for example, the operation loop including steps S119, S114, S115, S117 and S118 can be repeatedly executed, and the refresh operation in S116 for each row of memory cells identified as requiring a refresh operation in S114 can be performed at a later time, such as during an idle time of the non-volatile memory device).

[0113] For example, the controller 110 may determine that the result of checking the read operation indicates that the reliability of the data is low. The controller 110 may perform operation S115 to perform subsequent operations to improve reliability. In operation S115, the controller 110 may check the write disturbance of the memory cell for which an unacceptable number of bit errors have been detected in S114.

[0114] For example, as referenced Fig. 9 As described above, the write disturbance may reduce the resistance value "R" of the memory cell in the second state S2 or increase the resistance value "R" of the memory cell in the first state S1. The controller 110 may determine whether the error is caused by the write disturbance by additionally performing a read operation (e.g., a check read operation) on the memory cells in which a large number of bit errors have been detected in step S114 (e.g., memory locations (e.g., memory cell rows) in which the number of bit errors is equal to or greater than a threshold value).

[0115] When a check read operation is performed on the same memory cell (e.g., adjacent identical memory cell rows) using different reference resistance values, the controller 110 can check whether the number of bit errors changes. For example, the memory cell row can be subjected to several check read operations (in a manner similar to a standard read operation using a reference resistance value RR) using different resistance values ​​as a reference, and three corresponding read data sets and the number of bit errors of each read data set are obtained by comparing each of the resistance values ​​"R" of the memory cell with (i) the reference resistance value RR, (ii) a first resistance value less than the reference resistance value RR, and (iii) a second resistance value less than the first resistance value. When the number of bit errors in the read data read from the memory cell obtained from each of these check read operations decreases in the order of (i) the read data obtained using the reference resistance value RR, (ii) the read data obtained using the first resistance value, and (iii) the read data obtained using the second resistance value, the controller 110 can determine that the error is caused by write disturbance.

[0116] In some examples, the controller 110 may use a comparison resistance value that increases relative to a reference resistance value RR to check whether the number of bit errors changes. For example, a memory cell row may be subjected to several check read operations that use different resistance values ​​as references, and three corresponding read data sets and the number of bit errors of each read data set are obtained by comparing each of the resistance values ​​"R" of the memory cell (i) with the reference resistance value RR, (ii) with a third resistance value greater than the reference resistance value RR, and (iii) with a fourth resistance value greater than the third resistance value. When the number of bit errors in the read data read from the memory cell obtained from each of these check read operations decreases in the order of (i) the read data obtained using the reference resistance value RR, (ii) the read data obtained using the third resistance value, and (iii) the read data obtained using the fourth resistance value, the controller 110 may determine that the error is caused by write disturbance.

[0117] When it is determined that the bit error is caused by write disturbance, the controller 110 may perform a first subsequent operation (e.g., operation S116) and a second subsequent operation (e.g., operations S117 to S119), wherein the first subsequent operation is used to correct the bit error caused by the write disturbance and the second subsequent operation is used to check for higher order write disturbances (which, as described herein, includes checking for write disturbances to other memory cell rows).

[0118] The first subsequent operation or the second subsequent operation may be performed immediately after the check read operation. For another example, the controller 110 may retain the first subsequent operation (S116) and / or the second subsequent operation (S117 to S119) so that the first subsequent operation or the second subsequent operation is performed during an idle time when no task is assigned to the non-volatile memory device by the memory controller 10 (e.g., there is no pending access operation that needs to be completed). As an example, Fig.11 The method can be Fig.11 The sequence shown is performed except that step S116 may be initially skipped for each row of memory cells identified in S114 as having an unacceptably high number of bit errors. The loop of operations of steps S119, S114 to S118 may be repeated (except for skipping S116) until Fig.11 The method terminates otherwise (for example, exactly at Fig.11 Before the "end" of step S114). After identifying multiple rows of memory cells that require refresh operations (e.g., rows identified each time step S114 determines as "yes"), the refresh operation of step S116 can be performed for each of these memory cell rows during the idle time. In some examples, the multiple rows identified as requiring refresh operations (due to repeated execution of step S114) can identify a block of memory cell rows to be refreshed (e.g., a continuous memory segment including multiple memory cell rows). For example, each memory cell row in a range of memory cell rows extending between the two outermost memory cell rows of all memory cell rows identified as being to be refreshed in step S114 (in a particular memory bank) can be identified as requiring a refresh operation. The range of memory cell rows to be refreshed can be the same as that in the execution of step S114. Fig.11 The range from the minimum row address to the maximum row address among the row addresses of all word lines identified as to be refreshed in step S114 during the method.

[0119] In operation S116, the memory cell MC may be subjected to a refresh operation. The refresh operation includes writing the data read by the check read operation (e.g., during S111 or S113) back to the same memory cell MC, wherein the bit errors of the data are corrected (e.g., data without bit errors). In some examples, the memory cell MC may be first erased (or initialized) by performing a reset operation or a set operation on all memory cells MC (e.g., an entire row of memory cells MC) from which data was previously read by the check read operation. Then, the bit error-corrected data may be written by selectively performing a set operation or a reset operation on the memory cells MC from which data was previously read by the check read operation. In some examples, the bit error-corrected data may be written in a single write operation to overwrite the data containing the bit error by selectively performing a set operation on some of the memory cells MC and selectively performing a reset operation on other memory cells MC (e.g., the remaining memory cells in the memory cells MC).

[0120] The controller 110 may control the operation of the nonvolatile memory device when performing the refresh operation of step S116. For example, the controller 110 may determine the number of bit errors of the data in steps S111 and S114, and detect which bits in the read data are error bits (e.g., obtained in S111 or S114) from the data read by the check read operation. The controller 110 may invert the logic state of the bit determined to be the error bit in the data, and perform a write operation on the nonvolatile memory device to store the bit error-corrected data in the memory cell MC (e.g., those memory cells having the corresponding read data containing the bit error). Therefore, the controller 110 may correct the bit error of the read data by selectively performing a set operation or a reset operation on the corresponding memory cell, inverting the logic state of the bit corresponding to the error bit in the data stored in the memory cell.

[0121] For example, the controller 110 may detect the data that should have the first state S1 (reference data) according to the data read by the check read operation. Figure 7 ) or a memory cell in the second state S2. The controller 110 may restore data of the detected memory cell by performing a set operation or a reset operation on the detected memory cell.

[0122] When it is determined in operation S117 that the error is not caused by write disturbance, the check read operation ends. When it is determined in operation S117 that the error is caused by the write operation, operation S118 is performed. In operation S118, the controller 110 may determine whether an end condition is satisfied. The end condition may be a condition that allows the controller 110 to terminate the check read operation, otherwise the check read operation will be performed even if it is performed.

[0123] For example, when the operation loop of steps S119, S114 to S117 has been performed a predetermined number of times, when the refresh operation attempted to be performed in accordance with operation S116 is unsuccessful (e.g., the check read operation for checking successful writing of data without bit errors due to multiple write operations in step S116 has been performed a predetermined number of times but the data without bit errors has not been successfully written), and / or the controller 110 determines that other operations to be performed by the non-volatile memory device (e.g., access operations to the non-volatile memory device due to a request from the host) are more appropriate than continuing. Fig.11 The end condition of S118 may be satisfied when the method is to perform further check read operations and refresh operations according to the operation loop of steps S119, S114 to S117. In some examples, the end condition may be satisfied when the address (or physical location) at which the write operation is performed or the address (or physical location) at which the check read operation is performed belongs to a specific range (e.g., as identified by one or more registers of the controller 110) or corresponds to a boundary of a memory bank of the non-volatile memory device.

[0124] When the end condition is met, Fig.11 The inspection read method ends. When the end condition is not met, step S119 is executed. In operation S119, the checker 112 may instruct the controller 110 to perform an inspection read operation on the memory cell MC connected to the adjacent word line of the next sequence. The inspection read operation may be performed by comparing the resistance value of each memory cell MC with the reference resistance value RR. The adjacent word line of the next sequence may be the word line closest to the selected word line (in S111), which is located (i) on the same side of the selected word line as the adjacent word line that was initially subjected to the inspection read operation (in S113), and (ii) is an odd word line away from the selected word line (S111).

[0125] After performing the check read operation on the memory cell MC connected to the next sequential adjacent word line (next sequential memory cell row), the controller 110 may perform operation S114 again. That is, the number of bit errors may be detected based on the result of the next sequential check read operation, and whether the bit errors are caused by write disturbance may be checked. In the case where the number of bit errors in the data read from the next sequential adjacent word line is equal to or greater than the threshold value (S114) and it is determined that the bit errors are caused by write disturbance (S117), the operation loop of steps S119, S114 to S117 may be repeatedly performed for the next sequential adjacent word line to perform the corresponding check read operation and refresh operation.

[0126] Therefore, for word lines located on one side of the selected word line (e.g., selected for the write operation in S111), the check read operation and the corresponding refresh operation can be sequentially performed for word lines that are odd word lines away from the selected word line (S111). It should also be understood that the continuation of the operation loop of steps S119, S114 to S117 has been described with respect to the word lines located on one side of the selected word line (in S111). However, when operation S113 includes a check read operation for each word line that is immediately adjacent to the selected word line (in S111) (e.g., located on both sides of the selected word line (in S111), or located on four sides of the selected word line (e.g., in a 3D memory cell array)), the operation loop of steps S119, S114 to S117 can be performed separately for each word line set in the selected word line (in S111) corresponding to the side on which the initial check read operation of the immediately adjacent word line is performed in step S113.

[0127] For example, assume that a bank of a nonvolatile memory device includes n word lines WL1 to WLn, where n is an integer (eg, Fig.10 , Fig.14 and Fig.15, n=8, but n can be an integer greater than 8, such as 1024 or greater or 2048 or greater, etc.). Each of the n word lines can be individually activated by a row decoder of the memory body in response to a corresponding row address (e.g., provided by the controller 110) that uniquely identifies the word line to provide access to a row of memory cells connected to the activated (selected) word line. Assume that in operation S111, word line WLs is selected for a write operation, where s is an integer from 1 to n, and WLs is one of WL1 to WLn. In this example, word line WL(s+1), which is an adjacent word line to the selected word line WLs, is subjected to a check read operation (S113), and its bit error is compared with a threshold value (S114), checked for write disturbance (via the operation of S115), refreshed (S116), and its bit error (e.g., obtained from multiple check read operations using different read resistance values ​​in S115) is analyzed to determine whether the bit error originates from write disturbance (S117). Assuming the bit error is determined to be due to write disturbance (and the end condition is not met in S118), step S119 can be performed with respect to WL(s+p), where p=(2i-1), where i is an integer that is initially equal to one (1) and that increments each time the operation loop of S119, S114 to S117 is performed with respect to that particular side of the selected word line WLs (i.e., each time a check read operation in S119 is determined to be performed for the next sequential word line among those on the same side of the selected word line WLs (e.g., the word line WL(s+1) that is immediately adjacent to the selected word line WLs that was subjected to the initial check read operation of S113)).

[0128] As noted, word lines on multiple sides of the selected word line WLs may be checked for write disturbance and refreshed as appropriate. Thus, S113 may also include performing a check read operation on a word line (word line WL(s-1)) that is immediately adjacent to the selected word line WLs on the other side of WLs (compared to WL(s+1)). Steps S114, S115, S116, and S117 may also be performed with respect to WL(s-1). Assuming the bit error is determined to be due to write disturbance (and the end condition is not met in S118), step S119 can be performed with respect to WL(sp), where p = (2i-1), where i is an integer that is initially equal to one (1) and that increments each time the operation loop of S119, S114 to S117 is performed with respect to that particular side of the selected word line WLs (i.e., each time a check read operation in S119 is determined to be performed on the next sequential word line among those on the same side of the selected word line WLs (e.g., the word line WL(s-1) that is immediately adjacent to the selected word line WLs that was subjected to the initial check read operation of S113)). Therefore, the operation loops of S119, S114, S115, S116 and S117 can be repeated separately for each side of the selected word line WLs (in S111), and therefore, multiple operation loops can be performed sequentially (or the steps can be performed in an interleaved manner), and the termination of one operation loop may not require the termination of another operation loop.

[0129] Therefore, for word lines located on one side of a selected word line (e.g., selected for a write operation in S111), a check read operation and a corresponding refresh operation can be sequentially performed for word lines that are odd word lines away from the selected word line (S111), while avoiding the same check read operation and further evaluation described with respect to steps S119, S114 to S117 for word lines that are even word lines away from the selected word line (in S111).

[0130] However, it should be understood that it may be desirable to perform a refresh operation for a word line spaced apart from the selected word line (in S111) by an even number of word lines for any such word line located between two word lines that have been subjected to a refresh operation in S116 (and are spaced apart from the selected word line (in S111) by an odd number of word lines) and / or in S117 where a bit error is considered to be caused by a write operation (and are spaced apart from the selected word line (in S111) by an odd number of word lines). For such word lines spaced apart from the selected word line (in S111) by an even number (i.e., an odd number of word lines are inserted between these word lines and the selected word line (in S111)), a single read operation, bit error detection, and bit error correction (in order to implement a corresponding refresh operation) may be performed. However, the operations of steps S114, S115, and / or S117 may be omitted. For example, when performing a refresh operation on a word line that is spaced an even number apart from the selected word line (in S111), one or more or all of the following operations may be avoided: determining to perform a refresh operation based on the number of bit errors (S114), checking for write disturbance and / or performing multiple read operations on the word line using multiple read values ​​(S115), and determining whether the bit error is caused by write disturbance (S117). In the example discussed above, the word lines that are spaced an even number apart from the selected word line are WL(s+p) and WL(sp), where p=(2i) (and where, for each side of the selected word line WLs, i is an integer equal to 1 to the number of operation loops S119, S114 to S117 performed as described above).

[0131] As described above, according to an embodiment of the inventive concept, the memory module 100 can perform a check read operation when a check condition is satisfied. In the case where the number of bit errors caused by write disturbance is detected to be equal to or greater than a threshold value according to the result data of the check read operation, a check read operation of the next order is performed. Therefore, the reliability of the data stored in the memory cell MC is improved.

[0132] The above mentioned Figures 1 to 11 The embodiment of FIG. 1 describes the checker 112 as a part of the controller 110. However, the checker 112 may be arranged in Figure 2 The control logic block 250 of the non-volatile memory device 200 is shown in FIG. Figure 1100 in the embodiment of the present invention), each of the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139 may include a checker 112, which is configured to automatically perform the check read operation and the refresh operation described herein (for example, without control or receiving instructions from an external source (for example, from the controller 110)). Therefore, a plurality of checkers 112 may be provided, each of which is formed in a nonvolatile memory semiconductor chip (for example, when each of the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139 is formed as a semiconductor chip). When the checker is implemented in a nonvolatile memory semiconductor chip, bit error detection and bit error correction may be performed on the chip (an on-chip ECC circuit is provided in each nonvolatile memory semiconductor chip). In some examples, checkers 112 may be provided on-chip, each checker 112 being part of a corresponding non-volatile memory semiconductor chip, wherein each checker does not include a random number generator 116, but instead obtains a random number RN from an external source (e.g., the random number generator 116 of the controller 110) or obtains a sequence of numbers (which may or may not be random) (e.g., numbers programmed in a register of the non-volatile memory semiconductor chip).

[0133] Fig.12 is a block diagram illustrating a controller 110 according to an embodiment of the inventive concept. Figure 1 and Fig.12 , the controller 110 includes a buffer 111 , a checker 112 , a physical block 113 , and an error correction block 114 .

[0134] The buffer 111 is configured to store data to be written to one or more of the first and second nonvolatile memory devices 121 to 129 and 131 to 139 and store data read from one or more of the first and second nonvolatile memory devices 121 to 129 and 131 to 139 .

[0135] Data to be transferred from the buffer 111 to the first nonvolatile memory devices 121 to 129 or the second nonvolatile memory devices 131 to 139 may be encoded by an error correction code ECC driven by the error correction block 114. Data transferred from the first nonvolatile memory devices 121 to 129 or the second nonvolatile memory devices 131 to 139 to the buffer 111 may be decoded by the error correction block 114.

[0136] The error correction block 114 (which may also be referred to herein as an error correction circuit or an ECC circuit) may perform error correction encoding to add error correction parity bits (e.g., parity check codes) to the data. The error correction block 114 may perform error correction decoding in a conventional manner using the data and the error correction parity bits, and may detect and correct bit errors. The data transmitted from the buffer 111 to the non-volatile memory devices 121 to 129 and 131 to 139 and received from the non-volatile memory devices 121 to 129 and 131 to 139 may be in the form of a codeword (originally generated by the encoding operation of the error correction block 114). The codeword may take various conventional forms. The codeword may include a portion of the data provided in the original format of the data (e.g., a codeword with an ECC check code (e.g., a parity check code) attached thereto) before being encoded by the error correction block 114, or the codeword may contain data in a modified format.

[0137] The physical block 113 may communicate with the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139 to control them. The physical block 113 may include an interface (e.g., an input / output buffer and a driver) of the controller 110, and exchange internal data signals DQi and internal data strobe signals DQSi with the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139 through the first data buses 151 and 152.

[0138] The physical block 113 may transmit an internal address ADDRi, an internal command CMDi, and an internal control signal CTRLi to the first nonvolatile memory devices 121 to 129 or the second nonvolatile memory devices 131 to 139 through the first control lines 161 and 162 .

[0139] The checker 112 includes a logic block 115, a random number generator 116, a counter circuit 117, and a comparator circuit 118. The logic block 115 may control the operation of the checker 112 and may determine whether the number of bit errors of the read data indicates that the memory cell row should be refreshed. The counter circuit 117 may include a plurality of counters, each of which provides a count CNT associated with a corresponding one of the nonvolatile memory devices 121 to 129 and 131 to 139. When a write operation (e.g., a set operation and / or a reset operation) is performed with respect to a specific memory bank of the first nonvolatile memory device 121 to 129 or the second nonvolatile memory device 131 to 139, the logic block 115 may cause the counter circuit 117 to increase the count CNT corresponding to the specific memory bank. For example, if each of the nonvolatile memory devices 121 to 129 and 131 to 139 includes 8 memory banks, the counter circuit 117 may include seventy-two (72) counters, each of which provides a count that tracks the number of write operations of the corresponding memory bank.

[0140] The random number generator 116 may include a pseudo-random number generator and may generate a set of random numbers RN. The number of random numbers RN may correspond to the number of memory banks of the first non-volatile memory device 121 to 129 and the second non-volatile memory device 131 to 139 (e.g., initially generating seventy-two (72) random numbers RN, each for a memory bank). The random number generator 116 may include a plurality of registers that may store the generated random numbers RN. The random number generator 116 may provide the random numbers RN corresponding to the memory banks to the comparator circuit 118. The random used in the present disclosure includes pseudo-random. In the present disclosure, if the value of a number responds to a random number (which may be a pseudo-random number generated by a pseudo-random number generator), the number is considered to be a random number RN. For example, each random number RN may be randomly selected from a predetermined set of integers (e.g., integers within a predetermined range), and the selection thereof is determined by the generated random number. In some examples, the selections from the predetermined set of integers may be weighted to increase the chances of selecting certain integers over other integers (the selections being determined by the generation of the random numbers) to target and / or generate an average of the random numbers RN generated sequentially for any one particular memory bank. In some examples, the digital output of the generator 116 may not be a random number, but rather a number or sequence of numbers stored in a register of the generator 116.

[0141] The counter circuit 117 may provide a number of counts CNT equal to the number of random numbers RN (e.g., corresponding to the number of memory banks of the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139). Under the control of the logic block 115, the counter circuit 117 may increase the count of the memory bank when the memory bank performs a write operation. The counter circuit 117 may provide the count CNT of the memory bank to the comparator circuit 118.

[0142] The comparator circuit 118 may compare the count CNT with the corresponding random number RN. The comparator circuit 118 may include a plurality of comparators, each of which corresponds to one of the memory banks in the first nonvolatile memory devices 121 to 129 and the second nonvolatile memory devices 131 to 139, and each of which includes an input of the count CNT and the random number RN corresponding to the memory bank corresponding to the comparator. When a specific count CNT reaches the corresponding random number RN, the corresponding comparator of the comparator circuit 118 may activate the enable signal EN associated with the specific count CNT. When the enable signal EN is activated, the logic block 115 may enter a check read mode and initiate a check read operation for the memory bank associated with the comparator that activated the enable signal EN (e.g., as described herein, for example, with respect to Fig.11As described above). Therefore, the memory bank associated with the comparator that activates the enable signal EN can be selected for the check read operation. Activating the enable signal EN can also reset the counter associated with the memory bank and cause the random number generator 116 to generate and store a new random number RN for the memory bank (thereby restarting to monitor the number of write operations of the memory bank to initiate a check read operation for the memory bank later when the memory bank performs another random number of write operations).

[0143] The logic block 115 may communicate with the memory bank selected for the check read operation via the physical block 113 to perform the check read operation on the selected memory bank (eg, Fig.11 For example, when the result data of the check read operation is received through the physical block 113, the received data may be provided to the error correction block 114 to perform error detection on the received data, and the logic block 115 may obtain the number of bit errors in the received data from the error correction block 114. When the number of bit errors is equal to or greater than the threshold, the logic block 115 may identify the memory cell row from which the data is read as requiring a refresh operation, and also perform a further read operation on the selected memory bank (communicated via the physical block 113) to determine whether the bit error is caused by write disturbance.

[0144] The logic block 115 may obtain information about whether the number of bit errors changes when a read operation is performed using different resistance reference values ​​based on the corresponding number of bit errors provided by the error correction block 114 for each corresponding read data. The logic block 115 may determine whether the bit error is caused by write disturbance based on the change in the number of bit errors. When it is determined that the bit error is caused by write disturbance, the logic block 115 may perform a next sequential check read operation on the selected memory bank.

[0145] When the number of bit errors is equal to or greater than the threshold value, the logic block 115 may perform a refresh operation on the corresponding memory cell as described herein. When the check read operation ends or is completed, the logic block 115 may cause the counter circuit 117 to reset or initialize a specific count associated with the selected storage body. In addition, the logic block 115 may cause the random number generator 116 to generate a random number associated with the selected storage body (and compared with the count associated with the selected storage body). Therefore, the check read mode of the logic block associated with the selected storage body may be terminated. It should be understood that the logic block may enter the check read mode for several storage bodies at the same time.

[0146] As described above, when the number of set operations or reset operations performed on a specific memory bank reaches a random number, the checker 112 can perform a check read operation on the specific memory bank. When performing the check read operation, the random number is updated. Therefore, the checker 112 can perform a random interval adjacent check RINC.

[0147] Although not in Fig.12 , but the controller 110 may also include a separate physical block for communicating with the memory controller 10. The buffer 111 may also be configured to store an external address ADDRe, an external command CMDe, and an external control signal CTRLe received through a separate physical block.

[0148] Although not in Fig.12 , but the controller 110 may further include a controller core for generating an internal address ADDRi, an internal command CMDi, and an internal control signal CTRLi according to the external address ADDRe, the external command CMDe, and the external control signal CTRLe stored in the buffer 111.

[0149] Fig.13 is a diagram showing an example of a method of determining whether an error is caused by write disturbance. Figures 1 to 9 and Fig.13 , a memory cell initially programmed to the second state S2 may have its memory cell characteristics (eg, resistance value) shifted to a fourth state S4 (refer to Fig. 9 ).

[0150] When performing the check read operation, the resistance value "R" of the memory cell MC may be compared with the reference resistance value RR. When the number of bit errors of the data read by the check read operation is equal to or greater than a threshold value, the controller 110 may also perform a read operation (e.g., a disturbance check read operation) to determine whether the bit error is caused by write disturbance.

[0151] The controller 110 may perform a first disturbance check read operation and may compare the resistance value "R" of the memory cell MC with a first resistance value CR1 (e.g., a first check read resistance value) lower than the reference resistance value RR. The controller 110 may perform a second disturbance check read operation and may compare the resistance value "R" of the memory cell MC with a second resistance value CR2 (e.g., a second check read resistance value) lower than the first resistance value CR1. The reference resistance value RR may be used for a normal read operation of data, while the first resistance value CR1 and the second resistance value CR2 may not be used for a normal read operation.

[0152] like Fig.13As shown, in the case where the resistance value of the memory cell MC changes due to write disturbance, a read operation (e.g., a check read operation and a disturbance check read operation) is performed by using a gradually decreasing resistance value, and thus the number of bit errors gradually decreases. When it is determined that the trend of the error decreases, the controller 110 can determine that the error is caused by write disturbance.

[0153] Likewise, in the case where the number of bit errors gradually decreases when performing read operations using gradually increasing resistance values, the controller 110 may determine that errors associated with memory cells in the first state S1 are caused by write disturbance.

[0154] In some examples, logic block 115 (which may be part of controller 110 or on-chip as part of a non-volatile memory device semiconductor chip (e.g., 121 to 129 and 131 to 139)) may determine that the number of bit errors is unacceptably high and identify the memory cell row as requiring a refresh operation (e.g., a "yes" result in operation S114), and / or check for write disturbance without obtaining the number of bit errors detected from error correction block 114 (or other ECC circuitry). In some examples, logic block 115 may determine that the number of bit errors is unacceptably high and identify the memory cell row as requiring a refresh operation (e.g., a "yes" result in operation S114) without determining the number of bit errors of the data. For example, data encoding of data to be stored in a non-volatile memory device may include: error correction block 114 bit-equalizing the data to be stored in any memory cell row, and then storing the bit-equalized data in memory cells of the non-volatile memory device. Although the bit-equalized data in the memory cell row may be a codeword directly generated by the error correction block 114, the bit-equalized data in the memory cell row may come from other bit-equalizing processes (e.g., bit-equalizing processes of one or more codewords and / or a portion of a codeword generated by the error correction block 114). Bit-equalizing the data to be stored in the memory cell row may result in adjusting the number of logic high bits and the number of logic low bits of a certain data set (e.g., the data to be stored in the memory cell row) to be approximately the same (e.g., differing by + / -5% or + / -10% from each other). The bit-equalization of the data may follow a prescribed rule so that the minimum number and maximum number of bits of the data in the memory cell row are known. Therefore, the minimum number and maximum number of logic high ("1") bits and the minimum number and maximum number of logic ("0") low bits of the data in the memory cell row (without any bit errors) may be known (the minimum number and maximum number may be the same for the data stored in each memory cell row).

[0155] Therefore, determining that the number of bit errors is unacceptably high and identifying the memory cell row as requiring a refresh operation (e.g., a "yes" result in operation S114) may include counting the number of bits of data in the memory cell row that are a certain logic level (e.g., counting all bits of logic high "1" and / or counting all bits of logic low "0"), and determining whether the resulting count falls within a predetermined range (e.g., corresponding to a known minimum value and a known maximum value of logic bits that can be present in error-free data in the memory cell row after performing bit equalization). For example, the count of logic bits of a certain logic value may be compared to a first threshold to determine whether the count is less than the first threshold, and the count may be compared to a second threshold to determine whether the count is greater than the second threshold. If the count of logic bits is less than the first threshold or if the count of logic bits is greater than the second threshold, the logic block 115 may determine that the number of bit errors is unacceptably high and identify the memory cell row (storing data whose logic bits have been counted) as requiring a refresh operation ("yes" in operation S114). The first threshold and the second threshold can be respectively a known minimum number and a known maximum number of logical bits that will be present in error-free data after bit equalization of the data stored in the memory cell row (or can be this known minimum value minus an offset and this known maximum value plus an offset, where the offset can allow a larger acceptable number of erroneous bits to be present in the data before identifying the memory cell row as requiring a refresh operation (e.g., a "yes" result in operation S11)).

[0156] The check write disturbance (S115) of the logic block 115 can be performed in the same or similar manner as described herein. In some examples, instead of counting the number of bit errors (e.g., as determined by the error correction block 114 as described herein) of the data read from the memory cell row, the data can be read with different resistance reference values ​​(e.g., as described herein, the first resistance value and the second resistance value, and / or the third resistance value and the fourth resistance value), and the resulting read data (a plurality of read data sets respectively generated by using different resistance reference values) can have a counted number of bits of a certain logic level. If the number of bits having a certain logic level in the read data deviates less from a predetermined range corresponding to a larger difference of the corresponding resistance reference value for the read data relative to the read reference value RR, it can be determined that the bit error is caused by write disturbance (as noted, the predetermined range can correspond to a known minimum value and a known maximum value of a logic bit that will exist in the error-free data after performing bit equalization).

[0157] In this example, the refresh operation (S116) can be performed by logic block 115 in the same manner as described herein, although the data may need to be processed later by error correction block 114 (if not already performed) to identify which bits in the data are erroneous bits to be corrected by the refresh operation.

[0158] In this example, identifying whether a memory cell row requires a refresh operation (e.g., a "yes" result in operation S114) and determining whether a bit error is caused by a write disturbance (S115) can be performed in a simple manner without performing complex calculations by the error correction block 114 to determine the number of bit errors, thereby saving power. In addition, determining whether a memory cell row requires a refresh operation (e.g., a "yes" result in operation S114) and determining whether an error is caused by a write disturbance (S115) can be performed with a simple circuit, which can be part of a non-volatile memory device chip. For example, all or some of the logic block 115 circuits can be part of each non-volatile memory device chip. For example, each non-volatile memory device chip can include a counter, a comparator, and a register, the counter counts the number of bits of a certain logic level (high or low) in the data read from the memory cell row of the memory bank of the non-volatile memory device (e.g., the read data stored in the buffer (e.g., page buffer) of the non-volatile memory device), the comparator compares the count of the counter with the first threshold and the second threshold described herein, and the register stores the first threshold and the second threshold. In some examples, the first threshold and the second threshold may be programmable, for example by programming a set of mode registers of the nonvolatile memory device via an external source (e.g., controller 110). When the nonvolatile memory device includes such circuitry for performing operations S114 and S115, data read as part of operations S114 and / or S115 need not be output from the nonvolatile memory device to an external source (e.g., to controller 110). If the nonvolatile memory device includes an on-chip error correction block 114 (e.g., as described herein), data read as part of operations S113 to S119 need not be output to an external source, but erroneous bits may be detected and corrected on-chip. Thus, operations S113 to S119, including performing any refresh operations (S116), may be automatically performed by the nonvolatile memory device (e.g., without receiving related commands from controller 110).

[0159] Fig.14 is a diagram showing an example of performing a check read operation on a memory cell MC. Figures 1 to 9 and Fig.14 In operation S211, a write operation (eg, a set operation and / or a reset operation) may be performed on the memory cells MC of the fifth word line WL5. Fig.12As described above, when operation S211 is performed, the count CNT may reach the random number RN, and thus, the check condition may be satisfied.

[0160] When the check condition is satisfied, in operation S212, a check read operation may be performed on the memory cell MC in the sixth word line WL6, which is the first adjacent word line in the first order. It may be detected that the number of bit errors is less than the threshold value in the check read operation associated with the memory cell MC of the sixth word line WL6. Therefore, the check read operation associated with the memory cell MC of the sixth word line WL6 ends.

[0161] In operation S213, a check read operation may be performed on a memory cell MC in a fourth word line WL4, which is a second adjacent word line in the first order of adjacent word lines. It may be detected that the number of bit errors reaches a threshold value in the check read operation associated with the memory cell MC of the fourth word line WL4. Therefore, it should be determined whether the error is caused by write disturbance with respect to the memory cell MC of the fourth word line WL4.

[0162] Fig.15 It shows that Fig.14 Figure 1 shows an example of a check read operation performed afterwards. Figures 1 to 9 and Fig.15 In operation S214, write disturbance is checked for the memory cells MC of the fourth word line WL4. For example, an error of the memory cells MC of the fourth word line WL4 may be determined to be caused by write disturbance. After checking the write disturbance, in operation S215, a refresh operation may be performed on the memory cells MC of the fourth word line WL4, and thus, the reliability of the data may be restored.

[0163] In operation S216, a check read operation may be performed on the memory cells MC of the second word line WL2 as the second order adjacent word line. For example, the i-th order adjacent word line (i is a positive integer greater than 1) may be

[0164] For example, when a set operation or a reset operation is performed on the memory cell MC of the fifth word line WL5, the memory cell MC of the fourth word line WL4 may experience write interference together with the memory cell MC of the sixth word line WL6. In addition, when a set operation or a reset operation is performed on the memory cell MC of the third word line WL3, the memory cell MC of the fourth word line WL4 may experience write interference together with the memory cell MC of the second word line WL2.

[0165] This has already been performed in operation S212. Therefore, a second sequential inspection-read operation may be performed on the memory cells MC of the second word line WL2.

[0166] In an embodiment, the i-th order adjacent word line may be located at a (2i-1)th position from a word line performing an initial write operation (e.g., a set operation or a reset operation). A word line may be inserted between the i-th order adjacent word line and the (i-1)-th order adjacent word line. The i-th order adjacent word line may be adjacent to the (i-1)-th order adjacent word line with a word line inserted therebetween.

[0167] Fig.16 4 is a block diagram showing a computing device 400 according to an embodiment of the inventive concept. Fig.16 The computing device 400 may be implemented using one of various computing devices, such as a desktop computer, a notebook computer, a data server, an application server, a smart phone, and a smart tablet computer.

[0168] The processor 410 may be a central processing unit (CPU) or an application processor (AP) that performs various operations. The processor 410 may be implemented in a manner of combining a central processing unit (CPU) and an application processor (AP) with a graphics processing unit (GPU) or a neural processing unit (NPU).

[0169] The processor 410 may include a memory controller 411. The processor 410 may access the main memory 420 by using the memory controller 411. The main memory 420 may perform access operations such as read and write operations (e.g., set operations, reset operations) under the control of the memory controller 411. The memory controller 411 may be the memory controller 10 described elsewhere herein.

[0170] The main memory 420 may receive an address ADDR, a command CMD, and a control signal CTRL from the memory controller 411. The main memory 420 may exchange a data signal DQ with the memory controller 411. The main memory 420 may include a reference Figure 1 The memory module 100 described and / or referenced Figure 3 A non-volatile memory device 200 is described.

[0171] System interconnect 430 may provide a channel between components of computing device 400. System interconnect 430 may be implemented in accordance with one of various standards, such as Peripheral Component Interconnect Express (PCIe) and Advanced Microcontroller Bus Architecture (AMBA).

[0172] The storage device 440 may be used as a secondary memory of the computing device 400. The storage device 440 may have a slower access speed than the main memory 420, and may have a larger storage capacity than the main memory 420. The storage device 440 may include a hard disk drive (HDD), a solid state drive (SSD), a portable memory, etc.

[0173] The user interface 450 may exchange information with the user. The user interface 450 may include a user input interface (eg, keyboard, mouse, touch pad, or microphone) for receiving information from the user and a user output interface (eg, monitor, speaker, or motor) for providing information to the user.

[0174] Modem 460 is configured to perform wired or wireless communication with an external device. Modem 460 may be configured to implement at least one of various standards, such as Long Term Evolution (LTE), Ethernet, Wireless Fidelity (Wi-Fi), and Bluetooth. In an embodiment, modem 460 may be included in processor 410.

[0175] As reference Figures 1 to 15 As described above, the main memory 420 may include phase change memory cells. The main memory 420 may perform a set operation or a reset operation on the phase change memory cells for each memory cell row (e.g., corresponding to those memory cells connected to a word line). When the check condition is met after performing the set operation or the reset operation, the main memory 420 may perform a check read operation as described herein.

[0176] For example, the main memory 420 may perform a random interval adjacent check RINC. When a write disturbance is detected from the result of the check read operation, the main memory 420 may sequentially perform a check read operation on the i-th order adjacent word line. Therefore, the reliability of the main memory 420 and the computing device 400 is improved.

[0177] In addition, even if a check read operation is required, the main memory 420 can stop (or skip) the check read operation when the end condition is met. Therefore, the delay of the main memory 420 is prevented from being excessively increased due to the check read operation. The main memory 420 can provide a trade-off between reliability and delay by dynamically or adaptively adjusting the end condition. For example, the threshold for determining the end condition analysis of step S118 can be adjusted, such as by analyzing memory usage, environmental conditions (e.g., temperature and / or humidity), or by programming a mode register of the main memory 420 (by a host that can respond to user input from a user).

[0178] In an embodiment, the checker 112 may be included in the memory controller 411. The memory controller 411 may perform a set operation or a reset operation on the phase change memory cell for each row of the main memory 420. When a check condition is satisfied after performing the set operation or the reset operation, the memory controller 411 may perform a check read operation.

[0179] For example, the memory controller 411 may perform a random interval adjacent check RINC. When a write disturbance is detected from the result of the check read operation, the memory controller 411 may sequentially perform a check read operation on the i-th order adjacent word line. Even if the check read operation is required, the memory controller 411 may stop (or skip) the check read operation when the end condition is met.

[0180] As described above, the components (e.g., memory module 100 and non-volatile memory device 200) or operations of the embodiments described above are described by using ordinals such as "first", "second", "third". It should be understood that these ordinals can simply be used as labels for certain elements, steps, etc. to distinguish these elements, steps, etc. from each other. Terms that are not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, terms referenced with a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0181] In the above embodiments, the circuits of the embodiments of the inventive concept are described in terms of blocks (and / or are represented as blocks in the figures, such as the checker 112). It should be understood that these blocks can be implemented by various hardware devices, such as integrated circuits, application specific ICs (ASICs), field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs), firmware driven in hardware devices, and / or general controllers configured by software such as applications, or a combination of hardware devices and software. In addition, blocks may include circuits or intellectual property (IP) implemented using semiconductor components in integrated circuits.

[0182] According to the inventive concept, a check read operation for checking interference is sequentially performed on adjacent memory cells of the accessed memory cell. When interference is detected, subsequent operations for addressing and correcting interference can be performed. Therefore, a semiconductor memory device including a phase change memory device for checking and resolving interference, and a method for accessing a phase change memory device are provided. However, it is emphasized again that describing the non-volatile memory in the embodiment as a phase change memory should not mean that the present invention is limited to use with a phase change memory, and other non-volatile memories can have write interference bit errors detected and corrected according to the novel aspects of the present invention.

[0183] While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the inventive concept as described in the appended claims.

Claims

1. A memory device, comprising: a memory cell array including a plurality of memory banks, each memory bank including a plurality of memory cells arranged in a plurality of memory cell rows, each memory cell including a variable resistor including a material having a variable resistance; a plurality of word lines, each word line being connected to a corresponding row of memory cells; a control logic circuit configured to write data into the memory cell array and read data from the memory cell array; as well as a checker circuit configured to count a number of write operations to each of the plurality of memory banks, Wherein, in response to a write operation on a first memory cell row of one of the multiple memory banks and based on the number of write operations on the one of the multiple memory banks, the checker circuit is configured to cause a check read operation on a second memory cell row adjacent to the first memory cell row of the one of the multiple memory banks to determine whether a programming state of the second memory cell row indicates write interference with the programming state of the second memory cell row.

2. The memory device according to claim 1, in, The checker circuit is configured to: in response to determining that the programming state of the second memory cell row indicates write disturb, perform a check read operation of a fourth memory cell row to determine whether the programming state of the fourth memory cell row indicates write disturb of the programming state of the fourth memory cell row, The third memory cell row is inserted between the second memory cell row and the fourth memory cell row and is adjacent to both of them.

3. The memory device according to claim 2, wherein: The checker circuit is configured to identify a first memory cell row block to be refreshed and cause a refresh operation of each memory cell row in the first memory cell row block.

4. The memory device according to claim 3, wherein: The checker circuit is configured to cause a refresh operation using bit error-corrected data among data of each memory cell row in the first memory cell row block.

5. The memory device according to claim 1, in, The checker circuit is configured to obtain a first count of a number of logic high bits or a number of logic low bits in the second memory cell row, and Wherein the checker circuit is configured to determine whether a programming state of the second memory cell row indicates write disturbance by comparing the first count with a predetermined value.

6. The memory device according to claim 1, wherein: The check read operation of the checker circuit includes a first read operation and a second read operation for the same bit of data in the data stored by the second memory cell row, the first read operation and the second read operation use a first resistance value and a second resistance value, respectively, the first resistance value and the second resistance value being different from each other.

7. The memory device according to claim 6, wherein: The first resistance value and the second resistance value are provided as a first voltage and a second voltage, respectively.

8. The memory device according to claim 1, wherein: The memory device is a phase change memory semiconductor chip, and the memory cell array, the plurality of word lines, the control logic circuit, and the checker circuit are formed on the phase change memory semiconductor chip.

9. The memory device according to claim 1, wherein: The checker circuit is configured to perform randomly spaced proximity checks.

10. The memory device according to claim 9, in, The checker circuit is configured to identify the first row of memory cells as a row of memory cells associated with an nth write operation of write operations performed on a portion of the memory cell array, where n is a randomly generated integer.

11. The memory device according to claim 1, in, The memory cell array includes n memory banks, where n is an integer equal to or greater than 2, Wherein, the checker circuit comprises: n counters, each counter configured to provide a count of the number of write operations performed by a corresponding memory bank, n registers, each configured to store a random number, and n comparators, each comparator being configured to compare a random number stored by a corresponding one of the n registers with a count provided by a corresponding one of the n counters, and to output an enable signal when the random number stored by the corresponding one of the n registers is equal to the count provided by the corresponding one of the n counters.

12. The memory device according to claim 11, wherein: The checker circuit causes a check read operation of the second memory cell row immediately adjacent to the first memory cell row in response to an output of an enable signal from one of the n comparators.

13. The memory device according to claim 11, further comprising: The random number generator is configured to generate and provide a corresponding random number for each of the n registers.

14. The memory device according to claim 13, in, The random number generator provides a new random number to a first register among the n registers in response to an output of a first enable signal from a first comparator among the n comparators, and The first comparator is connected to the first register and a first counter among the n counters.

15. The memory device according to claim 1, wherein: The checker circuit is configured to enter a check-read mode, wherein the checker circuit in the check-read mode is configured to perform a plurality of check-read operations on a corresponding memory cell row, wherein an initial check-read operation among the plurality of check-read operations is the check-read operation of the second memory cell row, wherein each remaining one of the plurality of check read operations subsequent to the initial check read operation is performed in response to the checker circuit determining that an immediately preceding check read operation of the corresponding row of memory cells indicated that a programming state of the corresponding row of memory cells was subject to write disturbance.

16. The memory device according to claim 15, wherein: In the check read mode of the checker circuit, the checker circuit is configured to: sequentially select every other row of memory cell rows in a first group of memory cell rows of the one memory body among the multiple memory bodies as at least some of the multiple memory cell rows that are subjected to the multiple check read operations, the first group of memory cell rows being located on a first side of the first memory cell rows.

17. The memory device according to claim 16, wherein: In the check read mode of the checker circuit, the checker circuit is configured to: sequentially select every other row of memory cell rows in a second group of memory cell rows of the one memory bank among the multiple memory banks as at least some of the multiple memory cell rows that are subjected to the multiple check read operations, the second group of memory cell rows being located at a second side of the first memory cell row opposite to the first side of the first memory cell row.

18. The memory device according to claim 15, wherein: In the inspecting read mode, the inspector circuit is configured to identify a row of memory cells to be subjected to a refresh operation.

19. The memory device according to claim 18, wherein: For each of the memory cell rows identified by the checker circuit as being subject to a refresh operation, the checker circuit is configured to perform a refresh operation by reading data from the identified corresponding memory cell row, subjecting the read data to error correction to obtain error-corrected data, and writing the error-corrected data to the identified corresponding memory cell row.

20. The memory device according to claim 18, in, The memory device is a phase change memory semiconductor chip, and the memory cell array, the plurality of word lines, the control logic circuit and the checker circuit are formed on the phase change memory semiconductor chip, The checker circuit is configured to perform a refresh operation on the memory cell row identified as being subject to a refresh operation during an idle time of the phase change memory semiconductor chip.

21. The memory device of claim 1, further comprising: an error correction code circuit configured to determine bit errors in data read from the memory cell array, Wherein the checker circuit is configured to determine whether the programming state of the second memory cell row indicates write disturbance by determining that the number of bit errors in the second memory cell row provided by the error correction code circuit is greater than or equal to a predetermined value.

22. The memory device according to claim 1, in, The control logic circuit is configured to: write data to the one of the multiple storage bodies by performing a set operation to achieve a first resistance state of some memory cells in the first memory cell row, and performing a reset operation to achieve a second resistance state of other memory cells in the first memory cell row that is different from the first resistance state.

23. The memory device according to claim 1, further comprising a controller semiconductor chip, a first phase change memory semiconductor chip, and a bus providing communication between the controller semiconductor chip and the first phase change memory semiconductor chip, in, The memory cell array, the plurality of word lines, and the control logic circuit are formed as an integrated circuit of the first phase-change memory semiconductor chip, and the checker circuit is formed as an integrated circuit of the controller semiconductor chip.

24. The memory device according to claim 23, further comprising a plurality of second phase change memory semiconductor chips, each second phase change memory semiconductor chip communicating with the controller semiconductor chip, in, For each of the second phase-change memory semiconductor chips, the checker circuit is configured to perform a check-read operation and determine whether the check-read operation indicates write disturbance.

25. A method of operating a memory device, the method comprising: counting a number of write operations performed on each of a plurality of memory banks of a memory cell array or a portion of each of the plurality of memory banks of the memory cell array, each of the plurality of memory banks comprising a plurality of memory cells arranged in a plurality of memory cell rows, each memory cell comprising a variable resistor, the variable resistor comprising a material having a variable resistance; causing a first write operation to a first row of memory cells of one of the plurality of memory banks, wherein counting the number of write operations provides a counted number of write operations in response to the first write operation and based on the number of write operations to the one of the plurality of memory banks; determining that a counted number of write operations is equal to or greater than a first value stored in a first register; in response to determining that the counted number of write operations is equal to or greater than a first value, causing a check read operation of a second memory cell row of the one of the plurality of memory banks that is immediately adjacent to the first memory cell row; as well as Based on the checking read operation of the second memory cell row, it is determined whether the programmed state of the second memory cell row indicates write disturbance to the programmed state of the second memory cell row.

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