Display device and method of manufacturing the same

Abstract

A display device and a manufacturing method thereof are provided. The display device includes: a first active pattern including a silicon semiconductor; a first insulating layer covering the first active pattern; a first gate electrode disposed on the first insulating layer; a second insulating layer covering the first gate electrode; a gate wiring pattern disposed on the second insulating layer and including a lower layer and an upper layer, the lower layer including titanium or a titanium alloy, and the upper layer including molybdenum or a molybdenum alloy; a third insulating layer covering the gate wiring pattern; and a second active pattern disposed on the third insulating layer and including an oxide semiconductor.

Description

Technical Field

[0001] Exemplary embodiments of the invention relate generally to display devices, and more particularly, to an organic light emitting display device and a method of manufacturing the same. Background Art

[0002] Organic light emitting display devices are capable of emitting light to display images. Due to advantages of organic light emitting display devices such as light weight and thin thickness, which are particularly useful for flexible display devices, the use of organic light emitting display devices is increasing.

[0003] In order to efficiently drive an organic light emitting diode, an organic light emitting display device including a silicon-based semiconductor element and an oxide-based semiconductor element is recently being developed.

[0004] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0005] Exemplary embodiments of the invention provide a display device having improved reliability and a method of manufacturing the display device.

[0006] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0007] A display device according to an exemplary embodiment includes a first active pattern including a silicon semiconductor, a first insulating layer covering the first active pattern, a first gate electrode disposed on the first insulating layer, a second insulating layer covering the first gate electrode, a gate wiring pattern disposed on the second insulating layer, a third insulating layer covering the gate wiring pattern, and a second active pattern disposed on the third insulating layer and including an oxide semiconductor. The gate wiring pattern includes a first lower layer and a first upper layer. The first lower layer includes titanium or a titanium alloy, and the first upper layer includes molybdenum or a molybdenum alloy.

[0008] The thickness of the first lower layer may be approximately To about And the thickness of the first upper layer may be approximately To about

[0009] The first lower layer may include titanium, and the first upper layer may include molybdenum.

[0010] The third insulating layer may include: a lower barrier layer including silicon nitride; and an upper barrier layer disposed on the lower barrier layer and including silicon oxide.

[0011] The thickness of the lower barrier layer may be approximately To about And the thickness of the upper barrier layer can be about To about

[0012] The display device may further include a bottom gate electrode disposed between the second insulating layer and the third insulating layer and overlapping the second active pattern.

[0013] The bottom gate electrode may include a second lower layer including titanium or a titanium alloy and a second upper layer including molybdenum or a molybdenum alloy.

[0014] The display device may further include a top gate electrode disposed on the second active pattern.

[0015] The display device may further include an organic light emitting diode electrically connected to the first active pattern.

[0016] A display device according to another exemplary embodiment includes a first active pattern including a silicon semiconductor, a first insulating layer covering the first active pattern, a first gate electrode disposed on the first insulating layer, a second insulating layer covering the first gate electrode, a bottom gate electrode disposed on the second insulating layer, a third insulating layer covering the bottom gate electrode, a second active pattern disposed on the third insulating layer overlapping the bottom gate electrode and including an oxide semiconductor, and a top gate electrode disposed on the second active pattern. The third insulating layer includes a lower barrier layer including silicon nitride and an upper barrier layer disposed on the lower barrier layer and including silicon oxide.

[0017] According to an exemplary embodiment, a method for manufacturing a display device includes the following steps: forming a first active pattern including a silicon semiconductor; forming a first insulating layer to cover the first active pattern; forming a first gate electrode on the first insulating layer; forming a second insulating layer to cover the first gate electrode; forming a gate metal layer on the second insulating layer, wherein the gate metal layer includes a lower layer including titanium or a titanium alloy and an upper layer including molybdenum or a molybdenum alloy; etching the upper layer by using a first etching gas including fluorine; etching the lower layer by using a second etching gas different from the first etching gas to form a gate metal pattern; forming a third insulating layer on the gate metal pattern; and forming a second active pattern including an oxide semiconductor on the third insulating layer.

[0018] According to another exemplary embodiment, a method for manufacturing a display device includes the following steps: forming a first active pattern including a silicon semiconductor; forming a first insulating layer to cover the first active pattern; forming a first gate electrode on the first insulating layer; forming a second insulating layer to cover the first gate electrode; forming a gate metal layer on the second insulating layer; etching the gate metal layer by using a first etching gas including fluorine to form a gate metal pattern including a bottom gate electrode; forming a third insulating layer on the gate metal pattern, wherein the third insulating layer includes a lower barrier layer including silicon nitride and an upper barrier layer disposed on the lower barrier layer and including silicon oxide; forming a second active pattern including an oxide semiconductor on the third insulating layer; and forming a top gate electrode on the second active pattern.

[0019] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification.

[0021] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 is a cross-sectional view illustrating a method for manufacturing an organic light emitting display device according to an exemplary embodiment.

[0022] Fig.12 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment.

[0023] Fig.13 , Fig.14 , Fig.15 and Fig.16 is a cross-sectional view illustrating a method for manufacturing an organic light emitting display device according to an exemplary embodiment.

[0024] Fig.17 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment.

[0025] Fig.18 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0026] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the invention. "Embodiment" and "implementation" as used herein are interchangeable words as non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is clear that various exemplary embodiments can be practiced without these specific details or in the case of one or more equivalent arrangements. In other cases, well-known structures or devices are shown in block diagram form to avoid making various exemplary embodiments unnecessarily obscure. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, without departing from the inventive concept, the specific shape, construction and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0027] Unless otherwise stated, the exemplary embodiments shown are to be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0028] Cross hatching and / or shadows used in the drawings are generally provided to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence and absence of cross hatching or shadows do not express or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the illustrated elements and / or any other characteristics, attributes, properties, etc. of the element. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0029] When an element or layer is referred to as being "on" another element or layer, "connected to" or "bonded to" another element or layer, the element or layer may be directly on, directly connected to or directly bonded to the other element or layer, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bonded to" another element or layer, there is no intermediate element or intermediate layer. For this reason, the term "connection" may refer to physical connection, electrical connection and / or fluid connection with or without the presence of an intermediate element. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system such as an x-axis, a y-axis and a z-axis, but may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be understood as any combination of only X, only Y, only Z, or two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0030] Although the terms "first", "second", etc. may be used to describe various types of elements herein, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the disclosed teachings, the first element discussed below may be named as the second element.

[0031] For descriptive purposes, spatially relative terms such as "under", "below", "under", "below", "above", "upper", "above", "higher", "side" (e.g., as in "sidewall"), etc. may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. Spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "below" other elements or features will subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "under" can include both above and below orientations. In addition, the device can be positioned otherwise (e.g., rotated 90 degrees or at other orientations), so the spatially relative descriptors used herein are interpreted accordingly.

[0032] The terms used here are for the purpose of describing specific embodiments, and are not intended to be limited. As used here, unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and / or "include" and their variations are used in this specification, the descriptions indicate the existence of stated features, integral bodies, steps, operations, elements, components and / or their groups, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It should also be noted that, as used here, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than as terms of degree, so that they are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0033] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances, are expected to occur. Therefore, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the shapes of the specific illustrated areas, but rather to include deviations in shape due to, for example, manufacturing. In this manner, the areas illustrated in the figures may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and as such, no limitation is necessarily intended.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be understood in an idealized or overly formal sense unless explicitly defined as such herein.

[0035] Figures 1 to 11 is a cross-sectional view illustrating a method for manufacturing an organic light emitting display device according to an exemplary embodiment.

[0036] Reference Figure 1 , a semiconductor pattern 112 is formed on the base substrate 100 .

[0037] The base substrate 100 may include glass, quartz, silicon, polymer, etc. For example, the polymer may include polyethylene terephthalate, polyethylene naphthalate, polyether ketone, polycarbonate, polyarylate, polyether sulfone, polyimide, or a combination thereof.

[0038] A buffer layer 110 may be provided between the semiconductor pattern 112 and the base substrate 100. In this case, the semiconductor pattern 112 may be formed on the buffer layer 110. The buffer layer 110 may prevent or reduce the penetration of impurities, moisture, or external gas from the bottom of the base substrate 100, and may planarize the upper surface of the base substrate 100. For example, the buffer layer 110 may include an inorganic material such as oxide, nitride, etc. In an exemplary embodiment, the buffer layer 110 may have a multilayer structure including a lower layer including silicon nitride and an upper layer including silicon oxide.

[0039] In an exemplary embodiment, the semiconductor pattern 112 may include polysilicon. To form the semiconductor pattern 112, an amorphous silicon layer may be formed on the base substrate 100 and then crystallized to form a polysilicon layer.

[0040] For example, the amorphous silicon layer may be formed by sputtering, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), etc. The amorphous silicon layer may be crystallized by excimer laser annealing (ELA), sequential lateral solidification (SLS), etc.

[0041] For example, the polysilicon layer may be polished by chemical mechanical polishing (CMP) etc. to planarize the surface of the polysilicon layer. Thereafter, the polysilicon layer may be patterned by photolithography etc. to form a semiconductor pattern. The semiconductor pattern may be doped with n-type impurities or p-type impurities.

[0042] Thereafter, a first insulating layer 120 is formed to cover the semiconductor pattern 112 . The first insulating layer 120 may insulate a channel formed by the semiconductor pattern 112 from a gate electrode formed on the first insulating layer 120 .

[0043] For example, the first insulating layer 120 may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. In addition, the first insulating layer 120 may include insulating metal oxides such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. The first insulating layer 120 may have a single-layer structure or a multi-layer structure including silicon nitride and / or silicon oxide.

[0044] Reference Figure 2 A first gate metal layer is formed on the first insulating layer 120 , and a first photoresist pattern PR1 is formed on the first gate metal layer.

[0045] The first gate metal layer may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. For example, the first gate metal layer may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta) or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers.

[0046] The first photoresist pattern PR1 may partially overlap the semiconductor pattern 112. For example, a photoresist composite including a binder resin such as a phenol resin, an acrylic resin, etc. may be coated, exposed, and developed, thereby forming the first photoresist pattern PR1.

[0047] Thereafter, the first gate metal layer may be etched by using the first photoresist pattern PR1 as a mask to form the first gate electrode GE1. For example, the first gate metal layer may be etched by a dry etching method using plasma, etc. As the first gate electrode GE1 is formed, the first insulating layer 120 adjacent to the first gate electrode GE1 may be exposed.

[0048] Reference Figure 3 , impurities are provided to the exposed first insulating layer 120. For example, the impurities may include p-type impurities such as boron. In this way, the peripheral portion of the semiconductor pattern 112 that does not overlap the first gate electrode GE1 is doped with the p-type impurities, thereby forming the first doping region PD1 and the second doping region PD2. In the semiconductor pattern 112, the portion of the semiconductor pattern 112 that overlaps the first gate electrode GE1 may not be doped, thereby defining the channel region CH1.

[0049] As such, the first doping region PD1, the second doping region PD2, and the channel region CH1 may be continuously disposed on the same layer. A pattern including the first doping region PD1, the second doping region PD2, and the channel region CH1 may be defined as a first active pattern AP1.

[0050] The first photoresist pattern PR1 may be removed before or after the doping process.

[0051] Reference Figure 4 A second insulating layer 130 is formed to cover the first gate electrode GE1. A second gate metal layer GL2 is formed on the second insulating layer 130. A second photoresist pattern PR2 is formed on the second gate metal layer GL2.

[0052] For example, the second insulating layer 130 may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. In addition, the second insulating layer 130 may include insulating metal oxides such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. For example, the second insulating layer 130 may include silicon nitride.

[0053] In an exemplary embodiment, the second gate metal layer GL2 includes a lower layer LL and an upper layer HL disposed on the lower layer LL. The lower layer LL may include titanium or a titanium alloy, and the upper layer HL may include molybdenum or a molybdenum alloy. For example, the lower layer LL may include titanium, and the upper layer HL may include molybdenum.

[0054] The thickness of the upper layer HL may be greater than the thickness of the lower layer LL. In an exemplary embodiment, the thickness of the lower layer LL may be approximately To about And the thickness of the upper layer HL can be about To about In this way, a preferred oblique taper angle can be achieved.

[0055] Reference Figures 4 to 6 , the upper layer HL is etched by using the second photoresist pattern PR2 as a mask.

[0056] In an exemplary embodiment, the upper layer HL including molybdenum may be etched by plasma of a first etching gas including a fluorine-containing compound. For example, the fluorine-containing compound may include SiF 4 CF 4 , C 3 F 8 , C 2 F 6 , CHF 3 , SF 6 Or a combination of these.

[0057] In an exemplary embodiment, the lower layer LL may be etched by a plasma of a material different from that of the first etching gas. For example, the second etching gas for etching the lower layer LL may include a chlorine-containing compound. In an exemplary embodiment, the second etching gas may include a chlorine-containing compound and oxygen. For example, the lower layer LL may be etched by a plasma of a material different from that of the first etching gas. For example, the second etching gas for etching the lower layer LL may include a chlorine-containing compound and oxygen. 2 and O 2 The mixed gas plasma is used to etch the lower layer LL.

[0058] Thus, the gate wiring pattern GP may be formed on the second insulating layer 130. The gate wiring pattern GP may include a lower layer GPb including titanium or an alloy thereof and an upper layer GPa including molybdenum or an alloy thereof.

[0059] The gate wiring pattern GP may include at least one of a data signal wiring providing a data signal, a gate signal wiring providing a gate signal, an initialization signal wiring providing an initialization signal, a light emitting signal wiring providing a light emitting signal, and a power supply voltage wiring providing a power supply voltage. In an exemplary embodiment, at least a portion of the gate wiring pattern GP may overlap the first gate electrode GE1 or the first active pattern AP1.

[0060] When the second gate metal layer GL2 is etched by a first etching gas including a fluorine-containing compound, fluorine ions generated from the first etching gas may remain on the surface of the second insulating layer 130 or may be combined with the insulating material (e.g., silicon nitride) of the second insulating layer 130. When the fluorine ions diffuse into the third insulating layer 140 to be disposed on the second insulating layer 130, the oxide semiconductor element in contact with the third insulating layer 140 may be degraded. In an exemplary embodiment, the second gate metal layer GL2 has a multilayer structure of molybdenum / titanium. In this way, the lower layer LL in contact with the second insulating layer 130 may be etched by a material other than a fluorine-containing compound. In this way, fluorine ions may be substantially prevented from remaining on the surface of the second insulating layer 130 or from being combined with the second insulating layer 130.

[0061] Reference Figure 7 A third insulating layer 140 is formed to cover the gate wiring pattern GP. A second active pattern AP2 is formed on the third insulating layer 140.

[0062] The third insulating layer 140 may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. In addition, the third insulating layer 140 may include an insulating metal oxide such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. For example, the third insulating layer 140 may include silicon oxide.

[0063] The second active pattern AP2 includes an oxide semiconductor. For example, the second active pattern AP2 may include a binary compound (AB) that may include indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), and magnesium (Mg). x ), ternary compounds (AB x C y ) or quaternary compound (AB x C y D z For example, the second active pattern AP2 may include zinc oxide (ZnO x ), gallium oxide (GaO x ), titanium oxide (TiO x ), tin oxide (SnO x ), indium oxide (InO x), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc tin oxide (ZTO), zinc zirconium oxide (ZnZr x O y ), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium hafnium oxide (IGHO), indium aluminum zinc oxide (TAZO), indium gallium tin oxide (IGTO), etc.

[0064] Reference Figure 8 A preliminary insulating layer 150 is formed to cover the second active pattern AP2. A third gate metal layer GL3 is formed on the preliminary insulating layer 150. A fourth photoresist pattern PR4 is formed on the third gate metal layer GL3. The fourth photoresist pattern PR4 overlaps the second active pattern AP2.

[0065] The preliminary insulating layer 150 may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. In addition, the preliminary insulating layer 150 may include insulating metal oxides such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. For example, the preliminary insulating layer 150 may include silicon oxide.

[0066] The third gate metal layer GL3 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. For example, the third gate metal layer GL3 may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta) or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers.

[0067] Reference Fig. 9 , the third gate metal layer GL3 is etched by using the fourth photoresist pattern PR4 as a mask, thereby forming a second gate electrode GE2. Thereafter, the initial insulating layer 150 is etched by using the second gate electrode GE2 as a mask, thereby forming a gate insulating pattern 152. In this way, the gate insulating pattern 152 may have substantially the same shape as the second gate electrode GE2 in a plan view.

[0068] In the process of forming the gate insulating pattern 152 or through an additional process, the metal element may be reduced to metal in the exposed portion of the second active pattern AP2, thereby improving the conductivity of the second active pattern AP2. Therefore, the exposed portion of the second active pattern AP2 may serve as an ohmic contact.

[0069] Reference Fig.10, a fourth insulating layer 160 is formed to cover the second gate electrode GE2 and the second active pattern AP2. The fourth insulating layer 160 is patterned to form a contact hole exposing the second gate electrode GE2 and the second active pattern AP2, and the fourth insulating layer 160, the third insulating layer 140, the second insulating layer 130, and the first insulating layer 120 are sequentially patterned to form a contact hole exposing the doped regions PD1 and PD2 of the first active pattern AP1.

[0070] Thereafter, a first data metal layer is formed to fill the contact hole. The first data metal layer is patterned to form a first data metal pattern including a first source electrode SE1 contacting the first doping region PD1 of the first active pattern AP1, a first drain electrode DE1 contacting the second doping region PD2, a second source electrode SE2 contacting the second active pattern AP2, a second drain electrode DE2 contacting the second active pattern AP2 and spaced apart from the second source electrode SE2, and a gate connection electrode GCE contacting the second gate electrode GE2.

[0071] For example, the fourth insulating layer 160 may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. In addition, the fourth insulating layer 160 may include an insulating metal oxide such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. For example, the fourth insulating layer 160 may have a multilayer structure including a lower layer including silicon oxide and an upper layer including silicon nitride.

[0072] The first data metal layer may include metal, metal alloy, metal nitride, conductive metal oxide, etc. For example, the first data metal layer may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), or alloys thereof, and may have a single-layer structure or a multi-layer structure including different metal layers.

[0073] Reference Fig.11 , a fifth insulating layer 170 is formed to cover the first data metal pattern. The fifth insulating layer 170 is patterned to form a contact hole exposing the first drain electrode DE1. Thereafter, a second data metal layer is formed to fill the contact hole, and then, the second data metal layer is patterned to form a connection electrode CE contacting the first drain electrode DE1.

[0074] Thereafter, a sixth insulating layer 180 is formed to cover the connection electrode CE. The sixth insulating layer 180 is patterned to form a contact hole exposing the connection electrode CE. Thereafter, a lower electrode layer is formed to fill the contact hole, and then the lower electrode layer is patterned to form the lower electrode 210 of the organic light emitting diode 200.

[0075] For example, the fifth and sixth insulating layers 170 and 180 may include an organic insulating material such as phenol resin, acrylic resin, polyimide resin, polyamide resin, siloxane resin, epoxy resin, etc. The fifth and sixth insulating layers 170 and 180 may have flat upper surfaces, thereby flattening the upper surface of the base substrate 100 .

[0076] In an exemplary embodiment, the lower electrode 210 may be used as an anode. For example, depending on the emission type of the organic light-emitting display device, the lower electrode 210 may be formed as a transmissive electrode or a reflective electrode. When the lower electrode 210 is a transmissive electrode, the lower electrode 210 may include indium tin oxide, indium zinc oxide, zinc tin oxide, indium oxide, zinc oxide, tin oxide, etc. When the lower electrode 210 is a reflective electrode, the lower electrode 210 may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta) or alloys thereof, and may have a stacked structure that also includes a material that can be used for a transmissive electrode.

[0077] A pixel defining layer 190 may be disposed on the sixth insulating layer 180. The pixel defining layer 190 may include an opening exposing at least a portion of the lower electrode 210. For example, the pixel defining layer 190 may include an organic insulating material.

[0078] The light emitting layer 220 is formed on the lower electrode 210. The light emitting layer 220 may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an organic light emitting layer, an electron transport layer (ETL), and an electron injection layer (EIL). For example, the light emitting layer 220 may include a low molecular weight organic compound or a high molecular weight organic compound.

[0079] In an exemplary embodiment, the light emitting layer 220 may emit red light, green light, or blue light. In another exemplary embodiment, the light emitting layer 220 may emit white light. The light emitting layer 220 emitting white light may have a multilayer structure including a red emission layer, a green emission layer, and a blue emission layer, or a single layer structure including a mixture of a red emission material, a green emission material, and a blue emission material.

[0080] The light emitting layer 220 may be formed by a screen printing method, an inkjet printing method, a deposition method, or the like.

[0081] An upper electrode 230 is formed on the light emitting layer 220. In an exemplary embodiment, the upper electrode 230 may be used as a cathode. For example, according to the emission type of the organic light emitting display device, the upper electrode 230 may be formed as a transmissive electrode or a reflective electrode. For example, when the upper electrode 230 is a transmissive electrode, the upper electrode 230 may include lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), or a combination thereof.

[0082] The upper electrode 230 may extend continuously across a plurality of pixels in the display area. In an exemplary embodiment, a capping layer and a barrier layer may be formed on the upper electrode 230.

[0083] In an exemplary embodiment, an encapsulation layer 300 may be formed on the organic light emitting diode 200. The encapsulation layer 300 may have a stacked structure of an inorganic layer and an organic layer. For example, the organic layer may include a cured resin such as poly(meth)acrylate, etc. For example, the inorganic layer may include silicon oxide, silicon nitride, silicon carbide, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0084] In an exemplary embodiment, the organic light emitting display device may have a front emission type in which light is emitted through the upper electrode 230. However, the inventive concept is not limited thereto. For example, the organic light emitting display device may have a rear emission type in which light is emitted in a reverse direction.

[0085] The organic light emitting display device includes an oxide-based semiconductor element and a silicon-based semiconductor element. In an exemplary embodiment, the silicon-based semiconductor element may be used as a driving transistor that supplies current to the organic light emitting diode 200.

[0086] In exemplary embodiments, the silicon-based semiconductor element may include a first active pattern AP1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0087] For example, the first active pattern AP1 includes a channel region CH1, a first doping region PD1, and a second doping region PD2. The first gate electrode GE1 may be disposed on the first active pattern AP1 and may overlap the channel region CH1. The first source electrode SE1 may contact the first doping region PD1, and the first drain electrode DE1 may contact the second doping region PD2.

[0088] In an exemplary embodiment, the oxide-based semiconductor element may be used as a switching transistor to control the driving transistor. For example, the drain electrode of the oxide-based semiconductor element may be electrically connected to the gate electrode of the silicon-based semiconductor element.

[0089] In an exemplary embodiment, the oxide-based semiconductor element may include a top gate structure. For example, the oxide-based semiconductor element may include a second gate electrode GE2, a second active pattern AP2 disposed under the second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0090] Fig.12 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment.

[0091] In addition to the third insulating layer 140 disposed under the second active pattern AP2, Fig.12 The organic light emitting display device shown in Fig.11 The organic light emitting display devices shown in FIG. 1 have substantially the same configuration.

[0092] Reference Fig.12 The third insulating layer 140 covers the gate wiring pattern GP and the second insulating layer 130. The second active pattern AP2 including an oxide semiconductor is disposed on the third insulating layer 140.

[0093] The third insulating layer 140 may include a lower barrier layer 142 contacting the second insulating layer 130 and the gate wiring pattern GP, ​​and an upper barrier layer 144 disposed on the lower barrier layer 142 .

[0094] In an exemplary embodiment, the lower barrier layer 142 may include silicon nitride. Therefore, the lower barrier layer 142 may prevent fluorine ions remaining at the second insulating layer 130 from diffusing upward.

[0095] In an exemplary embodiment, the upper barrier layer 144 may include silicon oxide. Therefore, the upper barrier layer 144 may prevent hydrogen ions of the lower barrier layer 142 from diffusing upward.

[0096] In this manner, the third insulating layer 140 may prevent characteristics of the second active pattern AP2 disposed on the third insulating layer 140 from being degraded due to hydrogen ions or fluorine ions.

[0097] In exemplary embodiments, the third insulating layer 140 may prevent characteristics of the second active pattern AP2 disposed on the third insulating layer 140 from being degraded by hydrogen ions or fluorine ions.

[0098] In an exemplary embodiment, the thickness of the upper barrier layer 144 may be greater than the thickness of the lower barrier layer 142. For example, the thickness of the lower barrier layer 142 may be approximately To about And the thickness of the upper barrier layer 144 may be about To about When the upper barrier layer 144 and the lower barrier layer 142 are too thin, their barrier capabilities may be deteriorated.

[0099] Fig.12 The third insulating layer 140 is shown to have a double-layer structure. However, the inventive concept is not limited thereto. For example, in another exemplary embodiment, the third insulating layer 140 may include at least three layers including a lower barrier layer including silicon nitride and an upper barrier layer including silicon oxide.

[0100] Figures 13 to 16 is a cross-sectional view illustrating a method for manufacturing an organic light emitting display device according to an exemplary embodiment.

[0101] Reference Fig.13 , a buffer layer 110 is formed on the base substrate 100 .

[0102] A semiconductor pattern is formed on the buffer layer 110. A first insulating layer 120 is formed to cover the semiconductor pattern. A first gate electrode GE1 is formed on the first insulating layer 120. The semiconductor pattern is locally doped to form a first active pattern AP1 including a first doping region PD1, a second doping region PD2 spaced apart from the first doping region PD1, and a channel region CH1 disposed between the first doping region PD1 and the second doping region PD2. A second insulating layer 130 is formed to cover the first gate electrode GE1.

[0103] Methods for forming the buffer layer 110, the first active pattern AP1, the first insulating layer 120, the first gate electrode GE1, and the second insulating layer 130 are similar to those described in the reference Figures 1 to 4 The methods shown are substantially the same, and thus, their repeated descriptions will be omitted to avoid redundancy.

[0104] Thereafter, a second gate metal layer GL2 is formed on the second insulating layer 130. A second photoresist pattern PR2 and a third photoresist pattern PR3 are formed on the second gate metal layer GL2. In an exemplary embodiment, the second photoresist pattern PR2 may overlap the first gate electrode GE1, and the third photoresist pattern PR3 may be spaced apart from the second photoresist pattern PR2.

[0105] The second gate metal layer GL2 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. For example, the second gate metal layer GL2 may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta) or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers. In an exemplary embodiment, the second gate metal layer GL2 may include molybdenum or an alloy thereof.

[0106] Reference Fig.13 and Fig.14The second gate metal layer GL2 is patterned by using the second photoresist pattern PR2 and the third photoresist pattern PR3 as masks. In this way, a gate metal pattern including a gate wiring pattern GP disposed under the second photoresist pattern PR2 and a bottom gate electrode BGE disposed under the third photoresist pattern PR3 can be formed.

[0107] The second gate metal layer GL2 may be patterned by a dry etching process. For example, for the dry etching process, a plasma containing a fluorine compound may be provided to the second gate metal layer GL2. For example, the fluorine compound may include SiF 4 CF 4 , C 3 F 8 , C 2 F 6 , CHF 3 , SF 6 Or a combination of these.

[0108] When the second gate metal layer GL2 is etched by an etching gas including a fluorine-containing compound, fluorine ions generated from the etching gas may remain on the surface of the second insulating layer 130 or may be combined with an insulating material (e.g., silicon nitride) of the second insulating layer 130. In an exemplary embodiment, a post-treatment such as a surface treatment may be performed to remove the fluorine ions.

[0109] For example, Fig.14 As shown in 6 and O 2 The plasma of the treatment gas is provided to the second insulating layer 130. The surface treatment can remove the fluorine ions remaining on the second insulating layer 130 or remove the silicon nitride combined with fluorine. In this way, the diffusion of the fluorine ions can be prevented, which can improve the reliability of the organic light emitting display device.

[0110] Surface treatment may be performed before or after removing the second photoresist pattern PR2 and the third photoresist pattern PR3.

[0111] Reference Fig.15 , a third insulating layer 140 is formed to cover the bottom gate electrode BGE and the gate wiring pattern GP.

[0112] The third insulating layer 140 may include a lower barrier layer 142 in contact with the second insulating layer 130 and the bottom gate electrode BGE, and an upper barrier layer 144 disposed on the lower barrier layer 144. In an exemplary embodiment, the lower barrier layer 142 may include silicon nitride, and the upper barrier layer 144 may include silicon oxide. Therefore, fluorine ions remaining at the second insulating layer 130 may be prevented from diffusing upward, and hydrogen ions of the lower barrier layer 142 may be prevented from diffusing upward.

[0113] Reference Fig.16 , a second active pattern AP2 is formed on the third insulating layer 140. An initial insulating layer and a third gate metal layer are formed on the second active pattern AP2, and then the initial insulating layer and the third gate metal layer are patterned to form a top gate electrode TGE disposed on the second active pattern AP2 and a gate insulating pattern 152 disposed between the top gate electrode TGE and the second active pattern AP2.

[0114] The fourth insulating layer 160 is formed to cover the top gate electrode TGE, the second active pattern AP2 and the third insulating layer 140 .

[0115] Thereafter, a first data metal pattern including a first source electrode SE1, a first drain electrode DE1, a second source electrode SE2, a second drain electrode DE2, and a gate connection electrode GCE is formed. The first source electrode SE1 contacts the first doping region PD1 of the first active pattern AP1. The first drain electrode DE1 contacts the second doping region PD2 of the first active pattern AP1. The second source electrode SE2 and the second drain electrode DE2 contact the second active pattern AP2. The second drain electrode DE2 is spaced apart from the second source electrode SE2. The gate connection electrode GCE contacts the top gate electrode TGE.

[0116] Thereafter, a fifth insulating layer 170 is formed to cover the first data metal pattern. A connection electrode CE is formed to pass through the fifth insulating layer 170 so that the connection electrode CE contacts the first drain electrode DE1. A sixth insulating layer 180 is formed to cover the connection electrode CE.

[0117] Thereafter, the organic light emitting diode 200, the pixel defining layer 190, and the encapsulation layer 300 are formed. The organic light emitting diode 200 includes a lower electrode 210, a light emitting layer 220, and an upper electrode 230.

[0118] According to an exemplary embodiment, an organic light emitting display device includes an oxide-based semiconductor element and a silicon-based semiconductor element, and has a double-gate structure in which a top gate electrode and a bottom gate electrode are respectively disposed above and below an active pattern of the oxide-based semiconductor element. In this way, the reliability of the oxide-based semiconductor element can be improved, and the oxide-based semiconductor element can be controlled more accurately.

[0119] In addition, since the third insulating layer 140 including the lower barrier layer 142 including silicon nitride and the upper barrier layer 144 including silicon oxide to serve as a barrier insulating layer is disposed between the bottom gate electrode BGE and the second active pattern AP2, diffusion of fluorine ions from the bottom gate electrode BGE and the insulating layer thereunder can be prevented. Therefore, the reliability of the oxide-based semiconductor element can be improved.

[0120] Fig.17is a cross-sectional view illustrating an organic light emitting display device according to an exemplary embodiment.

[0121] Reference Fig.17 , except for the bottom gate electrode BGE and the gate wiring pattern GP having a double-layer structure, the organic light emitting display device according to the exemplary embodiment is Fig.16 The organic light emitting display devices shown in are basically the same.

[0122] More specifically, the bottom gate electrode BGE and the gate wiring pattern GP are disposed on the second insulating layer 130 .

[0123] The bottom gate electrode BGE includes a lower layer GEb including titanium or a titanium alloy and an upper layer GEa including molybdenum or a molybdenum alloy. The gate wiring pattern GP includes a lower layer GPb including titanium or a titanium alloy and an upper layer GPa including molybdenum or a molybdenum alloy.

[0124] In exemplary embodiments, the bottom gate electrode BGE and the gate wiring pattern GP may be formed of a second gate metal layer including an upper layer including titanium or a titanium alloy and a lower layer including molybdenum or a molybdenum alloy.

[0125] In an exemplary embodiment, the upper layer may be etched by plasma of a fluorine-containing compound, and the lower layer may be etched by plasma of a material different from the fluorine-containing compound.

[0126] Therefore, the lower layer contacting the second insulating layer 130 may be etched by the plasma of the material other than the fluorine-containing compound. In this manner, fluorine ions remaining on the second insulating layer 130 or combined with the second insulating layer 130 may be substantially reduced.

[0127] In addition, a third insulating layer 140 is disposed on the bottom gate electrode BGE and the gate wiring pattern GP, ​​and includes a lower barrier layer 142 including silicon nitride and an upper barrier layer 144 including silicon oxide to serve as a blocking insulating layer. Therefore, diffusion of fluorine ions from the bottom gate electrode BGE can be prevented.

[0128] Fig.18 is a cross-sectional view illustrating an organic light emitting display device according to an exemplary embodiment.

[0129] Reference Fig.18 , except for the first active pattern AP1, the organic light emitting display device according to the exemplary embodiment is Fig.16 The organic light emitting display devices shown in are basically the same.

[0130] For example, the silicon-based semiconductor element of the organic light-emitting display device may have Fig.18For example, the first active pattern AP1 of the driving transistor may include a channel region CH1, a first high-doped region NHD1, a first low-doped region NLD1, a second low-doped region NLD2, and a second high-doped region NHD2.

[0131] The first and second high doping regions NHD1 and NHD2 may be doped with high concentration of n-type impurities such as phosphorus, arsenic, etc. The first and second low doping regions NLD1 and NLD2 may be doped with low concentration of n-type impurities.

[0132] The channel region CH1 may be defined by an undoped portion of the first active pattern AP1.

[0133] The first low-doped region NLD1 may be disposed between the first high-doped region NHD1 and the channel region CH1 , and the second low-doped region NLD2 may be disposed between the second high-doped region NHD2 and the channel region CH1 .

[0134] The first highly doped region NHD1 may be connected to the first source electrode SE1 , and the second highly doped region NHD2 may be connected to the first drain electrode DE1 .

[0135] The first active pattern AP1 having an NMOS structure may be applied to Fig.11 , Fig.12 and Fig.17 The organic light emitting display device shown in FIG.

[0136] The exemplary embodiments may be applied to various display devices. For example, the exemplary embodiments may be applied to vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, etc.

[0137] According to an exemplary embodiment, a gate metal pattern including a bottom gate electrode or a gate wiring pattern has a multi-layer structure including molybdenum / titanium. Therefore, fluorine ions may be prevented from diffusing into an insulating layer disposed on the gate metal pattern.

[0138] In addition, a blocking insulating layer is disposed on the gate metal pattern, and the blocking insulating layer includes a lower blocking layer including silicon nitride and an upper blocking layer disposed on the lower blocking layer and including silicon oxide. Therefore, fluorine ions can be blocked from diffusing from the gate metal pattern and the insulating layer disposed under the gate metal pattern.

[0139] Furthermore, after the gate metal pattern is formed, fluorine ions may be removed from the insulating layer disposed under the gate metal pattern by using plasma of a process gas.

[0140] Therefore, the reliability of the oxide-based semiconductor element can be improved.

[0141] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the claims and various obvious modifications and equivalent arrangements as will be apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: a first active pattern including a silicon semiconductor; a first insulating layer, covering the first active pattern; A first gate electrode, disposed on the first insulating layer; a second insulating layer, covering the first gate electrode; a gate wiring pattern disposed on the second insulating layer and comprising a first lower layer and a first upper layer, wherein the first lower layer comprises titanium or a titanium alloy, and the first upper layer comprises molybdenum or a molybdenum alloy; a third insulating layer covering the gate wiring pattern; and a second active pattern disposed on the third insulating layer and including an oxide semiconductor, wherein the first upper layer is formed by etching using a first etching gas including fluorine, and The first lower layer is formed by etching using a second etching gas that does not include fluorine.

2. The display device according to claim 1, wherein: The thickness of the first lower layer is 50Å to 300Å, and the thickness of the first upper layer is 2000Å to 2500Å.

3. The display device according to claim 2, wherein: The first lower layer includes titanium, and the first upper layer includes molybdenum.

4. The display device according to claim 1, wherein: The third insulating layer comprises: a lower barrier layer comprising silicon nitride; and The upper barrier layer is disposed on the lower barrier layer and comprises silicon oxide.

5. The display device according to claim 4, wherein: The thickness of the lower barrier layer is 200Å to 1000Å, and the thickness of the upper barrier layer is 1000Å to 3000Å.

6. The display device according to claim 1, further comprising: A bottom gate electrode is disposed between the second insulating layer and the third insulating layer and overlaps the second active pattern.

7. The display device according to claim 6, wherein: The bottom gate electrode comprises: a second lower layer comprising titanium or a titanium alloy; and The second upper layer includes molybdenum or a molybdenum alloy.

8. The display device according to claim 7, further comprising: A top gate electrode is disposed on the second active pattern.

9. The display device according to claim 1, further comprising: An organic light emitting diode is electrically connected to the first active pattern.

10. A method for manufacturing a display device, the method comprising: forming a first active pattern including a silicon semiconductor; forming a first insulating layer to cover the first active pattern; forming a first gate electrode on the first insulating layer; forming a second insulating layer to cover the first gate electrode; forming a gate metal layer on the second insulating layer, the gate metal layer comprising a lower layer including titanium or a titanium alloy and an upper layer including molybdenum or a molybdenum alloy; etching the upper layer by using a first etching gas including fluorine; etching the lower layer by using a second etching gas different from the first etching gas to form a gate metal pattern; forming a third insulating layer on the gate metal pattern; as well as forming a second active pattern including an oxide semiconductor on the third insulating layer, Wherein, the second etching gas does not include fluorine.

11. The method according to claim 10, wherein: The first etching gas includes at least one of SiF4, CF4, C3F8, C2F6, CHF3 and SF6.

12. The method according to claim 10, wherein: The second etching gas includes chlorine and oxygen.

13. The method according to claim 12, wherein: The second etching gas includes Cl2 and O2.

14. The method according to claim 10, wherein: The third insulating layer includes: a lower barrier layer comprising silicon nitride; and an upper barrier layer disposed on the lower barrier layer and comprising silicon oxide.

15. The method according to claim 10, wherein: The gate metal pattern includes a gate wiring pattern overlapping the first gate electrode or the first active pattern.

16. The method according to claim 15, wherein: The gate metal pattern further includes a bottom gate electrode overlapping the second active pattern.

17. The method according to claim 10, further comprising: A top gate electrode is formed on the second active pattern.

18. A method for manufacturing a display device, the method comprising: forming a first active pattern including a silicon semiconductor; forming a first insulating layer to cover the first active pattern; forming a first gate electrode on the first insulating layer; forming a second insulating layer including silicon nitride to cover the first gate electrode; forming a gate metal layer on the second insulating layer; etching the gate metal layer by using a first etching gas including fluorine to form a gate metal pattern; treating the second insulating layer using a plasma of a process gas comprising SF6 and O2; forming a third insulating layer on the gate metal pattern, the third insulating layer comprising a lower barrier layer comprising silicon nitride and an upper barrier layer disposed on the lower barrier layer and comprising silicon oxide; forming a second active pattern including an oxide semiconductor on the third insulating layer; as well as A top gate electrode is formed on the second active pattern.

19. The method according to claim 18, wherein: The gate metal pattern includes a gate wiring pattern overlapping the first gate electrode.

20. The method according to claim 18, wherein: The gate metal pattern includes a bottom gate electrode overlapping the second active pattern.

21. A display device, the display device being formed by the method according to any one of claims 18 to 20.

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