Variable resistance memory device

Abstract

A variable resistance memory device may include a first conductor, a plurality of stacked structures, and a molded pattern. The first conductor may be formed on a substrate. The plurality of stacked structures may be formed on the first conductor, and each of the plurality of stacked structures includes a lower electrode, a variable resistance pattern, and an intermediate electrode stacked on top of each other. The molded pattern may be formed on the first conductor to fill the space between the plurality of stacked structures. The upper portion of the molded pattern may include a surface-treated layer, and the lower portion of the molded pattern may include a non-surface-treated layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0098297, filed on August 23, 2018, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to a variable resistance memory device and a method of manufacturing the same. More specifically, exemplary embodiments of the present invention relate to a variable resistance memory device having a stacked crosspoint array structure and a method of manufacturing the same. Background Technology

[0004] As memory devices become highly integrated, variable resistance memory devices with vertically stacked cross-point array structures have been fabricated. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a variable resistance memory device may include a first conductor, a plurality of stacked structures, and a molded pattern. The first conductor may be formed on a substrate. The plurality of stacked structures may be formed on the first conductor, and each of the plurality of stacked structures includes a lower electrode, a variable resistance pattern, and an intermediate electrode stacked on top of each other. The molded pattern may be formed on the first conductor to fill the space between the plurality of stacked structures. The upper portion of the molded pattern may include a surface-treated layer, and the lower portion of the molded pattern may include a non-surface-treated layer.

[0006] According to an exemplary embodiment of the present invention, a variable resistance memory device may include a plurality of stacked structures, a molded pattern, and a selection pattern. The plurality of stacked structures may include a lower electrode, a variable resistance pattern, and an intermediate electrode stacked on top of each other, and each of the plurality of stacked structures may have a U-shape. The molded pattern may fill the space between the plurality of stacked structures. The selection pattern may be formed on the intermediate electrode of each of the plurality of stacked structures. The upper portion of the molded pattern may include a surface-treated layer, and the lower portion of the molded pattern may include a non-surface-treated layer.

[0007] According to an exemplary embodiment of the present invention, a variable resistance memory device may include a plurality of first conductors, a plurality of stacked structures, a molded pattern, a selection pattern, and a second conductor. The plurality of first conductors may be formed on a substrate and may extend in a first direction parallel to the upper surface of the substrate. The plurality of stacked structures may be formed on the plurality of first conductors and each may include a lower electrode, a variable resistance pattern, and an intermediate electrode stacked on top of each other. The molded pattern may be formed on the plurality of first conductors to fill the space between the plurality of stacked structures. The upper portion of the molded pattern may include a surface-treated layer, and the lower portion of the molded pattern may include a non-surface-treated layer. The selection pattern may be formed on the intermediate electrode of each of the plurality of stacked structures. The second conductor may be formed on the selection pattern and may extend in a direction perpendicular to the first direction. Attached Figure Description

[0008] The above and other features of the inventive concept will be more clearly understood by describing in detail the exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0009] Figure 1 This is a perspective view illustrating an exemplary embodiment of a variable resistance memory device according to a concept conceived in the present invention;

[0010] Figure 2 This is a perspective view illustrating a portion of an exemplary variable resistance memory device according to a concept conceived in the present invention;

[0011] Figure 3 This is a cross-sectional view showing a portion of a variable resistance memory device according to an exemplary embodiment of the present invention;

[0012] Figures 4 to 17 This is a perspective view illustrating the various stages of a method for manufacturing a variable resistance memory device according to an exemplary embodiment of the concept of the present invention;

[0013] Figure 18 This is a perspective view illustrating the various stages of a method for manufacturing a variable resistance memory device according to an exemplary embodiment of the concept of the present invention;

[0014] Figure 19 This is a perspective view illustrating an exemplary embodiment of a variable resistance memory device according to a concept conceived in the present invention;

[0015] Figure 20 This is a cross-sectional view illustrating an exemplary embodiment of a variable resistance memory cell according to a concept conceived in the present invention;

[0016] Figures 21 to 27 This is a cross-sectional view illustrating various stages of a method for manufacturing a variable resistance memory device according to an exemplary embodiment of the concept of the present invention;

[0017] Figure 28This is a cross-sectional view illustrating an exemplary embodiment of a variable resistance memory device according to the present invention. Detailed Implementation

[0018] An exemplary embodiment of the present invention provides a variable resistance memory device.

[0019] In the following description, exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. Throughout this application, the same reference numerals may refer to the same elements.

[0020] Figure 1 This is a perspective view illustrating an exemplary embodiment of a variable resistance memory device according to a concept conceived in the present invention. Figure 2 This is a perspective view illustrating a portion of an exemplary variable resistance memory device according to a concept conceived in the present invention. Figure 3 This is a cross-sectional view illustrating a portion of a variable resistance memory device according to an exemplary embodiment of the present invention. Specifically, Figure 3 It is along Figure 1 A sectional view taken by line I-I'.

[0021] Reference Figures 1 to 3 The variable resistance memory device may include a first conductive line 102a, a variable resistance memory cell, and a second conductive line 136. The variable resistance memory device may be formed on a substrate 100.

[0022] The first wire 102a may extend in a first direction parallel to the upper surface of the substrate 100. The second wire 136 may extend in a second direction parallel to the upper surface of the substrate 100 and perpendicular to the first direction. The first wire 102a and the second wire 136 may be spaced apart from each other in a third direction perpendicular to the upper surface of the substrate 100.

[0023] The variable resistance memory cell may be located at the intersection of the first conductor 102a and the second conductor 136. The variable resistance memory cell may contact the upper surface of the first conductor 102a and the lower surface of the second conductor 136.

[0024] Substrate 100 may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. Substrate 100 may include III-V compounds, such as GaP, GaAs, GaSb, etc. The upper portion of substrate 100 may include a well region doped with p-type or n-type impurities.

[0025] In an exemplary embodiment of the present invention, an insulating layer may also be formed on the substrate 100. Therefore, the first conductive line 102a may be formed on the insulating layer. In an exemplary embodiment of the present invention, peripheral circuitry including transistors, contact plugs, wiring, etc., may be formed on the substrate 100. A lower insulating layer may be formed on the substrate 100 to at least cover the peripheral circuitry.

[0026] The first conductor 102a may include a metal or a metal nitride, such as copper, aluminum, tungsten, cobalt, titanium, tantalum, titanium nitride (TiNx), tungsten nitride (WNx), tantalum nitride (TaNx), etc.

[0027] The variable resistance memory cell may include a lower electrode 110c, a variable resistance pattern 120c, an intermediate electrode 122a, and a selection pattern 132a stacked in sequence. The variable resistance memory cell may be formed on a first conductor 102a and may have a cylindrical shape.

[0028] In an exemplary embodiment of the present invention, the variable resistance memory cell may further include an upper electrode stacked on the selection pattern 132a.

[0029] The lower electrode 110c can contact the upper surface of the first wire 102a. In an exemplary embodiment of the present invention, the lower electrode 110c may have a U-shape in a cross-sectional view taken along a first direction. Therefore, the protruding portion of the U-shaped structure may extend in a second direction. The lower electrode 110c can be used as a heating electrode, thereby generating Joule heating through the lower electrode 110c.

[0030] The lower electrode 110c may include a metal nitride or a metal silicon nitride with a resistance higher than that of the first wire 102a. For example, the lower electrode 110c may include titanium nitride, titanium silicon nitride, tungsten nitride, tungsten silicon nitride, tantalum nitride, tantalum silicon nitride, zirconium nitride, zirconium silicon nitride, etc.

[0031] In an exemplary embodiment of the present invention, an insulating liner 112c may be formed on the lower electrode 110c. The insulating liner 112c may be conformally formed on the inner surface of the U-shaped lower electrode 110c. Therefore, the insulating liner 112c may also be U-shaped. The insulating liner 112c may include, for example, silicon oxide.

[0032] The variable resistance pattern 120c may protrude from the uppermost end of the lower electrode 110c in a third direction. Therefore, the variable resistance pattern 120c may be formed on the two uppermost surfaces of the lower electrodes 110c facing each other. Each of the variable resistance patterns 120c may be formed on the lower electrode 110c and may extend in a second direction. Therefore, the stacked structure including the lower electrode 110c and the variable resistance pattern 120c may have a U-shape in a cross-sectional view taken along the first direction.

[0033] In other words, two variable resistor patterns 120c can be formed on the lower electrode 110c. Therefore, two variable resistor memory cells can be formed on one lower electrode 110c.

[0034] In an exemplary embodiment of the present invention, the width of the variable resistor pattern 120c in the first direction may be greater than the width of the lower electrode 110c in the first direction. For example, the width of the variable resistor pattern 120c in the first direction may be substantially equal to the sum of the width of the lower electrode 110c in the first direction and the width of the insulating liner 112c in the first direction.

[0035] Since the stacked structure including the lower electrode 110c and the variable resistance pattern 120c can be U-shaped, the contact area between the lower electrode 110c and the variable resistance pattern 120c can be reduced. Therefore, the heat transfer efficiency from the lower electrode 110c to the variable resistance pattern 120c can be increased.

[0036] The variable resistance pattern 120c may include a phase change material, which may undergo a phase transition between an amorphous and a crystalline state due to Joule heating transferred from the lower electrode 110c. The resistance of the variable resistance pattern 120c can be changed by the phase transition of the variable resistance pattern 120c, thus the variable resistance memory cell can be in a set state or a reset state. In this case, the variable resistance memory cell can be used in a phase change random access memory (PRAM) device.

[0037] In an exemplary embodiment of the present invention, the phase change material may include a GST material in which germanium (Ge), antimony (Sb), and / or tellurium (Te) may be combined in a predetermined ratio. In an exemplary embodiment of the present invention, the variable resistance pattern 120c may have a superlattice structure comprising alternately stacked GeTe and SbTe layers. The variable resistance pattern 120c may include an In-Sb-Te (IST) material or a Bi-Sb-Te (BST) material.

[0038] In an exemplary embodiment of the present invention, the variable resistance pattern 120c may include a material whose resistance can be changed by a magnetic field or by rotationally transmitted torque (STT). For example, the variable resistance pattern 120c may include a ferromagnetic material, such as iron (Fe), nickel (Ni), cobalt (Co), dysprosium (Dy), gadolinium (Gd), etc. In this case, the variable resistance memory cell can be used in a magnetic random access memory (MRAM) device.

[0039] In an exemplary embodiment of the present invention, the variable resistance pattern 120c may include a perovskite-based material or a transition metal oxide. Perovskite-based materials may include, for example, STO (SrTiO3), BTO (BaTiO3), and PCMO (PrTiO3). 1-X Ca X MnO3, etc. For example, transition metal oxides may include zirconium oxide (ZrO3). x ), Hafnium oxide (HfO) x ), aluminum oxide (AlO) x In this case, variable resistance memory cells can be used in resistive random access memory (ReRAM) devices.

[0040] Intermediate electrodes 122a may be formed on each of the variable resistance patterns 120c. Intermediate electrodes 122a may extend in a second direction. Therefore, in a cross-sectional view taken along the first direction, the first stacked structure including the stacked lower electrodes 110c, variable resistance patterns 120c, and intermediate electrodes 122a may have a U-shape.

[0041] The intermediate electrode 122a may include a metal nitride or a metal silicon nitride. For example, the intermediate electrode 122a may include, for example, titanium nitride, titanium silicon nitride, tungsten nitride, tungsten silicon nitride, tantalum nitride, tantalum silicon nitride, zirconium nitride, zirconium silicon nitride, etc.

[0042] Multiple first stacked structures may be located on the first conductor 102a. Furthermore, the first stacked structures may be arranged in a first direction and a second direction.

[0043] A first molded pattern 106 may be formed between the outer walls of the first stacked structure in a first direction. The first molded pattern 106 may include silicon nitride. A second molded pattern 116 may fill the inner space of the U-shaped first stacked structure. The second molded pattern 116 may include silicon nitride.

[0044] A combined structure including a first stacked structure and a first molded pattern 106 and a second molded pattern 116 can be formed on the first conductor 102a and can extend in a first direction.

[0045] The upper portions of the first molded pattern 106 and the second molded pattern 116 may include a surface-treated layer formed by performing a surface treatment. Additionally, the lower portions of the first molded pattern 106 and the second molded pattern 116 include a non-surface-treated layer that does not require surface treatment. Therefore, the hardness of the upper portion of the first molded pattern 106 may differ from the hardness of the lower portion. Similarly, the hardness of the upper portion of the second molded pattern 116 may differ from the hardness of the lower portion. In other words, the hardness of the upper portions of the first molded pattern 106 and the second molded pattern 116 may be greater than the hardness of the lower portions, respectively.

[0046] For example, the upper portions of the first molded pattern 106 and the second molded pattern 116 may respectively include first silicon nitride 106a and 115a by performing surface treatments. The first molded pattern 106 and the second molded pattern 116 may also respectively include second silicon nitride 106b and 115b without performing surface treatments. The hardness of the first silicon nitride 106a and 115a may be greater than the hardness of the second silicon nitride 106b and 115b.

[0047] Furthermore, the polishing selectivity and tolerance of the first silicon nitrides 106a and 115a can be greater than those of the second silicon nitrides 106b and 115b. For example, the first silicon nitrides 106a and 115a can be almost completely removed during the polishing process of the variable resistance layer.

[0048] In an exemplary embodiment of the present invention, the upper portions of the first molding pattern 106 and the second molding pattern 116 may include first silicon nitride 106a and 115a modified by performing a low-temperature plasma treatment. The lower portions of the first molding pattern 106 and the second molding pattern 116 may include second silicon nitride 106b and 115b without performing a low-temperature plasma treatment. For example, the defects and dangling bonds in the first silicon nitride 106a and 115a may be fewer than those included in the second silicon nitride 106b and 115b.

[0049] In an exemplary embodiment of the present invention, the first silicon nitrides 106a and 115a may further include a gas for plasma processing. Therefore, when analyzing the composition of the first silicon nitrides 106a and 115a, peak values ​​of the composition of the gas used for plasma processing in the first silicon nitrides 106a and 115a can be detected. The gas used for plasma processing may include argon, hydrogen, helium, etc.

[0050] In an exemplary embodiment of the present invention, the upper portion of the first molding pattern 106 and the second molding pattern 116 may include first silicon nitride 106a and 115a modified by an ion doping process. The lower portion of the first molding pattern 106 and the second molding pattern 116 may include second silicon nitride 106b and 115b without doped ions.

[0051] In an exemplary embodiment of the present invention, the first silicon nitrides 106a and 115a may include ions for the doping process. Therefore, when analyzing the composition of the first silicon nitrides 106a and 115a, peak values ​​of the ion composition in the first silicon nitrides 106a and 115a can be detected. The ions for the doping process may include silicon ions.

[0052] In an exemplary embodiment of the present invention, the first silicon nitride 106a and 115a may have a certain thickness such that a portion thereof can be retained after polishing of the variable resistance layer. In an exemplary embodiment of the present invention, the first silicon nitride 106a and 115a may have approximately [thickness missing] from the upper surface of the first molding pattern 106 and the second molding pattern 116 downwards. to approximately The thickness. In an exemplary embodiment of the present invention, the first silicon nitride 106a and 115a may be located at a position above the top surface of the lower electrode 110c.

[0053] In an exemplary embodiment of the present invention, the first silicon nitrides 106a and 115a may be opposite to at least a portion of the sidewall of the intermediate electrode 122a. In an exemplary embodiment of the present invention, the first silicon nitrides 106a and 115a may be opposite to at least a portion of the sidewall of the intermediate electrode 122a and the sidewall of the variable resistance pattern 120c.

[0054] The first sidewall of the variable resistor pattern 120c is contactable with the first molded pattern 106, and the second sidewall of the variable resistor pattern 120c facing the first sidewall is contactable with the second molded pattern 116. A recess can be defined by a sidewall of the first molded pattern 106, a sidewall of the second molded pattern 116, and the top surfaces of the lower electrode 110c and the insulating liner 112c. The longitudinal direction of the recess can be a second direction. The variable resistor pattern 120c and the intermediate electrode 122a can be formed in the recess.

[0055] The filling insulating layer 130 may be formed in the second direction between the first conductive lines 102a, and in the second direction between the merged structure including the first stacked structure and the first molded pattern 106 and the second molded pattern 116. The filling insulating layer 130 may be formed on the substrate 100 and may extend in the first direction. For example, the filling insulating layer 130 may include silicon nitride or silicon oxide. The filling insulating layer 130 may be a layer that does not undergo low-temperature plasma processing or ion doping processes.

[0056] The upper surfaces of the first stacked structure, the first molded pattern 106 and the second molded pattern 116, and the filling insulating layer 130 may be coplanar with each other and substantially flat.

[0057] Pattern 132a can be selected to contact the upper surface of the intermediate electrode 122a. Pattern 132a can be cylindrical. Pattern 132a can be used as a switching element.

[0058] In an exemplary embodiment of the present invention, the selected pattern 132a may include a bidirectional threshold switch (OTS) material based on a chalcogenide compound. In an exemplary embodiment of the present invention, the selected pattern 132a may include arsenic (As), and may also include at least two selected from silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), selenium (Se), indium (In), and tin (Sn). In an exemplary embodiment of the present invention, the selected pattern 132a may include Se, and may also include at least two selected from As, Si, Ge, Sb, Te, In, and Sn.

[0059] In an exemplary embodiment of the present invention, selected pattern 132a may include a compound with five components such as AsTeGeSiIn, or a compound with six components such as AsTeGeSiSbS. In an exemplary embodiment of the present invention, selected pattern 132a may also include dopants such as carbon, boron, oxygen, nitrogen, sulfur and / or phosphorus.

[0060] The first insulating pattern 134a can be formed (see Figure 16 The space between the selected patterns 132a is filled in the second direction. The first insulating pattern 134a may comprise silicon nitride or silicon oxide. The structure including the selected patterns 132a and the first insulating pattern 134a may extend in the second direction.

[0061] The second conductor 136 may be formed on the selected pattern 132a and the first insulating pattern 134a. The second conductor 136 may comprise a metal or a metal nitride, such as copper, aluminum, tungsten, cobalt, titanium, tantalum, or titanium nitride (TiN). x ), Tungsten nitride (WN) x ), Tantalum nitride (TaN) x )wait.

[0062] The structure including the selected pattern 132a and the first insulating pattern 134a and the second conductor can be stacked sequentially and can extend in a second direction. A second insulating layer 140 can be formed on the second conductors 136 to fill the space between the second conductors 136. The second insulating layer 140 may include silicon nitride or silicon oxide.

[0063] In an exemplary embodiment of the present invention, the first insulating pattern 134a may include a material substantially the same as the material of the second insulating layer 140.

[0064] As described above, in a variable resistance memory device according to an exemplary embodiment of the present invention, a variable resistance memory cell may be formed at the intersection of the first wire 102a and the second wire 136.

[0065] Figures 4 to 17This is a perspective view illustrating the various stages of a method for manufacturing a variable resistance memory device according to an exemplary embodiment of the present invention.

[0066] Reference Figure 4 The first conductive layer 102 and the first molding layer 104 may be formed on the substrate 100 in sequence.

[0067] The first conductive layer 102 and the first molding layer 104 can be formed by physical vapor deposition (PVD), sputtering, or chemical vapor deposition (CVD).

[0068] The first conductive layer 102 may include a metal or a metal nitride, such as copper, aluminum, tungsten, cobalt, titanium, tantalum, or titanium nitride (TiN). x ), Tungsten nitride (WN) x For example, the first molding layer 104 may include silicon nitride, tantalum nitride, etc.

[0069] The first molding layer 104 can be used as a portion for forming the lower electrode, the variable resistance pattern, and the intermediate electrode. Therefore, the first molding layer 104 can be formed with a height equal to or greater than the height of the first stacked structure including the lower electrode, the variable resistance pattern, and the intermediate electrode.

[0070] Reference Figure 5 The first molding layer 104 may be partially etched to form a first initial molding pattern 104a extending in the second direction.

[0071] A first trench 108 may be formed between first initial molded patterns 104a, and the first trench 108 may extend in a second direction. A first conductive layer 102 may be exposed through the bottom of the first trench 108.

[0072] Reference Figure 6 The lower electrode layer 110 and the insulating inner liner layer 112 may be formed sequentially and conformally on the surface of the first trench 108 and the upper surface of the first initial molding pattern 104a. A second molding layer 114 may be formed on the insulating inner liner layer 112 to fully fill the inner space of the first trench 108.

[0073] The lower electrode layer 110, the insulating inner liner layer 112, and the second molding layer 114 can be formed by, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes.

[0074] The lower electrode layer 110 may be formed as a metal nitride or a metal silicon nitride with a resistance higher than that of the first conductive layer 102. For example, the lower electrode layer 110 may include, for example, titanium nitride, titanium silicon nitride, tungsten nitride, tungsten silicon nitride, tantalum nitride, tantalum silicon nitride, zirconium nitride, zirconium silicon nitride, etc. For example, the insulating inner liner layer 112 may include silicon oxide. For example, the second molding layer 114 may include silicon nitride. In other words, the first initial molding pattern 104a and the second molding layer 114 may include the same insulating material.

[0075] Reference Figure 7 The second molding layer 114, the insulating inner liner layer 112, and the lower electrode layer 110 can be planarized until the upper surface of the first initial molding pattern 104a can be exposed, so as to form the second initial molding pattern 114a, the first initial insulating inner liner 112a, and the first initial lower electrode 110a in the first trench 108, respectively.

[0076] For example, the planarization process may include a chemical mechanical polishing (CMP) process. When the planarization process is performed, the upper surfaces of the first initial molding pattern 104a and the second initial molding pattern 114a, the first initial insulating liner 112a, and the first initial lower electrode 110a may be exposed.

[0077] Reference Figure 8 A surface treatment process can be performed to harden the upper part of the first initial molded pattern 104a and the second initial molded pattern 114a.

[0078] For example, the upper portions of the first initial molding pattern 104a and the second initial molding pattern 114a include first silicon nitride 106a and 115a modified by a surface treatment process. The lower portions of the first initial molding pattern 104a and the second initial molding pattern 114a may include second silicon nitride 106b and 115b without performing a surface treatment process. Defects and dangling bonds included in the upper portions of the first initial molding pattern 104a and the second initial molding pattern 114a can be cured or removed by a surface treatment process. Therefore, the hardness of the first silicon nitride 106a and 115a may be greater than the hardness of the second silicon nitride 106b and 115b. In addition, the polishing selectivity and etching selectivity of the first silicon nitride 106a and 115a may be higher than the polishing selectivity and etching selectivity of the second silicon nitride 106b and 115b.

[0079] In an exemplary embodiment of the present invention, the first silicon nitride 106a and 115a may have a certain thickness, such that a portion of the first silicon nitride 106a and 115a can be retained after a subsequent polishing process of the variable resistance layer. Therefore, the first silicon nitride 106a and 115a may not be completely consumed, and the shape of the first silicon nitride 106a and 115a can be retained. Furthermore, the first silicon nitride 106a and 115a may have a certain thickness, such that a portion of the first silicon nitride 106a and 115a can be retained after a subsequent partial etching process of the first initial insulating liner.

[0080] In an exemplary embodiment of the present invention, the first silicon nitrides 106a and 115a may have approximately [missing information - likely a number] downwards from the upper surfaces of the first molding pattern 106 and the second molding pattern 116. to approximately The thickness. In an exemplary embodiment of the present invention, the first silicon nitride 106a and 115a may be located above the top surface of the subsequently formed lower electrode.

[0081] In exemplary embodiments of the present invention, the surface treatment process may include low-temperature plasma treatment or ion doping. The surface treatment process can be performed at a temperature that will not cause thermal damage to the underlying components or layers.

[0082] For example, low-temperature plasma treatment can be performed on the upper surfaces of the first initial molding pattern 104a and the second initial molding pattern 114a, the first initial insulating liner 112a, and the first initial lower electrode 110a.

[0083] Cryogenic plasma processing can be performed at temperatures ranging from approximately 100°C to 300°C. In cryogenic plasma processing, gases such as argon, hydrogen, or helium can be used. When performing cryogenic plasma processing, first silicon nitrides 106a and 115a may be formed on top of the first initial molding pattern 104a and the second initial molding pattern 114a. Additionally, the first silicon nitrides 106a and 115a may also include a plasma processing gas for cryogenic plasma processing, such as argon, hydrogen, or helium.

[0084] In an exemplary embodiment of the present invention, an ion doping process may be performed on the upper surfaces of the first initial molding pattern 104a and the second initial molding pattern 114a, the first initial insulating liner 112a, and the first initial lower electrode 110a. The doping process may be performed at a temperature of about 100°C to about 300°C. In the doping process, silicon ions may be doped, for example.

[0085] When the doping process is performed, the first silicon nitrides 106a and 115a may be formed on top of the first initial molding pattern 104a and the second initial molding pattern 114a. Therefore, the first silicon nitrides 106a and 115a may also include ions for the doping process, such as silicon ions.

[0086] Reference Figure 9 The upper portions of the first initial lower electrode 110a and the first initial insulating liner 112a can be etched to form the second initial lower electrode 110b and the second initial insulating liner 112b, respectively. Therefore, a recess 117 extending in the second direction can be formed in the etched portions of the first initial lower electrode 110a and the first initial insulating liner 112a. The recess 117 can be defined by a sidewall of the first initial molding pattern 104a, a sidewall of the second initial molding pattern 114a, and the upper surfaces of the second initial lower electrode 110b and the second initial insulating liner 112b.

[0087] Since the recess 117 can be formed by partially removing the first initial lower electrode 110a and the first initial insulating liner 112a, the width of the recess 117 in the first direction can be greater than the width of the first initial lower electrode 110a in the first direction. Furthermore, the width of the recess 117 in the first direction can be substantially the same as the sum of the widths of the first initial lower electrode 110a and the first initial insulating liner 112a in the first direction.

[0088] The etching of the upper portion of the first initial lower electrode 110a and the upper portion of the first initial insulating liner 112a can be performed by isotropic etching processes. For example, each of the isotropic etching processes may include a wet etching process. The first initial lower electrode 110a may be etched using a first etchant, and the first initial insulating liner 112a may be etched using a second etchant different from the first etchant.

[0089] The upper portions of the first initial molding pattern 104a and the second initial molding pattern 114a may respectively include first silicon nitride 106a and 115a having high etch selectivity and high etch tolerance. Therefore, process defects such as damage or removal of the upper portions of the first initial molding pattern 104a and the second initial molding pattern 114a during the etching process can be reduced.

[0090] In a cross-sectional view taken along the first direction, the second initial lower electrode 110b and the second initial insulating liner 112b may have a U-shape.

[0091] In an exemplary embodiment of the present invention, the recess 117 can be used as a portion for forming a variable resistance pattern and an intermediate electrode. Therefore, the bottom of the recess 117 can correspond to the top surface of the lower electrode and the insulating liner, which are formed later. In an exemplary embodiment of the present invention, the bottom of the recess 117 can be lower than the bottom of the first silicon nitride 106a.

[0092] Reference Figure 10 The variable resistance layer 120 can be formed on the first initial molding pattern 104a and the second initial molding pattern 114a to fill the recess 117. The variable resistance layer 120 may include a phase change material such as GST, IST, or BST. The variable resistance layer 120 can be formed by a CVD process or an ALD process.

[0093] Reference Figure 11 The variable resistance layer 120 may be planarized until the upper surfaces of the first initial molding pattern 104a and the second initial molding pattern 114a are exposed to form the first initial variable resistance pattern 120a in the recess 117. The planarization process may include a CMP (chemical mechanical polishing) process.

[0094] The first initial variable resistance pattern 120a may protrude from the uppermost surface of the second initial lower electrode 110b in a third direction and may extend in a second direction. The stacked structure including the second initial lower electrode 110b and the first initial variable resistance pattern 120a may have a U-shape.

[0095] Because the upper surfaces of the first initial molding pattern 104a and the second initial molding pattern 114a can have high polishing selectivity and high polishing resistance, damage or consumption of the first initial molding pattern 104a and the second initial molding pattern 114a can be reduced during the CMP process. Therefore, the first initial variable resistance pattern 120a can have the desired structure.

[0096] Reference Figure 12 The upper portion of the first initial variable resistance pattern 120a may be etched to form a second initial variable resistance pattern 120b. Therefore, the upper surface of the second initial variable resistance pattern 120b may include a second recess. For example, the etching process may include an etch-back process. The second recess may extend in a second direction.

[0097] An intermediate electrode layer may be formed on the first initial molding pattern 104a and the second initial molding pattern 114a to fill the second recess. The intermediate electrode layer may be planarized until the upper surfaces of the first initial molding pattern 104a and the second initial molding pattern 114a are exposed to form an initial intermediate electrode 122 in the second recess. The planarization process may include a CMP process.

[0098] Because the upper surfaces of the first initial molding pattern 104a and the second initial molding pattern 114a can have high polishing tolerance and polishing selectivity, damage or consumption of the first initial molding pattern 104a and the second initial molding pattern 114a can be reduced during the CMP process. Therefore, the initial intermediate electrode 122 can have the desired structure.

[0099] Reference Figure 13 The first initial molding pattern 104a, the second initial molding pattern 114a, the initial intermediate electrode 122, the second initial variable resistor pattern 120b, the second initial lower electrode 110b, the second initial insulating liner 112b, and the first conductive layer 102 can be partially etched to form a second trench 126 extending in the first direction. Therefore, a structure including the first conductor 102a, the lower electrode 110c, the insulating liner 112c, the variable resistor pattern 120c, the intermediate electrode 122a, the first molding pattern 106, and the second molding pattern 116 can be formed on the side of the second trench 126. This structure can extend in the first direction.

[0100] The first conductor 102a may extend in the first direction.

[0101] A first stacked structure may be formed on the first conductor 102a. The first stacked structure may include a stacked lower electrode 110c, a variable resistor pattern 120c, and an intermediate electrode 122a. An insulating liner 112c may be formed on the lower electrode 110c. A second molded pattern 116 may be formed to fill the inner space of the first stacked structure. Additionally, a first molded pattern 106 may be formed on the first conductor 102a, and the first molded pattern 106 may be formed on the sidewall of the merged structure including the first stacked structure and the second molded pattern 116 in a first direction.

[0102] In a cross-sectional view taken along the first direction, the lower electrode 110c may have a U-shape. The variable resistor pattern 120c and the intermediate electrode 122a may be formed on the uppermost surface of the lower electrode 110c. Therefore, the first stacked structure including the lower electrode 110c, the variable resistor pattern 120c, and the intermediate electrode 122a may have a U-shape.

[0103] Reference Figure 14 An insulating layer may be formed on the first molding pattern 106, the second molding pattern 116, and the intermediate electrode 122a to fill the second trench 126. The insulating layer may be planarized until the upper surfaces of the first molding pattern 106 and the second molding pattern 116 are exposed to form a filling insulating layer 130 in the second trench 126.

[0104] A filler insulating layer 130 may be formed on the substrate 100 and may extend in a first direction. The filler insulating layer 130 may include silicon nitride or silicon oxide. Surface treatment processes such as low-temperature plasma processing or ion doping may not be performed on the filler insulating layer 130.

[0105] Reference Figure 15 A selective material layer may be formed on the first molding pattern 106 and the second molding pattern 116, the filler insulating layer 130, and the intermediate electrode 122a. The selective material layer may be patterned to form an initial selective pattern 132 extending in a first direction. Each of the initial selective patterns 132 may contact the upper surface of the intermediate electrode 122a.

[0106] A third groove extending in the first direction can be formed between the initially selected patterns 132.

[0107] The first insulating layer may be formed to fill the third trench. The first insulating layer may be planarized until the upper surface of the initial selected pattern 132 is exposed to form a first initial insulating pattern 134. The first initial insulating pattern 134 may include silicon nitride or silicon oxide.

[0108] In exemplary embodiments of the present invention, an upper electrode layer may also be formed on the selected material layer. For example, the upper electrode layer may include a carbon-containing conductive material, such as C, CN, TiCN, TaCN, etc. In this case, the subsequently formed variable resistance memory device may further include an upper electrode between the selected pattern and the second conductor.

[0109] Reference Figure 16 A second conductive layer may be formed on the initial selection pattern 132 and the first initial insulating pattern 134. An etch mask extending in the second direction may be formed on the second conductive layer, and the second conductive layer may be etched using the etch mask to form a second conductive line 136 extending in the second direction.

[0110] Next, the initial selection pattern 132 and the first initial insulating pattern 134 can be etched using an etching mask to form the selection pattern 132a and the first insulating pattern 134a. The selection pattern 132a may be cylindrical and may contact the intermediate electrode 122a.

[0111] When the etching process is performed, a fourth trench 138 may be formed between the second conductors 136. The fourth trench 138 may extend in the second direction.

[0112] Reference Figure 17 A second insulating layer 140 is formed on the second conductor 136 to fill the fourth trench 138. The second insulating layer 140 may include silicon nitride or silicon oxide.

[0113] Through the above process, a variable resistance memory device can be manufactured as a variable resistance memory cell included at the intersection of the first conductor 102a and the second conductor 136. The variable resistance memory cell may include a lower electrode 110c, a variable resistance pattern 120c, an intermediate electrode 122a, and a selection pattern 132a. In a cross-sectional view taken along a first direction, the lower electrode 110c may have a U-shape. The variable resistance pattern 120c, the intermediate electrode 122a, and the selection pattern 132a may be formed on each of the two uppermost surfaces of the lower electrode 110c that face each other. Therefore, two variable resistance memory cells may be formed on the lower electrode 110c.

[0114] Figure 18 This is a perspective view illustrating the various stages of a method for manufacturing a variable resistance memory device according to an exemplary embodiment of the present invention.

[0115] The process described below can be referenced. Figures 4 to 17 The descriptions are basically the same, except for the order of the surface treatment processes used to harden the upper part of the first and second initial molded patterns.

[0116] First, executable and reference Figures 4 to 7 The processes shown are essentially the same or similar. Therefore, as Figure 7 As shown, a first initial molding pattern 104a and a second initial molding pattern 114a, a first initial insulating liner 112a, and a first initial lower electrode 110a can be formed. Then, as referred to Figure 9 As shown, the upper portions of the first initial lower electrode 110a and the first initial insulating liner 112a can be etched to form the second initial lower electrode 110b and the second initial insulating liner 112b. Therefore, referring to... Figure 18 The recess 117 extending in the second direction can be formed in the etched portions of the first initial lower electrode 110a and the first initial insulating liner 112a.

[0117] Then, as referenced Figure 8 As shown, a surface treatment process can be performed to harden the upper portions of the first initial molding pattern 104a and the second initial molding pattern 114a. In other words, the surface treatment process can be performed after the recess 117 is formed.

[0118] Next, executable and reference Figures 10 to 17 The processes shown are basically the same or similar, to form Figure 17 The variable resistance memory device shown.

[0119] Figure 19 This is a perspective view illustrating an exemplary embodiment of a variable resistance memory device according to a concept conceived in the present invention.

[0120] exist Figure 19 In this embodiment, the variable resistance memory device may include a cross-point cell array of a second-level memory cell structure according to an exemplary embodiment of the present invention. However, in an exemplary embodiment of the present invention, the variable resistance memory device may include a third-level memory cell structure or a cross-point cell array having more than three levels of memory cell structures.

[0121] Reference Figure 19 The variable resistance memory device may be formed on the substrate 100. The variable resistance memory device may include a first wire 102a, a second wire 136, a third wire 202a and a fourth wire 236, which may be spaced apart from each other in a third-direction orientation.

[0122] The first wire 102a and the second wire 136 may cross each other. The third wire 202a and the fourth wire 236 may cross each other. The first memory cell may be arranged at the intersection of the first wire 102a and the second wire 136, and the second memory cell may be arranged at the intersection of the third wire 202a and the fourth wire 236.

[0123] The first-level memory cell array, including the first wire 102a, the second wire 136, and the first memory cell, can be referenced. Figures 1 to 3 The ones shown are basically the same.

[0124] Additionally, the second-level memory cell array, including the third conductor 202a, the fourth conductor 236, and the second memory cell, can be referenced. Figures 1 to 3 The ones shown are basically the same.

[0125] In other words, a variable resistance memory device may include an array of memory cells having a substantially identical structure that is repeatedly stacked upwards on a third side.

[0126] The manufacturing process will be briefly described below. Figure 19 The method for the variable resistor memory device shown.

[0127] First, executable and reference Figures 4 to 17 The processes shown are essentially the same or similar to form the first-level memory cell array on the substrate.

[0128] Then, the reference can be executed again on the first-level memory cell array. Figures 4 to 17 The processes shown are essentially the same or similar, used to form a second-level memory cell array on the second insulating layer.

[0129] When forming the second-level memory cell array, the features of the first memory cells included in the first-level memory cells should not be damaged or altered. For example, when a surface treatment process is performed on the first and second molding patterns included in the second-level memory cell array, the underlying first memory cells should not be damaged.

[0130] In exemplary embodiments of the present invention, the surface treatment process may include a low-temperature plasma treatment or ion doping process performed at a temperature of about 100°C to about 300°C. In the surface treatment process, minimal thermal damage may occur in the underlying first memory cell. Therefore, the surface treatment process can be used in the fabrication of resistive memory devices having a second or more stacked array of memory cells.

[0131] Figure 20 This is a cross-sectional view illustrating an exemplary embodiment of a variable resistance memory cell according to a concept conceived in this invention.

[0132] Reference Figure 20 The variable resistance memory device may include a first conductive line 302a, a variable resistance memory cell, and a second conductive line 322. The variable resistance memory device may be formed on a substrate 300.

[0133] The first conductor 302a and the second conductor 322 may be spaced apart from each other in a third direction and may intersect each other vertically. A variable resistor memory cell may be formed at the intersection of the first conductor 302a and the second conductor 322. The variable resistor memory cell may contact the upper surface of the first conductor 302a and the lower surface of the second conductor 322. The first conductor 302a may extend in a first direction, and the second conductor 322 may extend in a second direction.

[0134] In an exemplary embodiment of the present invention, the variable resistance memory cell may include a lower electrode 304a, a variable resistance pattern 314a, an intermediate electrode 316, and a selection pattern 320 stacked in sequence. In an exemplary embodiment of the present invention, an upper electrode may also be formed on the selection pattern 320. The variable resistance memory cell may have a cylindrical shape.

[0135] The molded pattern 308 can be formed between the first conductor 302a, the variable resistor pattern 314a and the intermediate electrode 316.

[0136] Spacer 312 may surround a stacked structure including a variable resistance pattern 314a and an intermediate electrode 316. Spacer 312 may be disposed between stacked structures including the variable resistance pattern 314a, the intermediate electrode 316, and a molded pattern 308. Spacer 312 may include an insulating material, such as silicon nitride, silicon oxynitride, silicon oxide, etc.

[0137] The width of the variable resistor pattern 314a can be reduced by the spacer 312. The lower width of the variable resistor pattern 314a can be smaller than the width of the lower electrode 304a below the variable resistor pattern 314a. Therefore, the contact area between the variable resistor pattern 314a and the lower electrode 304a can be reduced, and the heat transfer efficiency from the lower electrode 304a to the variable resistor pattern 314a can be increased.

[0138] The upper surface of the molded pattern 308 and the upper surface of the intermediate electrode 316 can be coplanar.

[0139] The upper portion of the molded pattern 308 may include a surface-treated layer, and the lower portion of the molded pattern 308 may include a layer without surface treatment. Therefore, the hardness of the upper portion of the molded pattern 308 may differ from the hardness of the lower portion. In other words, the hardness of the upper portion of the molded pattern 308 may be greater than the hardness of the lower portion.

[0140] In an exemplary embodiment of the present invention, the upper portion of the molded pattern 308 may include a first silicon nitride 310a modified by surface treatment, and the lower portion of the molded pattern 308 may include a second silicon nitride 310b that has not undergone surface treatment.

[0141] In an exemplary embodiment of the present invention, the surface treatment may include a low-temperature plasma treatment process or an ion doping process. The hardness of the first silicon nitride 310a may be greater than the hardness of the second silicon nitride 310b.

[0142] For example, the first silicon nitride 310a may also include a gas for plasma processing. Therefore, when analyzing the composition of the first silicon nitride 310a, the peak value of the composition of the gas used for plasma processing in the first silicon nitride 310a can be detected. The gas used for plasma processing may include argon, hydrogen, helium, etc.

[0143] In an exemplary embodiment of the present invention, the first silicon nitride 310a may further include ions for use in the doping process. Therefore, when analyzing the composition of the first silicon nitride 310a, the peak value of the gas composition used in the doping process of the second silicon nitride 310b can be detected. Ions used for plasma processing may include silicon ions.

[0144] In an exemplary embodiment of the present invention, the first silicon nitride 310a may be opposite to at least a portion of the sidewall of the intermediate electrode 316. In an exemplary embodiment of the present invention, the first silicon nitride 310a may be opposite to at least a portion of the sidewall of the intermediate electrode 316 and the sidewall of the variable resistance pattern 314a.

[0145] Selected pattern 320 may be formed on intermediate electrode 316. First insulating pattern may be formed in a second direction between selected patterns 320. First insulating pattern may include silicon oxide or silicon nitride. In addition, second wire 322 may be formed on selected pattern 320 and first insulating pattern.

[0146] A second insulating layer 324 may be formed on the molded pattern 308 to fill the space between the second conductors 322. The second insulating layer 324 may include silicon oxide or silicon nitride. In an exemplary embodiment of the inventive concept, the second insulating layer 324 may include a material substantially the same as that of the first insulating pattern.

[0147] In an exemplary embodiment of the present invention, the intersection unit array structure may be a multi-level structure.

[0148] For example, a third conductor may also be formed above the second conductor and extend in the first direction. The second and third conductors may be spaced apart from each other in the third direction. Variable resistance memory cells may be formed at the intersection of the second and third conductors. Additionally, a molding pattern may be formed between the second conductor 322, the variable resistance pattern 314a, and the intermediate electrode in a manner substantially the same as the molding pattern described below. The second conductor may be used for both the lower and upper cell array structures.

[0149] Figures 21 to 27 This is a cross-sectional view illustrating various stages of a method for manufacturing a variable resistance memory device according to an exemplary embodiment of the present invention.

[0150] Reference Figure 21 The first conductive layer 302, the lower electrode layer 304, and the sacrificial layer 306 can be formed on the substrate 300 in sequence.

[0151] The sacrificial layer 306 can be used as a portion for forming the variable resistance pattern and the intermediate electrode. Therefore, the height of the sacrificial layer 306 can be equal to or greater than the height of the stacked structure including the variable resistance pattern and the intermediate electrode.

[0152] The sacrificial layer 306 can be formed by an ALD process or a CVD process. The sacrificial layer 306 may include oxides, such as silicon oxide.

[0153] Reference Figure 22 The sacrificial layer 306, the lower electrode layer 304, and the first conductive layer 302 may be partially etched to form the first conductive line 302a, the lower electrode 304a, and the sacrificial pattern 306a stacked sequentially on the substrate 300. In addition, a molded pattern 308 may be formed between the first conductive line 302a, the lower electrode 304a, and the sacrificial pattern 306a.

[0154] Specifically, an etch mask having a linear shape extending in the first direction can be formed on the sacrificial layer 306. The sacrificial layer 306, the lower electrode layer 304, and the first conductive layer 302 can be etched using the etch mask to form an initial structure extending in the first direction. A first conductive line 302a extending in the first direction can be formed by an etching process. In addition, a first trench extending in the first direction can be formed between the initial structures.

[0155] The molding layer may be formed to fill the first trench. The molding layer may include silicon nitride. The molding layer may be planarized until the upper surface of the sacrificial layer can be exposed to form a first initial molding pattern in the first trench.

[0156] Next, the sacrificial layer 306, the lower electrode layer 304, and the first initial molding pattern can be etched to form a second trench extending in the second direction. Therefore, a stacked structure including the sequentially stacked lower electrode 304a and sacrificial pattern 306a can be formed on the first conductor 302a. The stacked structure may have a cylindrical shape.

[0157] A molding layer may be formed to fill a second trench. The molding layer may include silicon nitride. The molding layer may be planarized until the upper surface of the sacrificial layer is exposed to form a second initial molding pattern in the second trench. The first initial molding pattern and the second initial molding pattern may be merged into a molding pattern 308. The molding pattern 308 may fill the gaps between the stacked structures.

[0158] Reference Figure 23 A surface treatment process can be performed to harden the upper part of the molded pattern 308.

[0159] For example, the upper portion of the molded pattern 308 includes a first silicon nitride 310a modified by a surface treatment process. The lower portion of the molded pattern 308 may include a second silicon nitride 310b without performing a surface treatment process.

[0160] The hardness of the upper part of the molded pattern 308 can be greater than that of the lower part. Furthermore, the polishing selectivity and etching selectivity of the upper part of the molded pattern 308 can be higher than those of the lower part. This reduces surface damage to the molded pattern during subsequent cleaning, etching, or polishing processes.

[0161] In an exemplary embodiment of the present invention, the surface treatment process may include low-temperature plasma treatment or ion doping process. The surface treatment process may be compared with reference to... Figure 8 The two are basically the same.

[0162] Reference Figure 24The upper portion of the sacrificial pattern 306a can be removed to form a first hole 311 that exposes the lower electrode 304a through the molded pattern 308. The removal process may include an isotropic etching process. The molded pattern 308 can be exposed through the sidewalls of the first hole 311.

[0163] The spacer layer may be conformally formed on the sidewalls and bottom of the first hole 311 and on the molded pattern 308. The spacer layer may include silicon nitride, silicon oxynitride, or silicon oxide. The spacer layer may be anisotropically etched to form spacers 312 on the sidewalls of the first hole 311.

[0164] Reference Figure 25 A variable resistance layer may be formed on the molded pattern 308 to fill the first hole 311. The variable resistance layer is planarized until the upper surface of the molded pattern 308 is exposed to form an initial variable resistance pattern 314 in the first hole 311.

[0165] Because the upper surface of the molded pattern 308 can have high polishing selectivity and high polishing tolerance, damage and consumption of the molded pattern 308 can be reduced in the CMP process.

[0166] Reference Figure 26 The upper portion of the initial variable resistor pattern 314 can be partially etched to form the variable resistor pattern 314a. Therefore, the upper surface of the variable resistor pattern 314a may have a recess. The etching process may include a back-etching process.

[0167] An intermediate electrode layer may be formed on the molded pattern 308 to fill the recess. The intermediate electrode layer may be planarized until the upper surface of the molded pattern 308 is exposed to form an intermediate electrode 316 in the recess.

[0168] Because the upper surface of the molded pattern 308 can have a high polishing tolerance, damage and consumption of the molded pattern 308 can be reduced during the CMP process. Therefore, the desired intermediate electrode 316 and variable resistance pattern 314a can be formed.

[0169] Reference Figure 27 A selected material layer may be formed on the variable resistance pattern 314a and the molding pattern 308. The selected material layer may be patterned to form an initial selected pattern extending in a first direction. A first initial insulating pattern may be formed to fill the space between the initial selected patterns. The first initial insulating pattern may include silicon nitride or silicon oxide. In an exemplary embodiment of the inventive concept, an upper electrode layer may also be formed on the selected material layer.

[0170] A second conductive layer may be formed on an initial selected pattern and a first initial insulating pattern. An etch mask extending in a second direction may be formed on the second conductive layer. The second conductive layer may be etched using the etch mask to form a second conductive line 322 extending in the second direction.

[0171] Next, the initial selection pattern and the first initial insulating pattern can be etched using an etching mask to form the selection pattern 320 and the first insulating pattern. The selection pattern 320 may contact the intermediate electrode 316 and may have a cylindrical shape.

[0172] Then, a second insulating layer 324 may be formed between the second conductors 322. The second insulating layer 324 may include silicon nitride or silicon oxide.

[0173] Therefore, through the above process, a variable resistance memory device including a variable resistance memory cell at the intersection of the first and second conductors can be manufactured.

[0174] Figure 28 This is a cross-sectional view illustrating an exemplary embodiment of a variable resistance memory device according to the present invention.

[0175] In a variable resistance memory device, the stacking order of the variable resistance memory cells can be... Figure 20 The stacking order of the memory cells shown is different.

[0176] Reference Figure 28 The variable resistance memory device may include a first wire 302a, a variable resistance memory cell, and a second wire 322.

[0177] The variable resistance memory cell may include a lower electrode 304a, a selection pattern 320, an intermediate electrode 350, a variable resistance pattern 314a, and an upper electrode 354 stacked in sequence. Spacers 312 may be formed on the sidewalls of the stacked structure including the variable resistance pattern 314a and the upper electrode 354.

[0178] A lower insulating pattern 352 may be formed between the stacked structures including a lower electrode 304a, a selection pattern 320, and an intermediate electrode 350. A molded pattern 308 may be formed on the lower insulating pattern 352 to fill the space between the stacked structures where spacers may be formed.

[0179] The upper portion of the molded pattern 308 includes a surface-treated layer that has undergone surface treatment, and the lower portion of the molded pattern 308 may include a non-surface-treated layer that has not undergone surface treatment. Therefore, the upper portion of the molded pattern 308 may have a different hardness than the lower portion of the molded pattern 308. In other words, the hardness of the upper portion of the molded pattern 308 may be greater than the hardness of the lower portion of the molded pattern 308.

[0180] For example, the upper portion of the molded pattern 308 may include a first silicon nitride 310a modified by performing a surface treatment. The lower portion of the molded pattern 308 may include a second silicon nitride 310b that has not undergone surface treatment.

[0181] In an exemplary embodiment of the present invention, the first silicon nitride 310a may be opposite to at least a portion of the sidewall of the upper electrode 354 on the variable resistance pattern 314a. In an exemplary embodiment of the present invention, the first silicon nitride 310a may be opposite to at least a portion of both the sidewall of the upper electrode 354 and the sidewall of the variable resistance pattern 314a.

[0182] For manufacturing a semiconductor device, the first conductive line 302a, the lower electrode 304a, the selection pattern 320, and the intermediate electrode 350 can be formed by a patterning process, and the lower insulating pattern 352 can be formed to fill the space between the first conductive line 302a, the lower electrode 304a, the selection pattern 320, and the intermediate electrode 350. Then, the variable resistor pattern 314a and the upper electrode 354 can be formed by a damascene process. In this case, the processes for forming the molded pattern 308, the spacer 312, the variable resistor pattern 314a, and the upper electrode 354 can be referenced. Figures 22 to 26 The ones shown are essentially the same. Then, a second wire 322 and a second insulating layer 324 can be formed on the upper electrode 354.

[0183] As described above, semiconductor devices can be applied to highly integrated variable resistance memory devices.

[0184] According to an exemplary embodiment of the present invention, in a variable resistance memory device, the upper surface of the molded pattern can be hardened, thereby allowing the variable resistance pattern between the molded patterns to have a desired structure. Therefore, the variable resistance memory device can have a stable structure and high reliability.

[0185] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of the inventive concept as defined by the claims.

Claims

1. A variable resistance memory device, comprising: The first conductive line on the substrate; The first conductor has a plurality of stacked structures, each of which includes a lower electrode, a variable resistance pattern, and an intermediate electrode stacked on top of each other; and The molded pattern on the first conductor fills the space between the plurality of stacked structures. The upper part of the molded pattern includes a surface treatment layer, and the lower part of the molded pattern includes a non-surface treatment layer. The upper part of the molded pattern includes a first silicon nitride, and the lower part of the molded pattern includes a second silicon nitride. The hardness of the first silicon nitride is greater than that of the second silicon nitride.

2. The variable resistance memory device according to claim 1, wherein, The lower electrode has a U-shape, and the variable resistance pattern and the intermediate electrode are formed sequentially on each of the uppermost surfaces of the lower electrode that face each other.

3. The variable resistance memory device according to claim 1, wherein, The variable resistance pattern and the intermediate electrode are formed in a recess defined by the top surface of the lower electrode and the sidewall of the molded pattern.

4. The variable resistance memory device according to claim 1, wherein, The upper part of the molded pattern is higher than the lower surface of the variable resistor pattern relative to the substrate.

5. The variable resistance memory device according to claim 1, wherein, The upper part of the molded pattern is opposite to at least some portions of the sidewall of the intermediate electrode.

6. The variable resistance memory device according to claim 1, wherein, The upper part of the molded pattern also includes argon, hydrogen, helium, or silicon for surface treatment.

7. The variable resistance memory device according to claim 1, wherein, Each of the plurality of structures includes the first conductor, the plurality of stacked structures, and the molded pattern. The plurality of structures extend in a first direction, and An insulating layer is used to fill the space between the plurality of structures.

8. The variable resistance memory device according to claim 1, further comprising: The selection pattern on the intermediate electrode of each of the plurality of stacked structures; as well as The second conductor on the selected pattern extends in a direction perpendicular to the extension direction of the first conductor.

9. A variable resistance memory device, comprising: Multiple stacked structures, each stacked structure including a lower electrode, a variable resistance pattern and an intermediate electrode stacked on top of each other, wherein each of the multiple stacked structures has a U-shape; Molded patterns that fill the spaces between the plurality of stacked structures; and The selection pattern on the intermediate electrode of each of the plurality of stacked structures. The upper part of the molded pattern includes a surface treatment layer, and the lower part of the molded pattern includes a non-surface treatment layer. The upper part of the molded pattern includes a first silicon nitride, and the lower part of the molded pattern includes a second silicon nitride. The hardness of the first silicon nitride is greater than that of the second silicon nitride.

10. The variable resistance memory device according to claim 9, wherein, The lower electrode has a U-shape, and the variable resistance pattern and the intermediate electrode are formed sequentially on each of the uppermost surfaces of the lower electrode that face each other.

11. The variable resistance memory device according to claim 9, wherein, The upper part of the molded pattern is opposite to at least some portions of the sidewall of the intermediate electrode.

12. The variable resistance memory device according to claim 9, wherein, The upper part of the molded pattern also includes argon, hydrogen, helium, or silicon for surface treatment.

13. The variable resistance memory device according to claim 9, further comprising: Substrate; Multiple first wires extend in a first direction parallel to the upper surface of the substrate; as well as A plurality of second conductive lines are spaced apart from the plurality of first conductive lines in a direction perpendicular to the upper surface of the substrate, and extend in a second direction perpendicular to the first direction and parallel to the upper surface of the substrate. The memory cell, which includes the plurality of stacked structures and the selected pattern, is located at the intersection of the plurality of first wires and the plurality of second wires.

14. A variable resistance memory device, comprising: Multiple first wires on a substrate, wherein each of the first wires extends in a first direction parallel to the upper surface of the substrate; Multiple stacked structures on the multiple first conductors, each of the multiple stacked structures including a lower electrode, a variable resistance pattern and an intermediate electrode stacked on top of each other; The molded patterns on the plurality of first conductors fill the space between the plurality of stacked structures, wherein the upper part of the molded pattern includes a surface-treated layer and the lower part of the molded pattern includes a non-surface-treated layer. The selection pattern on the intermediate electrode of each of the plurality of stacked structures; and The second guide wire on the selected pattern extends in a direction perpendicular to the first direction. The upper part of the molded pattern includes a first silicon nitride, and the lower part of the molded pattern includes a second silicon nitride. The hardness of the first silicon nitride is greater than that of the second silicon nitride.

15. The variable resistance memory device according to claim 14, wherein, The lower electrode has a U-shape, and the variable resistance pattern and the intermediate electrode are formed sequentially on each of the uppermost surfaces of the lower electrode that face each other.

16. The variable resistance memory device according to claim 14, wherein, The upper part of the molded pattern also includes argon, hydrogen, helium, or silicon for surface treatment.

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