Packaging structure forming method

Abstract

The present disclosure relates to a method for forming a packaging structure. A packaging structure includes a first redistribution structure formed on a substrate, and the first redistribution structure includes a first conductive line, a second conductive line, and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line parallel to the first conductive line has a second width, and the first overlapping conductive line has a third width greater than the first width and the second width. The packaging structure includes a first packaging unit formed above the first redistribution structure, the first packaging unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function from the first die stack.

Description

Technical Field

[0001] The present disclosure relates to a method for forming a package structure, and more particularly to a method for forming a package structure without using any intermediate substrate having a through-substrate via. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by conformably depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning the various material layers using lithography processes to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing along scribe lines between integrated circuits. Individual dies are typically packaged separately in multi-chip modules or other types of packages.

[0003] New packaging technologies have been developed, such as package on package (PoP), in which a top package with a device die is bonded to a bottom package with another device die. By adopting new packaging technologies, various packages with different or similar functions are integrated together.

[0004] While existing packages and methods of making packages are generally adequate for their intended purposes, they are not completely satisfactory in all respects. Summary of the invention

[0005] The present disclosure provides a method for forming a package structure. The method includes forming a dielectric layer on a carrier substrate, wherein the carrier substrate includes a first region, a second region, and a third region, and the third region is between the first region and the second region; forming a photoresist layer above the dielectric layer; performing a first exposure process on the photoresist layer to form a first single exposure region; performing a second exposure process on the photoresist layer to form a second single exposure region and a double exposure region, wherein the width of the double exposure region is greater than the width of the first single exposure region; developing the photoresist layer to form a patterned photoresist layer; patterning the dielectric layer by using the patterned photoresist layer as a mask to form a groove; forming a conductive layer in the groove in the dielectric layer, wherein the conductive layer includes a first conductive line in the first region, a second conductive line in the second region, and an overlapping conductive line in the third region, and the third width of the overlapping conductive line of the conductive layer is wider than the first width of the first conductive line of the conductive layer; and arranging a semiconductor die and a die stack above the conductive layer, wherein the semiconductor die has a different function from the die stack.

[0006] The present disclosure provides a method for forming a package structure. The method includes forming a dielectric layer on a carrier substrate, wherein the carrier substrate includes a first region, a second region, and a third region, and the third region is between the first region and the second region; forming a photoresist layer above the dielectric layer, wherein the photoresist layer includes a first portion in the first region, a second portion in the second region, and a third portion in the third region; setting a first photomask on the first region and the third region; performing a first exposure process on the first portion and the third portion of the photoresist layer; setting a second photomask on the second region and the third region; performing a second exposure process on the second portion and the third portion of the photoresist layer, wherein the third portion of the photoresist layer is exposed developing the photoresist layer to form a patterned photoresist layer; patterning the dielectric layer to form a groove; forming a first redistribution structure in the groove in the dielectric layer, wherein the first redistribution structure includes a first conductive line in the first region and an overlapping conductive line in the third region, and the third width of the overlapping conductive line is greater than the first width of the first conductive line; forming a first packaging unit above the first redistribution structure, wherein the first packaging unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a function different from that of the first die stack; forming a packaging layer above the first packaging unit; removing the carrier substrate; and forming a packaging substrate below the first redistribution structure.

[0007] The present disclosure provides a packaging structure. The packaging structure includes a first redistribution structure and a first packaging unit. The first redistribution structure is formed above a substrate. The first redistribution structure includes a first conductive line, a second conductive line, and a first overlapping conductive line, the first overlapping conductive line is between the first conductive line and the second conductive line, wherein the first conductive line has a first width, the second conductive line is parallel to the first conductive line and has a second width, and the first overlapping conductive line has a third width, the third width is greater than the first width and the second width. The first packaging unit is formed above the first redistribution structure. The first packaging unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function from the first die stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The concepts of the present disclosure can be better understood from the following examples and the accompanying drawings. It should be noted that the schematic diagrams are examples and that different features are not illustrated here. The sizes of different features may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 A top view of a package structure according to an embodiment of the present disclosure is shown.

[0010] Figures 2A to 2M Cross-sectional views of various sites for forming a package structure according to an embodiment of the present disclosure are shown.

[0011] Figure 2M' A cross-sectional view of a package structure according to an embodiment of the present disclosure is shown.

[0012] Figure 3A-1 A top view of an exposed region of a photoresist layer after a first exposure process according to an embodiment of the present disclosure is shown.

[0013] Figure 3A-2 Shown in Figure 3A-1 An enlarged schematic diagram of area A in FIG.

[0014] Figure 3B-1 A top view of an exposed region of a photoresist layer after a second exposure process according to an embodiment of the present disclosure is shown.

[0015] Figure 3B-2 Shown in Figure 3B-1 An enlarged schematic diagram of area A in FIG.

[0016] Figure 3C-1 The embodiment according to the present disclosure is shown in Figure 1 A top view of a conductive layer in a redistribution structure of a packaging structure.

[0017] Figure 3C-2 Shows Figure 3C-1 An enlarged schematic diagram of area A.

[0018] Figure 4A A top view of a first photomask and a second photomask according to an embodiment of the present disclosure is shown.

[0019] Figure 4B A top view showing the overlap between a first reticle and a second reticle according to an embodiment of the present disclosure is shown.

[0020] Figure 4C A top view showing the overlap between a first reticle and a second reticle according to an embodiment of the present disclosure is shown.

[0021] Figure 4D A top view of a monitoring pattern in a redistribution structure of a package structure according to an embodiment of the present disclosure is shown.

[0022] Figure 5A A top view of a package structure according to an embodiment of the present disclosure is shown.

[0023] Figure 5B An overlapping top view of a first reticle, a second reticle, a third reticle, and a fourth reticle according to an embodiment of the present disclosure is shown.

[0024] Figure 5C A top view of a conductive layer of a package structure according to an embodiment of the present disclosure is shown.

[0025] Figure 5DA top view of a conductive layer of a package structure according to an embodiment of the present disclosure is shown.

[0026] Fig. 6A A top view of a package structure according to an embodiment of the present disclosure is shown.

[0027] Figure 6B The embodiment of the present disclosure is shown along Fig. 6A Cross-sectional view taken along line segment C-C'.

[0028] Figure 6C A top view of a conductive layer of a package structure according to an embodiment of the present disclosure is shown.

[0029] Fig.6D A top view of a conductive layer of a package structure according to an embodiment of the present disclosure is shown.

[0030] Fig. 7A A top view of a package structure according to an embodiment of the present disclosure is shown.

[0031] Figure 7B The embodiment of the present disclosure is shown along Fig. 7A Cross-sectional view taken along line segment D-D'.

[0032] FIG. 7C to FIG. 7E A top view of a conductive layer of a package structure according to an embodiment of the present disclosure is shown.

[0033] Fig. 8A A top view of a package structure according to an embodiment of the present disclosure is shown.

[0034] Figure 8B The embodiment of the present disclosure is shown along Fig. 8A Cross-sectional view taken along line segment E-E'.

[0035] The reference numerals are described as follows:

[0036] 100a~Package structure

[0037] 174~Package Unit

[0038] 178~Input / output port

[0039] 180~Packaging substrate

[0040] 182~Ring

[0041] 104~Dielectric layer

[0042] 120~Semiconductor bare crystal

[0043] 130~Bare crystal stacking

[0044] W a ~Width

[0045] L a Length

[0046] A-A'~Line segment

[0047] 102~Carrier substrate

[0048] 106~Photoresist layer

[0049] 11~First Area

[0050] 12~Second Area

[0051] 13~Third Area

[0052] 104a, 106a~Part 1

[0053] 104b, 106b~Part 2

[0054] 104c, 106c~Part 3

[0055] 10~First mask

[0056] 15~First exposure process

[0057] E1~Single exposure area

[0058] B~Unexposed area

[0059] 20~Second mask

[0060] 25~Second exposure process

[0061] E2~Double Exposure Area

[0062] A~Area

[0063] 27~Development process

[0064] 107~Groove

[0065] 108~Conductive layer

[0066] 110~Redistribution structure

[0067] 108a~first conductive line

[0068] 108b~Second conductive line

[0069] 108c~Overlapping conductive wires

[0070] W1~First width

[0071] W2~Second width

[0072] W3~Third width

[0073] S1~First spacing

[0074] S2~Second spacing

[0075] S3~The third spacing

[0076] 112~Conductive pad

[0077] 108g~Connecting metal wire

[0078] 122~Substrate

[0079] 124, 144~Conductive pad

[0080] 126, 146~Conductive connector

[0081] 132A, 132B, 132C~Semiconductor bare die

[0082] 131~Buffer die

[0083] 136~Joint structure

[0084] 134~Through substrate hole

[0085] 138, 148 ~ Base glue layer

[0086] H1~First Height

[0087] H2~Second Height

[0088] G1~First gap

[0089] G2~Second gap

[0090] 150~Encapsulation layer

[0091] 160~Frame belt

[0092] 164~Conductive connector

[0093] 170~Adhesive layer

[0094] 172~cover structure

[0095] 100b~Package structure

[0096] L x , L y Length

[0097] W x , W y ~Width

[0098] 16~First Mark

[0099] 26~Second Mark

[0100] 10a~First cutting line

[0101] 20a~Second cutting line

[0102] L o ~Overlap length

[0103] L e ~Exposure length

[0104] 109~First monitoring conductive line

[0105] 209~Second monitoring conductive line

[0106] 100c~Package structure

[0107] B-B'~Line segment

[0108] 30~Third light mask

[0109] 40~Fourth light mask

[0110] 21~4th Area

[0111] 108d~Fourth conductive line

[0112] 22~Fifth Area

[0113] 108e~Fifth conductive line

[0114] 23~Sixth Area

[0115] 108f~Second overlapping conductive line

[0116] 100d~Package structure

[0117] C-C'~Line segment

[0118] G3~Third gap

[0119] 174a~First packaging unit

[0120] 110a~First redistribution structure

[0121] 174b~Second packaging unit

[0122] 110b~Second redistribution structure

[0123] 100e~Package structure

[0124] D-D'~Line segment

[0125] 174c~Third packaging unit

[0126] 174d~Fourth packaging unit

[0127] 100f~Package structure

[0128] E-E'~Line segment DETAILED DESCRIPTION

[0129] The following disclosure provides many different embodiments or examples to implement the different features of the present invention. The following disclosure describes specific examples of various components and their arrangement ports to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present disclosure describes a first feature formed on or above a second feature, it means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the same reference symbols and / or marks may be reused in different examples of the following disclosure. These repetitions are for the purpose of simplification and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0130] Some variations of the embodiments are described. In various schematic diagrams and embodiments, the same figure marks are used to represent the same elements. It should be understood that additional operations can be provided before, between, and after the method, and for other embodiments of the method, some of the operations described can be replaced or removed.

[0131] Other features and procedures may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3D integrated circuit (IC) device. The test structure may include a test pad formed on a redistribution layer or substrate that allows the use of probes and / or probe cards, etc., to test the 3D package or 3D integrated circuit. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods of the present disclosure can be used in conjunction with a test method that combines intermediate verification of known good dies to increase yield and reduce costs.

[0132] The present disclosure provides an embodiment for a packaging structure and a method for forming the same. Figure 1 A top view of a package structure 100a according to an embodiment of the present disclosure is shown. The package structure 100a is a multi-chip module (MCM) including at least two different functional dies integrated on a fan-out redistribution structure. The package structure 100a may be a chip-on-wafer-on-substrate (CoWoS) package or other suitable package.

[0133] like Figure 1As shown, a package unit 174 and an input / output port 178 are formed over a package substrate 180, and a ring 182 surrounds the package unit 174. The package unit 174 includes a semiconductor die 120 and a plurality of die stacks 130 formed on a dielectric layer 104. The semiconductor die 120 has a different function from the die stacks 130. In some embodiments, the semiconductor die 120 is between two adjacent die stacks 130. In some embodiments, the size of the semiconductor die 120 is larger than the size of the die stacks 130.

[0134] In some embodiments, the semiconductor die 120 is sawn from a wafer and may be a "known-good-die". The semiconductor die 120 may be a system-on-chip (SoC). In some other embodiments, the semiconductor die 120 is a system on integrated circuit (SoIC), which includes two or more chips with integrated functions.

[0135] The die stack 130 includes a plurality of memory dies. The semiconductor die 120 has a different function from each of the plurality of memory dies. The memory die may include a static random access memory (SRAM) device, a dynamic random access memory (DRAM) device, a high bandwidth memory (HBM), or another memory die. In some embodiments, the semiconductor die 120 is a system on integrated circuit (SoIC) device, and the die stack 130 is a high bandwidth memory (HBM).

[0136] The input / output port 178 is formed adjacent to the package unit 174. The input / output port 178 is configured to receive signals from the semiconductor die 120 and the die stack 130 or to transmit signals to an external environment. The input / output port 178 may be a die.

[0137] In some embodiments, the package substrate 180 is a printed circuit board (PCB), a ceramic substrate, or another suitable package substrate. The ring 182 is used to protect the package unit 174 and prevent the package unit 174 from bending.

[0138] The ring 182 provides adequate auxiliary function and warpage control. In some embodiments, the ring 182 includes auxiliary materials, such as metal, ceramic or a combination thereof.

[0139] The package unit 174 has a width W along the vertical direction. a , and has a length L in the horizontal direction a In some embodiments, the area (W a ×L a ) at about 1710mm 2 To about 3430mm 2 within the range.

[0140] Although Figure 1 Four die stacks 130 are shown surrounding one semiconductor die 120 , but the number of semiconductor dies 120 and the number of die stacks 130 may be adjusted according to actual applications.

[0141] Figures 2A to 2M Cross-sectional views of various sites for forming a package structure 100 a according to an embodiment of the present disclosure are shown. Figure 2A Shows along Figure 1 Cross-sectional view taken along line segment A-A'.

[0142] like Figure 2A As shown, a dielectric layer 104 is formed over a carrier substrate 102. A photoresist layer 106 is formed over the dielectric layer 104. The carrier substrate 102 includes a first region 11, a second region 12, and a third region 13, the third region 13 being between the first region 11 and the second region 12. The dielectric layer 104 includes a first portion 104a in the first region 11, a second portion 104b in the second region 12, and a third portion 104c in the third region 13 between the first region 11 and the second region 12. The photoresist layer 106 includes a first portion 106a in the first region 11, a second portion 106b in the second region 12, and a third portion 106c in the third region 13.

[0143] The carrier substrate 102 is configured to provide temporary mechanical and structural assistance during subsequent process steps. According to some embodiments, the carrier substrate 102 includes glass, silicon oxide, aluminum oxide, metal, combinations thereof, and / or the like. According to some embodiments, the carrier substrate 102 includes a metal frame.

[0144] The dielectric layer 104 may be made of or include one or more polymer materials. The polymer material(s) may include polybenzoxazole (PBO), polyimide (PI), one or more other suitable polymer materials, or combinations thereof. In some embodiments, the polymer material is photosensitive. In some embodiments, some or all of the dielectric layer 104 may be made of or include a dielectric material other than a polymer material. The dielectric material may include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or combinations thereof.

[0145] Then, as shown in FIG. 2B , according to an embodiment of the present disclosure, a first photomask 10 is disposed over the photoresist layer 106, and a first exposure process 15 is performed on the photoresist layer 106. The first photomask 10 is disposed over the first region 11 and the third region 13, but not over the second region 12. After performing the first exposure process 15, some portions of the photoresist layer 106 are exposed and are marked as single exposure regions E1. Some other portions of the photoresist layer 106 are not exposed and are marked as unexposed regions B.

[0146] Next, as shown in FIG. 2C , according to an embodiment of the present disclosure, a second mask 20 is disposed over the photoresist layer 106, and a second exposure process 25 is performed on the photoresist layer 106. The second mask 20 is disposed over the second region 12 and the third region 13, but not over the first region 11. After performing the second exposure process 25, some portions of the photoresist layer 106 are exposed and are marked as single exposure regions E1. Some other portions of the photoresist layer 106 are not exposed and are marked as unexposed regions B. In addition, some portions of the photoresist layer 106 are exposed twice in the third region 13 and are marked as double exposure regions E2.

[0147] The first exposure process 15 and the second exposure process 25 are performed in the same chamber to reduce process cost and time. In some other embodiments, in addition to the first exposure process 15 and the second exposure process 25, the third exposure process and the fourth exposure process are performed in the same chamber, and then the metal material is developed once to form the conductive line in the redistribution structure.

[0148] Figure 3A-1 A top view of an exposed region of the photoresist layer 106 after the first exposure process 15 according to an embodiment of the present disclosure is shown. Figure 3A-2 Shown in Figure 3A-1 An enlarged schematic diagram of area A in FIG. Figure 3B-1A top view of an exposed region of the photoresist layer 106 after the second exposure process 25 according to an embodiment of the present disclosure is shown. Figure 3B-2 Shown in Figure 3B-1 An enlarged schematic diagram of area A in FIG.

[0149] like Figure 3A-1 and Figure 3A-2 As shown, the single exposure area E1 is in the first area 11 and the third area 13. Figure 3B-1 and Figure 3B-2 As shown, the single exposure area E1 is in the second area 12 and the third area 13. Since some parts of the photoresist layer 106 in the third area 13 are exposed twice, some parts of the photoresist layer 106 are called double exposure areas E2. The width of the double exposure area E2 is greater than the width of the single exposure area E1.

[0150] It should be noted that the first photomask 10 is limited to the maximum size of the proposed reticle. Since the first photomask 10 is not large enough to cover the entire area of ​​the photoresist layer 106, two or more masks can be used to expose the entire area of ​​the photoresist layer 106. In some embodiments, the first photomask 10 and the second photomask 20 are used to expose the entire area of ​​the photoresist layer 106.

[0151] Afterwards, if Figure 2D As shown, according to an embodiment of the present disclosure, the photoresist layer 106 is developed to form a patterned photoresist layer 106. The photoresist layer 106 is developed by performing a developing process 27.

[0152] There are two types of development processes: positive tone development (PTD) process and negative tone development (NTD) process. The positive tone development process uses a positive tone developer, which generally refers to a developer that selectively dissolves and removes the exposed portion of the photoresist layer 106. The negative tone development process uses a negative tone developer, which generally refers to a developer that selectively dissolves and removes the unexposed portion of the photoresist layer 106. In some embodiments, the positive tone developer is an aqueous-based developer, such as tetraalkylammonium hydroxide (TMAH). In some embodiments, the negative tone developer is an organic-based developer, such as n-butyl acetate (n-BA).

[0153] Then, if Figure 2EAs shown, a positive tone development (PTD) process is performed to remove the single exposure area E1 and the double exposure area E2 of the photoresist layer 106 by a developer, and the unexposed area B remains.

[0154] Afterwards, if Figure 2F As shown, according to an embodiment of the present disclosure, the dielectric layer 104 is patterned by using the patterned photoresist layer 106 as a mask. The pattern of the patterned photoresist layer 106 is transferred to the dielectric layer 104. As a result, the trench 107 is formed in the dielectric layer 104.

[0155] Afterwards, if Figure 2G As shown, according to an embodiment of the present disclosure, a metal material is formed in the trench 107 to form a conductive layer 108 . The conductive layer 108 is a part of the redistribution structure 110 .

[0156] The conductive layer 108 may be made of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta) or tantalum alloy. In some embodiments, the conductive layer 108 is formed by electroplating, electroless plating, printing, chemical vapor deposition (CVD) process or physical vapor deposition (PVD) process.

[0157] Figure 3C-1 A top view of a conductive layer 108 in a redistribution structure 110 of a package structure 100 a according to an embodiment of the present disclosure is shown. Figure 3C-1 The locations of the first region 11 , the second region 12 and the third region 13 of the dielectric layer 104 in the redistribution structure 110 are shown. Figure 3C-2 Shows Figure 3C-1 An enlarged schematic diagram of area A.

[0158] like Figure 3C-1 and Figure 3C-2 As shown, the conductive layer 108 includes a first conductive line 108a in the first region 11, a second conductive line 108b in the second region 12, and an overlapping conductive line 108c in the third region 13. The first conductive line 108a is parallel to the second conductive line 108b. In some embodiments, the first conductive line 108a and the second conductive line 108b are aligned in a straight line. In some other embodiments, the first conductive line 108a and the second conductive line 108b are not aligned.

[0159] The first conductive line 108a has a first width W1, the second conductive line 108b has a second width W2, and the overlapping conductive line 108c has a third width W3. The third width W3 is greater than the first width W1 and the second width W2. The first width W1 may be greater than, equal to, or less than the second width W2. In some embodiments, the third width (W3) of the overlapping conductive line 108c and the first width (W1) of the first conductive line 108a have a relationship as shown in equation (I):

[0160] W3 = W1 + y, unit: μm-----Equation (I), and y is about 0.4 μm to about 4 μm

[0161] within the range.

[0162] In some embodiments, the first width (W1) of the first conductive line 108a is about 2 μm, and the third width (W3) of the overlapping conductive line 108c is about 6 μm. In some embodiments, the first width (W1) of the first conductive line 108a is about 2 μm, and the third width (W3) of the overlapping conductive line 108c is about 2.4 μm. When the value of y is within the above range, the alignment accuracy between the first conductive line 108a and the second conductive line 108b can be improved, and the reliability of the redistribution structure 110 can be improved.

[0163] A first spacing S1 is defined as the distance between two adjacent first conductive lines 108a, a second spacing S2 is defined between two adjacent second conductive lines 108b, and a third spacing S3 exists between two adjacent overlapping conductive lines 108c. It should be noted that the third spacing S3 is smaller than the second spacing S2 and the first spacing S1. In some embodiments, the first spacing S1 is equal to the second spacing S2. In some other embodiments, the first spacing S1 is smaller than the second spacing S2.

[0164] Furthermore, semiconductor die 120 and die stack 130 are formed over dielectric layer 104 of redistribution structure 110. In some embodiments, overlapping conductive line 108c is directly below semiconductor die 120. In some other embodiments, overlapping conductive line 108c is directly below die stack 130.

[0165] Afterwards, if Figure 2H As shown, according to an embodiment of the present disclosure, a plurality of dielectric layers 104 are stacked, and a plurality of conductive layers 108 are formed in the dielectric layers 104, and adjacent conductive layers 108 are electrically connected to each other. Therefore, a redistribution structure 110 is formed above the carrier substrate 102. Each conductive layer 108 can be formed by a first exposure process 15, a second exposure process 25, and a development process 27 to form overlapping conductive lines 108c in the third region 13.

[0166] Then, a conductive pad 112 protrudes from the top surface of the topmost dielectric layer 104. The conductive pad 112 can be used as a bonding pad, and a conductive bump (e.g., a tin-containing solder bump) and / or a conductive pillar (e.g., a copper pillar) will be formed later in the conductive pad 112. In some embodiments, the conductive pad 112 in the third region 13 is an overlapping pad. The conductive pad 112 in the third region 13 has a greater width than the conductive pad 112 in the first region 11.

[0167] It should be noted that if Figure 2H As shown, the connection metal line 108g is used to electrically connect the semiconductor die 120 and the die stack 130 (to be formed later). The connection metal line 108g is formed in the redistribution structure 110. In some embodiments, the connection metal line 108g and the overlapping conductive line 108c are at the same level. In some embodiments, the width of the connection metal line 108g is equal to the first width W1 of the first conductive line 108a. In some embodiments, the connection metal line 108g is not in the third region 13. Since the line spacing between two adjacent connection metal lines 108g may be too small, there is not enough spacing to form an overlapping connection line.

[0168] Afterwards, if Fig.2I As shown, according to an embodiment of the present disclosure, a semiconductor die 120 and a die stack 130 are formed over a carrier substrate 102. In some embodiments, the semiconductor die 120 is between two die stacks 130. The semiconductor die 120 is disposed over a redistribution structure 110. The semiconductor die 120 has a substrate 122. In some embodiments, the substrate 122 is a silicon (Si) substrate.

[0169] In some embodiments, a plurality of conductive pads 124 are formed below the semiconductor die 120 , and each conductive pad 124 is bonded to the conductive pad 112 through a conductive connector 126 .

[0170] The conductive pad 124 is made of a metal material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta) or tantalum alloy. In some embodiments, the conductive pad 124 is formed by electroplating, electroless plating, printing, chemical vapor deposition (CVD) process or physical vapor deposition (PVD) process. The conductive connector 126 is made of a solder material, such as tin (Sn), tin silver (SnAg), tin lead (SnPb), tin silver copper (SnAgCu), tin silver zinc (SnAgZn), tin zinc (SnZn), tin bismuth indium (SnBiIn), tin indium (SnIn), tin gold (SnAu), tin copper (SnCu), tin zinc indium (SnZnIn), tin silver antimony (SnAgSb) or other suitable materials. In some embodiments, the conductive connector 126 is formed by electroplating, electroless plating, printing, chemical vapor deposition (CVD) process or physical vapor deposition (PVD) process.

[0171] The die stack 130 is disposed above the redistribution structure 110. The die stack 130 includes a plurality of semiconductor dies 132A, 132B, 132C. In some embodiments, the semiconductor dies 132A, 132B, 132C are memory dies. The number of semiconductor dies 132A, 132B, 132C is not limited to two, and the number can be adjusted according to actual applications.

[0172] The semiconductor dies 132A, 132B, 132C are stacked on a buffer die (or base die) 131 that performs as a logic circuit. The semiconductor dies 132A, 132B, 132C are bonded to each other through a plurality of bonding structures 136. A plurality of through substrate vias (TSVs) 134 are formed in the semiconductor dies 132A, 132B, 132C. Signals between the semiconductor dies 132A, 132B, 132C can be transmitted through the through substrate vias (TSVs) 134 and the bonding structures 136. An underfill layer 138 is formed between the bonding structures 136.

[0173] In some embodiments, a plurality of conductive pads 144 are formed on the die stack 130 , and each conductive pad 144 is bonded to the conductive pad 112 of the redistribution structure 110 through a conductive connector 146 .

[0174] The conductive pad 144 is made of a metal material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta) or tantalum alloy. In some embodiments, the conductive pad 144 is formed by electroplating, electroless plating, printing, chemical vapor deposition (CVD) process or physical vapor deposition (PVD) process.

[0175] The conductive connector 146 is made of a solder material, such as tin (Sn), tin-silver (SnAg), tin-lead (SnPb), tin-silver-copper (SnAgCu), tin-silver-zinc (SnAgZn), tin-zinc (SnZn), tin-bismuth-indium (SnBiIn), tin-indium (SnIn), tin-gold (SnAu), tin-copper (SnCu), tin-zinc-indium (SnZnIn), tin-silver-antimony (SnAgSb) or other suitable materials. In some embodiments, the conductive connector 146 is formed by electroplating, electroless plating, printing, chemical vapor deposition (CVD) process or physical vapor deposition (PVD) process.

[0176] The semiconductor die 120 has a first height H1 along the vertical direction, and the die stack 130 has a second height H2 along the vertical direction. The first height H1 is substantially equal to the second height H2. In some embodiments, the first height H1 of the semiconductor die 120 is in the range of about 750 μm to about 850 μm. There is a first gap G1 between the semiconductor die 120 and the die stack 130. In some embodiments, the first gap G1 is in the range of about 70 μm to about 190 μm. There is a second gap G2 between the edge of the die stack 130 and the edge of the redistribution structure 110. In some embodiments, the second gap G2 is in the range of about 600 μm to about 800 μm.

[0177] Thereafter, as shown in FIG. 2J , according to an embodiment of the present disclosure, an underfill layer 148 is formed between the semiconductor die 120 , the die stack 130 , and the redistribution structure 110 .

[0178] The primer layer 148 surrounds and protects the conductive connectors 126 and 146. In some embodiments, the primer layer 148 directly contacts the conductive connectors 126 and 146.

[0179] In some embodiments, the primer layer 148 is made of or includes a polymer material. The primer layer 148 may include an epoxy-based resin. In some embodiments, the primer layer 148 includes a filler dispersed in the epoxy-based resin.

[0180] In some embodiments, the formation of the primer layer 148 includes an injecting process, a spin-on process, a dispensing process, a film lamination process, an application process, one or more other suitable processes or a combination thereof. In some embodiments, a thermal curing process is used during the formation of the primer layer 148.

[0181] Afterwards, the encapsulation layer 150 is formed on the primer layer 148. An interface is provided between the primer layer 148 and the encapsulation layer 150, and the interface is lower than the top surface of the semiconductor die 120. The encapsulation layer 150 surrounds and protects the semiconductor die 120 and the die stack 130. In some embodiments, the encapsulation layer 150 directly contacts a portion of the semiconductor die 120 and a portion of the die stack 130.

[0182] The encapsulation layer 150 is made of a molding compound material. The molding compound may include a polymer material, such as an epoxy resin in which a filler is dispersed. In some embodiments, a liquid molding material is applied to the semiconductor die 120 (die stack 130). The liquid molding material may flow into the space between the semiconductor die 120 and the die stack 130. A thermal process is then used to cure the liquid molding material and transform it into the encapsulation layer 150.

[0183] Afterwards, if Figure 2K As shown, according to an embodiment of the present disclosure, a frame tape 160 is formed over the encapsulation layer 150. Thereafter, the carrier substrate 102 is removed.

[0184] The frame tape 160 is used as a temporary substrate. The substrate of the frame tape 160 provides mechanical and structural assistance during subsequent process steps, as described in detail later. In some embodiments, the semiconductor die 120 and the die stack 130 are bonded to the frame tape 160. For example, the encapsulation layer 150 is bonded to the frame tape 160 through an adhesive layer (not shown). The adhesive layer is used as a temporary adhesive layer.

[0185] Next, a portion of the redistribution structure 110 is removed. As a result, the conductive layer 108 of the redistribution structure 110 is exposed. Thereafter, a plurality of conductive connectors 164 are formed on the exposed conductive layer 108 of the redistribution structure 110. The conductive connectors 164 are electrically connected to the conductive layer 108 of the redistribution structure 110.

[0186] It should be noted that the overlapping conductive line 108c of the redistribution structure 110 is in direct contact with the conductive connector 164. In some embodiments, there is no via between the overlapping conductive line 108c and the conductive connector 164.

[0187] In some embodiments, the conductive connector 164 is referred to as a controlled collapse chip connection (C4) bump. In some other embodiments, the conductive connector 164 is a micro bump, a bump formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, a ball grid array (BGA) bump, etc.

[0188] It should be noted that the conductive connector 126 is formed on the top surface of the redistribution structure 110, and the conductive connector 164 is formed on the bottom surface of the redistribution structure 110. There is a first gap between two adjacent conductive connectors 126, and there is a second gap between two adjacent conductive connectors 164. The second gap is larger than the first gap. Therefore, the redistribution structure 110 implements a fan-out connection. The term "fan-out" means that the input / output (I / O) pads on the die can be redistributed to a larger area than the die itself, and thus the number of input / output pads packaged on the die surface can be increased.

[0189] Afterwards, if Figure 2L As shown, according to an embodiment of the present disclosure, an adhesive layer 170 is formed on the encapsulation layer 150 .

[0190] Adhesive layer 170 is formed over semiconductor die 120 and die stack 130. Adhesive layer 170 is made of a polymer having good thermal conductivity. In some embodiments, adhesive layer 170 includes a thermal interface material (TIM).

[0191] Next, a lid structure 172 is formed on the adhesive layer 170 to form a package unit 174. Therefore, the heat generated by the semiconductor die 120 and the die stack 130 can be dissipated to the lid structure 172 and then dissipated to the external environment. The lid structure 172 is made of a conductive material (e.g., metal) or a non-conductive material (e.g., silicon, glass, or ceramic).

[0192] Afterwards, if Figure 2M As shown, according to an embodiment of the present disclosure, the packaging unit 174 is bonded to the packaging substrate 180 through the conductive connector 164. In addition, the input / output port 178 is bonded to the packaging substrate 180 through the conductive connector 164. In some embodiments, the packaging substrate 180 is a printed circuit board (PCB), a ceramic substrate, or another suitable packaging substrate.

[0193] The redistribution structure 110 is used as a fan-out electrical connection to connect the signals of the semiconductor die 120 and the die stack 130 to the package substrate 180. The semiconductor die 120 and the die stack 130 are electrically connected to the input / output port 178 through the conductive layer and the via in the package substrate 180.

[0194] It should be noted that no through substrate vias (TSVs) are formed in the carrier substrate 102. TSVs may cause unnecessary insertion loss. "Insertion loss" is the loss of signal power caused by inserting a device in a transmission line. The present disclosure provides a method of forming a package structure 100a without using any interposer substrate (with TSVs) to prevent insertion loss.

[0195] Furthermore, if an interposer substrate made of silicon is used in the package structure, the coefficient of thermal expansion (CTE) of silicon does not match the CTE of the die stack 130. The redistribution structure 110 including the dielectric layer 104 and the conductive layer 108 has a CTE close to that of the die stack 130. By using the redistribution structure 110 instead of the interposer substrate, warpage caused by the mismatch in CTE between the die stack 130 and the interposer substrate is reduced.

[0196] In addition, since the plurality of die stacks 130 are integrated adjacent to the semiconductor die 120, the package structure 100a can be applied to high computing power devices. More plurality of die stacks 130 are used, and a higher capacity memory can be obtained. In some embodiments, when the die stack 130 is a high bandwidth memory (HBM), the memory bandwidth can be greater than 2TB. Therefore, the package structure can be applied to artificial intelligence (AI) applications.

[0197] Figure 2M' FIG. 1 shows a cross-sectional view of a package structure 100 b according to an embodiment of the present disclosure. The package structure 100 b is similar to FIG. 1 in that the semiconductor die 120 and the die stack 130 have different heights. Figure 2M The package structure 100a shown is similar or identical to the package structure 100b. The process and materials used to form the package structure 100b may be similar or identical to the process and materials used to form the package structure 100a, and will not be described again.

[0198] The semiconductor die 120 has a first height H1 along the vertical direction, and the die stack 130 has a second height H2 along the vertical direction. The second height H2 is greater than the first height H1. In some embodiments, the first height H1 of the semiconductor die 120 is in the range of about 750 μm to about 850 μm. In some embodiments, the second height H2 of the die stack 130 is in the range of about 900 μm to about 1000 μm. In some embodiments, the height difference (ΔH=H2-H1) between the second height H2 and the first height H1 is in the range of about 50 μm to about 150 μm. When the height difference is within the above range, the package structure 100b has good heat dissipation efficiency.

[0199] In addition, since the two die stacks 130 are protected by the encapsulation layer 150, the top surface of the die stacks 130 is not exposed by a planarization process (e.g., a chemical-mechanical planarization (CMP) process). During the planarization process, the two die stacks 130 are prevented from being damaged. Therefore, the quality and reliability of the package structure 100b are improved.

[0200] Figure 4A A top view of a first photomask 10 and a second photomask 20 according to an embodiment of the present disclosure is shown.

[0201] like Figure 4A As shown, the first light mask 10 has a length L x and width W x The second light mask 20 has a length L y and width W y The first mask 10 has a maximum area of ​​52 mm×34 mm, which is the maximum size of a reticle. The second mask 20 has a maximum area of ​​52 mm×34 mm, which is the maximum size of a reticle. In some embodiments, the length L of the first mask 10 is x In the range of about 1 mm to 52 mm, and the length L of the second light mask 20 is y In some other embodiments, the width W of the first mask 10 is in the range of 1 mm to 52 mm. x In the range of about 1 mm to about 34 mm, the width W of the second mask 20 is y In the range of about 1 mm to about 34 mm.

[0202] The first mark 16 is formed in the first mask 10, and the second mark 26 is formed in the second mask 20. The first mark 16 and the second mark 26 are used as monitoring patterns to ensure the alignment accuracy between the first mask 10 and the second mask 20. In some embodiments, the first mark 16 has a rectangular solid pattern. In some embodiments, the second mark 26 has a rectangular frame pattern.

[0203] In the first mask 10, the first cutting line 10a is located in the outer area of ​​the first mask 10, but not in the third area (overlapping area) 13. In addition, the second cutting line 20a is located in the outer area of ​​the second mask 20, but not in the third area 13. It should be noted that the first cutting line 10a and the second cutting line 20a are parts of the first mask 10 and the second mask 20, respectively. The first cutting line 10a and the second cutting line 20a are configured to define the position of the cutting line in the dielectric layer 104. In some embodiments, an electrical monitoring pattern and an overlapping alignment pattern are formed in the first cutting line 10a and the second cutting line 20a. In some embodiments, the width of the first cutting line 10a is in the range of about 50μm to about 220μm. In some embodiments, the width of the second cutting line 20a is in the range of about 50μm to about 220μm.

[0204] Figure 4B A top view showing the overlap between the first photomask 10 and the second photomask 20 according to an embodiment of the present disclosure is shown.

[0205] like Figure 4B As shown, the first mark 16 overlaps with the second mark 26 to display a specific pattern. When the first mask 10 and the second mask 20 are aligned with each other, the first mark 16 is surrounded by the second mark 26, and the rectangular solid pattern of the first mark 16 does not contact the frame shape of the second mark 26. If the first mask 10 and the second mask 20 are not aligned, the first mark 16 may contact the shape of the second mark 26.

[0206] As described above, the first mask 10 is disposed over the first region 11 and the third region 13 of the carrier substrate 102. The second mask 20 is disposed over the second region 12 and the third region 13. The overlapped portion between the first mask 10 and the second mask 20 has an overlapped length L. o . Exposure length L e The length L of the first mask 10 is defined as x and the length L of the second light mask 20 y The sum of the overlap length L o (L e =L x +L y -L o In some embodiments, the third region 13 (the overlapping portion between the first mask 10 and the second mask 20) ​​is approximately located within the exposure length L. e In some embodiments, the overlap length L o In the range of about 80 μm to about 150 μm. In addition, the first cutting line 10 a and the second cutting line 20 a are not formed in the third region 13 (or the overlapping region).

[0207] Figure 4C A top view showing the overlap between the first photomask 10 and the second photomask 20 according to an embodiment of the present disclosure is shown. Figure 4C and Figure 4B The difference between Figure 4C The third region 13 is not in the middle of the entire overlapping region of the first photomask 10 and the second photomask 20 .

[0208] like Figure 4C As shown, the size of the second mask 20 is larger than that of the first mask 10. The third area 13 is closer to the left and is not within the exposure length L e in the middle.

[0209] Figure 4D A top view of a monitoring pattern in a redistribution structure 110 of a package structure 100 a according to an embodiment of the present disclosure is shown.

[0210] like Figure 4D As shown, the first mark 16 and the second mark 26 are transferred to the first monitoring conductive line 109 and the second monitoring conductive line 209 in the redistribution structure 110, respectively. The first monitoring conductive line 109 and the second monitoring conductive line 209 are configured to identify whether the first photomask 10 is aligned with the second photomask 20. When the first photomask 10 is aligned with the second photomask 20, the first monitoring conductive line 109 does not contact the second monitoring conductive line 209. In some other embodiments, if the first photomask 10 is not aligned with the second photomask 20, the first monitoring conductive line 109 contacts the second monitoring conductive line 209.

[0211] Figure 5A FIG. 1 shows a top view of a package structure 100c according to an embodiment of the present disclosure. Figure 1 The package structure 100a shown is similar or identical, except that the size of the package structure 100c is larger than the size of the package structure 100a. The process and materials used to form the package structure 100c may be similar or identical to the process and materials used to form the package structure 100a, and this description will not be repeated. Figure 5A Cross-sectional view taken along line segment BB'.

[0212] like Figure 5A As shown, the package unit 174 is formed over the package substrate 180, and the ring 182 surrounds the package unit 174. In some embodiments, the package unit 174 includes two semiconductor dies 120 and eight die stacks 130 surrounding the semiconductor dies 120.

[0213] Figure 5B An overlapping top view of a first photomask 10 , a second photomask 20 , a third photomask 30 , and a fourth photomask 40 according to an embodiment of the present disclosure is shown.

[0214] like Figure 5B As shown, a first mask 10, a second mask 20, a third mask 30, and a fourth mask 40 are used to form conductive lines in a redistribution structure 110. A portion of the first mask 10 overlaps a portion of the second mask 20 to form a first overlapping portion. A portion of the third mask 30 overlaps a portion of the fourth mask 40 to form a second overlapping portion. The first overlapping portion is in the third region 13, and the second overlapping portion is in the sixth region 23.

[0215] Figure 5C A top view of the conductive layer 108 of the package structure 100c according to an embodiment of the present disclosure is shown. Since the size of the package structure 100c is larger than that of the package structure 100a, four masks may be used to form the redistribution structure 110 under the two semiconductor dies 120 and the eight die stacks 130.

[0216] like Figure 5C As shown, due to the use of the first mask 10, the second mask 20, the third mask 30 and the fourth mask 40 to form the redistribution structure 110, two overlapping regions are located in the dielectric layer 104. The first overlapping region is called the third region 13, and the second overlapping region is called the sixth region 23.

[0217] The redistribution structure 110 includes a plurality of conductive layers 108 in a plurality of dielectric layers 104. One of the conductive layers 108 includes a first conductive line 108a in a first region 11, a second conductive line 108b in a second region 12, and an overlapping conductive line (first overlapping conductive line) 108c in a third region 13. The first conductive line 108a is parallel to the second conductive line 108b. In addition, the package structure 100c also includes a fourth conductive line 108d in a fourth region 21, a fifth conductive line 108e in a fifth region 22, and a second overlapping conductive line 108f in a sixth region 23. The overlapping conductive line 108c extends along a first direction, and the second overlapping conductive line 108f extends along a second direction. The first direction is perpendicular to the second direction. In some embodiments, the overlapping conductive line 108c is directly below the semiconductor die 120. In some embodiments, the second overlapping conductive line 108f is directly below the channel (aisle) region between the semiconductor die 120 and the die stack 130.

[0218] Similar to the overlapped conductive line 108c, the width of the second overlapped conductive line 108f is greater than the width of the fourth conductive line 108d or the width of the fifth conductive line 108e. In addition, the middle region D where the third region 13 and the sixth region 23 intersect is exposed four times.

[0219] Figure 5DA top view of the conductive layer 108 of the package structure 100c according to an embodiment of the present disclosure is shown. Since the redistribution structure 110 is formed using the first mask 10, the second mask 20, the third mask 30, and the fourth mask 40, two overlapping regions are located in the dielectric layer 104. The first overlapping region is referred to as the third region 13, and the second overlapping region is referred to as the sixth region 23.

[0220] like Figure 5D As shown, overlapping conductive line 108c is formed in third region 13, and second overlapping conductive line 108f is formed in sixth region 23. In addition, overlapping conductive line 108c extends along a first direction, and second overlapping conductive line 108f extends along a second direction. In some embodiments, overlapping conductive line 108c (first overlapping conductive line) is directly below die stack 130. In some embodiments, second overlapping conductive line 108f is directly below semiconductor die 120 and die stack 130.

[0221] Fig. 6A A top view of a package structure 100d according to an embodiment of the present disclosure is shown. Figure 6B The embodiment of the present disclosure is shown along Fig. 6A Two fan-out packaging units are formed and surrounded by a ring 182.

[0222] Package structure 100d and Figure 5A The package structure 100c is similar or identical except that two package units 174 are formed on the package substrate 180. The process and materials used to form the package structure 100d may be similar or identical to the process and materials used to form the package structure 100c, and will not be described again.

[0223] like Fig. 6A and Figure 6B As shown, two packaging units (fan-out packaging units) 174 are formed on the packaging substrate 180. The first packaging unit 174a includes a semiconductor die 120 and four die stacks 130 (shown in FIG. 1 ) above the first redistribution structure 110a. Figure 6B The second packaging unit 174b includes a semiconductor die 120 and four die stacks 130 (shown in FIG. 1 ) above the second redistribution structure 110b. Figure 6B The third gap G3 is defined as the distance between the first package unit 174a and the second package unit 174b. In some embodiments, the third gap G3 is in the range of about 0.7 mm to about 2 mm.

[0224] Figure 6C A top view of the conductive layer 108 of the package structure 100 d according to an embodiment of the present disclosure is shown.

[0225] like Figure 6C As shown, the first packaging unit 174a (shown in Figure 6B The first redistribution structure 110a of the first package unit 174a is formed by two photomasks, and thus the third region 13 is formed in the first package unit 174a. The overlapping conductive line 108c is in the third region 13 in the first package unit 174a. Similarly, the second redistribution structure 110b of the second package unit 174b is formed by two photomasks, and thus the third region 13 is formed in the second package unit 174b. The overlapping conductive line 108c is in the third region 13 in the second package unit 174b.

[0226] Fig.6D A top view of the conductive layer 108 of the package structure 100 d according to an embodiment of the present disclosure is shown.

[0227] like Fig.6D As shown, the first redistribution structure 110a of the first encapsulation unit 174a is formed by four masks, and thus the third region 13 (first overlapping region) and the sixth region 23 (second overlapping region) are formed in the first encapsulation unit 174a. In addition, the third region 13 and the sixth region 23 are also formed in the second encapsulation unit 174b.

[0228] Fig. 7A A top view of a package structure 100 e according to an embodiment of the present disclosure is shown. Figure 7B The embodiment of the present disclosure is shown along Fig. 7A Four fan-out packaging units are formed in the ring 182.

[0229] like Fig. 7A As shown in FIG. 7B, a first package unit 174a, a second package unit 174b, a third package unit 174c, and a fourth package unit 174d are formed on a package substrate 180. The first package unit 174a, the second package unit 174b, the third package unit 174c, and the fourth package unit are insulated from each other. The first package unit 174a includes a semiconductor die 120 and two die stacks 130 above the first redistribution structure 110a. The second package unit 174b includes a semiconductor die 120 and two die stacks 130 on the second redistribution structure 110b.

[0230] FIG. 7C to FIG. 7E A top view of the conductive layer 108 of the package structure 100 e according to an embodiment of the present disclosure is shown.

[0231] like Figure 7C As shown, the first redistribution structure 110a of the first packaging unit 174a (shown in Figure 7BThe third region 13 is formed in the first packaging unit 174a. In addition, each of the second packaging unit 174b, the third packaging unit 174c, and the fourth packaging unit 174d has the third region 13.

[0232] As shown in FIG. 7D , each of the first package unit 174 a , the second package unit 174 b , the third package unit 174 c , and the fourth package unit 174 d has a third region 13 .

[0233] like Fig. 7E As shown, each of the first encapsulation unit 174 a , the second encapsulation unit 174 b , the third encapsulation unit 174 c , and the fourth encapsulation unit 174 d has a third region 13 and a sixth region 23 .

[0234] Fig. 8A A top view of a package structure 100f according to an embodiment of the present disclosure is shown. Figure 8B The embodiment of the present disclosure is shown along Fig. 8A Eight fan-out packaging units are formed in the ring 182.

[0235] like Fig. 8A and Figure 8B As shown, eight package units 174 are formed on a package substrate 180 . The package units 174 are all insulated from each other. Each package unit 174 includes a semiconductor die 120 and a die stack 130 above a redistribution structure 110 .

[0236] like Fig. 6A , Fig. 7A as well as Fig. 8A As shown, a plurality of fan-out redistribution structures 110 are formed in the ring 182. In other words, a plurality of package units 174 are formed over the package substrate 180. Since each dimension of the fan-out redistribution structure 110 is larger than the maximum dimension of a reticle, two or more masks are used to form a larger fan-out redistribution structure 110.

[0237] In some embodiments, two masks (e.g., first mask 10 and second mask 20) ​​are used to form overlapping conductive lines 108c in the third region 13 (overlapping region). In some embodiments, four masks are used to form overlapping conductive lines 108c (first overlapping conductive lines) in the third region 13 (first overlapping region) and to form second overlapping conductive lines 108f in the sixth region 23 (second overlapping region) 23. In addition, the problem of signal misalignment between two conductive lines can be solved by using overlapping conductive lines with a larger width.

[0238] It should be noted that there is no through substrate via (TSV) in the carrier substrate 102, and the redistribution structure 110 is electrically connected to the package substrate 180 through the conductive connector 164 without using any interposer substrate. Therefore, insertion loss and warpage caused by the interposer substrate can be prevented to obtain a high reliability package structure.

[0239] An embodiment of a packaging structure and a method for forming the same is provided. The packaging structure includes a redistribution structure formed on a carrier substrate. The redistribution structure is formed by more than two masks to form overlapping conductive lines between a first conductive line and a second conductive line. The packaging structure also includes a semiconductor die and a die stack formed above the redistribution structure. The carrier substrate is then removed, and a conductive connector is formed under the redistribution structure. The overlapping conductive lines can prevent misalignment between the first conductive line and the second conductive line. In addition, there are no through-substrate vias (TSVs) in the carrier substrate, and therefore insertion loss and warpage problems can be prevented. Therefore, the quality, yield, and reliability of the packaging structure are improved.

[0240] In some embodiments, a method for forming a package structure is provided. The method includes forming a dielectric layer on a carrier substrate, and the carrier substrate includes a first region, a second region, and a third region, and the third region is between the first region and the second region. The method also includes forming a photoresist layer above the dielectric layer. The method also includes performing a first exposure process on the photoresist layer to form a first single exposure region, and performing a second exposure process on the photoresist layer to form a second single exposure region and a double exposure region. The width of the double exposure region is greater than the width of the first single exposure region. The method also includes developing the photoresist layer to form a patterned photoresist layer, and patterning the dielectric layer to form a groove by using the patterned photoresist layer as a mask. The method also includes forming a conductive layer in the groove in the dielectric layer, and the conductive layer includes a first conductive line in the first region, a second conductive line in the second region, and an overlapping conductive line in the third region, and the third width of the overlapping conductive line of the conductive layer is wider than the first width of the first conductive line of the conductive layer. The method also includes disposing a semiconductor die and a die stack over the conductive layer, wherein the semiconductor die has a different function than the die stack.

[0241] In some embodiments, the method for forming a packaging structure also includes removing a carrier substrate to expose a portion of a dielectric layer; removing a portion of the dielectric layer to expose a portion of a conductive layer; forming a connector under the conductive layer, wherein the connector directly contacts overlapping conductive lines of the conductive layer; and disposing a substrate under the connector.

[0242] In some embodiments, the die stack includes a plurality of memory dies, and the semiconductor die has a different function than each of the memory dies.

[0243] In some embodiments, the overlapping conductive lines overlap the semiconductor die or die stack.

[0244] In some embodiments, the first exposure process and the second exposure process are performed in the same chamber.

[0245] In some embodiments, the first conductive line is parallel to the second conductive line.

[0246] In some embodiments, the method for forming the structure also includes forming a primer layer between the semiconductor die and the die stack; forming a packaging layer above the primer layer, wherein the interface between the primer layer and the packaging layer is lower than the top surface of the semiconductor die; and forming a ring around the packaging layer.

[0247] In some embodiments, no through-holes are formed in the carrier substrate.

[0248] In some embodiments, the semiconductor die has a first height, the die stack has a second height, and the second height is greater than the first height.

[0249] In some embodiments, a method for forming a package structure is provided. The method includes forming a dielectric layer on a carrier substrate, and the carrier substrate includes a first region, a second region, and a third region, and the third region is between the first region and the second region. The method also includes forming a photoresist layer above the dielectric layer, and the photoresist layer includes a first portion in the first region, a second portion in the second region, and a third portion in the third region. The method includes setting a first mask on the first region and the third region, and performing a first exposure process on the first portion and the third portion of the photoresist layer. The method also includes setting a second mask on the second region and the third region, and performing a second exposure process on the second portion and the third portion of the photoresist layer, and the third portion of the photoresist layer is a first overlapping portion exposed twice. The method also includes developing the photoresist layer to form a patterned photoresist layer, and patterning the dielectric layer to form a groove. The method also includes forming a first redistribution structure in the groove in the dielectric layer. The first redistribution structure includes a first conductive line in the first region and an overlapping conductive line in the third region, and the third width of the overlapping conductive line is greater than the first width of the first conductive line. The method further includes forming a first packaging unit above the first redistribution structure, wherein the first packaging unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function from the first die stack. The method further includes forming a packaging layer above the first packaging unit, and removing the carrier substrate. The method further includes forming a packaging substrate below the first redistribution structure.

[0250] In some embodiments, the packaging structure forming method also includes performing a third exposure process on a fourth portion and a sixth portion of the photoresist layer; and before developing the photoresist layer to form a patterned photoresist layer, performing a fourth exposure process on a fifth portion and a sixth portion of the photoresist layer, wherein the sixth portion is a second overlapping portion that is exposed twice.

[0251] In some embodiments, the packaging structure forming method also includes forming a second redistribution structure above the packaging substrate, wherein the second redistribution structure is insulated from the first redistribution structure, the second redistribution structure includes a third conductive line, a fourth conductive line and a second overlapping conductive line, the second overlapping conductive line is between the third conductive line and the fourth conductive line, and the sixth width of the second overlapping conductive line is greater than the fourth width of the fourth conductive line.

[0252] In some embodiments, the packaging structure forming method also includes forming a plurality of first conductive connectors on a first side of a first redistribution structure, wherein a first gap is formed between two adjacent first conductive connectors; and forming a plurality of second conductive connectors on a second side of the first redistribution structure, wherein a second gap is formed between two adjacent second conductive connectors, and the second gap is larger than the first gap.

[0253] In some embodiments, the method for forming a package structure further includes removing a portion of the dielectric layer after removing the carrier substrate to expose a portion of the first redistribution structure; and forming a second conductive connector under the first redistribution structure.

[0254] In some embodiments, a packaging structure is provided. The packaging structure includes a first redistribution structure formed above a substrate, and the first redistribution structure includes a first conductive line, a second conductive line, and a first overlapping conductive line, the first overlapping conductive line being between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line is parallel to the first conductive line and has a second width, and the first overlapping conductive line has a third width, the third width being greater than the first width and the second width. The packaging structure includes a first packaging unit formed above the first redistribution structure, wherein the first packaging unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function from the first die stack.

[0255] In some embodiments, the first redistribution structure also includes a third conductive line, a fourth conductive line and a second overlapping conductive line, the second overlapping conductive line is between the third conductive line and the fourth conductive line, the first overlapping conductive line extends along the first square line, the second overlapping conductive line extends along the second direction, and the first direction is perpendicular to the second direction.

[0256] In some embodiments, the packaging structure also includes a second redistribution structure formed adjacent to the first redistribution structure, wherein the first redistribution structure is insulated from the second redistribution structure; and a second packaging unit formed above the second redistribution structure, wherein the second packaging unit includes a second semiconductor die and a second die stack, and the second semiconductor die has a different function from the second die stack.

[0257] In some embodiments, the packaging structure further includes a ring surrounding the first packaging unit and the second packaging unit.

[0258] In some embodiments, the first semiconductor die has a first height, the first die stack has a second height, and the second height is greater than the first height.

[0259] In some embodiments, the package structure further includes a conductive connector formed below the first redistribution structure, wherein the conductive connector directly contacts the first redistribution structure.

[0260] The foregoing text summarizes the features of many embodiments so that those skilled in the art can better understand the present disclosure from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention of the present disclosure. Various changes, substitutions or modifications may be made to the present disclosure without departing from the spirit and scope of the invention of the present disclosure.

Claims

1. A method for forming a packaging structure, comprising: forming a dielectric layer on a carrier substrate, wherein the carrier substrate comprises a first region, a second region and a third region, and the third region is between the first region and the second region; forming a photoresist layer above the dielectric layer; Performing a first exposure process on the photoresist layer to form a first single exposure area; Performing a second exposure process on the photoresist layer to form a second single exposure region and a double exposure region, wherein a width of the double exposure region is greater than a width of the first single exposure region; developing the photoresist layer to form a patterned photoresist layer; patterning the dielectric layer by using the patterned photoresist layer as a mask to form a trench; forming a conductive layer in the trench in the dielectric layer, wherein the conductive layer includes a first conductive line in the first region, a second conductive line in the second region, and an overlapping conductive line in the third region, and a third width of the overlapping conductive line of the conductive layer is wider than a first width of the first conductive line of the conductive layer; as well as A semiconductor die and a die stack are arranged above the conductive layer, wherein the semiconductor die has a function different from that of the die stack.

2. The method for forming a package structure according to claim 1, further comprising: removing the carrier substrate to expose a portion of the dielectric layer; removing the portion of the dielectric layer to expose a portion of the conductive layer; forming a connector below the conductive layer, wherein the connector directly contacts the overlapping conductive lines of the conductive layer; and A substrate is arranged below the connector. 3 . The method for forming a package structure as claimed in claim 1 , wherein the die stack comprises a plurality of memory dies, and the semiconductor die has a function different from that of each of the memory dies. 4 . The method for forming a package structure as claimed in claim 1 , wherein the overlapping conductive line overlaps the semiconductor die or the die stack. 5 . The method for forming a package structure as claimed in claim 1 , wherein the first exposure process and the second exposure process are performed in the same chamber. 6 . The method for forming a package structure as claimed in claim 1 , wherein the first conductive line is parallel to the second conductive line.

7. The method for forming a package structure according to claim 1, further comprising: forming a primer layer between the semiconductor die and the die stack; Forming a packaging layer above the primer layer, wherein an interface between the primer layer and the packaging layer is lower than a top surface of the semiconductor die; as well as A ring is formed around the encapsulation layer. 8 . The method for forming a package structure as claimed in claim 1 , wherein no through hole is formed in the carrier substrate. 9 . The method for forming a package structure as claimed in claim 1 , wherein the semiconductor die has a first height, the die stack has a second height, and the second height is greater than the first height.

10. A method for forming a packaging structure, comprising: forming a dielectric layer on a carrier substrate, wherein the carrier substrate comprises a first region, a second region and a third region, and the third region is between the first region and the second region; forming a photoresist layer above the dielectric layer, wherein the photoresist layer includes a first portion in the first region, a second portion in the second region, and a third portion in the third region; Disposing a first light mask on the first area and the third area; Performing a first exposure process on the first portion and the third portion of the photoresist layer; Disposing a second light mask on the second area and the third area; Performing a second exposure process on the second portion and the third portion of the photoresist layer, wherein the third portion of the photoresist layer is a first overlapping portion exposed twice; developing the photoresist layer to form a patterned photoresist layer; patterning the dielectric layer to form a trench; forming a first redistribution structure in the trench in the dielectric layer, wherein the first redistribution structure comprises a first conductive line in the first region and an overlapping conductive line in the third region, a third width of the overlapping conductive line being greater than a first width of the first conductive line; forming a first packaging unit above the first redistribution structure, wherein the first packaging unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function from the first die stack; forming a packaging layer above the first packaging unit; removing the carrier substrate; as well as A packaging substrate is formed below the first redistribution structure.

11. The method for forming a package structure according to claim 10, further comprising: performing a third exposure process on a fourth portion and a sixth portion of the photoresist layer; as well as Before developing the photoresist layer to form a patterned photoresist layer, a fourth exposure process is performed on a fifth portion and the sixth portion of the photoresist layer, wherein the sixth portion is a second overlapping portion exposed twice.

12. The method for forming a package structure according to claim 10, further comprising: A second redistribution structure is formed above the packaging substrate, wherein the second redistribution structure is insulated from the first redistribution structure, the second redistribution structure includes a third conductive line, a fourth conductive line and a second overlapping conductive line, the second overlapping conductive line is between the third conductive line and the fourth conductive line, and a sixth width of the second overlapping conductive line is greater than a fourth width of the fourth conductive line.

13. The method for forming a package structure according to claim 10, further comprising: forming a plurality of first conductive connectors on a first side of the first redistribution structure, wherein a first gap is formed between two adjacent first conductive connectors; as well as A plurality of second conductive connectors are formed on a second side of the first redistribution structure, wherein a second gap is formed between two adjacent second conductive connectors, and the second gap is larger than the first gap.

14. The method for forming a package structure according to claim 13, further comprising: After removing the carrier substrate, removing a portion of the dielectric layer to expose a portion of the first redistribution structure; as well as The second conductive connector is formed below the first redistribution structure.

15. A package structure provided by the package structure forming method according to claim 10, comprising: The first redistribution structure is formed above the carrier substrate, wherein the first redistribution structure includes the first conductive line, a second conductive line and the overlapping conductive line, the overlapping conductive line is between the first conductive line and the second conductive line, wherein the first conductive line has the first width, the second conductive line is parallel to the first conductive line and has a second width, and the overlapping conductive line has the third width, and the third width is greater than the first width and the second width.

16. The packaging structure as described in claim 15, wherein the overlapping conductive line is a first overlapping conductive line, and the first redistribution structure further includes a third conductive line, a fourth conductive line and a second overlapping conductive line, the second overlapping conductive line is between the third conductive line and the fourth conductive line, the first overlapping conductive line extends along a first direction, the second overlapping conductive line extends along a second direction, and the first direction is perpendicular to the second direction.

17. The package structure according to claim 15, further comprising: a second redistribution structure formed adjacent to the first redistribution structure, wherein the first redistribution structure is insulated from the second redistribution structure; as well as A second packaging unit is formed above the second redistribution structure, wherein the second packaging unit includes a second semiconductor die and a second die stack, and the second semiconductor die has a different function from the second die stack.

18. The package structure according to claim 17, further comprising: A ring surrounds the first packaging unit and the second packaging unit. 19 . The package structure as claimed in claim 15 , wherein the first semiconductor die has a first height, the first die stack has a second height, and the second height is greater than the first height.

20. The package structure according to claim 15, further comprising: A conductive connector is formed below the first redistribution structure, wherein the conductive connector directly contacts the first redistribution structure.

21. A method for forming a packaging structure, comprising: forming a dielectric layer on a carrier substrate, wherein the carrier substrate comprises a first region, a second region and a third region, and the third region is between the first region and the second region; forming a photoresist layer above the dielectric layer; Performing a first exposure process on the photoresist layer to expose a first portion of the photoresist layer and an overlapping portion of the photoresist layer; Performing a second exposure process on the photoresist layer to expose a second portion of the photoresist layer and the overlapping portion of the photoresist layer, wherein the overlapping portion is located between the first portion and the second portion; developing the photoresist layer to form a patterned photoresist layer; Patterning the dielectric layer to form a trench located above the first region, the second region and the third region; forming a conductive layer in the trench in the dielectric layer, wherein the conductive layer includes a first conductive line in the first region, an overlapping conductive line in the third region, and a third width of the overlapping conductive line of the conductive layer is wider than a first width of the first conductive line of the conductive layer; as well as A semiconductor die and a die stack are arranged above the conductive layer, wherein the semiconductor die has a function different from that of the die stack. 22 . The method for forming a package structure as claimed in claim 21 , wherein the semiconductor die overlaps the overlapping conductive line, and the die stack does not overlap the overlapping conductive line in a normal direction of the carrier substrate. 23 . The method for forming a package structure as claimed in claim 21 , further comprising forming a ring surrounding the semiconductor die and the die stack. 24 . The method for forming a package structure as claimed in claim 21 , wherein the semiconductor die has a first height, the die stack has a second height, and the second height is greater than the first height. 25 . The method for forming a package structure as claimed in claim 21 , further comprising forming a conductive connector between the dielectric layer and the semiconductor die and between the dielectric layer and the die stack.

26. The method for forming a package structure according to claim 21, further comprising: removing the carrier substrate; Connecting the conductive layer to a packaging substrate via a plurality of conductive connectors; as well as An input / output port is combined onto the package substrate, wherein the input / output port is electrically connected to the conductive layer through the conductive connector.

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