Electronic chip packaging

Abstract

The invention relates to a device comprising a support, a conductive layer covering the support, a semiconductor substrate located on the conductive layer and an insulating shell.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to electronic devices including an electronic chip housed in a package. Background Art

[0002] An electronic chip is typically defined by a semiconductor substrate having one or more interconnected components (such as transistors) positioned within and at the top surface thereof for forming the circuitry of the chip. In certain applications (such as electrostatic discharge protection), the chip includes avalanche diodes.

[0003] Typically, the chip is housed in a package. The package includes connection terminals, usually for welding or soldering to a printed circuit such as a PCB ("printed circuit board"). For devices that include an electronic chip compactly housed in a package, a CSP-type package ("chip scale package") is usually used, that is, the package occupies a small surface area, usually less than 1.2 times the chip substrate. Summary of the Invention

[0004] One or more embodiments are directed to a device including a support, a conductive layer covering the support, a semiconductor substrate or chip on the conductive layer, and an insulating housing.

[0005] According to one embodiment, the device includes electronic components within and on top of a substrate.

[0006] According to one embodiment, the conductive layer is a metal.

[0007] According to one embodiment, the substrate includes a doped region defining an electrode of the avalanche diode.

[0008] According to one embodiment, the housing defines a CSP type package.

[0009] One embodiment provides a method of forming the device defined above.

[0010] According to one embodiment, the method comprises the step of simultaneously forming a plurality of devices as defined above.

[0011] According to one embodiment, the substrates of the devices are part of the same semiconductor wafer.

[0012] According to one embodiment, the method includes the step of forming a conductive layer on a rear surface of a semiconductor wafer.

[0013] According to one embodiment, the method comprises the step of arranging a support plate on the rear surface side of the conductive layer.

[0014] According to one embodiment, the method comprises the step of forming a trench delimiting the substrate, preferably up to a level situated in the support plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings.

[0016] Figure 1 To show Figure 1 A and show Figure 1 B schematically illustrates an embodiment of a device including an electronic chip in a package in cross-sectional and top view;

[0017] Figure 2 It is schematically shown Figure 1 A cross-sectional view of an example of a device in operation;

[0018] Figure 3 Shows the simultaneous formation Figure 1 Steps 3A to 3D of the method for a plurality of devices; and

[0019] Figure 4 Shows the simultaneous formation Figure 1 Steps 4A to 4C of the method for a plurality of devices. DETAILED DESCRIPTION

[0020] In different drawings, the same elements are represented by the same reference numerals. Specifically, the common structural and / or functional elements of different embodiments can be designated by the same reference numerals and can have the same structure, size and material properties.

[0021] For the sake of clarity, only those steps and elements that are helpful for understanding the embodiment are shown and described in detail. In particular, electronic chip circuits are not shown, and the embodiment is compatible with current chip circuits.

[0022] Throughout this disclosure, the term "connected" is used to designate a direct electrical connection between circuit elements, while the term "coupled" is used to designate an electrical connection between circuit elements that may be direct or may be via one or more intermediate elements (such as resistors, capacitors, transistors, or buffers). Unless otherwise specified, when the term "coupled" is used, a connection may be implemented by a direct connection.

[0023] In the following description, except Figure 1 B. When referring to terms that define absolute positions (such as "upper", "lower", "left", "right", etc.) or relative positions (such as "above", "below", "upper", "lower", etc.) or terms that define directions (such as the terms "horizontal", "vertical", etc.), this refers to the orientation of the accompanying drawings.

[0024] The terms "about," "substantially," and "order of magnitude" are used herein to designate a tolerance of plus or minus 10%, preferably plus or minus 5%, of the stated value.

[0025] Figure 1 To show Figure 1 A and show Figure 1 B schematically shows an embodiment of a device comprising an electronic chip in a package. Figure 1 A and show Figure 1 B are side and top views taken along corresponding sections AA and BB, respectively.

[0026] Device 100 includes a stack 102 of a support 104, a conductive layer 106, and a substrate 108. Layer 106 is located between support 104 and substrate 108.

[0027] Support 104 is preferably a semiconductor, preferably made of silicon, but can be made of any conductive or electrically insulating material, preferably a material that can be thinned by conventional means (such as glass, sapphire, gallium nitride, or silicon carbide). Layer 106 is preferably a metal, for example made of copper or aluminum. Layer 106 covers the rear surface of substrate 108, preferably covering the entire surface. Substrate 108 is an electronic chip or semiconductor chip that has an active surface in which one or more electronic circuit components are integrated. Substrate 108 is made of a semiconductor material, preferably silicon.

[0028] Preferably, the support 104, the metal layer 106 and the substrate 108 are stacked so that their edges coincide. The edges of the support 104, the metal layer 106 and the substrate 108 define the sides 109 of the stack. The stack 102 preferably has the shape of a parallelepiped. The shell then covers the six surfaces of the parallelepiped.

[0029] Device 100 also includes an insulating housing 110 covering laminate 102. Specifically, housing 110 covers the front surface, rear surface, and side surfaces 109 of laminate 102 and is in adhesive contact with side surfaces 109. Preferably, housing 110 entirely covers rear surface and side surfaces 109. Preferably, housing 110 intersects the front surface side of housing 110 via connection terminals 112. Preferably, housing 110 entirely covers the front surface of laminate 102, excluding connection terminals 112. Thus, housing 110 defines an electronic chip package. Preferably, the package is of the CSP type.

[0030] The presence of the support 104 enables providing a thin substrate 108, for example having a thickness of about 150 micrometers (μm) or less, preferably about 100 μm or less, while being easy to handle with current means.

[0031] As described in the example cases shown below, due to the association of a thin substrate and a conductive layer on the back surface of the thin substrate, the operation of the device is improved compared to devices without a thin substrate and a metal layer on the back surface.

[0032] In the example shown, substrate 108 is, for example, P-type doped. Separate N-type doped regions 114 and P-type doped regions 116 are located on the front surface of substrate 108. The doping levels (N+, P+) of regions 114 and 116 are preferably greater than the doping level of substrate 108. Substrate 108 and region 114 may together form a PN junction of an avalanche diode.

[0033] Preferably, the stack 102 includes an insulating layer 118 overlying the substrate 108. In the embodiment shown, the layer 118 extends from the regions 114 and 116 to the terminal 112 through a conductive region 120 (eg, metal).

[0034] Figure 2 It shows Figure 1 A cross-sectional view illustrating an example of operation of device 100 is shown.

[0035] For example, connection terminal 112 is coupled to a terminal to which a reference potential (e.g., ground GND) is applied and to terminal 10 to be protected from electrostatic discharge. When electrostatic discharge causes the potential of terminal 10 to increase, the PN junction between doped region 114 and substrate 108 begins to avalanche. Current flows from region 114 to region 116, which discharges the discharge to ground.

[0036] Due to the fact that substrate 108 is thin and covers metal layer 106, current flows vertically between each of regions 114 and 112 and metal layer 106 (arrow 202). The current is conducted laterally from a location below region 114 to a location below region 112 through conductive layer 106 (arrow 204). This results in a uniform distribution of current out of region 114. Compared to the case where the substrate is not thin and does not have a metal layer on its rear surface, this distribution can drain a current with a higher intensity to ground. Indeed, for the case where the substrate is not thin or there is no metal layer, the current will flow laterally between regions 114 and 116 through the substrate. The current flows out of region 114 and is concentrated on the side of region 114 near region 116. This concentration will limit the maximum intensity of the current.

[0037] Figure 1 and Figure 2 The embodiment is compatible with most electronic chip circuits. Layer 112 may include interconnect tracks between circuit components (such as transistors) located within and on top of substrate 106. The circuits are connected to conductive areas 120 that are in contact with terminals 120.

[0038] Figure 3 and Figure 4 is shown to form simultaneously Figure 1 Simplified partial cross-sectional views of steps 3A to 3D and 4A to 4C of a method implementing a plurality of devices of the same type.

[0039] exist Figure 3In step A, a semiconductor wafer 308 is provided. Wafer 308 will be divided into individual substrates or chips. Each future substrate 108 corresponds to a portion of the wafer. Future substrates 108 are preferably separated, for example, by tape 302. As an example, future substrates 108 are arranged in an array.

[0040] Electronic chip circuitry is formed within and on top of future substrate 108. The front surface of wafer 308 has conductive regions 120 connected to the circuitry formed thereon. Regions 120 are preferably accessible from the front surface. As an example, regions 120 are located within an insulating layer (not shown) covering the front surface. The insulating layer includes possible interconnect tracks.

[0041] In order to give the wafer 308 the thickness of the future substrate 108 , the wafer 308 is thinned, for example, preferably after forming the circuits.

[0042] The back surface of the wafer 308 is then covered with a conductive layer 106, preferably a metal. The layer 106 preferably has a thickness in the range of 0.5 μm to 0.5 μm. The thickness is preferably selected based on the conductivity of the material of the layer 106.

[0043] In step 3B, a support plate 304 is placed below the rear surface of the metal layer 106. The future support 104 is a portion of the plate 304. The thickness of the plate 304 is preferably greater than the thickness of the future support 104. For example, the plate 304 is bonded to the metal layer 106 by an adhesive. Preferably, the adhesive is distributed over the entire surface of the plate 304.

[0044] In step 3C, a metal pad 312 is formed covering the conductive region 120. A trench 330 is then formed (such as by etching) that defines the substrate 108. The trench 330 extends from the front surface of the substrate 108 to a level within the support plate 304. The depth of the trench 330 is preferably greater than the height of the future stack 102. A portion 332 of the plate 304 remains below the trench.

[0045] In step 3D, the entire structure obtained in step 3C is covered with an insulator 310A that fills the trench 330. Then, all components located above the level of the metal pad 312 are removed, for example, by surface treatment (such as polishing). This leaves the connection terminal 112 corresponding to the remaining portion of the pad 312. Except for the location of the terminal 112, the insulator 310A covers the upper surface of the substrate 108. The terminal 112 is flush with the upper surface of the insulator 310A.

[0046] In step 4A, the rear surface of the plate is surface-treated, such as by polishing, at least until the area 332 located below the groove 330 before polishing is completely removed from the plate 304. The insulator 310A is then flush with the lower surface of the structure obtained after polishing. This results in a stack 102 mechanically connected to each other by bonding the insulator to their side surfaces.

[0047] In step 4B, an insulator 310B is formed to cover the rear surface of the structure obtained in step 4 A. The insulator 310B is preferably made of the same material (eg, resin) as the insulator 310A.

[0048] In step 4C, the structure obtained in step 4B is cut into individual devices 100. To this end, insulator 310A is removed from region 350 across the entire height of the structure, for example by cutting. Region 350 is located in strip 302 and has a width less than the width of groove 330, leaving a portion of insulator 310A covering the sides of stack 102. Each housing 110 includes an insulator portion 310A covering the front and side surfaces of the corresponding stack 102 and an insulator portion 310B covering the back surface of the stack.

[0049] Various embodiments and variations have been described. These various embodiments and variations can be combined, and those skilled in the art will appreciate other variations. Finally, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art based on the functional instructions given above.

[0050] The various embodiments described above can be combined to provide further embodiments. These and other modifications can be made to the embodiments in light of the detailed description above. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to encompass all possible embodiments and the full scope of equivalents required by the claims. Therefore, the claims are not limited by this disclosure.

Claims

1. An electronic device comprising: Supporting parts; a conductive layer covering the support member; a semiconductor chip located on the conductive layer, wherein the semiconductor chip has a thickness of approximately 150 microns or less; as well as Insulation housing, The support, the semiconductor chip and the conductive layer have the same size and shape as each other in two dimensions. 2 . The electronic device according to claim 1 , wherein the semiconductor chip comprises an active surface for integrating electronic components. The electronic device according to claim 1 , wherein the conductive layer is a metal. The electronic device of claim 1 , wherein the semiconductor chip comprises a doped region defining an electrode of an avalanche diode. The electronic device according to claim 1 , wherein the insulating housing defines a CSP type package. The electronic device according to claim 1 , wherein the thickness of the semiconductor chip is less than 100 micrometers. 7 . The electronic device according to claim 1 , wherein the support member, the semiconductor chip, and the conductive layer form a stack in a parallelepiped shape.

8. A method for forming an electronic device, comprising: forming a conductive layer on a rear surface of the semiconductor wafer; coupling a support member to the conductive layer; forming a plurality of trenches in the semiconductor wafer to separate the plurality of chips of the semiconductor wafer from each other, wherein the trenches extend from the front surface of the semiconductor wafer to the support member; as well as An insulating material is used to cover the front surface of the semiconductor wafer and fill the trenches, so that an insulating housing is formed around the plurality of chips, the conductive layer, and the support, wherein the rear surface of the support remains exposed from the insulating housing.

9. The method according to claim 8, comprising: A portion of the support member is removed at the surface remaining exposed from the insulating housing. 10 . The method of claim 8 , comprising thinning the semiconductor wafer at the rear surface before forming the conductive layer. The method of claim 10 , wherein the semiconductor wafer is thinned to have a thickness of approximately 150 microns or less.

12. The method of claim 8, wherein coupling the support to the conductive layer comprises: An adhesive material is used to couple the support to the conductive layer.

13. The method of claim 8, wherein forming the plurality of trenches comprises: The semiconductor wafer, the conductive layer, and the support are etched.

14. A semiconductor package comprising: Supporting parts; a semiconductor chip located on the support; a conductive layer located between the semiconductor chip and the support, wherein the support, the semiconductor chip, and the conductive layer have coplanar side surfaces; as well as Insulating material is located on the coplanar side surfaces. 15 . The semiconductor package according to claim 14 , wherein the semiconductor chip has a thickness of approximately 150 μm or less. 16 . The semiconductor package of claim 14 , wherein the semiconductor chip includes a doped region defining an electrode of an avalanche diode. The semiconductor package according to claim 14 , wherein the conductive layer is a metal material.

18. The semiconductor package according to claim 14, wherein the insulating material covers a bottom surface of the support member. 19 . The semiconductor package according to claim 18 , wherein the insulating material covers an active surface of the semiconductor chip except for a plurality of terminals of the semiconductor chip.

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