Storage device and operation method thereof

Abstract

A storage device including a first nonvolatile memory device and a second nonvolatile memory device and an operation method thereof are provided. The method includes: detecting a sudden power failure; suspending an operation being executed in the first nonvolatile memory device in response to the detected sudden power failure; writing suspension information about the suspended operation to the second nonvolatile memory device; and performing a block management operation on the first nonvolatile memory device based on the suspension information written to the second nonvolatile memory device at power-on after the sudden power failure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0097281 filed on August 21, 2018, and Korean Patent Application No. 10-2018-0156245 filed on December 6, 2018, both of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the inventive concept relate to a semiconductor memory, and more particularly, to a memory device and an operating method thereof. Background Art

[0004] Semiconductor memory devices are classified into volatile memory devices in which stored data disappears when power is turned off, such as static random access memory (SRAM) or dynamic random access memory (DRAM), or non-volatile memory devices in which stored data is retained even when power is turned off, such as flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM).

[0005] A high-capacity storage device based on flash memory is operated by external power. In this case, if a sudden power outage (SPO) occurs during the operation of the storage device, the storage device completes the operation (e.g., programming operation or erasing operation) being performed in the storage device by using a separate auxiliary power source (such as a super capacitor or a tantalum capacitor). However, since it takes a lot of time to complete the operation being performed by the storage device, a high-capacity auxiliary power source is required, thereby increasing the area and cost of the storage device. Summary of the invention

[0006] Embodiments of the inventive concept provide a storage device capable of coping with a sudden power outage using a reduced auxiliary power supply and an operating method thereof.

[0007] According to some exemplary embodiments, an operating method of a storage device including a first nonvolatile memory device and a second nonvolatile memory device includes: detecting a sudden power failure; suspending an operation being executed in the first nonvolatile memory device in response to the detected sudden power failure; writing suspension information about the suspended operation to the second nonvolatile memory device; and upon power-on after the sudden power failure, performing a block management operation on the first nonvolatile memory device based on the suspension information written to the second nonvolatile memory device.

[0008] According to some exemplary embodiments, a storage device includes: a first nonvolatile memory device that stores user data; a second nonvolatile memory device that stores operation information about the operation of the first nonvolatile memory device; and a storage controller that suspends an operation being executed in the first nonvolatile memory device when a sudden power failure occurs, writes a sudden power failure flag in the operation information corresponding to the suspended operation among the operation information stored in the second nonvolatile memory device, and, when power is turned on after the sudden power failure, performs a block management operation on the first nonvolatile memory device based on the sudden power failure flag written to the second nonvolatile memory device.

[0009] According to some exemplary embodiments, a storage device includes: a first nonvolatile memory device; a second nonvolatile memory device temporarily storing user data to be stored in the first nonvolatile memory device; and a storage controller that suspends operations performed in the first nonvolatile memory device when power is suddenly cut off, writes a sudden power-off flag for data that is not stored in the first nonvolatile memory device among the user data temporarily stored in the second nonvolatile memory device, and when power is turned on after the sudden power cut, performs migration of the data that is not stored in the first nonvolatile memory device from the second nonvolatile memory device to the first nonvolatile memory device based on the sudden power-off flag written to the second nonvolatile memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present inventive concept will become apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a memory system according to some exemplary embodiments of the inventive concept.

[0012] Figure 2 It shows Figure 1 Block diagram of the software layers of a storage system.

[0013] Figure 3 It shows Figure 1 A block diagram of a storage controller.

[0014] Figure 4 It shows Figure 1 A flowchart of the operation of a storage device.

[0015] Figure 5 It shows Figure 4 Flow chart of operation S160.

[0016] FIG. 6A to FIG. 6C It describes the Figure 4 and Figure 5A flowchart is an illustration of the operation of a storage device.

[0017] Fig. 7A and Figure 7B is a diagram describing an erase operation according to a manner in which a verification operation is performed before the erase operation.

[0018] Fig. 8A and Figure 8B is a timing diagram illustrating an operation of writing suspend information to the second nonvolatile memory device.

[0019] Fig. 9 , Fig. 10A and Fig. 10B are diagrams describing operations of a memory device according to some exemplary embodiments of the inventive concept.

[0020] Fig.11 is a block diagram illustrating a memory system according to some exemplary embodiments of the inventive concept.

[0021] Fig.12 is a block diagram illustrating a memory system according to some exemplary embodiments of the inventive concept.

[0022] Fig.13 It shows Fig.12 A flowchart of the operation of a storage device.

[0023] FIG. 14A to FIG. 14C It describes the Fig.13 An illustration of the operation of a flowchart.

[0024] Fig.15 is a block diagram illustrating a memory system according to some exemplary embodiments of the inventive concept.

[0025] Fig.16 is a block diagram illustrating a memory system according to some exemplary embodiments of the inventive concept.

[0026] Fig.17 is a block diagram illustrating a memory system according to some exemplary embodiments of the inventive concept. DETAILED DESCRIPTION

[0027] Hereinafter, some exemplary embodiments of the inventive concept may be described in detail and clearly so that those skilled in the art can easily implement the inventive concept.

[0028] Figure 1 is a block diagram illustrating a storage system according to some exemplary embodiments of the inventive concept. Figure 1, the storage system 10 may include a host 11 and a storage device 100. The storage system 10 may be a computing system such as a personal computer, a server, a workstation, a notebook, a digital camera and / or a smart phone. The storage device 100 may be used as a high-capacity storage medium of the storage system 10.

[0029] The host 11 may store data to the storage device 100 or may read data stored in the storage device 100. In some exemplary embodiments, the host 11 may provide power PWR to the storage device 100.

[0030] The memory device 100 may include a memory controller 110 , a first nonvolatile memory device 120 , a second nonvolatile memory device 130 , and / or a power management integrated circuit PMIC.

[0031] Under the control of the host 11 , the memory controller 110 may store data to the first nonvolatile memory device 120 or may read data stored in the first nonvolatile memory device 120 .

[0032] The first nonvolatile memory device 120 may operate under the control of the memory controller 110. The second nonvolatile memory device 130 may store various information necessary for the memory controller 110 to operate.

[0033] In some exemplary embodiments, the first nonvolatile memory device 120 may be a NAND flash memory device, and the second nonvolatile memory device 130 may be a magnetic random access memory (MRAM). However, the inventive concept is not limited thereto. For example, the first nonvolatile memory device 120 and the second nonvolatile memory device 130 may include various nonvolatile memory devices such as flash memory, MRAM, PRAM, RRAM, and FRAM. In some exemplary embodiments, the second nonvolatile memory device 130 may have a higher operating speed than the first nonvolatile memory device 120.

[0034] The power management integrated circuit PMIC may provide power required for the memory device 100 to operate based on the power PWR from the host 11. For example, the power management integrated circuit PMIC may supply power required for each of the memory controller 110, the first nonvolatile memory device 120, and the second nonvolatile memory device 130 to operate.

[0035] In some exemplary embodiments, the power PWR from the host 11 may be suddenly blocked or turned off. This is called "sudden power off (SPO)". The power management integrated circuit PMIC may detect such a sudden power off and may send a sudden power off signal (hereinafter referred to as "SPO signal") to the memory controller 110.

[0036] In response to the SPO signal, the memory controller 110 may suspend the operation of the first nonvolatile memory device 120 and may store information about the suspended operation as suspend information SPI to the second nonvolatile memory device 130. The suspend information SPI may include command information and address information about the suspended operation in the first nonvolatile memory device 120.

[0037] After a sudden power failure, when the storage device 100 is powered on (e.g., the power supply is restored), the storage controller 110 may perform various block management operations based on the suspend information SPI stored in the second nonvolatile memory device 130. The block management operations based on the suspend information SPI after power on will be described more fully below with reference to the accompanying drawings.

[0038] In some exemplary embodiments, the operation of writing the suspend information SPI to the second non-volatile memory device 130 may be performed using a separate auxiliary power supply (not shown) included in the memory device 100. For example, the memory device 100 may include a separate device (not shown) for providing auxiliary power, such as a super capacitor or a tantalum capacitor. In the event of a sudden power failure, the power management integrated circuit PMIC may use the separate device to provide auxiliary power to the memory controller 110, the first non-volatile memory device 120, and the second non-volatile memory device 130. The second non-volatile memory device 130 may use the auxiliary power to perform the write operation associated with the above-mentioned suspend information SPI.

[0039] In some exemplary embodiments, in the event of a sudden power failure, a conventional storage device uses auxiliary power to complete an operation (e.g., a read operation, a program operation, or an erase operation) being performed in the first nonvolatile memory device 120. In this case, since the operation speed of the first nonvolatile memory device 120 is slower than the operation speed of the second nonvolatile memory device 130, it takes a lot of time to complete the operation being performed. This may cause an increase in the auxiliary power supply capacity required in the event of a sudden power failure.

[0040] In contrast, in the event of a sudden power failure, the storage device 100 according to some exemplary embodiments of the inventive concept suspends the operation being performed in the first nonvolatile memory device 120, and writes operation information (e.g., suspension information) about the suspended operation to the second nonvolatile memory device 130. That is, since the write operation is performed only on the second nonvolatile memory device 130 having a relatively high operation speed, the storage device 100 according to some exemplary embodiments of the inventive concept can cope with the sudden power failure using a relatively small auxiliary power source compared to the related art.

[0041] In some exemplary embodiments, the sudden power failure is described as a situation where the power PWR provided from the host 11 is suddenly blocked, but the inventive concept is not limited thereto. For example, even if the power PWR provided from the host 11 is maintained evenly, the power provided to the storage controller 110, the first nonvolatile memory device 120, or the second nonvolatile memory device 130 may become unstable due to various internal problems of the storage device 100. In this case, the power management integrated circuit PMIC may determine that a sudden power failure situation has occurred with respect to a specific device, and may output an SPO signal.

[0042] In some exemplary embodiments, it is described that the power management integrated circuit PMIC detects a sudden power failure and outputs an SPO signal, but the inventive concept is not limited thereto. For example, each of the storage controller 110, the first nonvolatile memory device 120, and the second nonvolatile memory device 130 may include a power detector (not shown) or a voltage detector (not shown). The power detector included in each of the storage controller 110, the first nonvolatile memory device 120, and the second nonvolatile memory device 130 may be configured to detect a sudden power failure situation that occurs with respect to the relevant configuration. That is, the power detector included in the storage controller 110 may detect a sudden power failure with respect to the power supplied to the storage controller 110. Alternatively, the power detector included in the first nonvolatile memory device 120 may detect a sudden power failure with respect to the power supplied to the first nonvolatile memory device 120. Alternatively, the power detector included in the second nonvolatile memory device 130 may detect a sudden power failure with respect to the power supplied to the second nonvolatile memory device 130.

[0043] That is, the sudden power failure may indicate a sudden power failure associated with power supplied to the storage device 100, or may indicate a sudden power failure associated with each of the storage controller 110, the first nonvolatile memory device 120, and the second nonvolatile memory device 130. Hereinafter, it will be described that the sudden power failure is a sudden power failure associated with the storage device 100; however, as described above, the sudden power failure may indicate a sudden power failure associated with each component.

[0044] Figure 2 It shows Figure 1 A block diagram of the software layers of a storage system. Figure 1 and Figure 2 , the software layers of the storage system 10 may include an application 11a, a file system 11b and / or a flash translation layer FTL.

[0045] The application 11a may include various application programs driven on the storage system 10 or the host 11. The file system 11b may organize files or data used by the application 11a. For example, the file system 11b may manage the storage space of the storage device 100 using logical addresses, and may assign logical addresses to data stored in the storage device 100 or to be stored in the storage device 100 for management.

[0046] In some exemplary embodiments, the type of the file system 11b may be different depending on the operating system OS of the storage system 10 or the host 11. In some exemplary embodiments, the file system 11b may include FAT (File Allocation Table), FAT32, NTFS (NT File System), HFS (Hierarchical File System), JSF2 (Journaling File System 2), XFS, ODS-5 (On-Disk Structure-5), UDF, ZFS, UFS (Unix File System), ext2, ext3, ext4, ReiserFS, Reiser4, ISO 9660, GnomeVFS, BFS, WinFS, etc. In some exemplary embodiments, the application 11a and the file system 11b may be a software layer driven on the host 11.

[0047] The flash translation layer FTL may perform various maintenance operations between the host 11 and the first nonvolatile memory device 120, thereby efficiently using the first nonvolatile memory device 120. For example, the flash translation layer FTL may perform a conversion operation between a logical address and a physical address. The logical address is information managed by the file system 11b, and the physical address is information indicating a physical location of the first nonvolatile memory device 120 where data is to be stored. The flash translation layer FTL manages the above-mentioned address conversion operation through a mapping table (not shown).

[0048] In some exemplary embodiments, the flash translation layer FTL may perform block management operations based on the suspend information SPI (see Figure 1 For example, the flash translation layer FTL may update or remap the mapping table based on the pause information SPI, or may adjust the garbage collection (GC) priority of the storage block of the first nonvolatile memory device 120.

[0049] Figure 3 It shows Figure 1 A block diagram of the storage controller 110 is shown in FIG. Figure 1 and Figure 3 , the memory controller 110 may include a processor 111 , a static RAM (SRAM) 112 , an error correction code (ECC) engine 113 , a non-volatile memory manager 114 , a host interface 115 and / or a flash memory interface 116 .

[0050] The processor 111 may control the overall operation of the memory controller 110. The SRAM 112 may be used as a cache memory or a working memory of the memory controller 110. Figure 2 The described flash translation layer FTL may be provided in the form of software, and program codes, instructions, etc. associated with the flash translation layer FTL may be stored in the SRAM 112. The flash translation layer FTL stored in the SRAM 112 may be executed by the processor 111.

[0051] The ECC engine 113 may be configured to correct errors of various data exchanged through the memory controller 110. For example, the ECC engine 113 may generate an error correction code for data provided from the host 11. Alternatively, the ECC engine 113 may correct errors based on data provided from the first nonvolatile memory device 120 and the error correction code. In some exemplary embodiments, the ECC engine 113 may perform an error correction operation on data stored in the second nonvolatile memory device 130.

[0052] The nonvolatile memory manager 114 may be configured to control the second nonvolatile memory device 130. For example, the nonvolatile memory manager 114 may read data stored in the second nonvolatile memory device 130 or may write data to the second nonvolatile memory device 130.

[0053] The storage controller 110 may communicate with the host 11 through the host interface 115. The host interface 115 may include at least one of various interfaces, such as a double data rate (DDR) interface, a low power DDR (LPDDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, a peripheral component interconnect (PCI) interface, a PCI Express (PCI-e) interface, an Advanced Technology Attachment (ATA) interface, a serial ATA (SATA) interface, a parallel ATA (PATA) interface, a small computer mini interface (SCSI) interface, an enhanced small disk interface (ESDI), an integrated drive electronics (IDE) interface, a mobile industry processor interface (MIPI), a non-volatile memory express (NVM-e) interface, and a universal flash storage (UFS) interface.

[0054] The storage controller 110 may communicate with the first non-volatile memory device 120 through a flash interface 116. The flash interface 116 may include a NAND interface.

[0055] Figure 4 It shows Figure 1 A flowchart of the operation of the storage device. Figure 1 and Figure 4In operation S110, the storage device 100 may detect a sudden power failure. For example, the power management integrated circuit PMIC may detect a shutdown of the power PWR provided from the host 11. In response to detecting the sudden power failure, the power management integrated circuit PMIC may provide an SPO signal to the storage controller 110.

[0056] In some exemplary embodiments, as described above, the power management integrated circuit PMIC may be configured to detect sudden power failure associated with each component of the storage device 100, or each component of the storage device 100 may be configured to detect sudden power failure through a power detector included in each component.

[0057] In operation S120, the storage device 100 may suspend the operation of the first nonvolatile memory device 120. For example, at the time point when the sudden power failure is detected, the first nonvolatile memory device 120 may be performing an operation such as a programming operation, a reading operation, or an erasing operation. The storage controller 110 may suspend the operation (e.g., a programming operation, a reading operation, or an erasing operation) currently being performed in the first nonvolatile memory device 120 in response to the SPO signal. In some exemplary embodiments, the storage controller 110 may provide a separate suspend command for suspending the operation of the first nonvolatile memory device 120 to the first nonvolatile memory device 120.

[0058] In operation S130, the storage device 100 may write the pause information SPI to the second non-volatile memory device 130 based on the suspended operation. For example, the storage controller 110 may write the command corresponding to the suspended operation and the address corresponding to the suspended operation as the pause information SPI. That is, in the case of suspending the programming operation associated with the first storage block among the plurality of storage blocks of the first non-volatile memory device 120, the storage controller 110 may write the address of the first storage block and the programming command as the pause information SPI. Hereinafter, for ease of description, the command included in the pause information SPI is referred to as a "suspended command", and the address included in the pause information SPI is referred to as a "suspended address".

[0059] Thereafter, in operation S140 , the storage device 100 may be powered on.

[0060] After power-on, in operation S150, the memory device 100 may scan the suspend information SPI stored in the second nonvolatile memory device 130. For example, the memory controller 110 may read the suspend information SPI stored in the second nonvolatile memory device 130 in an initialization operation according to power-on.

[0061] In operation S160, the storage device 100 may perform block management operations based on the pause information SPI. For example, the storage controller 110 may perform block management, such as processing invalid blocks on storage blocks, data migration, or adjusting GC priority based on the pause command and pause address included in the pause information SPI.

[0062] In some exemplary embodiments, upon detecting a sudden power failure associated with the first non-volatile memory device 120, the following operations may be performed: Figure 4 In some exemplary embodiments, in a case where a sudden power-off with respect to the second nonvolatile memory device 130 is detected and a sudden power-off with respect to the first nonvolatile memory device 120 is not detected, a separate suspend operation may not be performed, and a general operation (e.g., a programming operation or a reading operation) of the first nonvolatile memory device 120 may continue to be performed.

[0063] Figure 5 It shows Figure 4 Flow chart of operation S160. Figure 1 , Figure 4 and Figure 5 , the storage device 100 may perform operation S160 after operation S150. Operation S160 may include operations S161 to S163.

[0064] In operation S161, the memory device 100 may determine a command type. For example, the memory controller 110 may determine whether the suspended command is a read command RD, a program command PGM, or an erase command ERS.

[0065] When the suspended command is a read command RD, the storage device 100 may not perform a separate block management operation. For example, as described above, the suspended command indicates a command corresponding to an operation suspended in the first nonvolatile memory device 120. In the case of suspending an operation corresponding to the read command RD (e.g., a read operation), the data stored in the first nonvolatile memory device 120 may not be changed. That is, in the case where the suspended command is a read command RD, the data stored in the first nonvolatile memory device 120 may not be changed. Therefore, even if the storage device 100 does not perform a separate block management operation, the data stored in the first nonvolatile memory device 120 may be maintained.

[0066] In the case where the suspended command is a program command PGM, in operation S162, the storage device 100 may remap the storage block corresponding to the suspended address. For example, the storage controller 110 may set the storage block corresponding to the suspended address as an invalid block, may migrate the data stored in the storage block set as the invalid block to any other storage block (e.g., a free storage block), and may update the mapping table.

[0067] Specifically, in the case of suspending the programming operation associated with the first storage block of the first non-volatile memory device 120, the data may not be normally stored in the first storage block. That is, since the reliability of the data to be stored in the first storage block cannot be ensured, the storage controller 110 can set the first storage block to an invalid block. However, in order to ensure the reliability of the data previously stored in the first storage block (for example, the data stored before the programming operation is suspended), the data stored in the first storage block set as the invalid block can be migrated to any other storage block (for example, a free storage block). In this case, the storage controller 110 can map the logical address of the data stored in the first storage block to the physical address of the free storage block.

[0068] As described above, by setting the first storage block (whose programming operation is suspended) as an invalid block, performing migration of the data stored in the first storage block to the free storage block and mapping the logical address of the migrated data to the physical address of the free storage block, the reliability of the data previously stored in the first storage block can be ensured. Hereinafter, for ease of description, the above operation is referred to as "remapping operation on the first storage block". That is, in the case where the suspended command is a programming command PGM, the storage controller 110 can perform a remapping operation on the storage block corresponding to the suspended address.

[0069] In the case where the suspended command is an erase command ERS, in operation S163, the storage device 100 may adjust the GC priority of the storage block corresponding to the suspended address. For example, in the case where the suspended command is an erase command ERS, the storage controller 110 may set the storage block corresponding to the suspended address to an invalid block, and may make the GC priority of the storage block higher. The storage controller 110 may perform garbage collection according to the GC priority. That is, the storage controller 110 may first select the storage block corresponding to the suspended address (e.g., the storage block whose erase operation is suspended) as the target storage block, and may perform an erase operation on the target storage block.

[0070] Since the threshold voltage of the memory cell of the memory block (whose erase operation is suspended) is lower than the threshold voltage of the memory cell of the general memory block (for example, the memory block in which the user data is stored), the memory block whose erase operation is suspended can be erased faster than the general memory block. That is, by first selecting the memory block whose erase operation is suspended, the erase operation can be performed quickly on the target memory block, thereby improving the overall speed of the garbage collection operation.

[0071] FIG. 6A to FIG. 6C It describes the Figure 4 and Figure 5 1 is a flowchart of the operation of the storage device. For ease of description, it is assumed that the first non-volatile memory device 120 includes a first storage block BLK1 to a sixth storage block BLK6, and the first storage block BLK1 to the sixth storage block BLK6 correspond to the first address ADDR1 to the sixth address ADDR6, respectively. In addition, it is assumed that the first non-volatile memory device 120 is performing a read operation, a program operation, and an erase operation on the first storage block BLK1, the second storage block BLK2, and the third storage block BLK3, respectively. However, the inventive concept is not limited thereto.

[0072] refer to Fig. 6A , a sudden power failure may occur at the memory device 100. The power management integrated circuit PMIC may detect the sudden power failure and may provide an SPO signal to the memory controller 110. The memory controller 110 may suspend operations (e.g., a read operation, a program operation, and an erase operation) being performed in the first nonvolatile memory device 120 in response to the SPO signal.

[0073] Thereafter, the memory controller 110 may write information about the suspended operation to the second nonvolatile memory device 130 as the suspend information SPI. The suspend information SPI may include a suspended command and a suspended address associated with the suspended operation.

[0074] For example, Fig. 6AAs shown, in the case of suspending the read operation performed at the first memory block BLK1, the memory controller 110 may write the first suspend command CMD1 indicating the read operation RD suspended at the first memory block BLK1 and the first suspend address ADDR1 corresponding to the first memory block BLK1 as suspend information SPI to the second nonvolatile memory device 130. Similarly, in the case of suspending the program operation and the erase operation performed at the second memory block BLK2 and the third memory block BLK3, the memory controller 110 may write the second suspend command CMD2 and the third suspend command CMD3 indicating the program operation PGM and the erase operation ERS suspended at the second memory block BLK2 and the third memory block BLK3 and the second suspend address ADDR2 and the third suspend address ADDR3 corresponding to the second memory block BLK2 and the third memory block BLK3 as suspend information SPI to the second nonvolatile memory device 130.

[0075] Then, if Figure 6B and Figure 6C As shown, the memory device 100 may be powered on. In this case, the memory controller 110 may perform a block management operation based on the suspend information SPI stored in the second nonvolatile memory device 130.

[0076] For example, Figure 6B As shown, the memory controller 110 may perform a remapping operation on a specific memory block based on the suspend information SPI stored in the second nonvolatile memory device 130. Specifically, the memory controller 110 may identify that the program operation PGM of the second memory block BLK2 corresponding to the second suspend address ADDR2 is suspended based on the suspend information SPI. In this case, the memory controller 110 may perform a remapping operation on the second memory block BLK2.

[0077] That is, as described above, the storage controller 110 can set the second storage block BLK2 to the invalid block INV, and can perform the migration of the data stored in the second storage block BLK2 to the fifth storage block BLK5. According to the above migration operation, the storage controller 110 can remap or update the mapping table in the following manner: the second logical address LA2 corresponding to the data stored in the second storage block BLK2 is mapped to the fifth address ADDR5 of the fifth storage block BLK5, and the second address ADDR2 of the second storage block BLK2 is marked to the invalid block INV.

[0078] That is, thereafter, in a case where the host 11 accesses data corresponding to the second logical address LA2, the storage controller 110 may access the data stored in the fifth storage block BLK5 based on the remapped mapping table.

[0079] like Figure 6C As shown, the storage controller 110 can adjust the GC priority of a specific memory block based on the suspension information SPI stored in the second nonvolatile memory device 130. For example, the storage controller 110 can recognize that the erase operation ERS of the third memory block BLK3 corresponding to the third suspension address ADDR3 is suspended based on the suspension information SPI stored in the second nonvolatile memory device 130. In this case, as described above, the storage controller 110 can make the GC priority of the third memory block BLK3 higher.

[0080] Specifically, Figure 6C As shown, the sixth storage block BLK6 may be a free storage block, and the second storage block BLK2 may be an invalid block. The storage controller 110 may determine the GC priority of the sixth storage block BLK6 as the first priority #1, and may determine the GC priority of the second storage block BLK2 as the second priority #2. In this state, when performing garbage collection, the storage controller 110 may select the sixth storage block BLK6 with a higher priority as the target storage block, and may perform an erase operation on the sixth storage block BLK6.

[0081] In the case where the erase operation of the third storage block BLK3 is suspended when the power is suddenly cut off, and the storage device 100 is then powered on, the storage controller 110 can recognize that the erase operation of the third storage block BLK3 is suspended based on the pause information SPI stored in the second non-volatile memory device 130. In this case, the storage controller 110 can determine the GC priority of the third storage block BLK3 as the first priority #1, and can adjust or update the GC priorities of the sixth storage block BLK6 and the second storage block BLK2 to the second priority #2 and the third priority #3. In this state, when performing garbage collection, the storage controller 110 can select the third storage block BLK3 with the highest priority as the target storage block, and can perform an erase operation on the target storage block.

[0082] In some exemplary embodiments, the GC priority of the storage block set as an invalid block can be further adjusted according to the P / E cycle of the storage block set as an invalid block. For example, the storage controller 110 can perform wear leveling on multiple storage blocks of the first non-volatile memory device 120. That is, the storage controller 110 can make the GC priority of the storage block with the first P / E cycle higher than the GC priority of the storage block with the second P / E cycle greater than the first P / E cycle, so when garbage collection, the storage block with the first P / E cycle can be first selected as the target storage block. In this case, if the storage block with the second P / E cycle is an erase-suspended storage block, the storage controller 110 can adjust the GC priority so that the storage block with the second P / E cycle is first selected as the target storage block. However, in the case where the difference between the second P / E cycle and the first P / E cycle is not less than the reference value (for example, the second P / E cycle is greater than the first P / E cycle by as much as the reference value, or greater), the storage controller 110 may adjust the GC priority so that the storage block with the first P / E cycle is first selected as the target storage block for wear leveling management of the storage blocks.

[0083] As described above, in the case of a sudden power failure, the storage device 100 may suspend the operation of the first nonvolatile memory device 120, and may write information about the suspended operation to the second nonvolatile memory device 130 as the suspend information SPI. Thereafter, when the storage device 100 is powered on, the storage device 100 may perform a remapping operation or a GC priority adjustment operation on the first nonvolatile memory device 120 based on the suspend information SPI stored in the second nonvolatile memory device 130.

[0084] Fig. 7A and Figure 7B is a diagram describing an erase operation according to a manner in which a verification operation is performed before the erase operation. Figure 1 , Fig. 7A and Figure 7B ,like Fig. 7A As shown, each memory cell in a normal memory block of a plurality of memory blocks included in the first nonvolatile memory device 120 may have an erase state "E" and any one of the 1st to 15th program states P1 to P15. When the first erase operation 1st ERS is performed on the normal memory block, the memory cells of the normal memory block may have an erase state "E". For example, Figure 7BAs shown in , the memory device 100 can perform an erase operation on a normal memory block by performing a first erase operation 1st ERS including a plurality of erase cycles EL1 to ELn. Each of the plurality of erase cycles EL1 to ELn may include: lowering a threshold voltage of a memory cell by applying an erase voltage to the memory cell; and verifying whether the memory block is normally erased by applying an erase verification voltage Vvfy_e.

[0085] On the contrary, memory cells of a memory block (eg, the third memory block BLK3 of FIG. 6 ) whose erase operation is suspended (referred to as an “erase suspended memory block” for convenience of description) may form Fig. 7A , the threshold voltage distribution shown. In this case, the upper limit value Vth2 of the threshold voltage distribution of the memory cells in the erase-suspended memory block may be lower than the upper limit value Vth1 of the threshold voltage distribution of the memory cells in the normal memory block. In this case, when the second erase operation 2nd ERS is performed on the erase-suspended memory block, the memory cells of the erase-suspended memory block may have an erased state "E". For example, the memory device 100 may perform the second erase operation 2nd ERS including the initial verification interval Int.VFY and a plurality of erase cycles EL1 to ELk, as shown in FIG. Figure 7B shown.

[0086] The initial verification interval Int.VFY can be used to detect the upper limit value (e.g., Vth2) of the threshold voltage distribution of the memory cell in the erase suspended memory block by applying multiple verification voltages to the erase suspended memory block. The memory device 100 can perform multiple erase cycles EL1 to ELk according to the result of the initial verification interval Int.VFY. In this case, based on the result of the initial verification interval Int.VFY, the time Ters2 for applying the erase voltage in each of the multiple erase cycles EL1 to ELk, the number of the multiple erase cycles EL1 to ELk, or the size of the initial erase voltage Vers2 can be determined. For example, when the size of the upper limit value Vth2 determined according to the initial verification interval Int.VFY increases, the time Ters2 for applying the erase voltage in each of the multiple erase cycles EL1 to ELk, the number of the multiple erase cycles EL1 to ELk, or the size of the initial erase voltage Vers2 can be increased.

[0087] In some exemplary embodiments, the time Ters2 for applying the erase voltage in each of the plurality of erase cycles EL1 to ELk of the second erase operation 2nd ERS, the number of the plurality of erase cycles EL1 to ELk, or the size of the initial erase voltage Vers2 may be shorter than the time Ters1 for applying the erase voltage in each of the plurality of erase cycles EL1 to ELn of the first erase operation 1st ERS, the number of the plurality of erase cycles EL1 to ELn, or the size of the initial erase voltage Vers1. That is, the time for performing the second erase operation 2nd ERS may be shorter than the time for performing the first erase operation 1st ERS.

[0088] As described above, the memory controller 110 may perform different erasing operations on the normal memory blocks and the erase-suspended memory blocks. For example, the memory controller 110 may perform the first erasing operation 1st ERS on the normal memory blocks, and may perform the second erasing operation 2nd ERS on the erase-suspended memory blocks. As described above, since the time for performing the second erasing operation 2nd ERS is shorter than the time for performing the first erasing operation 1st ERS, the erase-suspended memory blocks may be first selected as the target memory blocks so as to perform the second erasing operation 2nd ERS, and thus the time spent on performing garbage collection may be reduced.

[0089] Fig. 8A and Figure 8B is a timing diagram illustrating an operation of writing suspend information to the second nonvolatile memory device. Fig. 8A and Figure 8B The timing diagram shown in may be an exemplary timing diagram describing the operation of the second nonvolatile memory device, and the inventive concept is not limited thereto. For example, the second nonvolatile memory device 130 may be configured to communicate with the memory controller 110 based on any one of various interfaces.

[0090] refer to Figure 1 , Figure 3 , Fig. 8A and Figure 8B , the second non-volatile memory device 130 may operate in response to a signal received from the non-volatile memory manager 114. For example, Fig. 8A As shown, during an active interval (e.g., a logic low interval) of the chip select signal CS and the write enable signal WEN, the second nonvolatile memory device 130 may receive addresses AD1 to AD4 and data DT1 to DT4 in synchronization with the clock signal CLK from the nonvolatile memory manager 114 of the memory controller 110. The second nonvolatile memory device 130 may write the received data DT1 to DT4 into an area corresponding to the received addresses AD1 to AD4.

[0091] like Figure 8B As shown, in the event of a sudden power off SPO, the memory controller 110 may activate the SPO signal (e.g., may allow the SPO signal to transition to logic low), and may provide the specific address AD_pd and the suspend information SPI to the second nonvolatile memory device 130 after a specified time has passed. The second nonvolatile memory device 130 may write the suspend information SPI to an area corresponding to the received specific address AD_pd in response to the SPO signal.

[0092] In some exemplary embodiments, the second nonvolatile memory device 130 may perform an operation of writing the pause information SPI after a specified time (e.g., several cycles of the clock signal CLK) has passed since the time point when the SPO signal is activated. In some exemplary embodiments, the specific address AD_pd may be an address corresponding to an area in the storage area of ​​the second nonvolatile memory device 130 that is predetermined in order to write the pause information SPI. In some exemplary embodiments, in order to write the pause information SPI, the second nonvolatile memory device 130 may operate in a burst mode.

[0093] The above-described operation of the second nonvolatile memory device 130 is an example, and it is understandable that various changes or modifications may be made to the operation of the second nonvolatile memory device 130 without departing from the technical concept of the inventive concept.

[0094] Fig. 9 , Fig. 10A and Fig. 10B 2 is a diagram describing the operation of a storage device according to some exemplary embodiments of the inventive concept. Fig. 9 , Fig. 10A and Fig. 10B In operation S205, the storage device 200 may write and manage the operation information about the first non-volatile memory device 220 into the second non-volatile memory device 230. For example, Fig. 10A As shown, the storage device 200 may perform a read operation RD on the first storage block BLK1 of the first nonvolatile memory device 220, perform a program operation PGM on the second storage block BLK2, perform an erase operation ERS on the third storage block BLK3, and perform a program operation PGM on the fourth storage block BLK4. In this case, the storage device 200 may write and manage information of the operation being performed in the first nonvolatile memory device 220 into the second nonvolatile memory device 230 as operation information.

[0095] The operation information stored in the second nonvolatile memory device 230 may include information about commands and addresses associated with operations being performed in the first nonvolatile memory device 220. In some exemplary embodiments, the operation information stored in the second nonvolatile memory device 230 may be management information managed separately, or may be a command queue of the first nonvolatile memory device 220 managed by the storage controller 110.

[0096] After that, the storage device 200 may perform operations S210 and S220. The storage device 200 may perform operations S210 and S220, that is, detect a sudden power failure and suspend the operation of the first nonvolatile memory device 220. Operations S210 and S220 are similar to Figure 4 Operation S110 and operation S120 are described above, and thus additional description will be omitted to avoid redundancy.

[0097] In operation S230, the storage device 200 may write an SPO flag in the operation information corresponding to the suspended operation. Fig. 10B As shown, the memory controller 210 may suspend the operation being performed in the first nonvolatile memory device 220 in response to the SPO signal. In this case, the program operation PGM of the fourth memory block BLK4 may be completed at the time point when the SPO signal is received, and the read operation RD, the program operation PGM, and the erase operation ERS performed in the first memory block BLK1, the second memory block BLK2, and the third memory block BLK3 may be suspended.

[0098] The storage controller 210 may write an SPO flag in the operation information corresponding to the suspended operation. For example, in the case where the read operation RD, the programming operation PGM, and the erase operation ERS being performed in the first storage block BLK1, the second storage block BLK2, and the third storage block BLK3 are suspended, the storage controller 210 may write an SPO flag in the operation information corresponding to the first storage block BLK1 to the third storage block BLK3 (e.g., CMD1 / ADDR1, CMD2 / ADDR2, CMD3 / ADDR3) in the operation information stored in the second nonvolatile memory device 230. Since the programming operation PGM of the fourth storage block BLK4 is completed, the storage controller 210 may not write a separate SPO flag in the operation information CMD4 / ADD4 corresponding to the fourth storage block BLK4.

[0099] That is, the storage controller 210 can store operation information (e.g., commands and addresses) about the operation being performed in the first non-volatile memory device 220 to the second non-volatile memory device 230 for management, and when a sudden power failure occurs, an SPO flag can be written in the operation information corresponding to the operation suspended in the first non-volatile memory device 220.

[0100] Then, in operation S240, the storage device 200 may be powered on.

[0101] In operation S250, the storage device 200 may scan the SPO flag from the operation information stored in the second nonvolatile memory device 230. For example, the storage controller 210 may identify the operation suspended in the first nonvolatile memory device 220 at the time of sudden power off by scanning the SPO flag from the operation information stored in the second nonvolatile memory device 230.

[0102] Then, in operation S260, the storage device 200 may perform a block management operation based on the scanned SPO flag. For example, as described above, the storage controller 210 may identify an operation suspended in the first nonvolatile memory device 220 at the time of a sudden power failure by scanning the SPO flag from the operation information stored in the second nonvolatile memory device 230. The storage controller 210 may perform a block management operation based on the suspended operation, such as referring to Figures 1 to 7B The block management operation is described above, so it will not be repeated here.

[0103] As described above, the storage device 200 may store the operation information about the operation being performed in the first non-volatile memory device 220 in the second non-volatile memory device 230 for management. In the event of a sudden power failure, the storage device 200 may suspend the operation being performed in the first non-volatile memory device 220, and may write an SPO flag in the operation information corresponding to the suspended operation at the second non-volatile memory device. Therefore, when a sudden power failure occurs, once the storage device 200 writes the SPO flag to the second non-volatile memory device 230, and the operation of the first non-volatile memory device 220 is not completed, the storage device 200 may use an auxiliary power supply with a smaller capacity to cope with the sudden power failure. In addition, when power is turned on after the sudden power failure, the storage device 200 may perform a block management operation based on the operation information and the SPO flag stored in the second non-volatile memory device 230, thereby ensuring the reliability of the data stored in the first non-volatile memory device 220.

[0104] Fig.11is a block diagram illustrating a storage system according to some exemplary embodiments of the inventive concept. Fig.11 , the storage system 30 may include a host 31 and / or a storage device 300. The storage device 300 may include a storage controller 310, a first nonvolatile memory device 320, a second nonvolatile memory device 330, a power management integrated circuit PMIC and / or a temperature sensor 340. The host 31, the storage device 300, the storage controller 310, the first nonvolatile memory device 320, the second nonvolatile memory device 330 and the power management integrated circuit PMIC are described above, so in order to avoid repetition, additional description will be omitted.

[0105] The temperature sensor 340 may detect the temperature of the storage device 300, and may provide temperature information TEMP about the detected temperature to the storage controller 310. The storage controller 310 may be configured to control the second nonvolatile memory device 330 based on the temperature information TEMP. For example, the second nonvolatile memory device 330 may adjust the number of times the second nonvolatile memory device 230 is rewritten based on the temperature of the storage device 300. In some exemplary embodiments, when a sudden power failure occurs, the storage controller 310 may write the temperature information TEMP to the second nonvolatile memory device 330.

[0106] Fig.12 is a block diagram illustrating a storage system according to some exemplary embodiments of the inventive concept. Fig.12 , the storage system 40 may include a host 41 and / or a storage device 400. The storage device 400 may include a storage controller 410, a first nonvolatile memory device 420, a second nonvolatile memory device 430 and / or a power management integrated circuit PMIC. The host 41, the storage controller 400, the first nonvolatile memory device 420 and the power management integrated circuit PMIC are described above, so in order to avoid repetition, additional description will be omitted.

[0107] Fig.12 The second nonvolatile memory device 430 may be used as a data buffer of the storage device 400. For example, user data UD received from the host 41 may be stored in the second nonvolatile memory device 430, and the user data UD stored in the second nonvolatile memory device 430 may be selectively moved (or copied) to the first nonvolatile memory device 420. Alternatively, the second nonvolatile memory device 430 may be configured to store user data UD read from the first nonvolatile memory device 420 and provide the stored user data UD to the host 41.

[0108] In response to the SPO signal from the power management integrated circuit PMIC, the memory controller 410 may suspend the operation of the first nonvolatile memory device 420, and may write an SPO flag associated with the user data UD to be provided from the second nonvolatile memory device 430 to the first nonvolatile memory device 420. In some exemplary embodiments, the user data UD to be provided to the first nonvolatile memory device 420 may indicate user data that is not stored in the first nonvolatile memory device 420 or user data corresponding to a program operation suspended in the first nonvolatile memory device 420.

[0109] When the storage device 400 is powered on after a sudden power failure, the storage controller 410 may perform migration of user data UD from the second nonvolatile memory device 430 to the first nonvolatile memory device 420 based on the user data UD stored in the second nonvolatile memory device 430 and the SPO flag.

[0110] As described above, when a sudden power failure occurs, the storage device 400 may suspend the operation of the first nonvolatile memory device 420, and may write the SPO flag associated with the user data UD to be stored in the first nonvolatile memory device 420 to the second nonvolatile memory device 430. That is, when a sudden power failure occurs, once the storage device 400 writes the SPO flag to the second nonvolatile memory device 430 without completing the operation of the first nonvolatile memory device 420, the storage device 420 may use the auxiliary power supply with reduced capacity to cope with the sudden power failure situation.

[0111] Fig.13 It shows Fig.12 A flowchart of the operation of a storage device. FIG. 14A to FIG. 14C It describes the Fig.13 Reference is made to a flowchart of the operation of Fig.12 , Fig.13 as well as FIG. 14A to FIG. 14C , the storage device 400 may perform operations S405 and S410. Operations S405 and S410 are similar to Figure 4 Operation S110 and operation S120 are described above, and thus additional description will be omitted to avoid redundancy.

[0112] In operation S420, the storage device 400 may determine whether the operation suspended in the first nonvolatile memory device 420 is a program operation PGM. Fig.14AAs shown in , the second nonvolatile memory device 430 may store first address ADDR1, second address ADDR2, and third address ADDR3 corresponding to first user data UD1, second user data UD2, and third user data UD3, respectively. The memory controller 410 may read the first to third user data UD1 to UD3 from the second nonvolatile memory device 430, and may program the read first to third user data UD1 to UD3 to first to third memory blocks BLK1 to BLK3 corresponding to the first to third addresses ADDR1 to ADDR3, respectively. Fig.14A The embodiment of the memory device 400 shown in FIG. 4 shows a case in which the third user data UD3 has been completely programmed into the third memory block BLK3 , and the first and second user data UD1 and UD2 are being programmed into the first and second memory blocks BLK1 and BLK2 .

[0113] In some example embodiments, the ECC engine 413 of the memory controller 410 may correct errors of user data read from the second nonvolatile memory device 430 , and may program the error-corrected user data into the first nonvolatile memory device 420 .

[0114] exist Fig.14A In the illustrated embodiment of the memory device 400 , in the event of a sudden power failure, the memory controller 410 may determine whether the operation suspended in the first nonvolatile memory device 420 is a programming operation.

[0115] In the case where the suspended operation is a programming operation, in operation S425, the storage device 400 may determine whether an ECC operation is completely performed on the data to be programmed into the first nonvolatile memory device 420. For example, Fig.14A As shown, the memory controller 410 may read the first user data UD1 from the second nonvolatile memory device 430, may perform an ECC operation on the read first user data UD1, and may provide the error-corrected first user data UD1′ to the first nonvolatile memory device 420. The first nonvolatile memory device 420 may program the error-corrected first user data UD1′ into the first memory block BLK1. At this time, a sudden power failure may occur.

[0116] That is, after the ECC operation is completely performed on the first user data UD1, when a sudden power failure occurs during the period when the error-corrected first user data UD1′ is programmed into the first nonvolatile memory device 420 (in other words, when the result of operation S425 corresponds to "yes"), in operation S430, the storage device 400 can rewrite the programmed user data into the second nonvolatile memory device 430.

[0117] For example, Fig. 14B As shown, the storage device 400 may write the first user data UD1′ after error correction into the second nonvolatile memory device 430. In some exemplary embodiments, the storage controller 410 may rewrite the first user data UD1′ after error correction into an area storing the first user data UD1 of the second nonvolatile memory device 430, or rewrite into a separate area. That is, since the first user data UD1′ after error correction is rewritten into the second nonvolatile memory device 430, the reliability of the first user data UD1 may be improved.

[0118] When the result of operation S425 corresponds to "No", the storage device 400 may not perform a separate data write operation. Fig.14A and Fig. 14B As shown, at the time point when the sudden power failure occurs, the storage controller 410 may be in a state where the ECC operation is not completely performed on the second user data UD2 (for example, in a state where the second user data UD2 is being read from the second nonvolatile memory device 430). In this case, since the second user data UD2 is stored in the second nonvolatile memory device 430, a separate rewrite operation may not be performed.

[0119] Thereafter, in operation S435, the storage device 400 may write the SPO flag into the second nonvolatile memory device 430. For example, Fig. 14B As shown, the memory device 400 may write an SPO flag associated with user data UD1 and UD2 corresponding to a program operation suspended in the first nonvolatile memory device 420 .

[0120] In operation S440 , the storage device 400 may be powered on.

[0121] In operation S445, the storage device 400 may scan the SPO flag from the second nonvolatile memory device 430. For example, in an initialization operation according to power-on, the storage device 400 may read the SPO flag stored in the second nonvolatile memory device 430. The storage device 400 may recognize user data (e.g., UD1′ and UD2) that is not stored in the first nonvolatile memory device 420 based on the SPO flag read from the second nonvolatile memory device 430.

[0122] In operation S450, based on the scanned SPO flag, the storage device 400 may perform migration of user data from the second nonvolatile memory device 430 to the first nonvolatile memory device 420. For example, Fig. 14CAs shown, the second nonvolatile memory device 430 may include an SPO flag associated with the first user data UD1′ and the second user data UD2. The storage controller 410 may read the first user data UD1′ and the second user data UD2 in which the SPO flags are written, respectively, and may perform an error correction operation (performed by the ECC engine 413) on the first user data UD1′ and the second user data UD2. The error-corrected first user data UD1′ and the second user data UD2′ may be written to the fifth storage block BLK5 and the sixth storage block BLK6, respectively.

[0123] In some exemplary embodiments, the first user data UD1 and the second user data UD2 may be user data to be written into the first storage block BLK1 and the second storage block BLK2 before the sudden power failure; however, when the programming operation of the first storage block BLK1 and the second storage block BLK2 is suspended due to the sudden power failure, the first storage block BLK1 and the second storage block BLK2 may be processed as invalid. The invalid block processing operation is described above, so in order to avoid repetition, additional description will be omitted. In this way, the storage controller 410 may program the first user data UD1′ and the second user data UD2 into any other storage block (e.g., BLK5 and BLK6) instead of programming into the first storage block BLK1 and the second storage block BLK2 set as invalid blocks. In some exemplary embodiments, when the first user data UD1′ and the second user data UD2 are programmed into any other storage block (e.g., BLK5 and BLK6), the mapping information about the first user data UD1′ and the second user data UD2 may be updated. In some exemplary embodiments, the mapping information may be managed by the memory controller 410 or may be stored in the second nonvolatile memory device 430 together with the first user data UD1 ′ and the second user data UD2 .

[0124] As described above, in the case where the second nonvolatile memory device 430 is used as a data buffer of the storage device 400, when a sudden power failure occurs, the storage device 400 may suspend the operation of the first nonvolatile memory device, and may write an SPO flag associated with user data that is not stored in the first nonvolatile memory device 420 among the user data stored in the second nonvolatile memory device 430. Thereafter, in the case where the storage device 400 is powered on, the storage device 400 may scan the SPO flag of the second nonvolatile memory device 430, and may perform migration or copying of user data from the second nonvolatile memory device 430 to the first nonvolatile memory device 420.

[0125] Fig.15 is a block diagram illustrating a storage system according to some exemplary embodiments of the inventive concept. Fig.15, the storage system 50 may include a host 51 and / or a storage device 500. The storage device 500 may include a storage controller 510, a first non-volatile memory device 520, a second non-volatile memory device 530 and / or a power management integrated circuit PMIC. The host 51, the storage device 500, the storage controller 510, the first non-volatile memory device 520 and the power management integrated circuit PMIC are described above, so in order to avoid repetition, additional description will be omitted.

[0126] As in reference Figures 12 to 14C As described in the given Fig.15 The second nonvolatile memory device 530 may be used as a data buffer of the storage device 500. That is, the second nonvolatile memory device 530 may be configured to store user data UD to be programmed into the first nonvolatile memory device or user data UD read from the first nonvolatile memory device 520. Figures 1 to 11 As stated, Fig.15 The second nonvolatile memory device 530 may be configured to store the suspend information SPI or the operation information about the first nonvolatile memory device 520. That is, the second nonvolatile memory device 530 may be used as a data buffer and a management buffer of the storage device 500.

[0127] In this case, as referenced Figures 1 to 11 As described above, when power is suddenly cut off, the storage device 500 may suspend the operation being executed in the first nonvolatile memory device 520, and may write information about the suspended operation into the second nonvolatile memory device 530 as suspension information. Figures 12 to 14C As described above, the memory device 500 may write an SPO flag in user data corresponding to the suspended program operation.

[0128] Fig.16 is a block diagram illustrating a storage system according to some exemplary embodiments of the inventive concept. Fig.16 , the storage system 60 may include a host 61 and / or a storage device 600. The storage device 600 may include a storage controller 610, a first nonvolatile memory device 620, a second nonvolatile memory device 630, a power management integrated circuit PMIC and / or a DRAM buffer 640. The host 61, the storage device 600, the storage controller 610, the first nonvolatile memory device 620, the second nonvolatile memory device 630 and the power management integrated circuit PMIC are described above, so in order to avoid repetition, additional description will be omitted.

[0129] Fig.16The storage device 600 may include a DRAM buffer 640. The DRAM buffer 640 may be used as a data buffer of the storage device 600. That is, the DRAM buffer 640 may be configured to temporarily store user data received from the host 61 or user data read from the first nonvolatile memory device 620. Alternatively, the DRAM buffer 640 may be configured to store various meta information (e.g., a mapping table and an FTL) required for the storage device 600 to operate.

[0130] In some exemplary embodiments, in the event of a sudden power outage, based on the reference Figures 1 to 11 According to the described method, the memory controller 610 may suspend the operation being executed in the first non-volatile memory device 620, and may write the suspension information SPI about the suspended operation to the second non-volatile memory device 630. In this case, the memory controller 610 may write the user data or meta information stored in the DRAM buffer 640 to the second non-volatile memory device 630.

[0131] After a sudden power failure, when the storage device 600 is powered on, by referring to Figures 1 to 15 With the described method, the storage device 600 may perform block management operations based on information stored in the second non-volatile memory device 630 .

[0132] Fig.17 is a block diagram illustrating a storage system according to some exemplary embodiments of the inventive concept. Fig.17 , the storage system 1000 may include a host 1100 and a storage device 1200. The storage device 1200 may include a storage controller 1210, a plurality of nonvolatile memory devices NVM, a plurality of nonvolatile memory controllers 1221 to 122n, a plurality of nonvolatile RAMs 1231 to 123n, a power management integrated circuit PMIC, and / or a RAM buffer 1240.

[0133] The storage controller 1210 may be configured to control the overall operation of the storage device 1200 under the control of the host 1100. A plurality of nonvolatile memory controllers (hereinafter referred to as "NVM controllers") 1221 to 122n may be configured to control a plurality of nonvolatile storage devices NVM and a plurality of nonvolatile RAMs 1231 to 123n, respectively. In some exemplary embodiments, the storage controller 1210 may communicate with the plurality of NVM controllers 1221 and 122n through a plurality of channels.

[0134] In some exemplary embodiments, the NVM controllers 1221 to 122n may be based on a reference Figures 1 to 16The described operation method is to control a plurality of nonvolatile memory devices NVM and a plurality of nonvolatile RAMs 1231 to 123n. For example, when a sudden power failure occurs, the NVM controllers 1221 to 122n may suspend the operation of the plurality of nonvolatile memory devices NVM, and may write suspend information or SPO flags to the plurality of nonvolatile RAMs 1231 to 123n. At power-on, the NVM controllers 1221 to 122n may perform a block management operation or a data migration operation based on the suspend information or SPO flags from the plurality of nonvolatile RAMs 1231 to 123n.

[0135] The RAM buffer 1240 may be configured to store various information required for the memory device 1200 to operate. Alternatively, the RAM buffer 1240 may be used as a data buffer for the memory device 1200.

[0136] The power management integrated circuit PMIC may provide various voltages required for the memory device 1200 to operate based on power from the host 1100. The power management integrated circuit PMIC may detect a sudden power failure occurring at the memory device 1200.

[0137] According to the present invention, in the event of a sudden power failure, the storage device can suspend the operation being performed in the first non-volatile memory device, and can write information about the suspended operation to the second non-volatile memory device. In this case, since the power consumption when writing the information about the suspended operation to the second non-volatile memory device is less than the power consumption when completing the operation of the first non-volatile memory device, the storage device can use a reduced capacity auxiliary power supply to cope with the sudden power failure. Therefore, a storage device with reduced cost and / or reduced area and an operating method thereof are provided.

[0138] While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A method for operating a storage device, the storage device comprising a first non-volatile memory device, a second non-volatile memory device, a storage controller, and a power management circuit, the method comprising: detecting, by the power management circuit, a sudden power outage occurring at at least one of the first non-volatile memory device, the second non-volatile memory device, and the memory controller; In response to the detected sudden power failure, suspending, by the storage controller, operations being executed in the first non-volatile memory device; writing, by the storage controller, suspension information about the suspended operation into the second non-volatile memory device; and At power-on after the sudden power-off, a block management operation is performed by the storage controller on the first nonvolatile memory device based on the suspend information written to the second nonvolatile memory device. 2 . The method according to claim 1 , wherein the suspend information comprises a suspended command and a suspended address corresponding to the suspended operation.

3. The method according to claim 2, wherein the block management operation comprises a remapping operation and a garbage collection (GC) priority adjustment operation, wherein when the suspended command is a programming command, the remapping operation is performed on the storage block corresponding to the suspended address, and When the suspended command is an erase command, the GC priority adjustment operation is performed on the storage block corresponding to the suspended address.

4. The method according to claim 3, wherein the remapping operation comprises: The storage block corresponding to the suspended address is processed as an invalid block, data stored in the storage block is migrated to another storage block, and a logical address corresponding to the migrated data is mapped to a physical address of the another storage block.

5. The method according to claim 3, wherein the GC priority adjustment operation comprises increasing the GC priority of the storage block corresponding to the paused address, The method further comprises: Based on the GC priority, a garbage collection operation is performed on the first non-volatile memory device. The method of claim 5 , wherein the GC priority of the memory block is further adjusted based on program and erase cycles of the memory block.

7. The method according to claim 2, further comprising: performing an erase operation on the first non-volatile memory device, Wherein, when the storage block targeted by the erase operation corresponds to the suspended address, the storage block is erased in a manner of performing a verification operation before the erase operation, and Wherein, when the storage block targeted by the erasing operation does not correspond to the suspended address, the storage block is erased based on a normal erasing method.

8. The method of claim 1, wherein the sudden power loss is a sudden power loss associated with the first non-volatile memory device.

9. The method of claim 1, wherein the second nonvolatile memory device operates faster than the first nonvolatile memory device.

10. The method of claim 1, wherein the first non-volatile memory device is a NAND flash memory device and the second non-volatile memory device is a magnetic random access memory (MRAM).

11. A storage device comprising: a first non-volatile memory device configured to store user data; a second non-volatile memory device configured to store operational information regarding the operation of the first non-volatile memory device; a storage controller configured to: suspend operations being executed in the first non-volatile memory device when a sudden power failure occurs; writing a sudden power-off flag in operation information corresponding to the suspended operation among the operation information stored in the second nonvolatile memory device, and performing a block management operation on the first nonvolatile memory device based on the sudden power-off flag written in the second nonvolatile memory device at power-on after the sudden power-off; as well as A power management circuit is configured to: supply power to the first non-volatile memory device, the second non-volatile memory device and the storage controller, detect a sudden power failure occurring at at least one of the first non-volatile memory device, the second non-volatile memory device and the storage controller, and provide a sudden power failure signal to the storage controller. 12 . The storage device of claim 11 , wherein the operation information comprises an operation command and an operation address associated with the operation of the first nonvolatile memory device.

13. The storage device according to claim 12, wherein the block management operation comprises a remapping operation and a garbage collection (GC) priority adjustment operation, in, When the operation command corresponding to the sudden power-off flag is a program command, performing the remapping operation on a storage block corresponding to the operation address among a plurality of storage blocks of the first nonvolatile memory device, and Wherein, when the operation command is an erase command, the GC priority adjustment operation is performed on the storage block corresponding to the operation address.

14. The storage device of claim 13, wherein the remapping operation comprises: The storage block corresponding to the operation address is processed as an invalid block, data stored in the storage block is migrated to another storage block, and a logical address corresponding to the migrated data is mapped to a physical address of the another storage block.

15. The storage device according to claim 13, wherein the GC priority adjustment operation comprises increasing the GC priority of the storage block corresponding to the operation address, and The storage controller is further configured to perform a garbage collection operation on the first non-volatile memory device based on the GC priority.

16. The storage device of claim 11, wherein an operation speed of the second nonvolatile memory device is faster than an operation speed of the first nonvolatile memory device.

17. The storage device according to claim 11, further comprising: A power detector at at least one of the first nonvolatile memory device, the second nonvolatile memory device, and the storage controller is configured to detect a sudden power loss associated with the at least one of the first nonvolatile memory device, the second nonvolatile memory device, and the storage controller.

18. A storage device comprising: a first non-volatile memory device; a second non-volatile memory device configured to temporarily store user data to be stored in the first non-volatile memory device; a storage controller configured to: suspend operations being executed in the first non-volatile memory device when power is suddenly cut off; For the data among the user data temporarily stored in the second non-volatile memory device that is not stored in the first non-volatile memory device, writing a sudden power-off flag; and, at power-on after the sudden power-off, performing migration of data not stored in the first non-volatile memory device from the second non-volatile memory device to the first non-volatile memory device based on the sudden power-off flag written in the second non-volatile memory device; as well as A power management circuit is configured to supply power to the first non-volatile memory device, the second non-volatile memory device, and the storage controller, detect a sudden power failure occurring at at least one of the first non-volatile memory device, the second non-volatile memory device, and the storage controller, and provide a sudden power failure signal to the storage controller.

19. The storage device according to claim 18, wherein the storage controller comprises: The error correction code (ECC) engine is configured to perform an error correction operation on the user data.

20. The storage device according to claim 19, wherein when the power is suddenly cut off, the storage controller is further configured to: rewrite the user data from the second non-volatile memory device, on which the error correction operation has been completed by the ECC engine, into the second non-volatile memory device.

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