Semiconductor device package

Abstract

A semiconductor device package includes a number of interposers mounted to a carrier, wherein the number of interposers can be arranged in an irregular pattern.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device package having at least one interposer layer. Background Technology

[0002] To increase packaging density, dual-sided assemblies are used in semiconductor packaging technology. That is, electronic components can be mounted to either the side of the carrier facing the printed circuit board to which it connects, or to the side of the carrier connecting to external components. Furthermore, the electronic components are encapsulated by a molding compound. Summary of the Invention

[0003] According to an exemplary embodiment of this disclosure, a semiconductor device package includes a carrier, a plurality of first interposers, a first encapsulator, and a second encapsulator. The carrier has a first surface and a second surface opposite to the first surface. The first interposers are disposed in the first surface of the carrier. The first encapsulator encapsulates the first surface of the carrier and the first interposers. Furthermore, the first encapsulator separates one of the first interposers from another of the plurality of first interposers. The second encapsulator encapsulates the second surface of the carrier. The first interposers are arranged in an irregular pattern.

[0004] According to another exemplary embodiment of this disclosure, a semiconductor device package includes a carrier and a first interposer. The carrier has a first surface, and the first interposer is disposed on the first surface of the carrier. Additionally, the first interposer includes a conductive via having an hourglass-shaped cross-section.

[0005] To further understand the present invention, the following embodiments and descriptions are provided to facilitate understanding of the invention; however, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the scope of the invention. Attached Figure Description

[0006] Figure 1A This is a top view of a semiconductor device package according to an embodiment of the present invention.

[0007] Figure 1B A semiconductor device package according to an embodiment of the present disclosure is shown in a molding process.

[0008] Figure 2A This is a top view of a semiconductor device package according to another embodiment of the present disclosure.

[0009] Figure 2B A semiconductor device package according to another embodiment of the present disclosure is shown in a molding process.

[0010] Figure 3A This is a top view of a semiconductor device package according to another embodiment of the present invention.

[0011] Figure 3B A semiconductor device package according to another embodiment of the present disclosure is shown in a molding process.

[0012] Figure 4A This is a top view of a semiconductor device package according to another embodiment of the present invention.

[0013] Figure 4B A semiconductor device package according to another embodiment of the present disclosure is shown in a molding process.

[0014] Figure 5A This is a top view of a semiconductor device package according to another embodiment of the present invention.

[0015] Figure 5B Explanation along Figure 5A The cross-sectional view of line II in the diagram.

[0016] Figure 6 A semiconductor device package according to another embodiment of the present disclosure is shown.

[0017] Figure 7 A semiconductor device package according to another embodiment of the present disclosure is shown.

[0018] Figure 8 A semiconductor device package according to another embodiment of the present disclosure is shown.

[0019] Figure 9 A semiconductor device package according to another embodiment of the present disclosure is shown. Detailed Implementation

[0020] The foregoing description and the following detailed description are exemplary and are intended to further explain the scope of the invention. Other objects and advantages relating to the invention will be explained in the following description and drawings.

[0021] Figure 1A A semiconductor device package 1 according to an embodiment of the present disclosure is shown. Reference Figure 1A In this embodiment, the semiconductor device package 1 includes a carrier 11, which may be a PCB board or a substrate. An interposer 12 and several components 13, 14, 15, and 16 may be disposed on the surface 111 of the carrier 11. The interposer 12 may be annular, and the components 13, 14, 15, and 16 may be surrounded by the interposer 12. (See reference) Figure 1A The surface 111 of the carrier 11 is basically divided into two regions 1121 and 1122, wherein region 1121 is located outside the annular intermediate layer 12 and region 1122 is located inside the annular intermediate layer 12.

[0022] When the encapsulating material 18 is formed on the surface 111 of the carrier 11 and the intermediate layer 12 and components 13, 14, 15 and 16 are encapsulated by molding process, the flow of the encapsulating material 18 will be uneven (see reference). Figure 1B When the encapsulating material 18 flows from side 113 of the carrier 11 towards side 114 of the carrier 11, the flow rate of the encapsulating material 18 flowing through region 1121 can be greater than the flow rate of the encapsulating material 18 flowing through region 1122. For example... Figure 1B As shown, most of region 1121 is covered by the encapsulating material 18, but only a small portion of region 1122 is covered by the encapsulating material 18.

[0023] Figure 2A A semiconductor device package 2 according to an embodiment of the present disclosure is shown. Reference Figure 2A In this embodiment, the semiconductor device package 2 includes a carrier 21, which may be a PCB board or a substrate. Several interposers 221, 222, 223, 224, 225, 226 and several components 23, 24, 25, 26 may be disposed on the surface 211 of the carrier 2. Interposers 221 and 222 may be substantially aligned with each other. Interposers 223 and 224 may be substantially aligned with each other. Interposers 225 and 226 may be substantially aligned with each other. (See reference) Figure 2A The surface 211 of the carrier is divided into seven regions. Regions 2121, 2123, 2125, and 2125 do not have any intermediary layers. Region 2122 includes intermediary layers 221 and 222. Region 2124 includes intermediary layers 223 and 224. Region 2126 includes intermediary layers 225 and 226.

[0024] When the encapsulating material 28 is formed on the surface 211 of the carrier 21 and the intermediate layers 221, 222, 223, 224, 225, 226 and components 23, 24, 25 and 26 are encapsulated using a molding process, the flow of the encapsulating material 28 will be uneven (see reference). Figure 2B When the encapsulating material 28 flows from side 213 of the carrier 21 towards side 214 of the carrier 21, the flow rate of the encapsulating material 28 flowing through regions 2121, 2123, 2125, and 2127 can be greater than the flow rate of the encapsulating material 18 flowing through regions 2122, 2124, and 2126. For example... Figure 2B As shown, most areas 2121, 2123, 2125, and 2127 are covered by the encapsulating material 28, but only a small portion of areas 2122, 2124, and 2126 are covered by the encapsulating material 28.

[0025] Figure 3A A semiconductor device package 3 is shown according to an embodiment of the present disclosure. Reference Figure 3AIn this embodiment, the semiconductor device package 3 includes a carrier 31, which can be a PCB board or a substrate. Several interposer layers 321, 322, 323, 324, 325, 326, 327, 328, 329 and several components 33, 34, 35, 36, 37 can be disposed on the surface 311 of the carrier 3. The interposer layers 321, 322, 323, 324, 325, 326, 327, 328, 329 can be randomly arranged on the surface 311 of the carrier 3. That is, the interposer layers 321, 322, 323, 324, 325, 326, 327, 328, 329 can be arranged in an irregular pattern. This means that the pattern formed by the arrangement of the interposer layers 321, 322, 323, 324, 325, 326, 327, 328, 329 is irregular in shape or form. (See reference) Figure 3A It appears that the intermediate layers 321, 322, 323, 324, 325, 326, 327, 328, and 329 are dispersed on the carrier 31. Furthermore, the pattern formed by the arrangement of the intermediate layers 321, 322, 323, 324, 325, 326, 327, 328, and 329 is not a regular geometric shape. In addition, at least one of the intermediate layers 321, 322, 323, 324, 325, 326, 327, 328, and 329 may have a redistribution layer. Furthermore, the intermediate layers 321 and 322, which can be arranged in an L-shape, can be integrated with each other.

[0026] When the encapsulating material 38 is formed on the surface 311 of the carrier 31 and the intermediate layers 321, 322, 323, 324, 325, 326, 327, 328, 329 and components 33, 34, 35, 36, 37 are encapsulated using a molding process, the flow of the encapsulating material 28 will be smooth (see reference). Figure 3B For example, such as Figure 3B As shown, the encapsulating material 38 flows from side 313 of the carrier 31 toward side 314 of the carrier 31. When the encapsulating material 38 flows to the middle portion of the surface 311 of the carrier 31, most of the left half of the surface 311 of the carrier 31 is covered by the encapsulating material 38. Therefore, when the encapsulating material 38 flows to side 314 of the carrier 31, most of the surface 311 of the carrier 31 will be covered by the encapsulating material 38.

[0027] Figure 4A A semiconductor device package 4 is shown according to an embodiment of the present disclosure. Reference Figure 4AIn this embodiment, the semiconductor device package 4 includes a carrier 41, which can be a PCB board or a substrate. Several interposer layers 421, 422, 423, 424, 425, 426, 427 and several components 43, 44, 45, 46, 47 can be disposed on the surface 411 of the carrier 4. The interposer layers 421, 422, 423, 424, 425, 426, 427 can be randomly arranged on the surface 411 of the carrier 4. That is, the interposer layers 421, 422, 423, 424, 425, 426, 427 can be arranged in an irregular pattern. This means that the pattern formed by the arrangement of the interposer layers 421, 422, 423, 424, 425, 426, 427 is irregular in shape or form. (See reference) Figure 4A It appears that the intermediate layers 421, 422, 423, 424, 425, 426, and 427 are scattered on the carrier 41. In addition, the pattern formed by the arrangement of the intermediate layers 421, 422, 423, 424, 425, 426, and 427 is not a regular geometric shape.

[0028] When the encapsulating material 48 is formed on the surface 411 of the carrier 41 and the intermediate layers 421, 422, 423, 424, 425, 426, 427 and components 43, 44, 45, 46, 47 are encapsulated using a molding process, the flow of the encapsulating material 28 will be smooth (see reference). Figure 4B For example, such as Figure 4B As shown, the encapsulating material 48 flows from side 413 of the carrier 41 toward side 414 of the carrier 41. When the encapsulating material 48 flows to the middle portion of the surface 411 of the carrier 41, most of the left half of the surface 411 of the carrier 41 is covered by the encapsulating material 48. Therefore, when the encapsulating material 48 flows to side 414 of the carrier 41, most of the surface 411 of the carrier 41 will be covered by the encapsulating material 48.

[0029] Figure 5A A semiconductor device package 5 is shown according to an embodiment of the present disclosure. Reference Figure 5A In this embodiment, the semiconductor device package 5 includes a carrier 51, which may be a PCB board or a substrate. Several interposers 521, 522, 523, 524, 525 and several components 531, 532, 533, 534, 535 may be disposed on the surface 511 of the carrier 5. The interposers 521, 522, 523, 524, 525 may be randomly arranged on the surface 511 of the carrier 5. That is, the interposers 521, 522, 523, 524, 525 may be arranged in an irregular pattern. This means that the pattern formed by the arrangement of the interposers 521, 522, 523, 524, 525 is irregular in shape or form. (See reference) Figure 5AThe intermediate layers 521, 522, 523, 524, and 525 appear to be dispersed on the carrier 51. Furthermore, the pattern formed by the arrangement of the intermediate layers 521, 522, 523, 524, and 525 is not a regular geometric shape. Additionally, at least one of the intermediate layers 521, 522, 523, 524, and 525 may have a re-laid layer. Furthermore, the encapsulating material 53 may be disposed on the surface 511 of the carrier 51, encapsulating the intermediate layers 521, 522, 523, 524, and 525, and the components 531, 532, 533, 534, and 535.

[0030] Figure 5B Explanation along Figure 5A The cross-sectional view of line II in the diagram. (See diagram below.) Figure 5B As shown, the encapsulating material 53 can encapsulate the surfaces 511 of the carrier, components 531 and 532, and the outer sides of intermediate layers 521 and 522. In particular, intermediate layers 521 and 522 can be separated from each other by the encapsulating material 53. Furthermore, a portion of the top surface 5301 of the encapsulating material 53 may be lower than the top surface 5211 of intermediate layer 521 or the top surface 5221 of intermediate layer 522. Intermediate layer 521 may include a plurality of conductive vias 5212, and intermediate layer 522 may include a plurality of conductive vias 5222. (Reference) Figure 5B Each of the conductive vias 5212 and 5222 may have an hourglass-shaped cross-section.

[0031] Furthermore, the carrier 51 further includes a surface 512 opposite to the surface 511. Components 541, 542, 543, and 544 can be mounted on the surface 512 of the carrier 51. Encapsulating material 55 can encapsulate a portion of the surface 512 of the carrier 51 and components 541, 542, and 543. That is, another portion of the surface 512 of the carrier 51 is not covered by encapsulating material 53. Additionally, as... Figure 5B As shown, component 544 is disposed on the portion of surface 512 of carrier 51 that is not encapsulated by encapsulating material 53. Therefore, component 544 is also not encapsulated by encapsulating material 53. Furthermore, refer to... Figure 5B The compartment shielding structure 545 can be installed between components 541 and 542.

[0032] Figure 6 A semiconductor device package 6 according to an embodiment of the present disclosure is shown. Reference Figure 6The semiconductor device package 6 may include a carrier 61, which may be a PCB board or a substrate. Interposers 621 and 622, and components 631, 632, 633, 634, 635, and 636 may be disposed on the surface 611 of the carrier 61. Encapsulating material 63 may encapsulate the surface 611 of the carrier 61, the components 631, 632, 633, 634, 635, and 636, and the outer surfaces of interposers 621 and 622. In particular, interposers 621 and 622 may be separated from each other by encapsulating material 63. Furthermore, a portion of the top surface 6301 of encapsulating material 63 may be lower than the top surface 6211 of interposer 621 or the top surface 6221 of interposer 622. Interposer 621 may include a plurality of conductive vias 6212, and interposer 622 may include a plurality of conductive vias 6222. Reference Figure 6 Each of the conductive vias 6212 and 6222 may have an hourglass-shaped cross-section. Intermediate layers 621 and / or 622 may have a re-laid layer.

[0033] Furthermore, the carrier 61 further includes a surface 612 opposite to the surface 611. Components 641, 642, 643, 644, 645, 646, 647, and 648 can be mounted on the surface 612 of the carrier 61. Encapsulating material 65 can encapsulate the surface 612 of the carrier 61 and components 641, 642, 643, 644, 645, 646, 647, and 648.

[0034] Figure 7 A semiconductor device package 7 according to an embodiment of the present disclosure is shown. Reference Figure 7 The semiconductor device package 7 may include a carrier 71, which may be a PCB board or a substrate. Interposers 721 and 722 and components 731, 732, 733, 734, 735, and 736 may be disposed on the surface 711 of the carrier 71. Additionally, an interposer 723 may be stacked on interposers 721 and 722, wherein the interposer 723 may be a PCB board or a substrate. The cross-sectional width of the interposer 723 is smaller than the cross-sectional width of the carrier 71. An encapsulating material 73 may encapsulate a portion of the surface 711 of the carrier 71, components 732, 733, 734, 735, and 736, interposers 721 and 722, and the outer side of the surface 7231 and interposer 723. That is, another portion of the surface 711 of the carrier 71 is not covered by the encapsulating material 73. Furthermore, as... Figure 7 As shown, component 731 is disposed on the portion of surface 711 of carrier 71 that is not encapsulated by encapsulating material 73. Therefore, component 731 is not encapsulated by encapsulating material 73.

[0035] Interposer 721 and interposer 722 can be separated from each other by encapsulating material 73. Furthermore, interposer 721 may include a plurality of conductive vias 7212, and interposer 722 may include a plurality of conductive vias 7222. (Reference) Figure 7 Each of the conductive vias 7212 and 7222 may have an hourglass-shaped cross-section. Intermediate layers 721 and / or 722 may have a re-laid layer.

[0036] In addition, refer to Figure 7 The interposer 723 may have an exposed surface 7232 opposite to the surface 7231. Two components 771 and 772 may be disposed on the surface 7232 of the interposer 723. In particular, components 771 and 772 may be a PCB board or a substrate.

[0037] Furthermore, the carrier 71 further includes a surface 712 opposite to the surface 711. Components 741, 742, 743, 744, 745, and 746 can be mounted on the surface 712 of the carrier 71, wherein all components 741, 742, 743, 744, 745, and 746 can be passive components. Encapsulating material 75 can encapsulate the surface 712 of the carrier 71 and components 741, 742, 743, 744, 745, and 746.

[0038] Figure 8 A semiconductor device package 8 according to an embodiment of the present disclosure is shown. Reference Figure 8 The semiconductor device package 8 may include a carrier 81, which may be a PCB board or a substrate. Interposers 821 and 822 and components 831, 832, 833, 834, 835, and 836 may be disposed on the surface 811 of the carrier 81. Additionally, an interposer 823 may be stacked on interposers 821 and 822, wherein the interposer 823 may be a PCB board or a substrate. The cross-sectional width of the interposer 823 is smaller than the cross-sectional width of the carrier 81. The interposer 823 may include a surface 8231 facing the surface 811 of the carrier 81. Components 881, 882, and 883 may be disposed on the surface 8231 of the interposer 823. When the interposer 823 is supported on interposers 821 and 822, the interposers 821 and 822 may be connected to the surface 8231 of the interposer 823. The encapsulating material 83 can encapsulate a portion of the surface 811 of the carrier 81, components 832, 833, 834, 835, 836, intermediate layers 821, 822, components 881, 882, 883, and the outer side of surface 8231 and intermediate layer 823. That is, another portion of the surface 811 of the carrier 81 is not covered by the encapsulating material 83. Additionally, as... Figure 8 As shown, component 831 is disposed on the portion of surface 811 of carrier 81 that is not encapsulated by encapsulating material 83. Therefore, component 831 is not encapsulated by encapsulating material 83.

[0039] Interposer 821 and interposer 822 can be separated from each other by encapsulating material 83. Furthermore, interposer 821 may include a plurality of conductive vias 8212, and interposer 822 may include a plurality of conductive vias 8222. (Reference) Figure 8 Each of the conductive vias 8212 and 8222 may have an hourglass-shaped cross-section. Intermediate layers 821 and / or 822 may have a re-laid layer.

[0040] In addition, refer to Figure 8 The interposer 823 may have an exposed surface 8232 opposite to the surface 8231. Two components 871, 872 may be disposed on the surface 8232 of the interposer 823. In particular, components 871, 872 may be a PCB board or a substrate.

[0041] Furthermore, the carrier 81 further includes a surface 812 opposite to the surface 811. Components 841, 842, 843, 844, 845, 846, 847, and 848 can be mounted on the surface 812 of the carrier 81. Encapsulating material 85 can encapsulate the surface 812 of the carrier 81 and the components 841, 842, 843, 844, 845, 846, 847, and 848.

[0042] Figure 9 A semiconductor device package 9 according to an embodiment of the present disclosure is shown. Reference Figure 9 The semiconductor device package 9 may include a carrier 91, which may be a PCB board or a substrate. Interposers 921 and 922 and components 931, 932, 933, 934, 935, and 936 may be disposed on the surface 911 of the carrier 91. Additionally, an interposer 923 may be stacked on interposers 921 and 922, wherein the interposer 923 may be a PCB board or a substrate. The cross-sectional width of the interposer 923 is smaller than the cross-sectional width of the carrier 91. The interposer 923 may include a surface 9231 facing the surface 911 of the carrier 91. An encapsulating material 93 may encapsulate a portion of the surface 911 of the carrier 91, components 932, 933, 934, 935, and 936, interposers 921 and 922, surface 9231, and the outer side of the interposer 923. That is, another portion of the surface 911 of the carrier 91 is not covered by the encapsulating material 93. Furthermore, as... Figure 9 As shown, component 931 is disposed on the portion of surface 911 of carrier 91 that is not encapsulated by encapsulating material 93. Therefore, component 931 is not encapsulated by encapsulating material 93.

[0043] Interposer 921 and interposer 922 can be separated from each other by encapsulating material 93. Furthermore, interposer 921 may include a plurality of conductive vias 9212, and interposer 922 may include a plurality of conductive vias 9222. (Reference) Figure 9 Each of the conductive vias 9212 and 9222 may have an hourglass-shaped cross-section. Intermediate layers 921 and / or 922 may have a re-laid layer.

[0044] In addition, refer to Figure 9Intermediate layer 923 may have an exposed surface 9232 opposite to surface 9231. Two components 971, 972 may be disposed on surface 9232 of intermediate layer 923. In particular, components 971, 972 may be a PCB board or a substrate.

[0045] Furthermore, the carrier 91 further includes a surface 912 opposite to surface 811. Components 941, 942, 943, 944 and encapsulation units 945, 946 can be mounted on surface 912 of the carrier 91. Encapsulating material 95 can encapsulate surface 912 of the carrier 91 and components 941, 942, 943, 944 and encapsulation units 945, 946. A compartmentalized shielding structure 948 can be disposed between encapsulation unit 945 and component 942.

[0046] Furthermore, the packaging unit 945 may include a substrate 9451 having a surface 9452. Components 9453, 9454, and 9455 may be mounted on the surface 9452 of the substrate 9451. An encapsulating material 9456 may encapsulate the surface 9452 of the substrate 9451 and components 9453, 9454, and 9455. Additionally, a shielding layer 9457 may be formed on the encapsulating material 9456 and electrically connected to the substrate 9451. Furthermore, a component 9458 may be embedded in the substrate 9451.

[0047] The encapsulation unit 946 may include a substrate 9461 having a surface 9462. Components 9463, 9464, and 9465 may be mounted on the surface 9462 of the substrate 9461. Encapsulating material 9466 may encapsulate the surface 9462 of the substrate 9461 and components 9463, 9464, and 9465. Furthermore, the substrate 9461 has a surface 9468 opposite to the surface 9462 and facing the carrier 91. Component 9469 and solder balls 9460 may be mounted to the surface 9468 of the substrate 9461. The encapsulation unit 9466 may be mounted to the surface 9468 of the substrate 9461 via solder balls 9460. Encapsulating material 9471 may encapsulate the surface 9468 of the substrate 9461, the outer side of the solder balls 9460, and component 9469. Additionally, a shielding layer 9467 may be formed on and electrically connected to the substrate 9461 of the encapsulating materials 9466 and 9471.

[0048] In addition, active or passive dies may be embedded in carrier 91 and / or substrate 9461.

[0049] In this invention, the formation or positioning of the first feature above or on the second feature may include embodiments in which the first feature and the second feature are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact.

[0050] As used herein, the terms “approximately,” “substantially,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to a situation in which the event or situation has clearly occurred or is very close to occurring. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

[0051] For example, "basically parallel" can refer to an angular variation of less than or equal to ±10° relative to 0°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°. Similarly, "basically perpendicular" can refer to an angular variation of less than or equal to ±10° relative to 90°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°.

[0052] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0053] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural indicators.

[0054] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0055] Although the invention has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions may be made and equivalents substituted without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, artistic representations of the invention may differ from actual devices. Other embodiments of the invention may exist that are not specifically described. The description and illustrations should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the invention.

Claims

1. A semiconductor device package comprising: The carrier has an upper surface. A first intermediary layer and a second intermediary layer are disposed on the upper surface of the carrier. The third intermediary layer is stacked on top of the first and second intermediary layers, and A first encapsulant encapsulates the upper surface of the carrier, the lower surface and sides of the first intermediate layer, the second intermediate layer and the third intermediate layer, and... A second encapsulant encapsulates the lower surface of the carrier; A portion of the upper surface of the carrier is not encapsulated by the first encapsulant, and a first component is disposed on the portion of the upper surface of the carrier that is not encapsulated by the first encapsulant. The first component does not overlap with the third interlayer in a direction perpendicular to the upper surface, wherein the first component overlaps with the second encapsulant in that direction; The first encapsulation has a side surface facing the first component, wherein the side surface is not orthogonal to the upper surface of the carrier; The angle between the portion of the side surface and the portion of the upper surface of the carrier that is not encapsulated by the first encapsulant is greater than ninety degrees.

2. The semiconductor device package of claim 1, wherein the height of the first component is greater than the height of the third interposer.

3. In the semiconductor device package according to claim 1, the cross-sectional width of the third interposer is smaller than the cross-sectional width of the carrier.

4. The semiconductor device package of claim 1, further comprising a compartment shielding structure, wherein the compartment shielding structure is disposed on the lower surface of the carrier and covers the second encapsulant.

5. The semiconductor device package of claim 1, wherein a second component is further disposed on the upper surface of the third interposer and overlaps with the first component in the direction thereof.

6. The semiconductor device package of claim 5, wherein the second component overlaps with the first interposer in the direction.

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