Packaging structure and manufacturing method thereof

Abstract

The present disclosure is related to a packaging structure and a manufacturing method thereof. A packaging structure includes a semiconductor die and a redistribution wiring structure. The redistribution wiring structure is disposed on the semiconductor die and electrically connected to the semiconductor die, and includes a patterned conductive layer, a dielectric layer and an interlayer film. The dielectric layer is disposed on the patterned conductive layer. The interlayer film is sandwiched between the dielectric layer and the patterned conductive layer, wherein the patterned conductive layer is separated from the dielectric layer by the interlayer film.

Description

Technical Field

[0001] The disclosed embodiments relate to a packaging structure and a manufacturing method thereof. Background Art

[0002] Semiconductor devices and integrated circuits are typically fabricated on a single semiconductor wafer. The die of the wafer can be processed and packaged together with other semiconductor devices or dies at the wafer level, and various techniques have been developed for wafer level packaging (e.g., forming redistribution wiring structures / layers). In addition, such packaging can be further integrated into a semiconductor substrate or carrier after dicing. Summary of the invention

[0003] The disclosed embodiment provides a packaging structure including a semiconductor die and a redistribution wiring structure. The redistribution wiring structure is disposed on the semiconductor die and electrically connected to the semiconductor die, and includes a patterned conductive layer, a dielectric layer and an interlayer film. The dielectric layer is disposed on the patterned conductive layer. The interlayer film is sandwiched between the dielectric layer and the patterned conductive layer, wherein the patterned conductive layer is separated from the dielectric layer by the interlayer film. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0005] Figures 1 to 15 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0006] Fig.16 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0007] Fig.17 and Fig.18 is a flow chart illustrating a method of manufacturing a redistribution wiring structure / layer of a package structure according to some embodiments of the present disclosure.

[0008] Fig.19 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

[0009] Fig. 20 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

[0010] Figures 21 to 32are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0011] Fig.33 is a flow chart illustrating a method of manufacturing a redistribution wiring structure / layer of a package structure according to some embodiments of the present disclosure.

[0012] Fig.34 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

[0013] Fig.35 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

[0014] Figures 36 to 42 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0015] Fig.43 is a flow chart illustrating a method of manufacturing a redistribution wiring structure / layer of a package structure according to some embodiments of the present disclosure.

[0016] Fig.44 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

[0017] Fig.45 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

[0018] Fig.46 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

[0019] Fig.47 is a flow chart illustrating a method of manufacturing a redistribution wiring structure / layer of a package structure according to some embodiments of the present disclosure.

[0020] Fig.48 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

[0021] Fig.49 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

[0022] Fig.50 is a schematic cross-sectional view showing an example of an interlayer film according to some embodiments of the present disclosure.

[0023] [Explanation of Symbols]

[0024] 112: Carrier

[0025] 114: Peeling Layer

[0026] 116: Buffer layer

[0027] 130, 130-1, 130-2, 130-3: Semiconductor die

[0028] 130a: Active surface

[0029] 130b: pad

[0030] 130c: Passivation layer

[0031] 130d: Via hole

[0032] 130e: Protective layer

[0033] 130f: dorsal surface

[0034] 130s: Semiconductor substrate

[0035] 140, 140': Insulation enclosure

[0036] 140a: Top surface

[0037] 150, 250, 350, 450: Re-routing line structure

[0038] 151, 151a, 155, 155-1, 155-2, 155-3, 155a, 255, 255-1, 255-2, 255-3, 255-4, 255a, 355, 355-1, 355-2, 355-3, 455, 455-1, 455-2, 455-3, 455-4: interlayer film

[0039] 152, 152-1, 152-2, 152-3, 156, 252, 252-1, 252-2, 252-3, 252-4, 252a, 352, 356, 356-1, 356-2, 356-3, 356a, 356a', 452, 452-1, 452-2, 452-3, 452-4: dielectric layer

[0040] 153, 153-1, 153-2, 153-3, 153a, 253, 253-1, 253-2, 253-3, 253-4, 353, 353-1, 353-2, 353-3, 453, 453-1, 453-2, 453-3, 453-4, SL1: seed layer

[0041] 154, 154-1, 154-2, 154-3, 254, 254-1, 254-2a, 254-2b, 254-3, 254-4, 354, 354-1, 354-2, 354-3, 454, 454-1, 454-2a, 454-2b, 454-3, 454-4: patterned conductive layer

[0042] 160: Seed layer pattern

[0043] 170, 180, 190: Conductive elements

[0044] CP: Conductive Column

[0045] HD: Hold Device

[0046] O1, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12: Open

[0047] P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12: Package structure

[0048] PR1: Patterned photoresist layer

[0049] S10, S20, S30, S40, S41a, S41a-1, S41a-2, S41a-3, S41a-4, S41a-5, S41a-o, S41b, S41c, S41d, S42a, S42b, S42 c, S42d, S43a, S43b, S43c, S43d, S44a, S44b, S44c, S44d, S45a, S45b, S45d, S46a, S46b, S46d, S47a, S50, S60: Steps

[0050] S252-1, S252-2, S254-1, S254-2b, S255-1, S255-2: top surface

[0051] TH: Heat treatment

[0052] u1, u2: Under ball metal (UBM) pattern

[0053] X: Direction

[0054] Z: Direction / Stacking Direction DETAILED DESCRIPTION

[0055] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The following describes specific examples of components, values, operations, materials, arrangements, etc. to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. It is expected that there are other components, values, operations, materials, arrangements, etc. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0056] Furthermore, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0057] In addition, for ease of description, terms such as "first", "second", "third", "fourth", "fifth", etc. may be used herein to describe similar or different elements or features shown in the figures, and may be used interchangeably depending on the order of existence or the context of description.

[0058] Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may, for example, include a test pad formed in a redistribution layer or on a substrate, which enables testing of a 3D package or 3DIC, use of a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method including intermediate verification of a known good die to improve yield and reduce costs.

[0059] Figures 1 to 15 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig.16 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig.17 and Fig.18 is a flow chart showing a method for manufacturing a redistribution wiring structure / layer of a package structure according to some embodiments of the present disclosure, wherein Fig.17 and Fig.18 The method may be (but is not limited to) implemented in Fig.16 In some embodiments, the manufacturing method is part of a packaging process. Figures 1 to 15 In the figure, a (semiconductor) chip or tube die is shown to represent multiple (semiconductor) chips or tube dies of a wafer, and a (semiconductor) package structure is shown to represent multiple (semiconductor) package structures obtained after the (semiconductor) manufacturing method, but the present disclosure is not limited to this.

[0060] In some embodiments, according to Fig.16 In step S10, a carrier is provided. Figure 1 In some embodiments, a carrier 112 is provided on which a release layer 114 and a buffer layer 116 are coated. In one embodiment, the carrier 112 may be a glass carrier or any carrier suitable for carrying a semiconductor wafer or a reconstituted wafer for a semiconductor package manufacturing method.

[0061] In some embodiments, the peeling layer 114 is disposed on the carrier 112, and the material of the peeling layer 114 may be any material suitable for bonding and peeling the carrier 112 relative to the upper layer (e.g., the buffer layer 116) or for bonding and peeling any wafer disposed thereon (e.g., the carrier 112). In some embodiments, the peeling layer 114 may include a release layer (e.g., a light-to-heat conversion (LTHC) layer) or an adhesive layer (e.g., an ultraviolet curable adhesive or a heat curable adhesive layer).

[0062] like Figure 1As shown in , in some embodiments, the buffer layer 116 is disposed on the peeling layer 114, and the peeling layer 114 is located between the carrier 112 and the buffer layer 116. In some embodiments, the buffer layer 116 may be a dielectric material layer. In some embodiments, the buffer layer 116 may be a polymer layer made of polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB) or any other suitable polymer-based dielectric material. In some embodiments, the buffer layer 116 may be an Ajinomoto buildup film (ABF), a solder resist (SR), etc. The top surface of the buffer layer 116 may be flattened and may have a high degree of coplanarity.

[0063] For example, the release layer 114 and the buffer layer 116 may be formed by suitable manufacturing techniques such as spin-coating, lamination, deposition, etc. The present disclosure is not particularly limited thereto.

[0064] In some embodiments, according to Fig.16 In step S10, a semiconductor die is disposed on the carrier 112. In some embodiments, at least one semiconductor die 130 is provided. Figure 1 As shown in , for example, the at least one semiconductor die 130 includes a plurality of semiconductor dies, such as semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3. In some embodiments, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 are picked up and placed on carrier 112 and disposed on buffer layer 116. For example, as Figure 1 As shown in FIG. 1 , semiconductor dies 130 - 1 , 130 - 2 , and 130 - 3 are arranged side by side along a direction X, and the direction X is perpendicular to a stacking direction Z of carrier 112 , peeling layer 114 , buffer layer 116 , semiconductor die 130 - 1 , semiconductor die 130 - 2 , and semiconductor die 130 - 3 . Figure 1 As shown in , for illustration purposes, only three semiconductor dies 130 (eg, semiconductor die 130 - 1 , semiconductor die 130 - 2 , and semiconductor die 130 - 3 ) are presented, however, it should be noted that the number of semiconductor dies 130 may be one or more than one, and the present disclosure is not limited thereto.

[0065] In some embodiments, the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3 each include: a semiconductor substrate 130s having an active surface 130a and a backside surface 130f opposite to the active surface 130a; a plurality of pads 130b distributed on the active surface 130a; a passivation layer 130c covering the active surface 130a and a portion of the pads 130b; a plurality of vias 130d connected to the pads 130b exposed through the passivation layer 130c; and a protection layer 130e disposed on the vias 130d. The pads 130b, the passivation layer 130c, the vias 130d, and the protection layer 130e are formed on the semiconductor substrate 130s. The pads 130b are partially exposed through the passivation layer 130c, the vias 130d are respectively disposed on the pads 130b and electrically connected to the pads 130b, and the protection layer 130e covers the passivation layer 130c exposed through the vias 130d and the vias 130d.

[0066] However, the present disclosure may not be limited thereto. For example, the via 130d and the protection layer 130e may be omitted. In an alternative embodiment, the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3 may each include: a semiconductor substrate 130s having an active surface 130a and a backside surface 130f opposite to the active surface 130a; the plurality of pads 130b distributed on the active surface 130a; and a passivation layer 130c covering the active surface 130a and a portion of the pads 130b.

[0067] The material of the semiconductor substrate 130s may include a silicon substrate, which includes active components (e.g., transistors and / or memories, such as N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, etc.) and / or passive components (e.g., resistors, capacitors, inductors, etc.) formed therein. In some embodiments, such active components and passive components may be formed in a front-end-of-line (FEOL) process. In alternative embodiments, the semiconductor substrate 130s may be a bulk silicon substrate (e.g., a bulk single crystal silicon substrate), a doped silicon substrate, an undoped silicon substrate, or a silicon-on-insulator (SOI) substrate, wherein the dopant of the doped silicon substrate may be an N-type dopant, a P-type dopant, or a combination thereof. The present disclosure is not limited thereto.

[0068] In addition, the semiconductor substrate 130s may further include an interconnect structure (not shown) disposed on the active surface 130a. In some embodiments, the interconnect structure may include one or more interlayer dielectric layers and one or more patterned conductive layers alternately stacked to provide wiring functions for active components and passive components embedded in the semiconductor substrate 130s, wherein the pad 130b may be referred to as the outermost layer of the patterned conductive layer. In one embodiment, the interconnect structure may be formed in a back-end-of-line (BEOL) process. For example, the interlayer dielectric layer may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed by other suitable dielectric materials, and the interlayer dielectric layer may be formed by deposition, etc. For example, the patterned conductive layer may be a patterned copper layer or other suitable patterned metal layer, and the patterned conductive layer may be formed by electroplating or deposition. However, the present disclosure is not limited thereto.

[0069] For example, the pad 130b is an aluminum pad or other suitable metal pad. For example, the via 130d is a copper column, a copper alloy column, or other suitable metal column containing copper metal. In some embodiments, the passivation layer 130c and the protective layer 130e may be a polybenzoxazole (PBO) layer, a polyimide (PI) layer, or other suitable polymer. In some alternative embodiments, the passivation layer 130c and the protective layer 130e may be made of inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, or any suitable dielectric material. For example, the material of the passivation layer 130c may be the same as or different from the material of the protective layer 130e.

[0070] Note that at least one semiconductor die 130 described herein (e.g., semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3) may be referred to as a semiconductor chip or an integrated circuit (IC). In alternative embodiments, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 described herein may be semiconductor devices. In certain embodiments, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 may include one or more digital chips, analog chips, or mixed signal chips, such as an application-specific integrated circuit (ASIC) chip, a sensor chip, a wireless and radio frequency (RF) chip, a memory chip, a logic chip, or a voltage regulator chip.

[0071] In some embodiments, in addition to semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3, the at least one semiconductor die described herein may further include additional semiconductor dies of the same type or of a different type. In alternative embodiments, the additional semiconductor die may include a digital chip, an analog chip, or a mixed signal chip, such as an ASIC chip, a sensor chip, a wireless and RF chip, a memory chip, a logic chip, or a voltage regulator chip. The present disclosure is not limited thereto.

[0072] In the present disclosure, it should be understood that the illustrations of semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 and other components in all figures are schematic and not drawn to scale. In one embodiment, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 may be the same. In alternative embodiments, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 may be different from each other.

[0073] Continue to refer to Figure 1 In some embodiments, semiconductor die 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3) are disposed directly on buffer layer 116, wherein a backside surface 130f of each of semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 physically contacts the buffer layer. However, the present disclosure is not limited thereto.

[0074] In alternative embodiments, the buffer layer 116 may be optionally omitted from the peeling layer 114, wherein each of the semiconductor dies 130 (e.g., the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3) is then disposed on the peeling layer 114 by a connection film (not shown). In some embodiments, a first connection film is located between the semiconductor die 130-1 and the peeling layer 114, and two opposite sides of the first connection film physically contact the backside surface 130f of the semiconductor die 130-1 and the peeling layer 114. In some embodiments, a second connection film is located between the semiconductor die 130-2 and the peeling layer 114, and two opposite sides of the second connection film physically contact the backside surface 130f of the semiconductor die 130-2 and the peeling layer 114. In some embodiments, a third connection film is located between the semiconductor die 130-3 and the peeling layer 114, and two opposite sides of the third connection film physically contact the backside surface 130f of the semiconductor die 130-3 and the peeling layer 114. In some embodiments, due to the above connection film, the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3 are stably bonded to the peeling layer 114. In some embodiments, the above connection film may be (but not limited to) a die attach film or layer made of an adhesive, an epoxy-based resin, an acrylic polymer, other suitable insulating materials, etc., and it may or may not have a filler (such as silicon dioxide, aluminum oxide, etc.) filled therein. The present disclosure is not limited thereto.

[0075] Reference Figure 2 In some embodiments, according to Fig.16 In step S20, the semiconductor die 130 is encapsulated in an insulating encapsulation body 140. In some embodiments, the insulating encapsulation body 140 is formed on the buffer layer 116 and on the carrier 112. Figure 2 As shown in , for example, the insulating encapsulant 140 at least fills the gaps between the semiconductor die 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3). In some embodiments, the insulating encapsulant 140 covers the semiconductor die 130. In other words, for example, the semiconductor die 130 is embedded in the insulating encapsulant 140 and is not exposed by the insulating encapsulant 140 in a touchable manner.

[0076] In some embodiments, the insulating enclosure 140 is a molding compound formed by a molding process. In some embodiments, the insulating enclosure 140 may, for example, include a polymer (e.g., epoxy resin, phenolic resin, silicon-containing resin, or other suitable resin), a dielectric material, or other suitable material. In alternative embodiments, the insulating enclosure 140 may include an acceptable insulating enclosure material. In some embodiments, the insulating enclosure 140 may further include an inorganic filler or inorganic compound (e.g., silica, clay, etc.) that can be added thereto to optimize the coefficient of thermal expansion (CTE) of the insulating enclosure 140. The present disclosure is not limited thereto.

[0077] Reference Figure 3 In some embodiments, according to Fig.16 In step S30, the insulating encapsulation body 140 is planarized to form an insulating encapsulation body 140' exposing the semiconductor die 130. In some embodiments, as shown in FIG. Figure 3 As shown in , after planarization, the top surface of the semiconductor die 130 (e.g., the top surface of the via 130d of each of the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3 and the top surface of the protective layer 130e) is exposed through the top surface 140a of the insulating encapsulant 140'. That is, for example, the top surface of the semiconductor die 130 becomes substantially level with the top surface 140a of the insulating encapsulant 140'. In other words, the top surface of the semiconductor die 130 and the top surface 140a of the insulating encapsulant 140' are substantially coplanar with each other. In some embodiments, as Figure 3 As shown in FIG. 1 , the semiconductor die 130 is exposed through the insulating encapsulation body 140 ′ in a touchable manner. That is, for example, the via 130 d of the semiconductor die 130 is exposed through the insulating encapsulation body 140 ′ in a touchable manner.

[0078] For example, the insulating encapsulation 140 may be planarized by mechanical grinding or chemical mechanical polishing (CMP). After the planarization step, a cleaning step may be optionally performed, for example, to clean and remove residues generated from the planarization step. However, the present disclosure is not limited thereto, and the planarization step may be performed by any other suitable method.

[0079] In some embodiments, the vias 130d and the protective layer 130e of the semiconductor die 130-1, the semiconductor die 130-2, and / or the semiconductor die 130-3 may also be planarized during the planarization of the insulating encapsulation 140. In some embodiments, a planarization step may be performed, for example, on the overmolded insulating encapsulation 140 to level the top surface 140a of the insulating encapsulation 140' and the top surface of the via 130d and the top surface of the protective layer 130e of each of the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3.

[0080] In some embodiments, according to Fig.16 Step S40 (eg, involving Fig.17 Steps S41a to S47a and Fig.18 In steps S41a-1 to S41a-5 and step S41a-o), a redistribution circuit structure 150 is formed on the semiconductor die 130 and the insulating package 140'. In some embodiments, Figures 4 to 12 As shown in the figure, the redistribution wiring structure 150 includes an interlayer film 151, a dielectric layer 152 (e.g., dielectric layer 152-1, dielectric layer 152-2 and dielectric layer 152-3), a seed layer 153 (e.g., seed layer 153-1, seed layer 153-2 and seed layer 153-3), a patterned conductive layer 154 (e.g., patterned conductive layer 154-1, patterned conductive layer 154-2 and patterned conductive layer 154-3), an interlayer film 155 (e.g., interlayer film 155-1, interlayer film 155-2 and interlayer film 155-3) and a dielectric layer 156. However, in the present disclosure, the number of layers of the dielectric layer 152, the seed layer 153, the patterned conductive layer 154 and the interlayer film 155 is not limited to Figures 4 to 12 , wherein the number of layers of the dielectric layer 152, the seed layer 153, the patterned conductive layer 154, and the interlayer film 155 may be one or more than one. In some embodiments, the dielectric layer 152, the seed layer 153, the patterned conductive layer 154, and the interlayer film 155 are sandwiched between the interlayer film 151 and the dielectric layer 156 and are stacked in sequence.

[0081] Reference Figure 4 In some embodiments, according to Fig.17 In step S41a, an interlayer film 151a is formed on the via hole 130d of each of the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3 exposed by the protective layer 130e and the insulating encapsulation body 140'. In some embodiments, forming the interlayer film 151a may include (but is not limited to): applying an adhesive precursor ( Fig.18In step S41a-3), a thermal process is performed at a workable temperature of about 30° C. to about 80° C. for 1 to 5 minutes to form a bond between the adhesive precursor and the via 130d of the semiconductor die 130 ( Fig.18 Step S41a-4), and removing the adhesive precursor (not bonded to the via hole 130d of the semiconductor die 130) by cleaning. Fig.18 In some embodiments, before applying the adhesive precursor on the semiconductor die 130, a pre-cleaning step may be performed to remove any undesirable substances or particles remaining on the via hole 130d of the semiconductor die 130 (step S41a-5 shown); thereby forming an interlayer film 151a on the via hole 130d. Fig.18 For example, the pre-cleaning step includes using, for example, CX-100 (e.g., citric acid) or other suitable chemicals (e.g., HCl or H 2 SO 4 ) and other chemical cleaning agents. In some embodiments, after the pre-cleaning step, a rinse step (using deionized (DI) water) may be performed to remove the chemicals ( Fig.18 In addition, after each of the cleaning steps, such as step S41a-2 and / or step S41a-5, a drying step may be optionally performed, for example, by using nitrogen gas at a workable temperature of about 30° C. to about 80° C. for 1 minute. Fig.18 Steps S41a-o) are shown.

[0082] In some embodiments, the binder precursor includes a compound represented by the following chemical formula:

[0083]

[0084] Wherein the nitrogen (N) atoms in the above chemical formula are respectively bonded to the copper (Cu) atoms contained in and / or provided by the via 130d of the semiconductor die 130 to form a three-dimensional network structure including -(Cu-N)-bonds during the thermal process in step S41a-4. The interlayer film 151a is formed on the top surface of the via 130d of the semiconductor die 130 by crosslinking between the N atoms of the adhesive precursor and the Cu atoms of the via 130d of the semiconductor die 130. In some embodiments, as measured along the direction Z, the thickness of the interlayer film 151a is greater than or substantially equal to 50nm and less than or substantially equal to 350nm.

[0085] In the above chemical formula, Ar is an aromatic ring selected from the group consisting of aromatic rings represented by the following chemical formulas (1) to (35):

[0086] Chemical formula (1), Chemical formula (2), Chemical formula (3), Chemical formula (4), Chemical formula (5), Chemical formula (6), Chemical formula (7), Chemical formula (8), Chemical formula (9), Chemical formula (10), Chemical formula (11), Chemical formula (12), Chemical formula (13), Chemical formula (14), Chemical formula (15), Chemical formula (16), Chemical formula (17), Chemical formula (18), Chemical formula (19), Chemical formula (20), Chemical formula (21), Chemical formula (22), Chemical formula (23), Chemical formula (24), Chemical formula (25), Chemical formula (26), Chemical formula (27), Chemical formula (28), Chemical formula (29), Chemical formula (30), Chemical formula (31), Chemical formula (32), Chemical formula (33), Chemical formula (34) and Chemical formula (35).

[0087] In the above chemical formula, R 1represents a hydrogen atom, a substituted alkyl chain or an unsubstituted alkyl chain having a linear structure, a branched structure, a comb-like structure or a star-like structure, or an aromatic ring. 1 One of the two N atoms in the ring of is bonded to a hydrogen atom to form a group -NH, as shown above.

[0088] In the above chemical formula, R 2 To R 3 Each is independently a substituted alkylene or an unsubstituted alkylene, wherein n1 and n2 are each independently an integer ranging from 1 to 30. In one embodiment, R 2 To R 3 In one embodiment, n1 and n2 are the same as or different from each other.

[0089] In the above chemical formula, X and Y are each independently -H, -OH, -SH, -F, -Cl, -Br, -I, carboxyl group, ester group, amine group, quaternary ammonium cation, trimethylsilyl group, triethylsilyl group, sulfo group, carbonyl group, carbonate ester group, amide group. Or epoxy group. In one embodiment, X and Y are the same or different from each other.

[0090] For example, Fig.50 The bonding relationship between the interlayer film 151a and the via 130d of the semiconductor die 130 is partially schematically shown, wherein R is a hydrogen atom, an alkyl chain or an aromatic ring. However, the present disclosure is not limited thereto. In addition, the top layer of Cu atoms (shown in FIG. Fig.50 In the present disclosure, for example, the interlayer film 151a is formed in a layer having a copper complex of an imidazole derivative.

[0091] In some embodiments, applying the adhesive precursor on the semiconductor die 130 may include coating the adhesive precursor mixture on the semiconductor die 130, wherein the adhesive precursor mixture includes 0.01 weight percent (wt%) to 100 wt% of the adhesive precursor. In other words, based on the total amount of the adhesive precursor mixture, the amount of the adhesive precursor is about 0.01 wt% to about 100 wt%, and the amount of the solvent is about 0 wt% to about 99.99 wt%. For example, the aforementioned solvent refers to a solvent that enables the adhesive precursor to be uniformly distributed therein but does not react with it. In some embodiments, the solvent may be deionized water having a pH value greater than 7.

[0092] Reference Figure 5 In some embodiments, according to Fig.17 In step S42a, a dielectric layer 152-1 is formed on the interlayer film 151a. In some embodiments, the dielectric layer 152-1 is formed by (but not limited to) the following method: Figure 4 A dielectric material blanket layer is formed on the structure shown in the figure to completely cover the interlayer film 151a, and the dielectric material blanket layer is patterned to form a dielectric layer 152-1. In some embodiments, during the patterning of the dielectric material blanket layer to form the dielectric layer 152-1, the interlayer film 151a is also patterned, wherein a plurality of openings O1 are formed in the interlayer film 151a and the dielectric material blanket layer to form the interlayer film 151 and the dielectric layer 152-1, respectively. In other words, the vias 130d of the semiconductor die 130 are exposed through the interlayer film 151 and the dielectric layer 152-1 through the openings O1 in a touchable manner.

[0093] In some embodiments, the material of the dielectric layer 152-1 may be polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), nitrides such as silicon nitride, oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), combinations thereof, etc., which can be patterned by photolithography and / or etching processes. In some embodiments, the dielectric layer 152-1 may be formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD) (e.g., plasma-enhanced chemical vapor deposition (PECVD)), etc.

[0094] Reference Figure 6 In some embodiments, according to Fig.17 In step S43a, a seed layer 153a is formed on the dielectric layer 152-1. In some embodiments, the seed layer 153a is formed on the dielectric layer 152-1 and extends into the opening O1 formed in the dielectric layer 152-1 and the interlayer film 151 to physically contact the via 130d of the semiconductor die 130 exposed through the opening O1, the portion of the dielectric layer 152-1, and the portion of the interlayer film 151 (exposed through the opening O1). In other words, the seed layer 153a penetrates the dielectric layer 152-1 and the interlayer film 151, and the sidewall of the opening O1 is completely covered by the seed layer 153a.

[0095] In some embodiments, the seed layer 153a is formed on the carrier 112 in the form of a blanket layer made of a metal or metal alloy material, but the present disclosure is not limited thereto. In some embodiments, the seed layer 153a is referred to as a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer 153a includes titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, and the like. For example, the seed layer 153a may include a titanium layer and a copper layer located on the titanium layer. The seed layer 153a may be formed using, for example, sputtering, physical vapor deposition (PVD), and the like. In some embodiments, the seed layer 153a may be conformally formed on the dielectric layer 152-1 by sputtering, and contact the dielectric layer 152-1, the interlayer film 151, and the via 130d exposed through the opening O1.

[0096] Reference Figure 7 In some embodiments, according to Fig.17 In step S44a, a patterned conductive layer 154-1 is formed on the seed layer 153a. In some embodiments, the patterned conductive layer 154-1 may be formed by (but not limited to) the following methods: Figure 6 A blanket layer of conductive material is formed over the structure shown in the figure to completely cover the seed crystal 153a, and the blanket layer of conductive material is patterned to form a patterned conductive layer 154-1.

[0097] In one embodiment, the patterned conductive layer 154-1 may be made of a conductive material (e.g., copper, copper alloy, aluminum, aluminum alloy, or a combination thereof) formed by electroplating or deposition and patterned using a photolithography process and an etching process. In some embodiments, the patterned conductive layer 154-1 may be a patterned copper layer or other suitable patterned metal layer. Throughout this specification, the term "copper" is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing small amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

[0098] Reference Figure 8 In some embodiments, according to Fig.17In step S45a, the seed layer 153a is patterned to form a seed layer 153-1. In some embodiments, the seed layer 153a is patterned using the patterned conductive layer 154-1 as an etching mask to form the seed layer 153-1. For example, the etching process may be a dry etching process, a wet etching process, or a combination thereof; the present disclosure is not limited thereto. In other words, for example, in a vertical projection on the insulating encapsulation body 140' (for example, a vertical projection along the direction Z), the patterned conductive layer 154-1 completely overlaps with the seed layer 153-1. In some embodiments, as Figure 8 As shown in FIG. 1 , the patterned conductive layer 154 - 1 is electrically connected to the semiconductor die 130 by physically connecting the seed layer 153 - 1 and the via 130 d .

[0099] Reference Fig. 9 In some embodiments, according to Fig.17 In step S46a, an interlayer film 155a is formed on the patterned conductive layer 154-1 and the seed layer 153-1. The formation and use of the interlayer film 155a are as follows: Fig.18 The adhesive precursor described in the method is formed Figure 4 The process of forming the interlayer film 151a described in the above is the same or similar, and therefore, for the sake of brevity, it will not be described in detail herein. Fig. 9 As shown in FIG. 1 , for example, the patterned conductive layer 154 - 1 is completely wrapped by the interlayer film 155 a and the seed layer 153 - 1 , wherein the interlayer film 155 a physically contacts both the seed layer 153 - 1 and the patterned conductive layer 154 - 1 .

[0100] Reference Fig.10 In some embodiments, according to Fig.17 In step S47a, a dielectric layer 152-2 is formed. In some embodiments, the dielectric layer 152-2 is formed by (but not limited to) the following methods: Fig. 9 A dielectric material blanket is formed over the structure shown in the figure to completely cover the interlayer film 155a, and the dielectric material blanket is patterned to form a dielectric layer 152-2. In some embodiments, during the patterning of the dielectric material blanket to form the dielectric layer 152-2, the interlayer film 155a is also patterned, wherein a plurality of openings O2 are formed in the interlayer film 155a and the dielectric material blanket to form the interlayer film 155-1 and the dielectric layer 152-2, respectively. In other words, the openings O2 penetrate the interlayer film 155-1 and the dielectric layer 152-2, and thus a portion of the patterned conductive layer 154-1 is exposed through the interlayer film 155-1 and the dielectric layer 152-2 through the openings O2 in a touchable manner.

[0101] like Fig.10As shown in FIG. 1 , an interlayer film 151 is interposed between the via 130d and the dielectric layer 152-1, wherein the interlayer film 151 serves as a copper diffusion barrier between the conductive layer and the dielectric layer (e.g., the via 130d and the dielectric layer 152-1), and since the diffusion rate of copper atoms from the conductive layer (e.g., the copper layer) to the dielectric layer is reduced due to the interlayer film 151, the copper diffusion phenomenon is greatly suppressed. And therefore, the gap generated between the conductive layer and the dielectric layer due to the diffusion of copper atoms (e.g., the diffusion of copper atoms from the conductive layer to the dielectric layer) is significantly reduced. Therefore, due to the presence of the interlayer film 151, the bonding strength between the via 130d and the dielectric layer 152-1 is enhanced, and the delamination between the via 130d and the dielectric layer 152-1 is suppressed.

[0102] In some embodiments, Fig.10 As shown in FIG. 1 , the interlayer film 155-1 is sandwiched between the patterned conductive layer 154-1 and the dielectric layer 152-2. Due to the interlayer film 155-1, the adhesive strength between the patterned conductive layer 154-1 and the dielectric layer 152-2 and between the seed layer 153-1 and the dielectric layer 152-2 is enhanced, and the delamination between the patterned conductive layer 154-1 and the dielectric layer 152-2 and between the seed layer 153-1 and the dielectric layer 152-2 is suppressed.

[0103] In one embodiment, the material of dielectric layer 152-2 may be the same as the material of dielectric layer 152-1. In an alternative embodiment, the material of dielectric layer 152-2 may be different from the material of dielectric layer 152-1. The present disclosure is not limited in this regard.

[0104] Reference Fig.11 In some embodiments, Fig.10 The seed layer 153-2, the patterned conductive layer 154-2, the interlayer film 155-2 and the dielectric layer 152-3 are sequentially formed on the structure shown above. Figures 6 to 8 The process and materials for forming the seed layer 153-1 are the same or similar to those described in the above, and the process and materials for forming the patterned conductive layer 154-2 are the same or similar to those described in the above. Figure 7 The process and materials for forming the patterned conductive layer 154-1 are the same or similar to those described in the above, and the formation and materials of the interlayer film 155-2 are the same as those described in the above. Fig. 9 and Fig.10 The process and materials for forming the interlayer film 155-1 are the same or similar to those described in the above, and the formation and materials of the dielectric layer 152-3 are the same as those described in the above. Fig.10 The processes and materials for forming the dielectric layer 152 - 2 are the same or similar as those described in , and therefore are not described in detail herein.

[0105] In some embodiments, the seed layer 153-2 is formed on the dielectric layer 152-2 and extends into the opening O2 formed in the interlayer film 155-1 and the dielectric layer 152-2, so as to physically contact the patterned conductive layer 154-1 exposed through the opening O2 in addition to the portion of the interlayer film 155-1 and the portion of the dielectric layer 152-2 (exposed through the opening O2). In other words, the seed layer 153-2 penetrates the dielectric layer 152-2 and the interlayer film 155-1, and the sidewall of the opening O2 is completely covered by the seed layer 153-2. In some embodiments, the patterned conductive layer 154-2 is formed on the seed layer 153-2 (e.g., physically contacts the seed layer 153-2), wherein in the vertical projection along the direction Z on the insulating encapsulation body 140', the projection area of ​​the patterned conductive layer 154-2 overlaps with the projection area of ​​the seed layer 153-2. For example, as Fig.11 As shown in FIG. 1 , the patterned conductive layer 154 - 2 is electrically connected to the patterned conductive layer 154 - 1 through the seed layer 153 - 2 .

[0106] In some embodiments, an interlayer film 155-2 and a dielectric layer 152-3 are formed on the patterned conductive layer 154-2, wherein the interlayer film 155-2 is sandwiched between the patterned conductive layer 154-2 and the dielectric layer 152-3, and between the seed layer 153-2 and the dielectric layer 152-3. Due to the interlayer film 155-2, the adhesive strength between the patterned conductive layer 154-2 and the dielectric layer 152-3 and between the seed layer 153-2 and the dielectric layer 152-3 is enhanced, and delamination between the patterned conductive layer 154-2 and the dielectric layer 152-3 and between the seed layer 153-2 and the dielectric layer 152-3 is suppressed.

[0107] Reference Fig.12 In some embodiments, Fig.11 The seed layer 153-3, the patterned conductive layer 154-3, the interlayer film 155-3 and the dielectric layer 156 are sequentially formed on the structure shown above. Figures 6 to 8 The process and materials for forming the seed layer 153-1 are the same or similar to those described in the above, and the formation / material of the patterned conductive layer 154-3 is the same as those described in the above. Figure 7 The process and materials for forming the patterned conductive layer 154-1 are the same or similar to those described in the above, and the formation / material of the interlayer film 155-3 is the same as those described in the above. Fig. 9 and Fig.10 The process and materials for forming the interlayer film 155-1 are the same or similar to those described in the above, and the formation / material of the dielectric layer 156 is the same as those described in the above. Fig.10 The processes and materials for forming the dielectric layer 152 - 2 are the same or similar as those described in , and therefore are not described in detail herein.

[0108] In some embodiments, the seed layer 153-3 is formed on the dielectric layer 152-3 and extends into the opening O3 formed in the interlayer film 155-2 and the dielectric layer 152-3, so as to physically contact the patterned conductive layer 154-2 exposed through the opening O3 in addition to the portion of the interlayer film 155-2 and the portion of the dielectric layer 152-3 (exposed through the opening O3). In other words, the seed layer 153-3 penetrates the dielectric layer 152-3 and the interlayer film 155-2, and the sidewall of the opening O3 is completely covered by the seed layer 153-3. In some embodiments, the patterned conductive layer 154-3 is formed on the seed layer 153-3 (e.g., physically contacts the seed layer 153-3), wherein in the vertical projection along the direction Z on the insulating encapsulation body 140', the projection area of ​​the patterned conductive layer 154-3 overlaps with the projection area of ​​the seed layer 153-3. For example, as Fig.12 As shown in FIG. 1 , the patterned conductive layer 154 - 3 is electrically connected to the patterned conductive layer 154 - 2 through the seed layer 153 - 3 .

[0109] In some embodiments, an interlayer film 155-3 and a dielectric layer 156 are formed on the patterned conductive layer 154-3, wherein the interlayer film 155-3 is interposed between the patterned conductive layer 154-3 and the dielectric layer 156, and between the seed layer 153-3 and the dielectric layer 156. Due to the interlayer film 155-3, the adhesive strength between the patterned conductive layer 154-3 and the dielectric layer 156 and between the seed layer 153-3 and the dielectric layer 156 is enhanced, and delamination between the patterned conductive layer 154-3 and the dielectric layer 156 and between the seed layer 153-3 and the dielectric layer 156 is suppressed.

[0110] In some embodiments, Fig.12 As shown in FIG. 1 , a portion of the patterned conductive layer 154 - 3 is exposed through a plurality of openings O4 formed in the dielectric layer 156 and the interlayer film 155 - 3 to be electrically connected to a connector formed subsequently. At this point, the redistribution wiring structure 150 of the package structure P1 is completed.

[0111] Refer to Fig.10 , Fig.11 and Fig.12In some embodiments, a redistribution wiring structure 150 is formed on the semiconductor die 130 and the insulating encapsulation body 140', wherein the redistribution wiring structure 150 is electrically connected to the semiconductor die 130 (e.g., semiconductor die 130-1, 130-2, 130-3). For example, the redistribution wiring structure 150 is formed on the top surface of the semiconductor die 130 (e.g., the top surface of the via 130d of the semiconductor die 130 and the top surface of the protective layer 130e) and the top surface 140a of the insulating encapsulation body 140'. In some embodiments, the redistribution wiring structure 150 is electrically connected to the semiconductor die 130 through the via 130d and the pad 130b. In some embodiments, the redistribution wiring structure 150 is referred to as a front-side redistribution layer of the semiconductor die 130 for providing a wiring function. In some embodiments, the semiconductor die 130 is located between the redistribution wiring structure 150 and the buffer layer 116, and the insulating encapsulation body 140' is located between the redistribution wiring structure 150 and the buffer layer 116. Fig.12 As shown in FIG. 1 , semiconductor dies 130 - 1 , 130 - 2 , and 130 - 3 are electrically connected to each other, for example, via a redistribution wiring structure 150 .

[0112] In this disclosure, Fig.11 The layers formed in the embodiment (eg, the seed layer 153-2, the patterned conductive layer 154-2, the interlayer film 155-2 and the dielectric layer 152-3) and the Fig.12 The layers formed in the above-described structure (eg, seed layer 153-3, patterned conductive layer 154-3, interlayer film 155-3, and dielectric layer 156) may be individually referred to as a first build-up layer of redistribution wiring structure 150. Fig.12 The illustrated redistribution wiring structure 150 includes two first constituent layers; however, the present disclosure is not limited thereto. The number of first constituent layers included in the redistribution wiring structure 150 is not limited in the present disclosure. In one embodiment, the number of first constituent layers included in the redistribution wiring structure 150 may be zero. For example, the first constituent layers in the redistribution wiring structure 150 may be optionally omitted. Fig.11 The first constituent layer formed in Fig.12 In alternative embodiments, the number of first constituent layers included in redistribution wiring structure 150 may be one or more than one.

[0113] Reference Fig.13 In some embodiments, according to Fig.16 In step S50, a plurality of seed layer patterns 160 and a plurality of conductive elements 170 are formed on the redistribution wiring structure 150. In some embodiments, Fig.13As shown in , each seed layer pattern 160 is located between a corresponding one of the conductive elements 170 and the dielectric layer 156 of the redistribution wiring structure 150. Due to the seed layer pattern 160, the bonding strength between the conductive element 170 and the dielectric layer 156 is enhanced. In some embodiments, the seed layer pattern 160 is directly located on the portion of the patterned conductive layer 154-3 exposed by the opening O4 formed in the dielectric layer 156 and the interlayer film 155-3. Fig.13 As shown in , in some embodiments, the seed layer pattern 160 is electrically connected to the redistribution wiring structure 150 , and the conductive element 170 is electrically connected to the redistribution wiring structure 150 through the seed layer pattern 160 .

[0114] In some embodiments, the conductive elements 170 are electrically connected to the semiconductor die 130 through the redistribution wiring structure 150 and the seed layer pattern 160. For example, some of the conductive elements 170 are electrically connected to the semiconductor die 130-1 through the redistribution wiring structure 150 and the corresponding seed layer pattern in the seed layer pattern 160. For example, some of the conductive elements 170 are electrically connected to the semiconductor die 130-2 through the redistribution wiring structure 150 and the corresponding seed layer pattern in the seed layer pattern 160. For example, some of the conductive elements 170 are electrically connected to the semiconductor die 130-3 through the redistribution wiring structure 150 and the corresponding seed layer pattern in the seed layer pattern 160.

[0115] In some embodiments, the seed layer pattern 160 is formed by (but not limited to) the following methods: forming a blanket layer of seed layer material (not shown) on the dielectric layer 156; forming a conductive element 170 on the blanket layer of seed layer material; and patterning the blanket layer of seed layer material using the conductive element 170 as a mask. In some embodiments, the blanket layer of seed layer material is formed on the dielectric layer 156 and extends into the opening O4 formed in the dielectric layer 156 and the interlayer film 155-3 to physically and electrically contact the patterned conductive layer 154-3 exposed through the opening O4, to physically contact a portion of the dielectric layer 156 and a portion of the interlayer film 155-3 (exposed through the opening O4). In other words, the blanket layer of seed layer material penetrates the dielectric layer 156 and the interlayer film 155-3, and the sidewalls of the opening O4 are completely covered by the blanket layer of seed layer material. The formation and material of the blanket layer of seed layer material are the same or similar to the formation and material of the seed layer 153a, and therefore will not be described in detail herein.

[0116] In some embodiments, the conductive element 170 may be formed by: forming a patterned photoresist layer (not shown) having a plurality of openings exposing portions of the seed layer 160a by photolithography; and immersing the entire structure including the patterned photoresist layer formed thereon into a plating solution to plate the conductive element 170 on the blanket layer of seed layer material, the conductive element 170 corresponding in position to the portion of the blanket layer of seed layer material exposed by the opening formed in the patterned photoresist layer. In one embodiment, the patterned photoresist layer may be formed by a coating process and a photolithography process, etc. In some embodiments, the material of the patterned photoresist layer includes, for example, a positive resist material or a negative resist material suitable for a patterning process such as a photolithography process using a mask or a photolithography process without a mask (e.g., electron-beam (e-beam) writing or ion beam writing). Due to the patterned photoresist layer, the size and number of the conductive element 170 may be easily modified by adjusting the size and number of the openings in the patterned photoresist layer. As Fig.13 As shown in FIG. 1 , the conductive element 170 includes, for example, a copper pillar, a copper via, etc.; the present disclosure is not limited thereto.

[0117] After forming the conductive element 170, the patterned photoresist layer is removed to expose the blanket layer of seed layer material not covered by the conductive element 170. In one embodiment, the patterned photoresist layer is removed by an acceptable ashing process and / or photoresist stripping process such as using oxygen plasma, but the present disclosure is not limited thereto.

[0118] In some embodiments, the seed layer material blanket is patterned using the conductive element 170 as an etching mask to form the seed layer pattern 160. For example, the etching process can be a dry etching process, a wet etching process, or a combination thereof; the present disclosure is not limited thereto. In other words, the seed layer material blanket that is not covered by the conductive element 170 is removed to form the seed layer pattern 160. In some embodiments, as shown in FIG. Fig.13 As shown in FIG. 1 , a sidewall of the seed layer pattern 160 is aligned with a sidewall of a corresponding one of the conductive elements 170 .

[0119] Reference Fig.14 In some embodiments, according to Fig.16 Step S60 is shown, Fig.13The entire structure shown in FIG. 1 is flipped (turned upside down) together with the carrier 112, wherein the conductive element 170 is placed on the holding device HD, and then the carrier 112 is peeled off from the buffer layer 116. In some embodiments, the holding device HD may be a tape, a carrier film, or a suction pad. The present disclosure is not limited thereto.

[0120] In some embodiments, the buffer layer 116 is easily separated from the carrier 112 due to the peeling layer 114. In some embodiments, the carrier 112 is detached from the buffer layer 116 by a peeling process, and the carrier 112 and the peeling layer 114 are removed. Fig.14 As shown in FIG. 1 , the buffer layer 116 is exposed. In one embodiment, the debonding process is a laser debonding process. During the debonding step, before the carrier 112 and the debonding layer 114 are debonded, a holding device HD is used to fix the package structure P1 .

[0121] Reference Fig.15 In some embodiments, the conductive element 170 is released from the holding device HD to form the package structure P1. In some embodiments, before the conductive element 170 is released from the holding device HD, a cutting (singulation) process is performed to cut the multiple package structures P1 connected therebetween into individual and separated package structures P1. In one embodiment, the cutting (singulation) process is a wafer cutting process including mechanical blade sawing or laser cutting. The present disclosure is not limited to this. At this point, the manufacture of the package structure P1 is completed.

[0122] However, the present disclosure is not limited thereto. In alternative embodiments, the conductive element 170 may include a solder ball or a ball grid array (BGA) ball, see Fig.19 In other alternative embodiments, the package structure may further include a plurality of conductive pillars CP, see Fig. 20 The package structure P3 is shown in FIG.

[0123] Fig.19 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure. Fig.15 and Fig.19 , Fig.15 The package structure P1 and Fig.19; thus, elements similar to or substantially identical to the above elements will use the same reference numbers, and certain details or descriptions of the same elements (e.g., formation and materials) and the relationships of the elements (e.g., relative positioning configuration and electrical connections) will not be repeated herein. Fig.19 In the embodiment where the conductive element 170 shown in the figure is a solder ball or a BGA ball, the seed layer pattern 160 is replaced by an under-ball metallurgy (UBM) pattern u1 to prevent the solder material from diffusing from the conductive element 170 to the redistribution wiring structure 150, thereby ensuring the performance of the package structure P2. In some embodiments, the material of the UBM pattern u1 may include copper, nickel, titanium, tungsten or alloys thereof, and may be formed in a multi-layer manner (for example, having different materials in any two adjacent layers in the UBM pattern u1) by, for example, an electroplating process. The number of UBM patterns u1 is not limited in the present disclosure.

[0124] Fig. 20 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure. Fig.19 and Fig. 20 , Fig.19 The package structure P2 shown in FIG. Fig. 20 ; thus, elements similar to or substantially identical to the above elements will use the same reference numerals, and certain details or descriptions of the same elements (e.g., formation and materials) and the relationships of the elements (e.g., relative positioning configuration and electrical connections) will not be repeated herein. Fig. 20 Such an embodiment including conductive pillars CP is shown in FIG, wherein the conductive pillars CP are arranged beside the semiconductor die 130 along the direction X and embedded in the insulating encapsulation 140 ′. In some embodiments, the conductive pillars CP may be through-holes, such as integrated fan-out (InFO) through-holes. For simplicity, for illustrative purposes, in FIG. Fig. 20 Only two conductive pillars CP are shown in FIG. 1 , however, it should be noted that the number of conductive pillars CP may be less than two or more than two; the present disclosure is not limited thereto. The number of conductive pillars CP to be formed may be selected based on requirements.

[0125] In some embodiments, both ends of each of the conductive pillars CP are exposed through the insulating encapsulation 140'. For example, the conductive pillars CP are sandwiched between the buffer layer 116 and the redistribution wiring structure 150, wherein the first end of each conductive pillar CP is physically connected to the redistribution wiring structure 150, and the conductive pillars CP are electrically connected to the semiconductor die 130 through the redistribution wiring structure 150. For example, the conductive pillars CP are formed on the buffer layer 116 by photolithography, plating, photoresist stripping process, or any other suitable method. In one embodiment, the conductive pillars CP may be formed by (but not limited to) the following manner: forming a mask pattern (not shown) covering the buffer layer 116, the mask pattern having a plurality of openings exposing a plurality of portions of the buffer layer 116; forming a metal material filling the plurality of openings to form a plurality of conductive pillars CP by electroplating or deposition; and then removing the mask pattern. For example, the material of the conductive pillars CP may include a metal material, such as copper or a copper alloy. However, the present disclosure is not limited thereto.

[0126] Continue to refer to Fig. 20 , in some embodiments, a plurality of openings O5 are formed in the buffer layer 116 to expose the second end of each of the conductive pillars CP. The number of openings O5 is not limited in the present disclosure and may be specified based on requirements and design layout. In certain embodiments, a plurality of conductive elements 190 are respectively formed on the second end of each of the conductive pillars CP exposed by the openings O5, and a plurality of UBM patterns u2 are respectively formed between a conductive pillar in the conductive pillars CP and a corresponding one of the conductive elements 190. However, the present disclosure is not limited thereto, and in alternative embodiments, the UBM pattern u2 may be omitted based on the design layout and requirements. The formation and material of the conductive element 190 are the same or similar to the formation and material of the conductive element 180, and the formation and material of the UBM pattern u2 are the same or similar to the formation and material of the UBM pattern u1, and therefore will not be described in detail herein. As Fig. 20 As shown in FIG. 1 , the conductive element 190 is electrically connected to the semiconductor die 130 through the UBM pattern u2, the conductive pillar CP and the redistribution wiring structure 150. For example, after the conductive element 190 is disposed on the conductive pillar CP, a package structure P3 with a dual-side terminal is manufactured.

[0127] In some alternative embodiments, in addition to Fig.13 The conductive element 170 and / or Figures 19 to 20In addition to the conductive element 180 in the redistribution structure 150, additional semiconductor elements (not shown) may be disposed on the redistribution structure 150 through the seed layer pattern 160 and / or the UBM patterns u1, u2 to be electrically connected to at least one of the semiconductor dies 130. In some embodiments, the additional semiconductor elements may include passive components or active components. The number of additional semiconductor elements is not limited in the present disclosure and may be specified based on requirements and design layout.

[0128] Figures 21 to 32 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig.33 1 is a flow chart illustrating a method of manufacturing a redistribution wiring structure / layer of a package structure according to some embodiments of the present disclosure. Elements similar or substantially the same as previously described elements will use the same reference numbers, and certain details or descriptions of the same elements will not be repeated herein. Fig.15 and Fig.32 , Fig.32 The package structure P4 shown in FIG. Fig.15 The difference is that, in the package structure P4, the redistribution circuit structure 150 is replaced by the redistribution circuit structure 250.

[0129] In some embodiments, using Figure 21 to Figure 29 The process described in the above embodiment forms a redistribution wiring structure 250 on the semiconductor die 130 and the insulating package 140'. In some embodiments, as Figure 21 to Figure 29 As shown in the figure, the redistribution wiring structure 250 includes a dielectric layer 252 (for example, dielectric layer 252-1, dielectric layer 252-2, dielectric layer 252-3 and dielectric layer 252-4), a seed layer 253 (for example, seed layer 253-1, seed layer 253-2, seed layer 253-3 and seed layer 253-4), a patterned conductive layer 254 (for example, patterned conductive layer 254-1, patterned conductive layer 254-2a, patterned conductive layer 254-2b, patterned conductive layer 254-3 and patterned conductive layer 254-4) and an interlayer film 255 (for example, interlayer film 255-1, interlayer film 255-2 and interlayer film 255-3 and interlayer film 255-4). However, in the present disclosure, the number of dielectric layers 252, seed layers 253, patterned conductive layers 254, and interlayer films 255 is not limited to Figure 21 to Figure 29 , wherein the number of layers of the dielectric layer 252, the seed layer 253, the patterned conductive layer 254 and the interlayer film 255 can be one or more than one. In some embodiments, the dielectric layer 252, the seed layer 253, the patterned conductive layer 254 and the interlayer film 255 are formed on the insulating encapsulation body 140' and are stacked in sequence.

[0130] Reference Fig.21In some embodiments, Figure 3 After the process described in Fig.33 In step S41b shown, a seed layer SL1 is formed on the semiconductor die 130 and the insulating encapsulation body 140'. For example, the seed layer SL1 is formed on the semiconductor die 130 and the insulating encapsulation body 140' in the form of a blanket layer made of a metal or metal alloy material, but the present disclosure is not limited to this. In some embodiments, the seed layer SL1 is referred to as a metal layer, and the metal layer may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer SL1 may include titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, and the like. For example, the seed layer SL1 may include a titanium layer and a copper layer located above the titanium layer. The seed layer SL1 may be formed, for example, by sputtering, PVD, and the like. In some embodiments, the seed layer SL1 may be conformally formed on the semiconductor die 130 and the insulating encapsulation body 140' by sputtering. As Fig.21 As shown in FIG. 1 , in some embodiments, the seed layer SL1 physically contacts the via 130 d of the semiconductor die 130 and the top surface 140 a of the insulating encapsulation 140 ′.

[0131] A patterned photoresist layer PR1 is formed on the seed layer SL1, wherein the patterned photoresist layer PR1 includes, for example, at least one opening O6. Fig.21 As shown in FIG. 1 , a plurality of openings O6 are formed in the patterned photoresist layer PR1. In one embodiment, the patterned photoresist layer PR1 may be formed by a coating process and a photolithography process. The number of openings O6 may correspond to the number of conductive structures (such as conductive pillars or vias) to be formed subsequently. However, the present disclosure is not limited thereto. Fig.21 As shown in FIG. 1 , portions of the seed layer SL1 are exposed through openings O6 formed in the patterned photoresist layer PR1. In some embodiments, the material of the patterned photoresist layer PR1 includes, for example, a positive resist material or a negative resist material suitable for a patterning process such as a photolithography process using a mask or a photolithography process without a mask (e.g., electron beam (e-beam) writing or ion beam writing).

[0132] Reference Fig. 22 In some embodiments, according to Fig.33In step S42b shown, a patterned conductive layer 254-1 is formed in each of the openings O6. In some embodiments, the patterned conductive layer 254-1 is formed by a plating process or any other suitable method, and the plating process may include electroplating or electroless plating. In one embodiment, the patterned conductive layer 254-1 may be formed by forming a metal material filling the opening O6 by electroplating or deposition to form the patterned conductive layer 254-1. In one embodiment, the material of the patterned conductive layer 254-1 may include a metal material, such as copper or a copper alloy. The number of patterned conductive layers 254-1 may be selected based on demand and may be adjusted by changing the number of openings O6. In some embodiments, the material of the patterned conductive layer 254-1 may be the same as the material of the patterned conductive layer 154-1. In other embodiments, the material of the patterned conductive layer 254-1 may be different from the material of the patterned conductive layer 154-1.

[0133] Continue to refer to Fig. 22 For example, after forming the patterned conductive layer 254-1, the patterned photoresist layer PR1 is removed. In one embodiment, the patterned photoresist layer PR1 is removed by an acceptable ashing process and / or a photoresist stripping process, such as using oxygen plasma. The present disclosure is not limited thereto.

[0134] Reference Fig.23 In some embodiments, according to Fig.33 In step S43b, the seed layer SL1 is patterned to form the seed layer 253-1. In some embodiments, the portion of the seed layer SL1 not covered by the patterned conductive layer 254-1 (shown in FIG. 2 ) is removed. Fig. 22 In some embodiments, the seed layer SL1 is etched using the patterned conductive layer 254-1 as an etching mask to form the seed layer 253-1. For example, the etching process may include a dry etching process or a wet etching process. Fig.23 As shown in , the seed layer 253-1 includes, for example, one or more conductive segments that are mechanically (physically) and electrically isolated from each other. Fig.23 As shown in , the seed layer 253-1 is mechanically (physically) connected to and electrically connected to a corresponding one of the patterned conductive layers 254-1. In some embodiments, the sidewalls of the seed layer 253-1 are aligned with the sidewalls of the corresponding one of the patterned conductive layers 254-1. Fig.23As shown in , patterned conductive layer 254-1 is electrically connected to semiconductor die 130 through seed layer 253-1. In some embodiments, the material of seed layer 253-1 may be the same as the material of seed layer 153-1. In other embodiments, the material of seed layer 253-1 may be different from the material of seed layer 153-1.

[0135] Reference Fig.24 In some embodiments, according to Fig.33 In step S44b, an interlayer film 255a is formed to cover the seed layer 153-1 and the patterned conductive layer 254-1. The formation and material of the interlayer film 255a are similar to those in Figure 4 Based on Fig.18 The process of forming the interlayer film 151a described in the method shown is the same or similar, and therefore will not be described in detail herein. Fig.24 As shown in FIG. 2 , for example, the patterned conductive layer 254 - 1 is wrapped together with the interlayer film 255 a and the seed layer 253 - 1 .

[0136] Reference Fig.25 In some embodiments, according to Fig.33 In step S45b, a dielectric layer 252a is formed on the interlayer film 255a. The dielectric layer 252a is formed by (but not limited to) the following method: Fig.24 A blanket layer of dielectric material is formed on the structure shown in the figure to completely cover the interlayer film 155a and the semiconductor die 130 and the insulating encapsulation body 140' exposed by the interlayer film 155a. In some embodiments, the material of the dielectric layer 252a can be polyimide, PBO, BCB, nitrides such as silicon nitride, oxides such as silicon oxide, PSG, BSG, BPSG, combinations thereof, etc. In some embodiments, the dielectric layer 252a can be formed by suitable manufacturing techniques such as spin coating, CVD (e.g., PECVD), etc.

[0137] Reference Fig.26 In some embodiments, according to Fig.33 In step S46b, a planarization step is performed on dielectric layer 252a to form dielectric layer 252-1. For example, dielectric layer 252a may be planarized by mechanical grinding or CMP. In some embodiments, the material of dielectric layer 252a may be the same as the material of dielectric layer 152-1. In other embodiments, the material of dielectric layer 252a may be different from the material of dielectric layer 152-1.

[0138] During the planarization of the dielectric layer 252a, the interlayer film 255a is also planarized to form the interlayer film 255-1 exposing the top surface S254-1 of the patterned conductive layer 254-1. Fig.26As shown in , for example, the sidewalls of the patterned conductive layer 254-1 and the sidewalls of the seed layer 253-1 are wrapped by the interlayer film 255-1. In some embodiments, the material of the interlayer film 255-1 may be the same as the material of the interlayer film 155-1. In other embodiments, the material of the interlayer film 255-1 may be different from the material of the interlayer film 155-1. In some embodiments, for example, a planarization step may be performed on the dielectric layer 252a to flatten the top surface S252-1 of the dielectric layer 252-1, the top surface S254-1 of the patterned conductive layer 254-1, and the top surface S255-1 of the interlayer film 255-1. For example, the top surface S254-1 of the patterned conductive layer 254-1 and the top surface S255-1 of the interlayer film 255-1 are exposed in a touchable manner through the top surface S252-1 of the dielectric layer 252-1.

[0139] During the planarization of the dielectric layer 252a and the interlayer film 255a, the patterned conductive layer 254-1 may also be planarized. After the planarization step, a cleaning step may be optionally performed, for example, to clean and remove residues resulting from the planarization step. However, the present disclosure is not limited thereto, and the planarization step may be performed by any other suitable method. Due to the interlayer film 255-1, the adhesion strength between the patterned conductive layer 254-1 and the dielectric layer 252-1 and between the seed layer 253-1 and the dielectric layer 252-1 is enhanced, and delamination between the patterned conductive layer 254-1 and the dielectric layer 252-1 and between the seed layer 253-1 and the dielectric layer 252-1 is suppressed. In the present disclosure, Figure 21 to Figure 26 The layers formed in the above-described structure (eg, the seed layer 253 - 1 , the patterned conductive layer 254 - 1 , the interlayer film 255 - 1 , and the dielectric layer 252 - 1 ) may be referred to as a second build-up layer of the redistribution wiring structure 250 .

[0140] Reference Fig. 27 In some embodiments, a seed layer 253-2, a patterned conductive layer 254-2a, a patterned conductive layer 254-2b, an interlayer film 255-2, and a dielectric layer 252-2 are sequentially formed on the dielectric layer 252-1. Fig. 27The layers formed in the patterned conductive layer 250 (e.g., seed layer 253-2, patterned conductive layer 254-2a / 254-2b, interlayer film 255-2, and dielectric layer 252-2) may be referred to as a layer of the third build-up layer of the redistribution wiring structure 250. Note that in the present disclosure, the plating process of the patterned conductive layer 254-2b and the plating process of the patterned conductive layer 254-2a share the same seed layer (e.g., seed layer 253-2), wherein different patterned photoresist layers having openings of different sizes are used in the formation of the patterned conductive layers 254-2a and 254-2b. That is, the seed layer 253-2 may be used as a seed layer for plating both the patterned conductive layers 254-2a and 254-2b. The materials and formation of the above patterned photoresist layers having openings of different sizes are the same or similar to the materials and formation of the patterned photoresist layer PR1, and therefore are not described in detail herein.

[0141] In some embodiments, the seed layer 253-2 is directly located on the dielectric layer 252-1, the patterned conductive layer 254-1, and the interlayer film 255-1. For example, the seed layer 253-2 is electrically connected to the patterned conductive layer 254-1. In some embodiments, the patterned conductive layer 254-2a is located on the seed layer 253-2 and is electrically connected to the seed layer 253-2. In some embodiments, the sidewall of the seed layer 253-2 is aligned with the sidewall of a corresponding one of the patterned conductive layers 254-2a. Fig. 27 As shown in FIG. 2 , the seed layer 253 - 2 is interposed between the patterned conductive layer 254 - 2 a and the patterned conductive layer 254 - 1 , and the patterned conductive layer 254 - 2 a is electrically connected to the patterned conductive layer 254 - 1 through the seed layer 253 - 2 .

[0142] In some embodiments, the patterned conductive layer 254-2b is formed on the patterned conductive layer 254-2a. Fig. 27 As shown in , for example, the patterned conductive layer 254-2b is directly located on the patterned conductive layer 254-2a and is electrically connected to the patterned conductive layer 254-2a. In some embodiments, the patterned conductive layer 254-2a is sandwiched between the patterned conductive layer 254-2b and the seed layer 253-2, and the patterned conductive layer 254-2b is electrically connected to the seed layer 253-2 through the patterned conductive layer 254-2a.

[0143] The formation and material of the seed layer 253-2 are the same or similar to those of the seed layer 253-1, and thus will not be described in detail herein. The formation and material of each of the patterned conductive layers 254-2a / 254-2b are the same or similar to those of the patterned conductive layer 254-1, and thus will not be described in detail herein.

[0144] In some embodiments, the interlayer film 255-2 covers at least a portion of the patterned conductive layer 254-2b, the patterned conductive layer 254-2a, and the seed layer 253-2. Fig. 27 As shown in, for example, the sidewalls of the patterned conductive layers 254-2a, 254-2b and the sidewalls of the seed layer 253-2 are wrapped by the interlayer film 255-2, wherein the top surface S254-2b of the patterned conductive layer 254-2b is exposed by the top surface S255-2 of the interlayer film 255-2. The formation and material of the interlayer film 255-2 are the same or similar to the formation and material of the interlayer film 255-1, and therefore will not be described in detail herein.

[0145] In some embodiments, the dielectric layer 252-2 is located on the patterned conductive layer 254-2b, the patterned conductive layer 254-2a, the seed layer 253-2, the interlayer film 255-2 and the dielectric layer 252-1. Fig. 27 As shown in , the top surface S255-2 of the interlayer film 255-2 and the top surface S254-2b of the patterned conductive layer 254-2b are exposed in a touchable manner through the top surface S252-2 of the dielectric layer 252-2. The formation and material of the dielectric layer 252-2 are the same or similar to the formation and material of the dielectric layer 252-1, and therefore are not described in detail herein. Due to the interlayer film 255-2, the bonding strength between the patterned conductive layer 254-2 and the dielectric layer 252-2 and between the seed layer 253-2 and the dielectric layer 252-2 is enhanced, and the delamination between the patterned conductive layer 254-2 and the dielectric layer 252-2 and between the seed layer 253-2 and the dielectric layer 252-2 is suppressed.

[0146] Reference Fig.28 In some embodiments, a seed layer 253-3, a patterned conductive layer 254-3, an interlayer film 255-3, and a dielectric layer 252-3 are sequentially formed on the dielectric layer 252-2. Fig.28 The layers formed in the structure 250 (eg, the seed layer 253 - 3 , the patterned conductive layer 254 - 3 , the interlayer film 255 - 3 , and the dielectric layer 252 - 3 ) may be referred to as a fourth build-up layer of the redistribution wiring structure 250 .

[0147] In some embodiments, the seed layer 253-3 is directly located on the dielectric layer 252-2, the patterned conductive layer 254-2b and the interlayer film 255-2. Fig.28As shown in , the seed layer 253-3 is electrically connected to the patterned conductive layer 254-2b. In some embodiments, the patterned conductive layer 254-3 is located on the seed layer 253-3 and is electrically connected to the seed layer 253-3. In some embodiments, the sidewall of the seed layer 253-3 is aligned with the sidewall of a corresponding one of the patterned conductive layers 254-3. Fig.28 As shown in , the seed layer 253-3 is sandwiched between the patterned conductive layer 254-3 and the patterned conductive layer 254-2b, and the patterned conductive layer 254-3 is electrically connected to the patterned conductive layer 254-2b through the seed layer 253-3. The formation and material of the seed layer 253-3 are the same or similar to the formation and material of the seed layer 253-1, and therefore will not be described in detail herein. The formation and material of the patterned conductive layer 254-3 are the same or similar to the formation and material of the patterned conductive layer 254-1, and therefore will not be described in detail herein.

[0148] In some embodiments, the interlayer film 255-3 is formed to cover the patterned conductive layer 254-3 and the seed layer 253-3. Fig.28 As shown in , for example, the sidewalls of the patterned conductive layer 254-3 and the sidewalls of the seed layer 253-3 are wrapped by the interlayer film 255-3. The formation and material of the interlayer film 255-3 are the same or similar to the formation and material of the interlayer film 155-2, and therefore are not described in detail herein. In some embodiments, a dielectric layer 252-3 is formed on the interlayer film 255-3, the patterned conductive layer 254-3, the seed layer 253-3, and the dielectric layer 252-2. Fig.28 As shown in, for example, a plurality of openings O7 are formed in the dielectric layer 252-3 and the interlayer film 255-3, wherein a portion of the patterned conductive layer 254-3 is exposed through the openings O7. The formation and material of the dielectric layer 252-3 are the same or similar to the formation and material of the dielectric layer 152-2, and therefore are not described in detail herein. Due to the interlayer film 255-3, the bonding strength between the patterned conductive layer 254-3 and the dielectric layer 252-3 and between the seed layer 253-3 and the dielectric layer 252-3 is enhanced, and the delamination between the patterned conductive layer 254-3 and the dielectric layer 252-3 and between the seed layer 253-3 and the dielectric layer 252-3 is suppressed.

[0149] Reference Fig.29 In some embodiments, a seed layer 253-4, a patterned conductive layer 254-4, an interlayer film 255-4, and a dielectric layer 252-4 are sequentially formed. The formation and materials of the seed layer 253-4, the patterned conductive layer 254-4, the interlayer film 255-4, and the dielectric layer 252-4 are the same or similar to the formation and materials of the seed layer 153-3, the patterned conductive layer 154-3, the interlayer film 155-3, and the dielectric layer 256, and therefore, they may not be described in detail herein. In the present disclosure, Fig.29 The layers formed in the structure 250 (eg, the seed layer 253 - 4 , the patterned conductive layer 254 - 4 , the interlayer film 255 - 4 , and the dielectric layer 252 - 4 ) may be referred to as a layer of the first constituent layer of the redistribution wiring structure 250 .

[0150] In some embodiments, the seed layer 253-4 is located on the dielectric layer 252-3 and extends to the opening O7 formed in the interlayer film 255-3 and the dielectric layer 252-3 to physically contact the patterned conductive layer 254-3 exposed through the opening O7. In other words, the seed layer 253-4 penetrates the dielectric layer 252-3 and the interlayer film 255-3, and is directly located on the patterned conductive layer 254-3 exposed through the opening O7. In some embodiments, the sidewalls of the opening O7 are completely covered by the seed layer 253-4. In some embodiments, the patterned conductive layer 254-4 is located on the seed layer 253-4 (e.g., physically contacts the seed layer 253-4), wherein in the vertical projection along the direction Z on the insulating encapsulation 140', the projection area of ​​the patterned conductive layer 254-4 overlaps with the projection area of ​​the seed layer 253-4. For example, as Fig.29 As shown in , the patterned conductive layer 254-4 is electrically connected to the patterned conductive layer 254-3 through the seed layer 253-4. In some embodiments, the interlayer film 255-4 and the dielectric layer 252-4 are located on the patterned conductive layer 254-4 and the seed layer 253-4, wherein the interlayer film 255-4 is sandwiched between the patterned conductive layer 254-4 and the dielectric layer 252-4, and sandwiched between the seed layer 253-4 and the dielectric layer 252-4. Due to the interlayer film 255-4, the adhesion strength between the patterned conductive layer 254-4 and the dielectric layer 252-4 and between the seed layer 253-4 and the dielectric layer 252-4 is enhanced, and the delamination between the patterned conductive layer 254-4 and the dielectric layer 252-4 and between the seed layer 253-4 and the dielectric layer 252-4 is suppressed.

[0151] like Fig.29 As shown in FIG. 1 , a portion of the patterned conductive layer 254-4 is exposed through a plurality of openings O8 formed in the dielectric layer 252-4 and the interlayer film 255-4 to be electrically connected to a connector formed subsequently. At this point, the redistribution wiring structure 250 of the package structure P4 is manufactured. Fig.32 The method shown and Figure 21 to Figure 26 , Fig. 27 and / or Fig.28 By using the process described in (eg, using the second constituent layer, the third constituent layer, and the fourth constituent layer), the redistribution wiring structure 250 further obtains a fine pitch structure for routing functions. Fig.29 As shown in FIG. 1 , semiconductor dies 130 - 1 , 130 - 2 , and 130 - 3 are electrically connected to each other, for example, via a redistribution wiring structure 250 .

[0152] For illustration purposes, Fig.29 The redistribution wiring structure 250 shown includes four constituent layers (e.g., one layer of each of the first constituent layer, the second constituent layer, the third constituent layer, and the fourth constituent layer); however, the present disclosure is not limited to this. The number of the first constituent layer, the second constituent layer, the third constituent layer, and the fourth constituent layer included in the redistribution wiring structure 250 is not limited in the present disclosure. For example, the number of the first constituent layer, the second constituent layer, and the third constituent layer included in the redistribution wiring structure 250 may be one or more than one, and the number of the fourth constituent layer included in the redistribution wiring structure 250 may be zero, one, or more than one.

[0153] Reference Fig.30 In some embodiments, a plurality of seed layer patterns 160 and a plurality of conductive elements 170 are sequentially formed on the redistribution wiring structure 150. The bonding strength between the conductive elements 170 and the dielectric layer 252-4 is enhanced due to the seed layer patterns 160. In some embodiments, the seed layer patterns 160 are directly located on the portion of the patterned conductive layer 254-4 exposed through the openings O8 formed in the dielectric layer 252-4 and the interlayer film 255-4.

[0154] In some embodiments, the seed layer pattern 160 is electrically connected to the redistribution wiring structure 250, and the conductive element 170 is electrically connected to the redistribution wiring structure 250 through the seed layer pattern 160. Fig.30 As shown in , for example, conductive element 170 is electrically connected to semiconductor die 130 through redistribution wiring structure 250 and corresponding seed layer patterns in seed layer pattern 160. Fig.13 The formation and materials of the seed layer pattern 160 and the conductive element 170 are described in the illustrated process, and therefore will not be described again herein.

[0155] Reference Fig.31 In some embodiments, Fig.30 The entire structure shown in FIG. 1 is flipped (turned upside down) together with the carrier 112, wherein the conductive element 170 is placed on the holding device HD and through the peeling layer 114, and then the carrier 112 is peeled off from the buffer layer 116. During the peeling step, the holding device HD is used to fix the package structure P4 before the carrier 112 and the peeling layer 114 are peeled off.

[0156] Reference Fig.32In some embodiments, the conductive element 170 is released from the holding device HD to form the package structure P4. In some embodiments, before the conductive element 170 is released from the holding device HD, a cutting (singulation) process is performed to cut the plurality of package structures P4 connected therebetween into individual and separated package structures P4. At this point, the manufacture of the package structure P4 is completed.

[0157] In some embodiments, the conductive element 170 may include a copper pillar, a copper via, etc. Fig.32 However, the present disclosure is not limited thereto. In alternative embodiments, the conductive element 170 may include a solder ball or a BGA ball, and the seed layer pattern 160 may be replaced by a UBM pattern u1. Fig.34 In other alternative embodiments, the conductive element 170 may include a solder ball or a BGA ball, and the seed layer pattern 160 may be replaced by the UBM pattern u1, and may further include a plurality of conductive pillars CP in the presence of the conductive element 190 and the UBM pattern u2, see Fig.35 However, the present disclosure is not limited thereto, and in alternative embodiments, the UBM pattern u2 may be omitted based on design layout and requirements.

[0158] In some alternative embodiments, in addition to Fig.32 The conductive element 170 and / or Figure 34 to Figure 35 In addition to the conductive element 180 in the redistribution structure 250, additional semiconductor elements (not shown) may be provided on the redistribution structure 250 through the seed layer pattern 160 and / or the UBM patterns u1, u2. The additional semiconductor elements may include passive components or active components. The number of additional semiconductor elements is not limited in the present disclosure and may be specified based on requirements and design layout.

[0159] As shown in package structures P1 to P6, in the redistribution wiring structure 150 / 250, since the interlayer film (e.g., 151 / 155-1 / 155-2 / 155-3, 255-1 / 255-2 / 255-3 / 255-4) is located between the dielectric layer (e.g., 152-1 / 152-2 / 152-3 / 156, 252-1 / 252-2 / 252-3 / 252-4) and the patterned conductive layer (e.g., 154-1 / 154-2 / 154-3, 254-1 / 254-2a / 254-2b / 254-3 / 254- 4), so the dielectric layer (e.g., 152-1 / 152-2 / 152-3 / 156, 252-1 / 252-2 / 252-3 / 252-4) is separated from the patterned conductive layer (e.g., 154-1 / 154-3 / 154-3, 254-1 / 254-2a / 254-2b / 254-3 / 254-4) by the interlayer film (e.g., 151 / 155-1 / 155-2 / 155-3, 255-1 / 255-2 / 255-3 / 255-4), and so the gap generated therebetween is greatly reduced, thereby suppressing the delamination phenomenon. In addition, as shown in package structures P1 to P6, in the redistribution wiring structure 150 / 250, since the interlayer film (e.g., interlayer film 151, 255-1) is located between the via (e.g., via 130d) and the dielectric layer (e.g., dielectric layer 152-1, 252-1), the dielectric layer (e.g., dielectric layer 152-1, 252-1) is separated from the via (e.g., via 130d) by the interlayer film (e.g., interlayer film 151, 255-1), and the gap generated therebetween is also reduced, thereby suppressing the delamination phenomenon. In the present disclosure, as measured along direction Z, the thickness of each of the interlayer films 151-1, 155-1 to 155-3, 255-1 to 255-3 is greater than or substantially equal to 50nm and less than or substantially equal to 350nm. Due to such a configuration, the adhesive strength between one of the patterned conductive layers and its corresponding one of the dielectric layers is enhanced, and thus better yield and reliability of the package structures P1 to P6 are achieved.

[0160] Figure 36 to Figure 42 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig.43 1 is a flow chart illustrating a method of manufacturing a redistribution wiring structure / layer of a package structure according to some embodiments of the present disclosure. Elements similar or substantially the same as previously described elements will use the same reference numbers, and certain details or descriptions of the same elements will not be repeated herein. Fig.15 and Fig.42 , Fig.42 The package structure P7 shown in FIG. Fig.15The difference is that, in the package structure P7, the redistribution circuit structure 150 is replaced by the redistribution circuit structure 350.

[0161] In some embodiments, using Figure 36 to Figure 39 The process described in the above embodiment forms and arranges the redistribution wiring structure 350 on the semiconductor die 130 and the insulating package 140'. In some embodiments, as Figure 36 to Figure 39 As shown in the figure, the redistribution wiring structure 350 includes a dielectric layer 352, a seed layer 353 (e.g., seed layer 353-1, seed layer 353-2, and seed layer 353-3), a patterned conductive layer 354 (e.g., patterned conductive layer 354-1, patterned conductive layer 354-2, and patterned conductive layer 354-3), an interlayer film 355 (e.g., interlayer film 355-1, interlayer film 355-2, and interlayer film 255-3), and a dielectric layer 356 (e.g., dielectric layer 356-1, dielectric layer 356-2, and dielectric layer 356-3). However, in the present disclosure, the number of layers of the seed layer 353, the patterned conductive layer 354, the interlayer film 355, and the dielectric layer 356 is not limited to Figure 31 to Figure 39 The number of layers of the seed layer 253, the patterned conductive layer 254, the interlayer film 355 and the dielectric layer 356 may be one or more than one. In some embodiments, the seed layer 253, the patterned conductive layer 254, the interlayer film 355 and the dielectric layer 356 are formed on the dielectric layer 252 and stacked in sequence.

[0162] Reference Fig.36 In some embodiments, Figure 3 After the process described in Fig.43 In step S41c, a dielectric layer 352 is formed on the semiconductor die 130 and the insulating encapsulation body 140'. The formation and material of the dielectric layer 352 are the same or similar to the formation and material of the dielectric layer 152-1, and therefore will not be described in detail herein. Fig.36 As shown in FIG. 3 , for example, the vias 130 d of the semiconductor die 130 are exposed through the plurality of openings O9 formed in the dielectric layer 352 . In other words, the vias 130 d of the semiconductor die 130 are exposed through the openings O9 formed in the dielectric layer 352 in an accessible manner.

[0163] In some embodiments, according to Fig.43 In step S42c, the seed layer 353-1 is formed to be directly located on the dielectric layer 352, and the patterned conductive layer 354-1 is formed to be disposed on the seed layer 353-1. The formation and materials of the seed layer 353-1 and the patterned conductive layer 354-1 are the same or similar to the formation and materials of the seed layer 153-1 and the patterned conductive layer 154-1, respectively, and therefore are not further described herein. Fig.36As shown in , the seed layer 351-1 penetrates the dielectric layer 352, wherein the seed layer 351-1 extends into the opening O9 to be physically connected to the via 130d of the semiconductor die 130 exposed through the opening O9. In some embodiments, the sidewalls of the opening O9 are completely covered by the seed layer 353-1. In some embodiments, the patterned conductive layer 354-1 is located on the seed layer 353-1 (e.g., physically contacts the seed layer 353-1), wherein in the vertical projection along the direction Z on the insulating encapsulation 140', the projection area of ​​the patterned conductive layer 354-1 overlaps with the projection area of ​​the seed layer 353-1. For example, as shown in Fig.36 As shown in FIG. 1 , the patterned conductive layer 354 - 1 is electrically connected to the via 130 d of the semiconductor die 130 through the seed layer 353 - 1 .

[0164] Continue to refer to Fig.36 In some embodiments, according to Fig.43 In step S43c, a dielectric layer 356a is disposed on the patterned conductive layer 354-1. For example, the dielectric layer 356a is coated on the seed layer 353-1, the patterned conductive layer 354-1, and the dielectric layer 352 exposed by the seed layer 353-1 and the patterned conductive layer 354-1. In other words, the seed layer 353-1 and the patterned conductive layer 354-1 are embedded in the dielectric layer 356a, wherein the dielectric layer 352 exposed by the seed layer 353-1 and the patterned conductive layer 354-1 is covered by the dielectric layer 356a. For example, the dielectric layer 356a is coated on the seed layer 353-1, the patterned conductive layer 354-1, and the dielectric layer 352 exposed by the seed layer 353-1 and the patterned conductive layer 354-1 by (but not limited to) the following method: a blanket layer of the dielectric material mixture is formed on the seed layer 353-1, the patterned conductive layer 354-1, and the dielectric layer 352 exposed by the seed layer 353-1 and the patterned conductive layer 354-1 to completely cover the seed layer 353-1, the patterned conductive layer 354-1, and the dielectric layer 352 exposed by the seed layer 353-1 and the patterned conductive layer 354-1. In some embodiments, the dielectric layer 356a can be formed by a suitable manufacturing technique such as spin coating.

[0165] In some embodiments, the dielectric material mixture includes a dielectric material and an additive. For example, the dielectric material may include polyimide, PBO, BCB, nitrides such as silicon nitride, oxides such as silicon oxide, PSG, BSG, BPSG, acrylate resins, combinations thereof, and the like. For example, the additive may include a small molecule (such as a silane-based small molecule) having an average molecular weight of less than 1000 g / mol or an oligomer (such as a polyethylene glycol based oligomer, an acrylate-based oligomer, etc.) having an average molecular weight of about 1000 g / mol to about 10000 g / mol. In some embodiments, based on the total amount of the dielectric material mixture, the amount of the dielectric material is about 95 wt % to about 99 wt %, and the amount of the additive is about 1 wt % to about 5 wt %. In an alternative embodiment, a solvent may be optionally added to the dielectric material mixture to promote mixing between the additive and the dielectric material, the solvent being a solvent that enables the additive and the dielectric material to be uniformly mixed therein but does not react therewith. In some embodiments, the solvent may include n-methylpyrrolidone (NMP) or a nitrogen-containing solvent.

[0166] Reference Fig.37 In some embodiments, according to Fig.43 Step S44c is shown, Fig.36 The structure shown above is subjected to a heat treatment TH to form an interlayer film 355-1 on the patterned conductive layer 354-1. For example, the dielectric layer 356a is subjected to a heat treatment TH to form a fully cured dielectric layer 356a' and an interlayer film 355-1, wherein the interlayer film 355-1 is located between the fully cured dielectric layer 356a' and the patterned conductive layer 354-1. In some embodiments, the thickness of the interlayer film 355-1 is greater than or substantially equal to 5 nm and less than or substantially equal to 250 nm. Fig.37 As shown in FIG. 3 , for example, the interlayer film 355 - 1 is directly located on the patterned conductive layer 354 - 1 , wherein the dielectric layer 356 a ′ is separated from the patterned conductive layer 354 - 1 by the interlayer film 355 - 1 .

[0167] In some embodiments, during the heat treatment TH, the dielectric layer 356a is sufficiently cured, and the additives contained in the dielectric layer 356a interact with the copper (Cu) atoms of the patterned conductive layer 254-1 to form an interlayer film 355-1, wherein additional oxygen (O) atoms (e.g., from the external atmosphere) are provided during the heat treatment TH to further perform an oxidation process, so that the interlayer film 355-1 is formed with a nanostructure composed of copper oxide with a grain size of 200nm or more. In some embodiments, the interlayer film 355-1 includes a polycrystalline copper oxide (poly crystalline Cu 2 O) is a nanostructure layer. In the present disclosure, the interlayer film 355-1 is conductive, and the interlayer film 355-1 is electrically connected to the patterned conductive layer 354-1. During the execution of the heat treatment TH, based on the needs and design layout, the parameters in the formation of the interlayer film 355-1 (for example, the oxidation rate of copper atoms, the crystal orientation and the layer density) can be controlled by adjusting the addition (type and / or amount) of the additives included in the dielectric material mixture used to form the dielectric layer 356a. Due to the additives included in the dielectric material mixture, the curing temperature of the dielectric layer 356a is significantly reduced. In one embodiment, the heat treatment TH is performed at a workable temperature of about 170°C to about 320°C and a workable pressure of about 50 torr to about 100 torr. For example, additional oxygen atoms can be provided by (but not limited to) providing pure oxygen gas.

[0168] In some embodiments, Fig.38 As shown in FIG. 1 , the dielectric layer 356 a ′ is patterned to form a dielectric layer 356 - 1 having a plurality of openings O10 , wherein the openings O10 expose portions of the interlayer film 355 - 1 . The number of the openings O10 is not limited to Fig.38 The number shown in FIG. 1 is not a number shown in FIG. 1 and can be specified based on requirements and design layout.

[0169] Continue to refer to Fig.38In some embodiments, the patterned conductive layer 354-1 is completely wrapped by the seed layer 353-1 and the interlayer film 355-1. In some embodiments, the interlayer film 355-1 is located between the patterned conductive layer 354-1 and the dielectric layer 356-1 and between the seed layer 353-1 and the dielectric layer 356-1, wherein the patterned conductive layer 354-1 and the seed layer 353-1 are independently separated from the dielectric layer 356-1 by the interlayer film 355-1. Since the interlayer film 355-1 is interposed between the patterned conductive layer 354-1 and the dielectric layer 356-1 and between the seed layer 353-1 and the dielectric layer 356-1, the interlayer film 355-1 having a grain size of 200 nm or more serves as a copper diffusion barrier between the conductive layer and the dielectric layer (e.g., the patterned conductive layer 354-1 and the dielectric layer 356-1, and the seed layer 353-1 and the dielectric layer 356-1), and thus the copper diffusion phenomenon is greatly suppressed because the diffusion rate of copper atoms from the conductive layer (e.g., the copper layer) to the dielectric layer is reduced due to the interlayer film 355-1. In detail, the number of grain boundaries in a given area decreases as the grain size increases, so that the voids generated between the conductive layer and the dielectric layer (which are caused by the diffusion of copper atoms diffused from the conductive layer to the dielectric layer and the grain boundaries of the grains in the conductive layer) are significantly reduced. Therefore, due to the presence of the interlayer film 355-1, the adhesive strength between the patterned conductive layer 354-1 and the dielectric layer 356-1 and between the seed layer 353-1 and the dielectric layer 356-1 is enhanced, and delamination between the patterned conductive layer 354-1 and the dielectric layer 356-1 and between the seed layer 353-1 and the dielectric layer 356-1 is suppressed. Due to the interlayer film 355-1, the adhesive strength between the patterned conductive layer 354-1 and the dielectric layer 356-1 and between the seed layer 353-1 and the dielectric layer 356-1 is enhanced, and delamination between the patterned conductive layer 354-1 and the dielectric layer 356-1 and between the seed layer 353-1 and the dielectric layer 356-1 is suppressed.

[0170] Reference Fig.39In some embodiments, a seed layer 353-2, a patterned conductive layer 354-2, an interlayer film 355-2, and a dielectric layer 356-2 are sequentially formed on the dielectric layer 356-1, and a seed layer 353-3, a patterned conductive layer 354-3, an interlayer film 355-3, and a dielectric layer 356-3 are sequentially formed on the dielectric layer 356-2. The formation and materials of the seed layers 353-2 and 353-3 are the same as or similar to the formation and materials of the seed layer 353-1, the formation and materials of the patterned conductive layers 354-2 and 354-3 are the same as or similar to the formation and materials of the patterned conductive layer 354-1, the formation and materials of the interlayer films 355-2 and 355-3 are the same as or similar to the formation and materials of the interlayer film 355-1, and the formation and materials of the dielectric layers 356-2 and 356-3 are the same as or similar to the formation and materials of the dielectric layer 356-1, and therefore will not be described in detail herein.

[0171] In some embodiments, the seed layer 353-2 is located on the dielectric layer 356-1 and extends into the opening O10 formed in the dielectric layer 356-1 to physically contact the portion of the interlayer film 355-1 exposed through the opening O10. In other words, the seed layer 353-2 penetrates the dielectric layer 356-1, and the sidewall of the opening O10 is completely covered by the seed layer 353-2. Fig.39 As shown in , for example, the seed layer 353-2 is electrically connected to the patterned conductive layer 354-1 through the interlayer film 355-1. In some embodiments, the patterned conductive layer 354-2 is located on the seed layer 353-2 (e.g., physically contacts the seed layer 353-2), wherein in the vertical projection along the direction Z on the insulating encapsulation body 140', the projection area of ​​the patterned conductive layer 354-2 overlaps with the projection area of ​​the seed layer 353-2. For example, as Fig.39 As shown in , the patterned conductive layer 354-2 is electrically connected to the patterned conductive layer 354-1 through the seed layer 353-2 and the interlayer film 355-1. In some embodiments, the interlayer film 355-2 is located on the patterned conductive layer 354-2 (for example, physically contacts the patterned conductive layer 354-2), wherein the surface of the patterned conductive layer 354-2 that is not in contact with the seed layer 353-2 and the sidewall of the seed layer 353-2 are covered by the interlayer film 355-2. Fig.39As shown in , for example, the interlayer film 355-2 is electrically connected to the patterned conductive layer 354-2 and the seed layer 353-2. In some embodiments, the dielectric layer 356-2 is located on the interlayer film 355-2, wherein the interlayer film 355-2 is sandwiched between the patterned conductive layer 354-2 and the dielectric layer 356-2, and between the seed layer 353-2 and the dielectric layer 356-2. Due to the interlayer film 355-2, the adhesion strength between the patterned conductive layer 354-2 and the dielectric layer 356-2 and between the seed layer 353-2 and the dielectric layer 356-2 is enhanced, and the delamination between the patterned conductive layer 354-2 and the dielectric layer 356-2 and between the seed layer 353-2 and the dielectric layer 356-2 is suppressed. In some embodiments, as Fig.39 As shown in FIG. 3 , portions of the interlayer film 355 - 2 are exposed through a plurality of openings O11 formed in the dielectric layer 356 - 2 to be electrically connected to a connector to be formed subsequently.

[0172] In some embodiments, the seed layer 353-3 is located on the dielectric layer 356-2 and extends into the opening O11 formed in the dielectric layer 356-2 to physically contact the portion of the interlayer film 355-2 exposed through the opening O11. In other words, the seed layer 353-3 penetrates the dielectric layer 356-2, and the sidewall of the opening O11 is completely covered by the seed layer 353-3. Fig.39 As shown in , for example, the seed layer 353-3 is electrically connected to the patterned conductive layer 354-2 through the interlayer film 355-2. In some embodiments, the patterned conductive layer 354-3 is located on the seed layer 353-3 (e.g., physically contacts the seed layer 353-3), wherein in the vertical projection along the direction Z on the insulating encapsulation body 140', the projection area of ​​the patterned conductive layer 354-3 overlaps with the projection area of ​​the seed layer 353-3. For example, as Fig.39 As shown in , the patterned conductive layer 354-3 is electrically connected to the patterned conductive layer 354-2 through the seed layer 353-3 and the interlayer film 355-2. In some embodiments, the interlayer film 355-3 is located on the patterned conductive layer 354-3 (for example, physically contacts the patterned conductive layer 354-3), wherein the surface of the patterned conductive layer 354-3 that is not in contact with the seed layer 353-3 and the sidewall of the seed layer 353-3 are covered by the interlayer film 355-3. Fig.39As shown in , for example, the interlayer film 355-3 is electrically connected to the patterned conductive layer 354-2 and the seed layer 353-3. In some embodiments, the dielectric layer 356-3 is located on the interlayer film 355-3, wherein the interlayer film 355-3 is sandwiched between the patterned conductive layer 354-3 and the dielectric layer 356-3, and between the seed layer 353-3 and the dielectric layer 356-3. Due to the interlayer film 355-3, the adhesion strength between the patterned conductive layer 354-3 and the dielectric layer 356-3 and between the seed layer 353-3 and the dielectric layer 356-3 is enhanced, and the delamination between the patterned conductive layer 354-3 and the dielectric layer 356-3 and between the seed layer 353-3 and the dielectric layer 356-3 is suppressed. In some embodiments, as Fig.39 As shown in FIG. 1 , a portion of the interlayer film 355-3 is exposed through a plurality of openings O12 formed in the dielectric layer 356-3 to be electrically connected to a connector formed subsequently. At this point, the redistribution wiring structure 350 of the package structure P7 is completed. Fig.39 As shown in FIG. 1 , semiconductor dies 130 - 1 , 130 - 2 , and 130 - 3 are electrically connected to each other, for example, via a redistribution wiring structure 350 .

[0173] In this disclosure, Fig.39 The seed layer 353-2, the patterned conductive layer 354-2, the interlayer film 355-2 and the dielectric layer 356-2 formed in Fig.39 The seed layer 353-3, the patterned conductive layer 354-3, the interlayer film 355-3, and the dielectric layer 356-3 formed in the redistribution wiring structure 350 may be respectively referred to as a layer of the fifth build-up layer of the redistribution wiring structure 350. The number of fifth build-up layers included in the redistribution wiring structure 350 is not limited in the present disclosure. In one embodiment, the number of fifth build-up layers included in the redistribution wiring structure 350 may be zero. For example, the fifth build-up layer in the redistribution wiring structure 350 may be optionally omitted. Fig.39 In alternative embodiments, the number of the fifth constituent layers included in the redistribution wiring structure 350 may be one or more than one.

[0174] Reference Fig.40 In some embodiments, a plurality of seed layer patterns 160 and a plurality of conductive elements 170 are sequentially formed on the redistribution wiring structure 350. Due to the seed layer pattern 160, the adhesive strength between the conductive element 170 and the dielectric layer 356-3 is enhanced. In some embodiments, the seed layer pattern 160 is directly located on the portion of the interlayer film 355-3 exposed by the opening O12 formed in the dielectric layer 356-3, and the seed layer pattern 160 is electrically connected to the patterned conductive layer 354-3 through the interlayer film 355-3.

[0175] In some embodiments, the seed layer pattern 160 is electrically connected to the redistribution wiring structure 350, and the conductive element 170 is electrically connected to the redistribution wiring structure 350 through the seed layer pattern 160. Fig.40 As shown in , for example, some of the conductive elements 170 are electrically connected to the semiconductor die 130 through the redistribution wiring structure 350 and the corresponding seed layer pattern in the seed layer pattern 160. Fig.13 The formation and materials of the seed layer pattern 160 and the conductive element 170 are described in the illustrated process, and therefore will not be described again herein.

[0176] Reference Fig.41 In some embodiments, Fig.40 The entire structure shown in FIG. 1 is flipped (turned upside down) together with the carrier 112, wherein the conductive element 170 is placed on the holding device HD, and the carrier 112 is then peeled off from the buffer layer 116 due to the peeling layer 114. During the peeling step, the holding device HD is used to fix the package structure P7 before the carrier 112 and the peeling layer 114 are peeled off.

[0177] Reference Fig.42 In some embodiments, the conductive element 170 is released from the holding device HD to form the package structure P7. In some embodiments, before the conductive element 170 is released from the holding device HD, a cutting (singulation) process is performed to cut the plurality of package structures P7 connected therebetween into individual and separated package structures P7. At this point, the manufacture of the package structure P7 is completed.

[0178] In some embodiments, the conductive element 170 may include a copper pillar, a copper via, etc. Fig.42 However, the present disclosure is not limited thereto. In alternative embodiments, the conductive element 170 may include a solder ball or a BGA ball, and the seed layer pattern 160 may be replaced by a UBM pattern u1. Fig.44 In other alternative embodiments, the conductive element 170 may include a solder ball or a BGA ball, and the seed layer pattern 160 may be replaced by the UBM pattern u1, and may further include a plurality of conductive pillars CP in the presence of the conductive element 190 and the UBM pattern u2, see Fig.45 However, the present disclosure is not limited thereto, and in alternative embodiments, the UBM pattern u2 may be omitted based on design layout and requirements.

[0179] In some alternative embodiments, in addition to Fig.42 The conductive element 170 and / or Figure 44 to Figure 45In addition to the conductive element 180 in the redistribution structure 350, additional semiconductor elements (not shown) may be provided on the redistribution structure 350 through the seed layer pattern 160 and / or the UBM patterns u1, u2. The additional semiconductor elements may include passive components or active components. The number of additional semiconductor elements is not limited in the present disclosure and may be specified based on requirements and design layout.

[0180] Fig.46 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure. Fig.47 1 is a flow chart illustrating a method of manufacturing a redistribution wiring structure / layer of a package structure according to some embodiments of the present disclosure. Elements similar or substantially the same as previously described elements will use the same reference numbers, and certain details or descriptions of the same elements will not be repeated herein. Fig.15 and Fig.46 , Fig.46 The package structure P10 shown in FIG. Fig.15 The package structure P1 is shown in FIG. 1 ; the difference is that, in the package structure P10 , the redistribution circuit structure 150 is replaced by the redistribution circuit structure 450 .

[0181] In some embodiments, using Fig.47 The steps (processes) described in the above are used to form and arrange the redistribution wiring structure 450 on the semiconductor die 130 and the insulating package 140'. In some embodiments, as Fig.46 As shown in the figure, the redistribution wiring structure 450 includes a dielectric layer 452 (for example, dielectric layer 452-1, dielectric layer 452-2, dielectric layer 452-3 and dielectric layer 452-4), a seed layer 453 (for example, seed layer 453-1, seed layer 453-2, seed layer 453-3 and seed layer 453-4), a patterned conductive layer 454 (for example, patterned conductive layer 454-1, patterned conductive layer 454-2a, patterned conductive layer 454-2b, patterned conductive layer 454-3 and patterned conductive layer 454-4) and an interlayer film 455 (for example, interlayer film 455-1, interlayer film 455-2 and interlayer film 455-3 and interlayer film 455-4). However, in the present disclosure, the number of dielectric layers 452, seed layers 453, patterned conductive layers 454, and interlayer films 455 is not limited to Fig.46, wherein the number of layers of the dielectric layer 452, the seed layer 453, the patterned conductive layer 454, and the interlayer film 455 may be one or more than one. In some embodiments, the dielectric layer 452, the seed layer 453, the patterned conductive layer 454, and the interlayer film 455 are formed on the insulating encapsulation body 140' and are stacked in sequence. In the present disclosure, the interlayer films 455-1 to 455-4 are independently formed with a nanostructure composed of copper oxide with a grain size of 200nm or more. In some embodiments, the interlayer films 455-1 to 455-4 include a nanostructure composed of polycrystalline copper oxide (Cu 2 In the present disclosure, the interlayer films 455-1 to 455-4 are conductive.

[0182] like Fig.46 As shown in , in some embodiments, the patterned conductive layer 454-1 is completely wrapped (covered) by the seed layer 453-1 and the interlayer film 455-1. For example, the interlayer film 455-1 is located between the patterned conductive layer 454-1 and the dielectric layer 456-1 and between the seed layer 453-1 and the dielectric layer 456-1, wherein the patterned conductive layer 454-1 and the seed layer 453-1 are independently and physically separated from the dielectric layer 456-1 by the interlayer film 455-1. Due to the interlayer film 455-1, the adhesion strength between the patterned conductive layer 454-1 and the dielectric layer 456-1 and between the seed layer 453-1 and the dielectric layer 456-1 is enhanced, and the delamination between the patterned conductive layer 454-1 and the dielectric layer 456-1 and between the seed layer 453-1 and the dielectric layer 456-1 is suppressed. As shown in FIG. Fig.46 As shown in FIG. 4 , the conductive layer 454 - 1 is electrically connected to the via hole 130 d through the seed layer 453 - 1 , and is electrically connected to the interlayer film 455 - 1 through direct contact.

[0183] In some embodiments, the patterned conductive layer 454-2a and the patterned conductive layer 454-2b disposed thereon are completely wrapped (covered) by the seed layer 453-2 and the interlayer film 455-2. For example, the interlayer film 455-2 is located between the patterned conductive layers 454-2a, 454-2b and the dielectric layer 456-2 and between the seed layer 453-2 and the dielectric layer 456-2, wherein the patterned conductive layers 454-2a, 454-2b and the seed layer 453-2 are independently and physically separated from the dielectric layer 456-2 by the interlayer film 455-2. Due to the interlayer film 455-2, the adhesive strength between the patterned conductive layers 454-2a, 454-2b and the dielectric layer 456-2 and between the seed layer 453-2 and the dielectric layer 456-2 is enhanced, and the delamination between the patterned conductive layers 454-2a, 454-2b and the dielectric layer 456-2 and between the seed layer 453-2 and the dielectric layer 456-2 is suppressed. Fig.46As shown in the figure, the patterned conductive layer 454-2a is electrically connected to the patterned conductive layer 454-1 through the seed layer 453-2 and the interlayer film 455-1, and is electrically connected to the interlayer film 455-2 through direct contact, while the patterned conductive layer 454-2b is electrically connected to the patterned conductive layer 454-2a and the interlayer film 455-2 through direct contact.

[0184] In some embodiments, the patterned conductive layer 454-3 is completely wrapped (covered) by the seed layer 453-3 and the interlayer film 455-3. For example, the interlayer film 455-3 is located between the patterned conductive layer 454-3 and the dielectric layer 456-3 and between the seed layer 453-3 and the dielectric layer 456-3, wherein the patterned conductive layer 454-3 and the seed layer 453-3 are independently and physically separated from the dielectric layer 456-3 by the interlayer film 455-3. Due to the interlayer film 455-3, the bonding strength between the patterned conductive layer 454-3 and the dielectric layer 456-3 and between the seed layer 453-3 and the dielectric layer 456-3 is enhanced, and the delamination between the patterned conductive layer 454-3 and the dielectric layer 456-3 and between the seed layer 453-3 and the dielectric layer 456-3 is suppressed. Fig.46 As shown in FIG. 4 , the conductive layer 454-3 is electrically connected to the conductive layer 454-2a through the seed layer 453-3 and the interlayer film 455-2.

[0185] In some embodiments, the patterned conductive layer 454-4 is completely wrapped (covered) by the seed layer 453-4 and the interlayer film 455-4. For example, the interlayer film 455-4 is located between the patterned conductive layer 454-4 and the dielectric layer 456-4 and between the seed layer 453-4 and the dielectric layer 456-4, wherein the patterned conductive layer 454-4 and the seed layer 453-4 are independently and physically separated from the dielectric layer 456-4 by the interlayer film 455-4. Due to the interlayer film 455-4, the bonding strength between the patterned conductive layer 454-4 and the dielectric layer 456-4 and between the seed layer 453-4 and the dielectric layer 456-4 is enhanced, and the delamination between the patterned conductive layer 454-4 and the dielectric layer 456-4 and between the seed layer 453-4 and the dielectric layer 456-4 is suppressed. Fig.46 As shown in FIG. 4 , the conductive layer 454-4 is electrically connected to the conductive layer 454-3 through the seed layer 453-4 and the interlayer film 455-3.

[0186] For example, for illustrative purposes, the following Fig.47 The process steps S41d to S46d are shown to perform the formation of the redistribution wiring structure 450. The present disclosure is not limited thereto.

[0187] In certain embodiments, Figure 3 After the process described in Fig.47In step S41d, a seed layer (not shown) is formed on the semiconductor die 130 and the insulating package 140'. For example, the formation and material of the seed layer are similar to Fig.21 The formation and materials of the seed layer SL1 shown in FIG. 1 are similar or substantially the same, and therefore will not be described in detail herein. Fig.47 In step S42d, a patterned conductive layer 454-1 is formed on the seed layer. For example, the formation and material of the patterned conductive layer 454-1 are similar to Fig. 22 The formation and materials of the patterned conductive layer 254-1 shown in FIG. 1 are similar or substantially the same, and therefore are not described in detail herein. Fig.47 In step S43d, the seed layer is patterned using the patterned conductive layer 454-1 as an etching mask to form a seed layer 453-1. For example, the formation and material of the seed layer 453-1 are similar to Fig.23 The formation and materials of the seed layer 253-1 shown in FIG. 1 are similar or substantially the same, and therefore are not described in detail herein. Fig.47 In step S44d, a dielectric layer (not shown) is disposed on the patterned conductive layer 454-1. For example, the formation and material of the dielectric layer are similar to Fig.36 The formation and materials of the dielectric layer 356a shown in FIG. 1 are similar or substantially the same, and therefore are not described in detail herein. Fig.47 In step S45d, heat treatment is then performed to form an interlayer film 455-1 on the patterned conductive layer 454-1. For example, the heat treatment process is similar to Fig.37 The heat treatment process described in the embodiment is similar or substantially the same and therefore will not be described in detail herein. Fig.47 In step S46d, a patterning step is performed on the dielectric layer to form a dielectric layer 452-1 and expose the interlayer film 455-1. For example, the process of the patterning step is similar to Fig.26 The process of the planarization step described in is similar or substantially the same, and therefore will not be described in detail herein.

[0188] In addition, the formation and materials of the dielectric layers 452-2 to 452-4, the seed layers 453-2 to 453-4, the patterned conductive layers 454-2a, 454-2b, 454-3, 454-4 and the interlayer films 455-2 to 455-4 are similar to those of the Fig.47 The dielectric layer 452-1, the seed layer 453-1, the patterned conductive layer 454-1 and the interlayer film 455-1 are similar to or substantially the same as those in the embodiment of the present invention, or are similar to or substantially the same as those in the embodiment of the present invention. Figure 36 to Figure 38The seed layer 353-1, the patterned conductive layer 354-1, the interlayer film 355-1 and the dielectric layer 356-1 described in the drawings are similar or substantially the same, and therefore, for the sake of brevity, they are not described in detail herein. In the present disclosure, in the redistribution wiring structure 450, a layer (e.g., seed layer 453-1, patterned conductive layer 454-1, interlayer film 455-1, and dielectric layer 452-1) may be referred to as a layer of the sixth build-up layer, a layer (e.g., seed layer 453-2, patterned conductive layers 454-2a, 454-2b, interlayer film 455-2, and dielectric layer 452-2) may be referred to as a layer of the seventh build-up layer, and a layer (e.g., seed layer 453-3, patterned conductive layer 454-3, interlayer film 455-3, and dielectric layer 452-3) may be referred to as an eighth build-up layer. layer), and the layer (eg, the seed layer 453-4, the patterned conductive layer 454-4, the interlayer film 455-4, and the dielectric layer 452-4) may be referred to as a layer of the fifth constituent layer. Fig.46 The illustrated redistribution wiring structure 450 includes four constituent layers (e.g., one layer of each of the fifth constituent layer, the sixth constituent layer, the seventh constituent layer, and the eighth constituent layer); however, the present disclosure is not limited thereto. The number of the fifth constituent layer, the sixth constituent layer, the seventh constituent layer, and the eighth constituent layer included in the redistribution wiring structure 450 is not limited in the present disclosure. For example, the number of the fifth constituent layer, the sixth constituent layer, and the seventh constituent layer included in the redistribution wiring structure 450 may be one or more than one, and the number of the eighth constituent layer included in the redistribution wiring structure 450 may be zero, one, or more than one.

[0189] Continue to refer to Fig.46 , a plurality of seed layer patterns 160 and a plurality of conductive elements 170 are sequentially formed on the redistribution wiring structure 450, and the carrier 112 is then peeled off from the buffer layer 116 due to the peeling layer 114. Fig.13The formation and materials of the seed layer pattern 160 and the conductive element 170 are described in the illustrated process, and therefore are not described in detail herein. In some embodiments, the conductive element 170 is electrically connected to the redistribution wiring structure 450 through the seed layer pattern 160. In some embodiments, some of the conductive elements 170 are electrically connected to the semiconductor die 130 through the redistribution wiring structure 450 and the corresponding seed layer pattern in the seed layer pattern 160. During the stripping step, before stripping the carrier 112 and the stripping layer 114, a retaining device HD is used to fix the package structure P10. In some embodiments, the conductive element 170 is released from the retaining device HD to form the package structure P10. In some embodiments, before releasing the conductive element 170 from the retaining device HD, a cutting (singulation) process is performed to cut the multiple package structures P10 connected therebetween into individual and separated package structures P10. At this point, the manufacture of the package structure P10 is completed.

[0190] In some embodiments, the conductive element 170 may include a copper pillar, a copper via, etc. Fig.46 However, the present disclosure is not limited thereto. In alternative embodiments, the conductive element 170 may include a solder ball or a BGA ball, and the seed layer pattern 160 may be replaced by a UBM pattern u1. Fig.48 In other alternative embodiments, the conductive element 170 may include a solder ball or a BGA ball, and the seed layer pattern 160 may be replaced by the UBM pattern u1, and may further include a plurality of conductive pillars CP in the presence of the conductive element 190 and the UBM pattern u2, see Fig.49 However, the present disclosure is not limited thereto, and in alternative embodiments, the UBM pattern u2 may be omitted based on design layout and requirements.

[0191] In some alternative embodiments, in addition to Fig.46 The conductive element 170 and / or Figure 48 to Figure 49 In addition to the conductive element 180 in the redistribution structure 450, additional semiconductor elements (not shown) may be provided on the redistribution structure 450 through the seed layer pattern 160 and / or the UBM patterns u1, u2. The additional semiconductor elements may include passive components or active components. The number of additional semiconductor elements is not limited in the present disclosure and may be specified based on requirements and design layout.

[0192] As shown in package structures P7 to P12, in the redistribution wiring structure 350 / 450, since the interlayer film (e.g., 355-1 / 355-2 / 355-3, 455-1 / 455-2 / 455-3 / 455-4) is located between the dielectric layer (e.g., 356-1 / 356-2 / 356-3, 452-1 / 452-2 / 452-3 / 452-4) and the patterned conductive layer (e.g., 354-1 / 354-2 / 354-3, 454-1 / 454-2a / 454-2b / 454-3 / 454- 4), so the dielectric layer (e.g., 356-1 / 356-2 / 356-3, 452-1 / 452-2 / 452-3 / 452-4) is separated from the patterned conductive layer (e.g., 354-1 / 354-2 / 354-3, 454-1 / 454-2a / 454-2b / 454-3 / 454-4) by the interlayer film (e.g., 355-1 / 355-2 / 355-3, 455-1 / 455-2 / 455-3 / 455-4), and so the gap generated therebetween is greatly reduced, thereby suppressing the delamination phenomenon. In the present disclosure, the thickness of each of the interlayer films 355-1 / 355-2 / 355-3, 455-1 / 455-2 / 455-3 / 455-4 is greater than or substantially equal to 5 nm and less than or substantially equal to 250 nm. Due to this configuration, the bonding strength between one of the patterned conductive layers and its corresponding dielectric layer is enhanced, and thus a better yield and reliability of the package structure P7 to the package structure P12 are achieved. In addition, due to the formation of the interlayer film (e.g., the addition of additives), the temperature for forming the redistribution wiring structure 350, 450 (e.g., the curing temperature of the dielectric layer) is reduced.

[0193] In some embodiments, the package structures P1 to P12 may be further mounted with additional packages, chips / dies, other electronic devices, or suitable substrates (eg, organic substrates) to form a stacked package structure, but the present disclosure is not limited thereto.

[0194] According to some embodiments, a package structure includes a semiconductor die and a redistribution wiring structure. The redistribution wiring structure is disposed on the semiconductor die and electrically connected to the semiconductor die, and includes a patterned conductive layer, a dielectric layer, and an interlayer film. The dielectric layer is disposed on the patterned conductive layer. The interlayer film is sandwiched between the dielectric layer and the patterned conductive layer, and the patterned conductive layer is separated from the dielectric layer by the interlayer film.

[0195] According to some embodiments, the packaging structure further includes: a seed layer, wherein the patterned conductive layer is disposed on the seed layer, and the patterned conductive layer is wrapped by the seed layer and the interlayer film. According to some embodiments, in the packaging structure, a first surface of the interlayer film physically contacts the patterned conductive layer, a second surface of the interlayer film physically contacts the dielectric layer, and the first surface is opposite to the second surface. According to some embodiments, in the packaging structure, the interlayer film includes an adhesive layer, and the adhesive layer is formed by contacting an adhesive precursor with the patterned conductive layer, and the adhesive precursor includes a compound represented by the following chemical formula: Wherein: Ar represents an aromatic ring selected from the group consisting of aromatic rings represented by the following chemical formulas (1) to (35): Chemical formula (1), Chemical formula (2), Chemical formula (3), Chemical formula (4), Chemical formula (5), Chemical formula (6), Chemical formula (7), Chemical formula (8), Chemical formula (9), Chemical formula (10), Chemical formula (11), Chemical formula (12), Chemical formula (13), Chemical formula (14), Chemical formula (15), Chemical formula (16), Chemical formula (17), Chemical formula (18), Chemical formula (19), Chemical formula (20), Chemical formula (21), Chemical formula (22), Chemical formula (23), Chemical formula (24), Chemical formula (25), Chemical formula (26), Chemical formula (27), Chemical formula (28), Chemical formula (29), Chemical formula (30), Chemical formula (31), Chemical formula (32), Chemical formula (33), Chemical formula (34) and Chemical formula (35), R 1 represents a hydrogen atom, an alkyl group or an aromatic ring, R 2 and R 3 Each independently represents a substituted alkylene group or an unsubstituted alkylene group, wherein n1 and n2 are each independently an integer from 1 to 30, and X and Y are each independently -H, -OH, -SH, -F, -Cl, -Br, -I, a carboxyl group, an ester group, an amine group, a quaternary ammonium cation, a trimethylsilyl group, a triethylsilyl group, a sulfonyl group, a carbonyl group, a carbonate group, an amide group or an epoxy group. According to some embodiments, in the package structure, the thickness of the interlayer film is greater than or substantially equal to 50 nanometers and less than or substantially equal to 350 nanometers. According to some embodiments, in the package structure, the interlayer film includes a nanostructure layer, and the nanostructure layer includes a polycrystalline Cu 2 O constitutes a nanostructure layer. According to some embodiments, in the packaging structure, the thickness of the nanostructure layer is greater than or substantially equal to 5 nanometers and less than or substantially equal to 250 nanometers. According to some embodiments, the packaging structure further includes: an insulating encapsulation body encapsulating the semiconductor die, wherein a surface of the insulating encapsulation body is substantially coplanar with a surface of the semiconductor die, and the redistribution wiring structure is disposed on the surface of the insulating encapsulation body substantially coplanar with the surface of the semiconductor die; and a plurality of conductive elements located on the redistribution wiring structure and electrically connected to the redistribution wiring structure, wherein the redistribution wiring structure is located between the insulating encapsulation body and the plurality of conductive elements. According to some embodiments, the packaging structure further includes: a plurality of through-holes arranged beside the semiconductor die and electrically connected to the redistribution wiring structure, wherein the plurality of through-holes are electrically connected to the semiconductor die through the redistribution wiring structure; an insulating encapsulant encapsulating the semiconductor die and the plurality of through-holes, wherein a surface of the insulating encapsulant is substantially coplanar with a surface of the semiconductor die and a surface of the plurality of through-holes, and the redistribution wiring structure is disposed on the surface of the insulating encapsulant substantially coplanar with the surface of the semiconductor die and the surface of the plurality of through-holes; and a plurality of conductive elements located on the redistribution wiring structure and electrically connected to the redistribution wiring structure, wherein the redistribution wiring structure is located between the insulating encapsulant and the plurality of conductive elements. According to some embodiments, the packaging structure further includes: one or more semiconductor devices disposed on the redistribution wiring structure and electrically connected to the redistribution wiring structure, wherein the one or more semiconductor devices are electrically connected to the semiconductor die through the redistribution wiring structure.

[0196] According to some embodiments, a method for manufacturing a packaging structure includes the following steps: providing a semiconductor die having multiple conductive terminals; forming a redistribution wiring structure on the semiconductor die, wherein the redistribution wiring structure is electrically connected to the semiconductor die, and forming the redistribution wiring structure includes: depositing a first dielectric layer on the semiconductor die, the first dielectric layer exposing portions of the multiple conductive terminals; forming a patterned conductive layer on the first dielectric layer, and connecting the patterned conductive layer to the portions of the multiple conductive terminals exposed through the first dielectric layer; forming a first interlayer film on the patterned conductive layer, and the first interlayer film conformally covers the patterned conductive layer; and depositing a second dielectric layer on the first interlayer film, wherein the patterned conductive layer is separated from the second dielectric layer by the first interlayer film; and forming multiple conductive elements on the redistribution wiring structure to electrically connect the multiple conductive elements to the redistribution wiring structure.

[0197] According to some embodiments, in the method of packaging structure, forming the first interlayer film includes: applying an adhesive precursor on the patterned conductive layer to form the first interlayer film on the patterned conductive layer, wherein a bond is formed between the adhesive precursor and the patterned conductive layer, and the adhesive precursor includes a compound represented by the following chemical formula: Wherein: Ar represents an aromatic ring selected from the group consisting of aromatic rings represented by the following chemical formulas (1) to (35): Chemical formula (1), Chemical formula (2), Chemical formula (3), Chemical formula (4), Chemical formula (5), Chemical formula (6), Chemical formula (7), Chemical formula (8), Chemical formula (9), Chemical formula (10), Chemical formula (11), Chemical formula (12), Chemical formula (13), Chemical formula (14), Chemical formula (15), Chemical formula (16), Chemical formula (17), Chemical formula (18), Chemical formula (19), Chemical formula (20), Chemical formula (21), Chemical formula (22), Chemical formula (23), Chemical formula (24), Chemical formula (25), Chemical formula (26), Chemical formula (27), Chemical formula (28), Chemical formula (29), Chemical formula (30), Chemical formula (31), Chemical formula (32), Chemical formula (33), Chemical formula (34) and Chemical formula (35), R 1 represents a hydrogen atom, an alkyl group or an aromatic ring, R 2 and R 3 Each independently represents a substituted alkylene group or an unsubstituted alkylene group, wherein n1 and n2 are each independently an integer from 1 to 30, and X and Y are each independently -H, -OH, -SH, -F, -Cl, -Br, -I, a carboxyl group, an ester group, an amine group, a quaternary ammonium cation, a trimethylsilyl group, a triethylsilyl group, a sulfonic group, a carbonyl group, a carbonate group, an amide group or an epoxy group; removing the portion of the adhesive precursor that is not bonded to the patterned conductive layer by washing; and drying the first interlayer film. According to some embodiments, the method of packaging structure further includes forming a second interlayer film on the plurality of conductive terminals, wherein forming the second interlayer film includes: applying an adhesive precursor on the plurality of conductive terminals to form the second interlayer film on the patterned conductive layer, wherein the adhesive precursor forms a bond with the plurality of conductive terminals, and the adhesive precursor includes a compound represented by the following chemical formula: Wherein: Ar represents an aromatic ring selected from the group consisting of aromatic rings represented by the following chemical formulas (1) to (35): Chemical formula (1), Chemical formula (2), Chemical formula (3), Chemical formula (4), Chemical formula (5), Chemical formula (6), Chemical formula (7), Chemical formula (8), Chemical formula (9), Chemical formula (10), Chemical formula (11), Chemical formula (12), Chemical formula (13), Chemical formula (14), Chemical formula (15), Chemical formula (16), Chemical formula (17), Chemical formula (18), Chemical formula (19), Chemical formula (20), Chemical formula (21), Chemical formula (22), Chemical formula (23), Chemical formula (24), Chemical formula (25), Chemical formula (26), Chemical formula (27), Chemical formula (28), Chemical formula (29), Chemical formula (30), Chemical formula (31), Chemical formula (32), Chemical formula (33), Chemical formula (34) and Chemical formula (35), R 1 represents a hydrogen atom, an alkyl group or an aromatic ring, R 2 and R 3 Each independently represents a substituted alkylene group or an unsubstituted alkylene group, wherein n1 and n2 are each independently an integer from 1 to 30, and X and Y each independently represent -H, -OH, -SH, -F, -Cl, -Br, -I, a carboxyl group, an ester group, an amine group, a quaternary ammonium cation, a trimethylsilyl group, a triethylsilyl group, a sulfonic group, a carbonyl group, a carbonate group, an amide group or an epoxy group; removing the portion of the adhesive precursor that is not bonded to the plurality of conductive terminals by washing; and drying the second interlayer film. According to some embodiments, in the method of the packaging structure, before forming the redistribution wiring structure, it also includes: encapsulating the semiconductor die in an insulating encapsulant. According to some embodiments, in the method of the packaging structure, before encapsulating the semiconductor die, it also includes: forming a plurality of perforations, the plurality of perforations are arranged next to the semiconductor die, wherein the plurality of perforations are electrically connected to the semiconductor die through the redistribution wiring structure, wherein encapsulating the semiconductor die also includes encapsulating the plurality of perforations in the insulating encapsulant. According to some embodiments, in the packaging structure method, after forming the redistribution wiring structure, it also includes: disposing one or more semiconductor devices on the redistribution wiring structure and electrically connecting the one or more semiconductor devices to the redistribution wiring structure.

[0198] According to some embodiments, a method for manufacturing a packaging structure includes the following steps: providing a semiconductor die; encapsulating the semiconductor die in an insulating encapsulation body; forming a redistribution wiring structure on the insulating encapsulation body, wherein the redistribution wiring structure is electrically connected to the semiconductor die, and forming the redistribution wiring structure includes: forming a patterned conductive layer on the semiconductor die, the patterned conductive layer electrically connected to the semiconductor die; and depositing a dielectric layer on the patterned conductive layer, and forming a nanostructure conductive layer between the dielectric layer and the patterned conductive layer; and forming a plurality of conductive elements on the redistribution wiring structure to electrically connect the redistribution wiring structure to the plurality of conductive elements.

[0199] According to some embodiments, in the method of packaging structure, depositing a dielectric layer on the patterned conductive layer includes mixing a dielectric material with an additive containing a small molecule or an oligomer to form a dielectric material mixture, and coating the dielectric material mixture on the patterned conductive layer to form the dielectric layer, and forming the nanostructure conductive layer between the dielectric layer and the patterned conductive layer includes subjecting the dielectric layer and the patterned conductive layer to a heat treatment to form the nanostructure conductive layer composed of metal oxide between the dielectric layer and the patterned conductive layer, wherein during the heat treatment, the additive contained in the dielectric layer interacts with the patterned conductive layer to form the nanostructure conductive layer composed of metal oxide. According to some embodiments, in the method of packaging structure, before encapsulating the semiconductor die, it also includes: forming a plurality of through-holes, the plurality of through-holes are arranged next to the semiconductor die, wherein the plurality of through-holes are electrically connected to the semiconductor die through the redistribution wiring structure, wherein encapsulating the semiconductor die also includes encapsulating the plurality of through-holes in the insulating encapsulation body. According to some embodiments, in the packaging structure method, after forming the redistribution wiring structure, it also includes: disposing one or more semiconductor devices on the redistribution wiring structure and electrically connecting the one or more semiconductor devices to the redistribution wiring structure.

[0200] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging structure, include: Semiconductor die; as well as A redistribution wiring structure is disposed on the semiconductor die and electrically connected to the semiconductor die, and includes: patterning a conductive layer; a dielectric layer disposed on the patterned conductive layer; and An interlayer film is sandwiched between the dielectric layer and the patterned conductive layer, wherein the interlayer film comprises a nanostructure layer composed of polycrystalline copper oxide, and the patterned conductive layer is separated from the dielectric layer by the interlayer film.

2. The packaging structure according to claim 1, further comprising: include: The seed layer, wherein the patterned conductive layer is disposed on the seed layer, and the patterned conductive layer is wrapped by the seed layer and the interlayer film. 3 . The package structure according to claim 1 , wherein a first surface of the interlayer film physically contacts the patterned conductive layer, a second surface of the interlayer film physically contacts the dielectric layer, and the first surface is opposite to the second surface. 4 . The package structure according to claim 1 , wherein a thickness of the nanostructure layer is greater than or substantially equal to 5 nanometers and less than or substantially equal to 250 nanometers.

5. The packaging structure according to claim 1, further comprising: include: an insulating encapsulant encapsulating the semiconductor die, wherein a surface of the insulating encapsulant is substantially coplanar with a surface of the semiconductor die, and the redistribution wiring structure is disposed on the surface of the insulating encapsulant substantially coplanar with the surface of the semiconductor die; as well as A plurality of conductive elements are located on the redistribution wiring structure and electrically connected to the redistribution wiring structure, wherein the redistribution wiring structure is located between the insulating enclosure and the plurality of conductive elements.

6. The packaging structure according to claim 1, further comprising: include: a plurality of through-vias arranged beside the semiconductor die and electrically connected to the redistribution wiring structure, wherein the plurality of through-vias are electrically connected to the semiconductor die through the redistribution wiring structure; an insulating encapsulant encapsulating the semiconductor die and the plurality of through-holes, wherein a surface of the insulating encapsulant is substantially coplanar with a surface of the semiconductor die and a surface of the plurality of through-holes, and the redistribution wiring structure is disposed on the surface of the insulating encapsulant substantially coplanar with the surface of the semiconductor die and the surface of the plurality of through-holes; as well as A plurality of conductive elements are located on the redistribution wiring structure and electrically connected to the redistribution wiring structure, wherein the redistribution wiring structure is located between the insulating enclosure and the plurality of conductive elements.

7. The packaging structure according to claim 1, further comprising: include: One or more semiconductor devices are disposed on the redistribution wiring structure and electrically connected to the redistribution wiring structure, wherein the one or more semiconductor devices are electrically connected to the semiconductor die through the redistribution wiring structure.

8. A method for manufacturing a packaging structure, include: providing a semiconductor die having a plurality of conductive terminals; forming a redistribution wiring structure on the semiconductor die, wherein the redistribution wiring structure is electrically connected to the semiconductor die, and forming the redistribution wiring structure comprises: depositing a first dielectric layer on the semiconductor die, the first dielectric layer exposing portions of the plurality of conductive terminals; forming a patterned conductive layer on the first dielectric layer and connecting the patterned conductive layer to the portions of the plurality of conductive terminals exposed through the first dielectric layer; forming an interlayer film on the patterned conductive layer, wherein the interlayer film comprises a nanostructure layer composed of polycrystalline copper oxide, and the interlayer film conformally covers the patterned conductive layer; and depositing a second dielectric layer on the interlayer film, wherein the patterned conductive layer is separated from the second dielectric layer by the interlayer film; and A plurality of conductive elements are formed on the redistribution wiring structure to electrically connect the plurality of conductive elements to the redistribution wiring structure.

9. The method according to claim 8, before forming the redistribution wiring structure, further comprising: include: The semiconductor die is encapsulated in an insulating encapsulation.

10. The method according to claim 9, before encapsulating the semiconductor die, further comprising: include: forming a plurality of through-holes, the plurality of through-holes being arranged beside the semiconductor die, wherein the plurality of through-holes are electrically connected to the semiconductor die through the redistribution wiring structure, Wherein encapsulating the semiconductor die further comprises encapsulating the plurality of through-holes in the insulating encapsulation body.

11. The method according to claim 8, after forming the redistribution wiring structure, further comprising: include: One or more semiconductor devices are disposed on the redistribution wiring structure and the one or more semiconductor devices are electrically connected to the redistribution wiring structure.

12. A method for manufacturing a packaging structure, include: providing semiconductor dies; encapsulating the semiconductor die in an insulating encapsulation; forming a redistribution wiring structure on the insulating package, wherein the redistribution wiring structure is electrically connected to the semiconductor die, and forming the redistribution wiring structure comprises: forming a patterned conductive layer on the semiconductor die, the patterned conductive layer electrically connecting the semiconductor die; and Depositing a dielectric layer on the patterned conductive layer, and forming a nanostructure layer composed of polycrystalline copper oxide between the dielectric layer and the patterned conductive layer; and A plurality of conductive elements are formed on the redistribution wiring structure to electrically connect the redistribution wiring structure with the plurality of conductive elements.

13. The method according to claim 12, wherein Depositing a dielectric layer on the patterned conductive layer comprises mixing a dielectric material with an additive comprising a small molecule or an oligomer to form a dielectric material mixture, and coating the dielectric material mixture on the patterned conductive layer to form the dielectric layer, and Forming the nanostructure layer composed of polycrystalline copper oxide between the dielectric layer and the patterned conductive layer includes subjecting the dielectric layer and the patterned conductive layer to a heat treatment to form the nanostructure layer composed of metal oxide between the dielectric layer and the patterned conductive layer, wherein during the heat treatment, the additive contained in the dielectric layer interacts with the patterned conductive layer to form the nanostructure layer composed of metal oxide.

14. The method according to claim 12, before encapsulating the semiconductor die, further comprising: include: forming a plurality of through-holes, the plurality of through-holes being arranged beside the semiconductor die, wherein the plurality of through-holes are electrically connected to the semiconductor die through the redistribution wiring structure, Wherein encapsulating the semiconductor die further comprises encapsulating the plurality of through-holes in the insulating encapsulation body.

15. The method according to claim 12, after forming the redistribution wiring structure, further comprising: include: One or more semiconductor devices are disposed on the redistribution wiring structure and the one or more semiconductor devices are electrically connected to the redistribution wiring structure.

16. A packaging structure, include: Semiconductor die; as well as A redistribution wiring structure is disposed on the semiconductor die and electrically connected to the semiconductor die, and includes: patterning a conductive layer; a dielectric layer disposed on the patterned conductive layer; and An interlayer film is sandwiched between the dielectric layer and the patterned conductive layer, wherein the patterned conductive layer is separated from the dielectric layer by the interlayer film, wherein the interlayer film includes an adhesive layer, and the adhesive layer is formed by bringing an adhesive precursor into contact with the patterned conductive layer and then performing a thermal process to form a bond therebetween, and the adhesive precursor includes a compound represented by the following chemical formula: in: Ar represents an aromatic ring selected from the group consisting of aromatic rings represented by the following chemical formulas (1) to (34): R 1 represents a hydrogen atom, an alkyl group or an aromatic ring, R 2 and R 3 each independently represents a substituted alkylene group or an unsubstituted alkylene group, wherein n1 and n2 are each independently an integer from 1 to 30, and X and Y each independently represent -H, -OH, -SH, -F, -Cl, -Br, -I, a carboxyl group, an ester group, an amine group, a quaternary ammonium cation, a trimethylsilyl group, a triethylsilyl group, a sulfone group, a carbonyl group, a carbonate group, an amide group or an epoxy group.

17. The packaging structure according to claim 16, further comprising: include: The seed layer, wherein the patterned conductive layer is disposed on the seed layer, and the patterned conductive layer is wrapped by the seed layer and the interlayer film. 18 . The package structure according to claim 16 , wherein a first surface of the interlayer film physically contacts the patterned conductive layer, a second surface of the interlayer film physically contacts the dielectric layer, and the first surface is opposite to the second surface. 19 . The package structure according to claim 16 , wherein a thickness of the interlayer film is greater than or substantially equal to 50 nanometers and less than or substantially equal to 350 nanometers.

20. The packaging structure according to claim 16, further comprising: include: an insulating encapsulant encapsulating the semiconductor die, wherein a surface of the insulating encapsulant is substantially coplanar with a surface of the semiconductor die, and the redistribution wiring structure is disposed on the surface of the insulating encapsulant substantially coplanar with the surface of the semiconductor die; as well as A plurality of conductive elements are located on the redistribution wiring structure and electrically connected to the redistribution wiring structure, wherein the redistribution wiring structure is located between the insulating enclosure and the plurality of conductive elements.

21. The packaging structure according to claim 16, further comprising: include: a plurality of through-vias arranged beside the semiconductor die and electrically connected to the redistribution wiring structure, wherein the plurality of through-vias are electrically connected to the semiconductor die through the redistribution wiring structure; an insulating encapsulant encapsulating the semiconductor die and the plurality of through-holes, wherein a surface of the insulating encapsulant is substantially coplanar with a surface of the semiconductor die and a surface of the plurality of through-holes, and the redistribution wiring structure is disposed on the surface of the insulating encapsulant substantially coplanar with the surface of the semiconductor die and the surface of the plurality of through-holes; as well as A plurality of conductive elements are located on the redistribution wiring structure and electrically connected to the redistribution wiring structure, wherein the redistribution wiring structure is located between the insulating enclosure and the plurality of conductive elements.

22. The packaging structure according to claim 16, further comprising: include: One or more semiconductor devices are disposed on the redistribution wiring structure and electrically connected to the redistribution wiring structure, wherein the one or more semiconductor devices are electrically connected to the semiconductor die through the redistribution wiring structure.

23. A method for manufacturing a packaging structure, include: providing a semiconductor die having a plurality of conductive terminals; forming a redistribution wiring structure on the semiconductor die, wherein the redistribution wiring structure is electrically connected to the semiconductor die, and forming the redistribution wiring structure comprises: depositing a first dielectric layer on the semiconductor die, the first dielectric layer exposing portions of the plurality of conductive terminals; forming a patterned conductive layer on the first dielectric layer and connecting the patterned conductive layer to the portions of the plurality of conductive terminals exposed through the first dielectric layer; Forming a first interlayer film on the patterned conductive layer, wherein the first interlayer film conformally covers the patterned conductive layer, wherein forming the first interlayer film comprises: Applying an adhesive precursor on the patterned conductive layer to form the first interlayer film on the patterned conductive layer, wherein a bond is formed between the adhesive precursor and the patterned conductive layer, and the adhesive precursor includes a compound represented by the following chemical formula: in: Ar represents an aromatic ring selected from the group consisting of aromatic rings represented by the following chemical formulas (1) to (34): R 1 represents a hydrogen atom, an alkyl group or an aromatic ring, R 2 and R 3 Each independently represents a substituted alkylene group or an unsubstituted alkylene group, wherein n1 and n2 are each independently an integer from 1 to 30, and X and Y each independently represent -H, -OH, -SH, -F, -Cl, -Br, -I, a carboxyl group, an ester group, an amine group, a quaternary ammonium cation, a trimethylsilyl group, a triethylsilyl group, a sulfonyl group, a carbonyl group, a carbonate group, an amide group or an epoxy group; removing portions of the adhesive precursor that are not bonded to the patterned conductive layer by washing; and Drying the first interlayer film; depositing a second dielectric layer on the first interlayer film, wherein the patterned conductive layer is separated from the second dielectric layer by the first interlayer film; and A plurality of conductive elements are formed on the redistribution wiring structure to electrically connect the plurality of conductive elements to the redistribution wiring structure.

24. The method according to claim 23, further comprising forming a second interlayer film on the plurality of conductive terminals, wherein the second interlayer film is formed include: Applying an adhesive precursor on the plurality of conductive terminals to form the second interlayer film on the patterned conductive layer, wherein the adhesive precursor forms a bond with the plurality of conductive terminals, and the adhesive precursor includes a compound represented by the following chemical formula: in: Ar represents an aromatic ring selected from the group consisting of aromatic rings represented by the following chemical formulas (1) to (34): R 1 represents a hydrogen atom, an alkyl group or an aromatic ring, R 2 and R 3 Each independently represents a substituted alkylene group or an unsubstituted alkylene group, wherein n1 and n2 are each independently an integer from 1 to 30, and X and Y each independently represent -H, -OH, -SH, -F, -Cl, -Br, -I, a carboxyl group, an ester group, an amine group, a quaternary ammonium cation, a trimethylsilyl group, a triethylsilyl group, a sulfonyl group, a carbonyl group, a carbonate group, an amide group or an epoxy group; removing portions of the adhesive precursor that are not bonded to the plurality of conductive terminals by washing; and The second interlayer film is dried.

25. The method according to claim 23, before forming the redistribution wiring structure, further comprising: include: The semiconductor die is encapsulated in an insulating encapsulation.

26. The method of claim 25, before encapsulating the semiconductor die, further comprising: include: forming a plurality of through-holes, the plurality of through-holes being arranged beside the semiconductor die, wherein the plurality of through-holes are electrically connected to the semiconductor die through the redistribution wiring structure, Wherein encapsulating the semiconductor die further comprises encapsulating the plurality of through-holes in the insulating encapsulation body.

27. The method according to claim 23, after forming the redistribution wiring structure, further comprising: include: One or more semiconductor devices are disposed on the redistribution wiring structure and the one or more semiconductor devices are electrically connected to the redistribution wiring structure.

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