Integrated circuit memory and method for forming the same

Abstract

The present invention provides an integrated circuit memory and a method for forming the same. An insulating structure is formed in a trench isolation structure between two word lines corresponding to the same active area, and the dielectric constant of the material of the insulating structure is smaller than the dielectric constant of the material of the trench isolation structure, thereby reducing the parasitic capacitance between the two word lines corresponding to the same active area and improving the performance and stability of the integrated circuit memory.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to an integrated circuit memory and a method for forming the same. Background Art

[0002] Existing integrated circuit memory chips usually include several access transistors. In order to reduce the area of ​​the integrated circuit memory to achieve maximum integration, a trench transistor structure is usually used, and two transistors with a common drain can be made in one active area to further reduce the area and reduce production costs. However, in this way, the distance between the two transistors is very close, and a large parasitic capacitance will be generated between their word lines, affecting the performance and stability of the device. Summary of the invention

[0003] The object of the present invention is to provide an integrated circuit memory and a method for forming the same, which can reduce the parasitic capacitance between two word lines corresponding to the same active area by reducing the dielectric constant of the dielectric between the two word lines, thereby improving the performance and stability of the device.

[0004] In order to achieve the above object, the present invention provides an integrated circuit memory, characterized in that the integrated circuit memory comprises:

[0005] A substrate having a plurality of trench isolation structures formed therein, wherein the trench isolation structures define a plurality of active regions,

[0006] A plurality of word lines arranged in parallel are formed in the substrate, and the word lines intersect with corresponding active regions and extend into the trench isolation structure, and each active region intersects with two word lines;

[0007] A plurality of insulating structures are formed in the trench isolation structure and are located between two word lines corresponding to the same active area, and the dielectric constant of the material of the insulating structure is smaller than the dielectric constant of the material of the trench isolation structure.

[0008] Optionally, the multiple active areas are arranged in an array, and the multiple active areas in the same column intersect with the same two word lines, so that two adjacent active areas in the same column and the two word lines surround an insulating area in the trench isolation structure, and the insulating structure is formed in the insulating area of ​​the trench isolation structure.

[0009] Optionally, the insulating structure includes an insulating material layer formed in an insulating trench, and the dielectric constant of the material of the insulating material layer is less than 4.

[0010] Optionally, the insulating structure further includes a stress buffer layer, wherein the stress buffer layer covers the sidewalls and the bottom wall of the insulating trench, and the insulating material layer is formed on the stress buffer layer and fills the insulating trench.

[0011] Optionally, the material of the insulating material layer includes one or more of free silicon oxide material, silicon carbide oxide, fluorine silicon glass, carbon-doped glass and organic polymer.

[0012] Optionally, in the extension direction of the word line, two adjacent insulating structures are separated by one active region.

[0013] Optionally, the active area is used to form two storage units of the integrated circuit memory, a drain region and two source regions are formed in each of the active areas, the two source regions are respectively located on both sides of the drain region, each of the storage units has an access transistor, and the two access transistors share the drain region.

[0014] The present invention also provides a method for forming an integrated circuit memory, comprising:

[0015] Providing a substrate, wherein a plurality of trench isolation structures are formed in the substrate, wherein the trench isolation structures define a plurality of active regions extending along a first direction;

[0016] Forming a plurality of insulating trenches in the trench isolation structure, wherein the plurality of insulating trenches are arranged along a second direction, and virtual lines corresponding to the plurality of insulating trenches arranged on the same straight line intersect with the active area;

[0017] Filling an insulating material layer in the insulating trench to form an insulating structure, wherein the dielectric constant of the material of the insulating material layer is smaller than the dielectric constant of the material of the trench isolation structure; and

[0018] A plurality of word lines extending along the second direction are formed in the substrate, the word lines intersect with corresponding active areas and extend into the trench isolation structure, each of the active areas intersects with two of the word lines, wherein two word lines corresponding to the same active area are respectively located on both sides of the insulating structure in the trench isolation structure.

[0019] Optionally, the step of forming a plurality of the insulating structures includes:

[0020] Forming a first mask layer extending along a second direction on the substrate, wherein a first opening corresponding to an insulating region and a portion of the active region is formed in the first mask layer, and the insulating region is used to form the insulating structure;

[0021] Etching the insulating region below the first opening to form a plurality of insulating trenches arranged along the second direction in the trench isolation structure; and,

[0022] An insulating material layer is filled in the insulating trench to form the insulating structure.

[0023] Optionally, the step of filling the insulating material layer in the insulating trench to form the insulating structure includes:

[0024] forming a stress buffer layer on the sidewalls and bottom wall of the insulating trench; and,

[0025] The insulating material layer is formed on the stress buffer layer, the insulating material layer fills the insulating trench, and the stress buffer layer and the insulating material layer together constitute the insulating structure.

[0026] Optionally, the step of forming the first mask layer includes:

[0027] forming a second mask layer extending along a second direction on the substrate, wherein the second mask layer covers a word line region;

[0028] forming a third mask layer on the substrate, wherein the third mask layer is adjacent to the second mask layer and constitutes the first mask layer with the second mask layer;

[0029] And, after forming the insulating structure, the step of forming the word line in the substrate includes:

[0030] Filling the first opening with a fourth mask layer and removing the second mask layer to form a second opening corresponding to the word line region;

[0031] Etching a word line region below the second opening to form a word line trench in the substrate;

[0032] A word line is formed in the word line trench.

[0033] Optionally, a material of the fourth mask layer is the same as a material of the third mask layer.

[0034] In the integrated circuit memory and the method for forming the same provided by the present invention, an insulating structure is formed in the trench isolation structure between the two word lines corresponding to the active area, and the dielectric constant of the material of the insulating structure is smaller than the dielectric constant of the material of the trench isolation structure, thereby reducing the parasitic capacitance between the two word lines corresponding to the same active area, thereby improving the performance and stability of the integrated circuit memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A top view of an integrated circuit memory provided by an embodiment of the present invention;

[0036] Figure 2 Integrated circuit memory provided by an embodiment of the present invention Figure 1 A local cross-sectional view obtained by cutting along the height direction at D-D';

[0037] Figure 3 A flowchart of a method for forming an integrated circuit memory provided by an embodiment of the present invention;

[0038] Figure 4-Figure 12 A partial cross-sectional view of a semiconductor structure formed by the method for forming an integrated circuit memory provided by an embodiment of the present invention;

[0039] The reference numerals are as follows:

[0040] 1-substrate; 11-trench isolation structure; 12-active region, 121-drain region, 122-source region;

[0041] 2-word line; 21-word line groove;

[0042] 3-insulating structure; 31-insulating groove; 32-insulating material layer;

[0043] 41-a second mask layer; 42-a fifth mask layer;

[0044] 43- a third mask layer; 44- a fourth mask layer;

[0045] 51-first opening; 52-second opening;

[0046] a-first direction; b-second direction. DETAILED DESCRIPTION

[0047] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0048] Figure 1 and Figure 2 A schematic diagram of the structure of the integrated circuit memory provided in this embodiment, such as Figure 1 and Figure 2 As shown, the integrated circuit memory includes a substrate 1, in which a plurality of trench isolation structures 11 are formed, and the trench isolation structures 11 define a plurality of active areas 12; a plurality of parallel word lines 2 are formed in the substrate 1, and the word lines 2 intersect with the corresponding active areas 12 and extend into the trench isolation structures 11, and each of the active areas 12 intersects with two of the word lines 2; a plurality of insulating structures 3 are formed in the trench isolation structures 11, and the dielectric constant of the material of the insulating structures 3 is smaller than the dielectric constant of the material of the trench isolation structures 11.

[0049] For the convenience of description, the two word lines 2 corresponding to the same active area 12 are defined as two adjacent word lines 2 herein, and the word lines 2 not corresponding to the same active area 12 are not adjacent. Figure 1 There are three pairs of adjacent word lines 2.

[0050] For details, please refer to Figure 1 , a plurality of trench isolation structures 11 are formed in the substrate 1, the trench isolation structures 11 separate the adjacent active areas 12 so that the active areas are arranged in an array of multiple rows and columns, the trench isolation structures 11 generally include a silicon oxide layer formed in the isolation trench, the active areas 12 are surrounded by the trench isolation structures 11, each of the active areas 12 includes two source areas 121 and a drain area 122, the drain area 122 is located between the two source areas 121, a plurality of parallel word lines 2 are located in the substrate 1, and each of the active areas 12 is passed through by two adjacent word lines 2, wherein the two adjacent word lines 2 respectively pass through the portion between the source area 121 and the drain area 122 in the active area 12 to separate each of the source area 121 and the drain area 122, and two access transistors are formed in each of the active areas, and the two access transistors share the drain area 122.

[0051] For further information, see Figure 2 , Figure 8 and Fig. 9 , the insulating structure 3 is located in the trench isolation structure 11 on both sides of each active area 12, and is located between two adjacent word lines 2. Specifically, the multiple active areas 12 are arranged in an array, and the multiple active areas 12 in the same column intersect with the same two word lines 2, so that the two adjacent active areas 12 in the same column and the two word lines 2 surround an insulating area in the trench isolation structure 11, and the insulating structure 3 is formed in the insulating area of ​​the trench isolation structure 11.

[0052] The insulating structure 3 includes an insulating material layer 32 formed in an insulating trench 31. The insulating material layer 32 is made of a low-K material with a dielectric constant less than 4, such as one or more of free silicon oxide, silicon carbide oxide, fluorine silicon glass, carbon-doped glass and organic polymer. It can be understood that since the insulating structure 3 is made of a low-K material and is located between two adjacent word lines 2, the parasitic capacitance between the two adjacent word lines 2 can be effectively reduced, thereby improving the performance of the device.

[0053] Further, if Figure 2As shown, the insulating structure 3 can be sunken deeper into the substrate 1 than the word line 2, and in the extension direction of the word line 2 (i.e., the second direction b), two adjacent insulating structures 3 are separated by an active area 12 (i.e., the two word lines 2 corresponding to the same active area 12 are all separated by the insulating structure 3 except the drain area 122), so that the area of ​​the insulating structure 3 is larger, which can further reduce the parasitic capacitance between the two adjacent word lines 2.

[0054] Optionally, the insulating structure 3 may further include a stress buffer layer (not shown), which covers the side walls and bottom walls of the insulating groove 31. The insulating material layer 32 is formed on the stress buffer layer and fills the insulating groove 31 to buffer and match the stress between film layers.

[0055] like Figure 3 As shown, this embodiment provides a method for forming an integrated circuit memory, comprising:

[0056] S1: forming a plurality of insulating trenches in the trench isolation structure, wherein the plurality of insulating trenches are arranged along a second direction, and virtual lines corresponding to the plurality of insulating trenches arranged on the same straight line intersect with the active area;

[0057] S2: filling an insulating material layer in the insulating trench to form an insulating structure, wherein the dielectric constant of the material of the insulating material layer is smaller than the dielectric constant of the material of the trench isolation structure;

[0058] S3: forming a plurality of word lines extending along the second direction in the substrate, wherein the word lines intersect with corresponding active areas and extend into the trench isolation structure, wherein each active area intersects with two word lines, wherein two word lines corresponding to the same active area are respectively located on both sides of the insulating structure in the trench isolation structure.

[0059] For details, please refer to Figure 1 , providing the substrate 1, in which a plurality of trench isolation structures 11 are formed, the trench isolation structures 11 define a plurality of active areas 12 extending along a first direction a, that is, each of the active areas 12 is surrounded by the trench isolation structures 11, so that the plurality of active areas 12 are isolated from each other, a drain area 122 and two source areas 121 are formed in each of the active areas 12, the two source areas 121 are respectively located on both sides of the drain area 122, the active areas are used to form two storage units of the integrated circuit memory, each of the storage units has an access transistor, and the two access transistors share the drain 122.

[0060] Then, if Figure 4-Figure 8As shown in FIG. 1 , a first mask layer extending along a second direction b is formed on the substrate 1, and the first mask layer is used as a mask to form the insulating trench 31. Specifically, the steps of forming the first mask layer include: first, Figure 4 As shown, a second mask layer 41 is formed on the substrate 1, and the second mask layer 41 covers a portion of the substrate 1 corresponding to a word line region, and the word line region is used to form a word line. It can be understood that the second mask layer 41 is in a strip shape and extends along the second direction b; then as shown Figure 5 As shown, a fifth mask layer 42 extending along the second direction b is formed on the substrate 1, and the fifth mask layer 42 covers the substrate 1 between two adjacent word line regions; then as shown Figure 6 As shown, a third mask layer 43 extending along the second direction b is formed on the substrate 1, the third mask layer 43 is adjacent to the second mask layer 41 and covers the remaining substrate 1; finally, as shown Figure 7 As shown, etching is performed to remove the fifth mask layer 42, and the second mask layer 41 and the third mask layer 43 are retained to form a first mask layer. It can be understood that after the fifth mask layer 42 is removed, the area covered by the fifth mask layer 42 is opened to form a first opening 51, which can be regarded as the first opening 51 formed in the first mask layer. The first opening 51 simultaneously exposes the drain region 122 and the insulating region, and the insulating region is used to form the insulating structure.

[0061] Next, if Figure 8 As shown, the insulating region is etched using the first mask layer as a mask to form an insulating trench 31 in the trench isolation structure 11. The insulating trench 31 may penetrate the entire trench isolation structure 11 or may not penetrate the trench isolation structure 11, which is not limited in the present invention. Fig. 9 As shown, a low-K material is filled in the insulating trench 31 to form an insulating material layer 32 , thereby finally forming the insulating structure 3 .

[0062] It is understandable that if Figure 1 and Figure 8 As shown, since the first opening 51 also corresponds to the drain region 122, when etching the insulating region to form the insulating trench 31, it is necessary to select an etchant with a high selectivity ratio for the material of the drain region 122 and the material of the trench isolation structure 11, so that the trench isolation structure 11 is etched to produce the insulating trench 31 but the effect on the drain region 122 is very small, so that the formed insulating trenches 31 are arranged on both sides of the drain region 122.

[0063] As a preferred solution, before forming the isolation material layer 32, a stress buffer layer can be first formed on the side walls and bottom walls of the insulating groove 31; and then the insulating material layer 32 is formed on the stress buffer layer, and the insulating material layer 32 fills the insulating groove 31. The stress buffer layer and the insulating material layer 32 together constitute the insulating structure 3. The stress buffer layer can play a role in stress matching and buffering, so that the stability between each film layer is better.

[0064] Further, if Fig.10 As shown, in order to form the word line, the first opening 51 may be filled with a fourth mask layer 44 extending along the second direction b. Then the second mask layer 41 is directly removed to form a second opening 52, which corresponds to the word line region.

[0065] Finally Figure 11-Figure 12 As shown, the third mask layer 43 and the fourth mask layer 44 are used as masks to etch the word line region to form a word line groove 21, and then a word line 2 is formed in the word line groove 21. Optionally, the word line 2 includes a gate dielectric layer and a gate conductive layer. The word line groove 21 is formed in the substrate 1 and passes through the portion between the drain region 122 and the source region 121. The gate dielectric layer covers the sidewalls and bottom wall of the word line groove 21. The gate conductive layer is formed on the gate dielectric layer and fills the word line groove 21. Finally, the third mask layer 43 and the fourth mask layer 44 are removed to form a Figure 2 The semiconductor structure shown.

[0066] Furthermore, the third mask layer 43 and the fourth mask layer 44 may be made of the same material, so as to achieve the effect of removing the second mask layer 41 and retaining the third mask layer 43 and the fourth mask layer 44 .

[0067] It can be understood that, in the present embodiment, since the first mask layer is composed of the second mask layer 41 and the third mask layer 43, when the word line 2 is formed after the insulating structure 3 is formed, the word line 2 can be formed by directly stripping off the second mask layer 41, and there is no need to form a new mask layer, thereby simplifying the process. It can also be understood that when forming the insulating structure 3 in the present embodiment, there is no need to redesign a new mask in the original process. On the basis of a relatively simple process, the performance of the device can be greatly improved.

[0068] In summary, in the integrated circuit memory and the method for forming the same provided in the embodiments of the present invention, an insulating structure is formed in the trench isolation structure between the two word lines corresponding to the active area, and the dielectric constant of the material of the insulating structure is smaller than the dielectric constant of the material of the trench isolation structure, thereby reducing the parasitic capacitance between the two word lines corresponding to the same active area, and improving the performance and stability of the integrated circuit memory.

[0069] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. An integrated circuit memory, characterized in that: The integrated circuit memory comprises: A substrate having a plurality of trench isolation structures formed therein, wherein the trench isolation structures define a plurality of active regions, A plurality of word lines arranged in parallel are formed in the substrate, and the word lines intersect with corresponding active regions and extend into the trench isolation structure, and each active region intersects with two word lines; A plurality of insulating structures are formed in the trench isolation structure and are located between two word lines corresponding to the same active area, and the dielectric constant of the material of the insulating structure is smaller than the dielectric constant of the material of the trench isolation structure.

2. The integrated circuit memory according to claim 1, wherein: The multiple active areas are arranged in an array, and the multiple active areas in the same column intersect with the same two word lines, so that two adjacent active areas in the same column and the two word lines surround an insulating area in the trench isolation structure, and the insulating structure is formed in the insulating area of ​​the trench isolation structure.

3. The integrated circuit memory according to claim 2, wherein: The insulating structure includes an insulating material layer formed in an insulating trench, and the dielectric constant of the material of the insulating material layer is less than 4.

4. The integrated circuit memory according to claim 3, wherein: The insulating structure further includes a stress buffer layer, which covers the sidewalls and the bottom wall of the insulating trench. The insulating material layer is formed on the stress buffer layer and fills the insulating trench.

5. The integrated circuit memory according to claim 3, wherein: The material of the insulating material layer includes one or more of free silicon oxide material, silicon carbide oxide, fluorine silicon glass, carbon-doped glass and organic polymer.

6. The integrated circuit memory according to claim 1, wherein: In the extending direction of the word line, two adjacent insulating structures are separated by one active region.

7. The integrated circuit memory according to claim 5, wherein: The active area is used to form two storage units of the integrated circuit memory, and a drain area and two source areas are formed in each of the active areas. The two source areas are respectively located on both sides of the drain area. Each of the storage units has an access transistor, and the two access transistors share the drain area.

8. A method for forming an integrated circuit memory, characterized in that: include: Providing a substrate, wherein a plurality of trench isolation structures are formed in the substrate, wherein the trench isolation structures define a plurality of active regions extending along a first direction; Forming a plurality of insulating trenches in the trench isolation structure, wherein the plurality of insulating trenches are arranged along a second direction, and virtual lines corresponding to the plurality of insulating trenches arranged on the same straight line intersect with the active area; Filling an insulating material layer in the insulating trench to form an insulating structure, wherein the dielectric constant of the material of the insulating material layer is smaller than the dielectric constant of the material of the trench isolation structure; and A plurality of word lines extending along the second direction are formed in the substrate, the word lines intersect with corresponding active areas and extend into the trench isolation structure, each of the active areas intersects with two of the word lines, wherein two word lines corresponding to the same active area are respectively located on both sides of the insulating structure in the trench isolation structure.

9. The method for forming an integrated circuit memory according to claim 8, wherein: The steps of forming a plurality of the insulating structures include: Forming a first mask layer extending along a second direction on the substrate, wherein a first opening corresponding to an insulating region and a portion of the active region is formed in the first mask layer, and the insulating region is used to form the insulating structure; Etching the insulating region below the first opening to form a plurality of insulating trenches arranged along the second direction in the trench isolation structure; and, An insulating material layer is filled in the insulating trench to form the insulating structure.

10. The method for forming an integrated circuit memory according to claim 9, wherein: The step of filling the insulating material layer in the insulating trench to form the insulating structure includes: forming a stress buffer layer on the sidewalls and bottom wall of the insulating trench; and, The insulating material layer is formed on the stress buffer layer, the insulating material layer fills the insulating trench, and the stress buffer layer and the insulating material layer together constitute the insulating structure.

11. The method for forming an integrated circuit memory according to claim 9, wherein: The step of forming the first mask layer comprises: forming a second mask layer extending along a second direction on the substrate, wherein the second mask layer covers a word line region; forming a third mask layer on the substrate, wherein the third mask layer is adjacent to the second mask layer and constitutes the first mask layer with the second mask layer; And, after forming the insulating structure, the step of forming the word line in the substrate includes: Filling the first opening with a fourth mask layer and removing the second mask layer to form a second opening corresponding to the word line region; Etching a word line region below the second opening to form a word line trench in the substrate; A word line is formed in the word line trench.

12. The method for forming an integrated circuit memory according to claim 11, wherein: The material of the fourth mask layer is the same as that of the third mask layer.

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