Storage devices and systems

Abstract

A storage device includes: a storage area in which first data is stored and the storage area is accessed using a first virtual address; and a memory controller configured to control the storage data stored in the storage area. The memory controller predicts second data to be accessed using a second virtual address based on the first virtual address, pre-fetches the second data into an external device, and modifies a physical address mapped to the second virtual address so that a host communicating with the storage device can access the pre-fetched second data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0109068 filed on September 12, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Exemplary embodiments of the present disclosure relate to data access in a storage device and a storage system. Background Art

[0004] The storage system includes a main memory device that allows fast access but may be small and expensive, and an auxiliary memory device that allows relatively slow access but has a large capacity and is cheap. An example of a main memory device is a dynamic random access memory (DRAM). Examples of auxiliary memory devices include block storage devices such as hard disk drives (HDDs) and solid-state drives (SSDs), and byte-accessible storage devices such as phase-change memory random access memory (PRAM) and spin transfer torque magnetic random access memory (STT-MRAM).

[0005] In order to take advantage of the fast access time of the main memory device, data in the frequently accessed auxiliary memory device can be read from the storage device and pre-fetched into the main memory device. Examples of such pre-fetching techniques include: modifying the host or application, or adding a separate layer for accessing the pre-fetched main memory device. However, these techniques require additional resources or a separate layer to operate, which may result in increased complexity and manufacturing costs. Summary of the invention

[0006] Exemplary embodiments of the present disclosure provide a storage device having improved operation performance.

[0007] Exemplary embodiments of the present disclosure also provide a storage system having improved operation performance.

[0008] According to an exemplary embodiment of the present disclosure, a storage device includes: a storage area, storing first data in the storage area, and accessing the storage area using a first virtual address; and a memory controller configured to control the storage data stored in the storage area. The memory controller predicts second data to be accessed using a second virtual address based on the first virtual address, pre-fetches the second data into an external device, and modifies a physical address mapped to the second virtual address. The pre-fetched second data can be accessed by a host communicating with the storage device.

[0009] According to an exemplary embodiment of the present disclosure, a storage system includes: a first storage device configured to store first data. A host uses a first virtual address to access the first data at a first speed. The storage system also includes: a second storage device configured to store second data. The host uses a second virtual address to access the second data at a second speed. The second virtual address is different from the first virtual address, and the second speed is different from the first speed. The second storage device predicts predicted data to be accessed by the host based on the second virtual address, and pre-fetches the predicted data into the first storage device.

[0010] According to an exemplary embodiment of the present disclosure, a storage system includes: a first storage device configured to store first data. A host accesses the first data using a first virtual address. The storage system also includes: a second storage device configured to store second data. The host accesses the second data using a second virtual address and a third virtual address. The second virtual address and the third virtual address are different from the first virtual address, and the second virtual address and the third virtual address are adjacent to each other. The second storage device predicts predicted data that the host is to access using a fourth virtual address adjacent to the third virtual address based on the second virtual address and the third virtual address, and pre-fetches the predicted data into the first storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating an address translation operation when a host accesses a memory device.

[0013] Figure 2 is a diagram showing address translation using a page table.

[0014] Figure 3 is a block diagram of a storage device according to an exemplary embodiment of the present disclosure.

[0015] Figure 4 is a flow chart illustrating a prefetch operation of a storage device.

[0016] Figure 5 is a flow chart illustrating the operation of a storage device when it receives a request to read data from a host.

[0017] Figure 6 It is shown Figure 4 Flowchart of the address prediction operation.

[0018] Figure 7 It is shown Figure 6 Block diagram of the address prediction operation.

[0019] Figure 8is a block diagram illustrating a physical address modification operation.

[0020] Fig. 9 is a diagram showing an exemplary embodiment according to the present disclosure. Figure 3 Another block diagram of a physical address modification operation performed by a memory controller.

[0021] Fig.10 is a diagram showing an exemplary embodiment according to the present disclosure. Figure 3 Another block diagram of a physical address modification operation performed by a memory controller.

[0022] Fig.11 It is shown that according to the above reference Figure 4 A block diagram depicting the process of a host accessing predicted data for a prefetch operation.

[0023] Fig.12 is a block diagram of a storage device according to an exemplary embodiment of the present disclosure.

[0024] Fig.13 It is shown Fig.12 A flowchart of the operation of a storage device.

[0025] Fig.14 is a block diagram of a storage device according to an exemplary embodiment of the present disclosure.

[0026] Fig.15 It is shown Fig.14 A flowchart of the operation of a storage device.

[0027] Fig.16 is a block diagram of a storage system according to an exemplary embodiment of the present disclosure.

[0028] Fig.17 It is shown Fig.16 A flow chart of the operation of a storage system.

[0029] Fig.18 It is shown Fig.16 Block diagram of a prefetch operation of a storage system.

[0030] Fig.19 It is shown Fig.16 A block diagram of a physical address modification operation of a storage system.

[0031] Fig. 20 is a block diagram of a storage system according to an exemplary embodiment of the present disclosure.

[0032] Fig.21 is a block diagram of a storage system according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] Exemplary embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings.The same reference numerals throughout the drawings may represent the same elements.

[0034] It should be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, in another exemplary embodiment, the "first" element in the exemplary embodiment can be described as the "second" element.

[0035] It will be further understood that descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

[0036] Figure 1 is a block diagram illustrating an address translation operation when a host accesses a memory device. Figure 2 is a diagram showing address translation using a page table.

[0037] refer to Figure 1 and Figure 2 , the host 100 can access the memory 124 with the help of, for example, the memory management unit 104 and the page table 150.

[0038] The host 100 may be implemented as, but not limited to, a host processor, an integrated circuit (IC), a mainboard, a system on chip (SoC), an application processor (AP), a mobile AP, a web server, a data server, or a database server.

[0039] In an exemplary embodiment, when the host 100 accesses the memory 124, the central processing unit (CPU) 130 may send a virtual memory address to the memory management unit 104. The memory management unit 104 may be implemented as a hardware component including, for example, a circuit. However, it should be understood that the exemplary embodiments of the present disclosure are not limited thereto. For example, in an exemplary embodiment, the memory management unit 104 may also be implemented as a software component for performing a specific function.

[0040] The memory management unit 104 converts virtual addresses to physical addresses and may perform functions such as memory protection, cache management, and bus arbitration. Additionally, in an exemplary embodiment, the memory management unit 104 may be responsible for bank switching in an 8-bit architecture.

[0041] The kernel 110 may allocate hardware resources between processes as needed. The kernel 110 is a component that executes system calls, process control, memory control, etc. required by programs such as an operating system, and may operate under the control of the operating system. The kernel 110 may also manage memory devices such as main memory devices and auxiliary memory devices in a virtual address space within the system. For example, when the host 100 accesses a device, the host 100 may access the device using a virtual address provided by the kernel 110 instead of a physical address. The kernel 110 may be included in the host 100.

[0042] Virtual addresses allow the system to effectively create a virtual memory space that is larger than the actual physical memory space. The process of dividing the actual memory space into virtual memory space is called paging.

[0043] The kernel 110 may utilize the memory management unit 104 to perform translations between virtual addresses and physical addresses. The kernel 110 may manage n The mapping unit of the virtual address space is a page of bit size (e.g., 4KB), where n is a natural number. Some virtual pages can be associated with a single page physical address. When the host 100 issues an access request, the CPU 130 can send the virtual address to the memory management unit 104.

[0044] In order to access data stored in the memory 124, the virtual address must be converted to a physical address. To this end, a page table 150 may be used, which is a translation table stored in the system memory. The page table 150 has a large size, so the page table 150 may be stored in the system memory (e.g., the memory management unit 104). The memory management unit 104 may convert the virtual address to a physical address.

[0045] The page table 150 may be a data structure used in a paging technique. The page table 150 may store page information of a process. Each process may have a single page table 150. The page table 150 may include indexes corresponding to page numbers, respectively. In addition, the page table 150 may store information including physical memory addresses assigned to pages. The operation of the page table 150 may differ depending on the architecture and operating system.

[0046] Accessing the page table 150 stored in the system memory (e.g., the memory management unit 104) may be a factor that slows down the overall system performance. Therefore, the memory management unit 104 may cache a portion of the page table 150 that has been recently used in the translation lookaside buffer (TLB) 108. By caching a portion of the page table 150 in the translation lookaside buffer 108, access latency to the page table 150 may be reduced. The translation lookaside buffer 108 may include physical address information or index information for data stored in the memory 124. For example, the CPU 130 may scan the translation lookaside buffer 108 to determine whether there is data to be accessed in the memory 124.

[0047] The conversion lookaside buffer 108 may be a special type of high-speed cache memory. Like other types of high-speed cache memories, the conversion lookaside buffer 108 may be implemented as a memory device with a relatively small capacity that is specially designed for fast access. For example, the conversion lookaside buffer 108 may have a relatively small capacity and a relatively fast access speed. Therefore, if the capacity of the conversion lookaside buffer 108 is fully used, old conversion information may be removed and new conversion information may be added.

[0048] The translation lookaside buffer 108 may include a data array and a tag array provided in a cache memory. In the tag array, each tag line stores a virtual address. The tag lines may then be associated with data lines in the data array, respectively, where a translation of a physical address associated with the virtual address is stored.

[0049] Assume that the host 100 accesses the memory 124. The CPU 130 may check whether the page table 150 including the translation information for converting the virtual address into the physical address is in the translation lookaside buffer 108, which can be quickly accessed by the memory management unit 104. If the page table 150 including the translation information is in the translation lookaside buffer 108, the host 100 may access the memory 124 using the physical address converted by the page table 150.

[0050] If the page table 150 is not found in the translation lookaside buffer 108 (if a translation lookaside buffer miss occurs), the translation lookaside buffer 108 and the memory management unit 104 share the page table 150. Therefore, the CPU 130 can access the translated physical address by using the page table 150 in the memory management unit 104.

[0051] Therefore, when the page table 150 is found in the translation lookaside buffer 108, the translated physical address may be used to achieve fast access.

[0052] There may be times when the CPU 130 cannot get a physical memory address from the page table 150. This is called a page fault or page miss. Typically, a page miss may occur because the page of the virtual address space is not in the memory 124. When this happens, the operating system may be responsible for handling it. The operating system may allocate the page in an empty memory space. If there is no empty memory space, the operating system may pull a page of real memory, store it in a secondary memory device (in a process called paging), and allocate the requested page there.

[0053] The bus 120 may be connected between the host 100 and the memory 124 and may facilitate communication between the host 100 and the memory 124. For example, data and requests may be transmitted through the bus 120. Thus, the host 100 may access a physical address in the memory 124 via the bus 120. Figure 2 In the illustrated page table 150, k is a natural number.

[0054] In the following description, it should be understood that when the host 100 is described as performing an access operation (eg, when the host 100 accesses or is accessing), the above-described operations are performed.

[0055] Figure 3 is a block diagram of a storage device according to an exemplary embodiment of the present disclosure.

[0056] Figure 2 The storage device 200 shown in FIG. 2 may include, for example, an interface 205 , a storage area 210 , and a memory controller 215 .

[0057] The host 100 may access the storage device 200 using the above-mentioned virtual address.

[0058] The storage device 200 may transmit / receive commands and / or data to / from the host 100 via the interface 205 .

[0059] The interface 205 may be implemented as, for example, a peripheral component interconnect (PCI) interface, a peripheral component interconnect express (PCIe) interface, a non-volatile memory express (NVMe) interface, a dual in-line memory module (DIMM) interface, etc., which provide byte accessibility. However, it should be understood that the interface 205 is not limited thereto. The interface 205 may transmit electrical signals or optical signals.

[0060] Data may be stored in a storage area 210 of the storage device 200. The storage area 210 may include, for example, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), a spin transfer torque magnetic random access memory (STT-MRAM), a ferroelectric random access memory (FeRAM), a NOR flash memory, or a NAND flash memory. However, it should be understood that the storage area 210 is not limited thereto.

[0061] In an exemplary embodiment, the storage area 210 may include block storage. In addition, in an exemplary embodiment, the interface 205 may be a byte-accessible interface that provides byte accessibility, such as a PCIe interface. In this case, the storage area 210 may include a byte-accessible storage device.

[0062] Data stored in the memory area 210 may be controlled by the memory controller 215. The memory controller 215 may receive an access request from the host 100 through the interface 205, thereby accessing the memory area 210. In this manner, the memory controller 215 may control transmission or processing of commands and / or data.

[0063] In an exemplary embodiment, the memory controller 215 may include a prefetcher 220 and an address prediction module 225. The prefetcher 220 and the address prediction module 225 may also be referred to as a prefetcher circuit and an address prediction circuit, respectively.

[0064] The prefetcher 220 may prefetch data frequently used by the host 100 and / or data predicted to be used next by the host 100 into another storage area (e.g., another external memory). As a result, the access time of the host 100 may be reduced. Here, the external device / memory may refer to a device / memory outside the storage device 200, and is described in further detail below.

[0065] Here, when data is described as being "pre-fetched" into a storage device, storage area, storage space, etc., it should be understood that the data is obtained from another location and stored in the storage device, storage area, storage space, etc.

[0066] The address prediction module 225 can predict in advance the data to be accessed next by the host 100. The prefetcher 220 can prefetch the data predicted by the address prediction module 225 into another space.

[0067] In the following, reference will be made to Figures 3 to 10 Describes a storage device (eg, Figure 3 operation of the storage device 200).

[0068] Figure 4 is a diagram showing a storage device (e.g., Figure 3 Flowchart of the pre-fetch operation of the storage device 200). Figure 5 is to show when a storage device (e.g., Figure 3 storage device 200) from a host (e.g., Figure 3 Flowchart of the operations when the host 100) receives a request to read data. Figure 6 It is shown Figure 4 Flowchart of the address prediction operation. Figure 7 It is shown Figure 6 Block diagram of the address prediction operation. Figure 8 is a block diagram illustrating a physical address modification operation. Fig. 9 is a diagram showing an exemplary embodiment according to the present disclosure. Figure 3 Another block diagram of the modification operation of the physical address performed by the memory controller 215. Fig.10 is a diagram showing an exemplary embodiment according to the present disclosure. Figure 3 Another block diagram of the modification operation of the physical address performed by the memory controller 215.

[0069] First, refer to Figure 4 , the host (for example, Figure 3 The host 100) uses the virtual address to access the storage device (for example, Figure 3 In an exemplary embodiment, the host 100 accesses the storage device 200 to request data, and the storage device 200 may return the requested data to the host 100. Hereinafter, reference will be made to Figure 3 and Figure 5 This operation is described in more detail.

[0070] First, refer to Figure 5 , the interface 205 of the storage device 200 receives a command and / or data from the host 100 (operation S210). Figure 3 When the host 100 accesses the storage device 200 , the interface 205 of the storage device 200 may read a command from the host 100 and send the command to the memory controller 215 of the storage device 200 .

[0071] Return to reference Figure 5 , the memory controller 215 may scan the storage area 210 to determine whether a command and / or data received from the host 100 exists in the storage area 210 (operation S220).

[0072] For example, refer to Figure 3 Once the memory controller 215 receives a command from the host 100 via the interface 205 , the memory controller 215 may check to determine whether data associated with the command received from the host 100 exists in the storage area 210 .

[0073] Return to reference Figure 5 If the data to be accessed by the host 100 is not found in the storage area 210 in operation S220, the memory controller 215 sends an access failure message to the host 100 via the interface 205 (operation S230).

[0074] For example, refer to Figure 3 If the memory controller 215 fails to find the data that the host 100 wants to access by scanning the storage area 210 , the memory controller 215 may send an access failure message to the host 100 via the interface 205 .

[0075] Return to reference Figure 5 If the data to be accessed by the host 100 is found in the storage area 210 in operation S220, the memory controller 215 reads the data from the storage area 210 (operation S240) and sends the data read in operation S240 to the host 100 via the interface 205 (operation S250).

[0076] For example, refer to Figure 3 If the memory controller 215 finds data that the host 100 wants to access in the storage area 210 , the memory controller 215 may send the data to the host 100 via the interface 205 .

[0077] Return to reference Figure 4 , the address prediction module 225 of the memory controller 215 predicts data to be accessed next by the host 100 based on the data accessed by the host 100 using the virtual address in operation S200 (operation S300 ).

[0078] Reference Figure 6 Operation S300 is described in more detail.

[0079] refer to Figure 6 , the host 100 accesses the data in the storage device 200, and the address prediction module 225 starts predicting the next data (operation S310). Operation S310 can be similar to the above reference Figure 4 Operation S200 described above is the same as, or may be the same as, the operation S200 described above. Figure 4 Operation S200 is described as a separate operation, depending on the implementation.

[0080] For example, refer to Figure 7 When the host 100 uses the virtual address to access the storage device 820, a read command may be sent to the storage device 820. The storage device 820 may be connected to the storage device 820. Figure 3 The storage device 200 shown in FIG. 8 is the same as or similar to the storage device 200 shown in FIG. Figure 7 Not shown, but can be used with Figure 3The memory controller 800 may be the same as or similar to the interface 205 shown in FIG. Figure 3 The memory controller 215 shown in FIG. 8 is the same as or similar to the memory controller 215 shown in FIG. Then, the address prediction module 830 of the memory controller 800 may start the prediction operation of the next data to be accessed by the host 100. The address prediction module 830 may be connected to Figure 3 The address prediction module 225 shown in FIG. 2 is the same as or similar to that shown in FIG.

[0081] Return to reference Figure 6 , in operation S315 , it is determined whether the request from the host 100 is a sequential request or a random request.

[0082] For example, refer to Figure 3 , the host 100 may access the storage device 200 by issuing a sequential request or a random request. Therefore, the memory controller 215 may determine whether the access of the host 100 is sequential or random.

[0083] First, a process performed when the host 100 accesses the storage device 200 according to the sequential request (Yes in operation S315 ) will be described.

[0084] refer to Figure 6 , the memory controller 215 checks to determine whether sequential requests have been made from the host 100 to the storage device 200 more than k times, where k is a natural number (operation S320). If sequential requests have been made more than k times (yes in operation S320), the memory controller 215 may prefetch the (k+1)th data into the external storage device (operation S330).

[0085] For example, refer to Figure 7 , when the host 100 accesses the storage device 820 continuously (e.g., first, second, third, etc.) from the physical address of the first data to the physical address of the kth data, the address prediction module 830 can predict that the data to be accessed next by the host 100 is the (k+1)th data. Therefore, the address prediction module 830 can pre-fetch the data having the physical address of the (k+1)th data into another storage device 850 (e.g., a main memory device) via the pre-fetcher 810. The pre-fetcher 810 can be connected to the storage device 820. Figure 3 As a result of the pre-fetch operation, the response speed of the host 100 accessing the storage device 200 can be improved. Figure 7 In the example, a storage device 820 and another storage device 850 constitute a storage system 840 .

[0086] Reference Figure 6The process performed when the sequential request from the host 100 to the storage device 200 is not made more than k times (No in operation S320) is described. Figure 7 In an exemplary embodiment, if the host 100 accesses only up to the (k−1)th data in the storage device 820 , the prefetcher 810 of the storage device 820 does not prefetch the (k+1)th data into another storage device 850 .

[0087] Reference Figure 6 A process performed when a random request is made from the host 100 to the storage device 200 (NO in operation S315) is described.

[0088] If the host 100 accesses the storage device 200 using a random request (No in operation S315), the memory controller 215 builds a database for random requests (operation S340), and checks to determine whether there is a rule in the physical address of the data until the kth request of the random request based on the database (operation S345). If there is a rule in the physical address of the data until the kth request (Yes in operation S345), the (k+1)th data can be pre-fetched into the expansion storage device according to the rule (operation S350).

[0089] Reference Figure 6 Describes the process performed when the random request from the host 100 to the storage device 200 is not made more than k times (No in operation S345). Figure 7 In an exemplary embodiment, if the host 100 accesses only up to the (k−1)th data in the storage device 820 , the prefetcher 810 of the storage device 820 does not prefetch the (k+1)th data into another storage device 850 .

[0090] For example, refer to Figure 7 , when the host 100 issues a random request to the storage device 820, the address prediction module 830 may not be able to easily predict the next access request data following the current access request. However, in an exemplary embodiment, the random request may have a specific pattern. If the address prediction module 830 recognizes (e.g., learns) a specific pattern of the random request, the address prediction module 830 is able to predict the next access request following the current access request.

[0091] The address prediction module 830 may have a learning capability of a pattern of requests to be accessed from the host 100. That is, in an exemplary embodiment, the address prediction module 830 may be configured to learn a pattern of requests to be accessed from the host 100. The address prediction module 830 may build a database of physical addresses of data accessed from the host 100 to provide a learning capability. For example, the address prediction module 830 may detect a rule between a physical address of currently accessed data and a physical address of data to be accessed next.

[0092] For example, the address prediction module 830 may identify a rule in the physical addresses of the data in the database until the physical addresses of the data accessed by the kth data (e.g., a rule that the physical address increases by four each time, such as the first, fifth, ninth, etc.). The address prediction module 830 may predict that the (k+1)th data to be accessed by the host 100 has the identified rule using the physical address of the kth data. The address prediction module 830 may prefetch the data having the physical address of the (k+1)th data into another storage device 850 (e.g., a main memory device) via the prefetcher 810. As a result, the response speed of the host 100 accessing the storage device 820 may be improved.

[0093] In an exemplary embodiment, the address prediction module 830 may regard data access up to the kth data as a batch read, and may prefetch the (k+1)th data into another storage space ( Figure 6 Operations S330 and S350 of the present invention are described in detail. If the continuous access or the random but regular access occurs less than k times, the prediction data may not be pre-fetched. According to an exemplary embodiment, the accuracy of the next prediction data can be increased only when the access of the host 100 is repeated more than a predetermined number of times, and the prediction data can be pre-fetched only for the access regarded as a batch read.

[0094] Return to reference Figure 4 , the memory controller 215 pre-fetches the data predicted in operation S300 into another storage device (eg, a main memory device) (operation S400). Figure 3 Once the address prediction module 225 of the memory controller 215 predicts the data that the host 100 will access next, the prefetcher 220 of the memory controller 215 can prefetch the predicted data into an external storage device (e.g., a main memory device) having a faster speed than the storage device 200.

[0095] Return to reference Figure 4 , the memory controller 215 modifies the physical address (operation S500).

[0096] For example, refer to Figure 8, the memory controller 215 may use the page table 150 in the memory management unit 104 to modify the physical address.

[0097] In addition, refer to Fig. 9 , the memory controller 215 may use the translation lookaside buffer 108 or the page table 150 in the management unit 104 to modify the physical address.

[0098] The memory management unit 104 and the translation lookaside buffer 108 are similar to those in the above reference Figure 1 Same as those described.

[0099] refer to Fig.10 , the memory controller 215 may modify the physical address of the page table 155 from the physical address corresponding to the storage area 210 before prefetching to the physical address corresponding to the external storage device after prefetching. Fig.10 The page table 155 shown in FIG. 1 may be used with Figure 2 The page table 150 shown in FIG. 1 is the same as or similar to that shown in FIG.

[0100] Fig.11 It is shown that according to the above reference Figure 4 Describes the host of prefetch operations (for example, Figure 3 A block diagram of the process of accessing prediction data by the host 100 shown in FIG.

[0101] refer to Fig.11 , as referenced above Figure 1 As described above, when accessing the memory 124 from the host 100, the CPU 130 may send a virtual address to the memory management unit 104. The page table 155 (see Fig.10 ) may be modified by the memory controller 215, as described above with reference to Figure 4 As described. For example, the physical address can be modified without the intervention of the host 100 (for example, without modifying the application or adding a separate layer). In this way, the host 100 does not need to recognize that the predicted data has been prefetched into another storage device. Instead, the memory controller 215 can access the predicted data stored in another storage device (for example, a main memory device with a relatively fast speed) by accessing the storage device storing the predicted data before prefetching using the physical address modified by the memory controller 215. Therefore, according to an exemplary embodiment, the access speed of the host 100 is improved by accessing the data after prefetching without modifying the application or adding another layer.

[0102] For example, in a conventional storage system including a main memory device having a relatively small capacity and providing relatively fast access, and an auxiliary memory device having a relatively large capacity and providing relatively slow access, frequently accessed data in the auxiliary memory device can be read and pre-fetched into the main memory device. However, pre-fetching techniques used to achieve this purpose include: modifying the host or host-level applications, or adding a separate layer to access the pre-fetched data pre-fetched into the main memory device. Since these techniques require additional resources, modifications to the host, and / or a separate layer to operate, the complexity and manufacturing cost of conventional storage systems are increased.

[0103] In contrast, an exemplary embodiment of the present disclosure provides a storage device including an auxiliary memory that predicts the next access operation from a host / application. Since the access speed of the auxiliary memory of the storage device is slower than that of the main memory buffer, the auxiliary memory (e.g., a memory controller in the auxiliary memory) can prefetch the predicted next data to the main memory buffer. In an exemplary embodiment, in order to prefetch the predicted next data, the auxiliary memory can modify the physical address of the predicted next data. This allows the host / application to access the predicted next data at a high access speed without modifying the host / application. For example, only the auxiliary memory changes the physical address of the predicted next data, thereby allowing the storage device to be used with the host / application without modifying the host / application and without adding a separate layer to access the prefetched next data, thereby providing an improved storage device with increased speed, reduced complexity, and reduced manufacturing costs.

[0104] For example, refer to Fig.10 , when the access to the host 100 is completed, the memory controller 215 may update the physical address of the page table 155 back to its original value. For example, the memory controller 215 may modify the page table 155 from the physical address corresponding to the extended storage device after prefetching to the physical address corresponding to the storage area 210 before prefetching, thereby restoring the physical address back to its original value. For example, after the host 100 completes accessing the storage device 200, the memory controller 215 may change the physical address of the page table 155 corresponding to the extended storage device after the prefetch operation back to the physical address corresponding to the storage area 210 before the prefetch operation, thereby restoring the physical address back to its original value.

[0105] Fig.12 is a block diagram of a storage device according to an exemplary embodiment of the present disclosure. Fig.13 It is shown Fig.12 A flowchart of the operation of a storage device.

[0106] Hereinafter, for the sake of convenience of explanation, further description of previously described components and technical aspects may be omitted, and the description may mainly focus on differences from the above-described exemplary embodiments.

[0107] refer to Fig.12 , the storage device 230 may use a direct memory access (DMA) engine 260 to perform pre-fetch operations. The storage device 230 may be connected to Figure 3 The storage device 200 shown in FIG. 1 is the same as or similar to that shown in FIG.

[0108] The storage device 230 can directly access an external device (e.g., another storage device, a hard disk, a graphics card, a network card, a sound card, etc.) via the DMA engine 260 to read / write data from / to the external device. The DMA engine 260 can be a bus-supported function. A portion of the storage device 230 can be designated as an area to be used for the DMA engine 260. By using the DMA engine 260, in an exemplary embodiment, the CPU 130 does not participate in data transmission. As a result, in an exemplary embodiment, data can be transferred with a larger bandwidth, and the performance of the storage device 230 can be improved. In the DMA engine 260, information such as the object to which data is transferred, the location (e.g., address) of the data to be transferred, and the size of the data to be transferred can be programmed or set. The DMA engine 260 can communicate with the external device according to the program or setting. The memory controller 245 can send data to another storage area with a larger bandwidth via the DMA engine 260. As a result, the speed of the storage device 230 can be increased. The memory controller 245 can communicate with the external device according to the program or setting. Figure 3 The memory controller 215 shown in FIG. 2 is the same as or similar to the memory controller 215 shown in FIG.

[0109] refer to Fig.13 In operation S610, the address prediction module 255 of the memory controller 245 predicts the data to be accessed next by the host 100 based on the data accessed by the host 100 using the virtual address in operation S600. Operations S600 and S610 are respectively related to Figure 4 Operations S200 and S300 are the same. Therefore, for the convenience of explanation, further description thereof will be omitted. Fig.12 The address prediction module 255 shown in FIG. Figure 3 The address prediction module 225 shown in FIG. 2 is the same as or similar to that shown in FIG.

[0110] The memory controller 245 of the memory device 230 prefetches the data predicted by the address prediction module 255 into the external memory device through the prefetcher 250. The prefetcher 250 prefetches the data into the external memory device via the DMA engine (operation S620).

[0111] For example, refer to Fig.12, the prefetcher 250 can prefetch the data predicted by the address prediction module 255 of the memory controller 245 into the external device via the DMA engine 260. Fig.12 In the embodiment, the interface 235 and the storage area 240 can be respectively connected to Figure 3 The interface 205 and storage area 210 shown in FIG. 2 are the same or similar.

[0112] Return to reference Fig.13 , after the DMA engine 260 completes the prefetch operation, the storage device 230 is notified of the completion of the prefetch operation (operation S630).

[0113] For example, refer to Fig.12 , the storage device 230 may perform other tasks while the DMA engine 260 performs the communication for the data pre-fetched from the pre-fetcher 250. Once the communication is complete, the DMA engine 260 may notify the storage device 230 of the completion by sending an interrupt indicating that the communication has been completed.

[0114] Return to reference Fig.13 After the pre-fetch operation has been completed, the memory controller 245 modifies the page table 155 with the pre-fetched physical address of the external memory device (operation S640).

[0115] For example, refer to Fig.12 After the prefetch operation has been completed, the memory controller 245 modifies the page table 155 with the physical address of the prefetched external storage device so that when the host 100 later accesses the predicted data, the host 100 can access the prefetched external storage device.

[0116] Fig.14 is a block diagram of a storage device according to an exemplary embodiment of the present disclosure. Fig.15 It is shown Fig.14 A flowchart of the operation of a storage device.

[0117] Hereinafter, for the sake of convenience of explanation, further description of previously described components and technical aspects may be omitted, and the description may mainly focus on differences from the above-described exemplary embodiments.

[0118] refer to Fig.14 , the storage area 275 of the storage device 265 may include a memory device 280 having a relatively large capacity, and a buffer memory 285 having a relatively small capacity and a relatively fast access time. The memory device 280 may also be referred to herein as a memory element capable of storing data. For example, compared to the capacity of the buffer memory 285, the memory device 280 may have a relatively large capacity, and compared to the access time of the memory device 280, the access time of the buffer memory 285 may be relatively fast. The storage device 265 and the storage area 275 may be respectively connected to Figure 3The storage device 200 and storage area 210 shown in FIG. 2 are the same or similar.

[0119] Memory device 280 may include, for example, PRAM, RRAM, MRAM, STT-MRAM, FeRAM, NOR flash memory, or NAND flash memory. Different types of memory devices may be combined. Memory device 280 may also include block storage. Interface 270 may be a byte-accessible interface that provides byte accessibility, such as a PCIe interface. Interface 270 may be connected to Figure 3 The interface 205 shown in FIG. 2 is the same as or similar to that shown in FIG.

[0120] The data transmission rate of the host 100 through the bus format may be relatively faster than the data transmission rate of the memory device 280 of the storage area 275. For example, when the interface speed of the host 100 is much faster, the performance degradation caused by the speed difference may be reduced by adopting the buffer memory 285. The buffer memory 285 may be implemented as, for example, a synchronous DRAM to provide sufficient buffering in the storage device 265 used as an auxiliary memory device with a large capacity. However, it should be understood that the exemplary embodiments of the present disclosure are not limited thereto.

[0121] The buffer memory 285 may store at least a portion of the data stored in the memory device 280. The write data provided from the host 100 may be temporarily stored in the buffer memory 285. In addition, the data pre-fetched from the memory device 280 in response to the read request from the host 100 may also be temporarily stored in the buffer memory 285. When the data existing in the memory device 280 at the time of the read request from the host 100 is cached in the buffer memory 285, the buffer memory 285 may support a cache function for directly providing the cached data to the host 100. Since the cached data can be directly provided to the host 100, in an exemplary embodiment, the host 100 does not access the memory device 280 at this time. For example, the cached data can be directly provided to the host 100 from the buffer memory 285 without the host 100 accessing the memory device 280. As a result, according to an exemplary embodiment, the speed of the storage device 265 is improved.

[0122] refer to Fig.15 In operation S710, the address prediction module 298 of the memory controller 290 of the storage device 265 predicts the data to be accessed next by the host 100 based on the data accessed by the host 100 using the virtual address in operation S700. Operations S700 and S710 are respectively related to Figure 4 Operations S200 and S300 are the same. Therefore, for the convenience of explanation, further description thereof will be omitted. Fig.14 The address prediction module 298 and the memory controller 290 shown in FIG. Figure 3 The address prediction module 225 and the memory controller 215 shown in FIG. 2 are the same or similar.

[0123] The data predicted by the address prediction module 298 of the memory controller 290 is cached in the buffer memory 285 in the storage area 275 (operation S720).

[0124] For example, refer to Fig.14 , the memory controller 290 may cache the data predicted by the address prediction module 298 in the buffer memory 285 .

[0125] Return to reference Fig.15 , the prediction data cached in the buffer memory 285 is pre-fetched into the external storage device (operation S730).

[0126] For example, refer to Fig.14 , the prefetcher 295 can prefetch the data cached in the buffer memory 285 to another storage device. The prefetcher 295 can be connected to Figure 3 The prefetcher 220 shown in FIG.

[0127] Return to reference Fig.15 After the pre-fetch operation is completed, the memory controller 290 modifies the physical address of the buffer memory 285 of the page table 155 into the physical address of the external memory device (operation S740).

[0128] For example, refer to Fig.14 After the prefetch operation has been completed, the memory controller 290 modifies the page table 155 with the physical address of the prefetched external memory space so that when the host 100 later accesses the predicted data, the host 100 can access the prefetched external memory device.

[0129] Fig.16 is a block diagram of a storage system according to an exemplary embodiment of the present disclosure.

[0130] refer to Fig.16 , the host 100 can be connected to the storage system 335 to implement a single data processing system. Such a data processing system can be implemented as, but not limited to, a personal computer (PC), a workstation, a data center, an Internet data center (IDC), a direct-attached storage (DAS) system, a storage area network (SAN) system, a network-attached storage (NAS) system, a redundant array of inexpensive disks or a redundant array of independent disks (RAID) system, or a mobile device.

[0131] The mobile device may be implemented as, but not limited to, a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a drone, or an e-book.

[0132] The storage system 335 may include executing the above reference Figure 3 The second storage device 325, the first storage device 315, and the bus 330 of the pre-fetch operation described above. The second storage device 325 can be connected to the first storage device 315. Figure 3 The storage device 200 shown in FIG. 1 is the same as or similar to that shown in FIG.

[0133] The first storage device 315 and the second storage device 325 may include a first interface 310 and a second interface 320, respectively. According to an exemplary embodiment of the present disclosure, the first interface 310 and the second interface 320 may be used as data transmission paths between the host 100 and the first storage device 315 and the second storage device 325, respectively.

[0134] The first interface 310 and the second interface 320 can be implemented as, but not limited to, an interface providing byte accessibility, such as a PCI interface, a PCIe interface, an NVMe interface, and a DIMM interface. The first interface 310 and the second interface 320 can transmit electrical signals or optical signals.

[0135] In an exemplary embodiment, the first interface 310 and the second interface 320 may be the same type of interface, or may be different types of interfaces. In an exemplary embodiment, the host 100 may be connected to the first storage device 315 and the second storage device 325 via different interfaces or via the same interface. In an exemplary embodiment, the same interface for connecting the host 100 to the first storage device 315 and the second storage device 325 may be a dual in-line memory module (DIMM), the first storage device may be a dynamic random access memory (DRAM), and the second storage device may be a non-volatile RAM (NVRAM).

[0136] The host 100 may access the first storage device 315 or the second storage device 325 using a virtual memory address, as shown in the drawing.

[0137] In an exemplary embodiment, the host 100 may access data stored in the first storage device 315 at a first speed v1, and access data stored in the second storage device 325 at a second speed v2. The first speed v1 may be different from the second speed v2. For example, the first speed v1 may be faster than the second speed v2. The host 100, the first storage device 315, and the second storage device 325 having such characteristics may be implemented in various ways.

[0138] First, the first interface 310 for connecting the host 100 and the first storage device 315 may be different from the second interface 320 for connecting the host 100 and the second storage device 325, so that the first speed v1 may be different from the second speed v2.

[0139] In addition, the first interface 310 for connecting the host 100 and the first storage device 315 may be the same as the second interface 320 for connecting the host 100 and the second storage device 325. The type of the first storage device 315 may be different from the type of the second storage device 325, so that the first speed v1 may be different from the second speed v2.

[0140] An example of this configuration will be described in detail below.

[0141] Fig.17 It is shown Fig.16 A flow chart of the operation of a storage system. Fig.18 It is shown Fig.16 Block diagram of a prefetch operation of a storage system. Fig.19 It is shown Fig.16 A block diagram of a physical address modification operation of a storage system.

[0142] refer to Fig.17 , the host 100 uses the virtual address to access the data (operation S800). Fig.16 , the host 100 can use the second virtual address 305 to access the second storage device 325. The host 100 can use the first virtual address 300 to access the first storage device 315.

[0143] Still reference Fig.16 In an exemplary embodiment, the first virtual address 300 refers to an address range including a third virtual address and a fourth virtual address continuous with the third virtual address, and the second virtual address 305 is continuous with the fourth virtual address and different from the third virtual address.

[0144] Still reference Fig.16In an exemplary embodiment, the first storage device 315 may store first data, and the host 100 may access the first data using the first virtual address 300. The second storage device 325 may store second data, and the host 100 may access the second data using the second virtual address 305 and a third virtual address adjacent to (e.g., directly adjacent to) the second virtual address 305. Therefore, Fig.16 The address range represented by 305 in the example may refer to a second virtual address and a third virtual address. The second virtual address and the third virtual address are different from the first virtual address 300. The second storage device 325 may use a fourth virtual address adjacent to (e.g., directly adjacent to) the third virtual address based on the second virtual address and the third virtual address to predict the predicted data to be accessed by the host 100, and may pre-fetch the predicted data into the first storage device 315. The second virtual address, the third virtual address, and the fourth virtual address may be consecutive virtual addresses. Therefore, Fig.16 The address range represented by 305 in the example may refer to a second virtual address, a third virtual address, and a fourth virtual address. In an exemplary embodiment, the second virtual address, the third virtual address, and the fourth virtual address may be consecutive virtual addresses. In an exemplary embodiment, the second virtual address, the third virtual address, and the fourth virtual address may be virtual addresses spaced apart from each other at a constant interval.

[0145] Reference again Fig.17 , the address prediction module predicts the next data (operation S810). For example, referring to Fig.16 , the second interface 320 may send information accessed by the host 100 to the second storage device 325. Then, the second storage device 325 may analyze the access pattern of the host 100 to predict the next data to be accessed.

[0146] Return to reference Fig.17 , the memory controller of the second storage device 325 ( Fig.16 Not shown but can be used with Figure 3 ) pre-fetches the next data into the first storage device 315 (operation S820). Fig.16 , the second storage device 325 can pre-fetch the prediction data into the first storage device 315 via the bus 330. Referring to the exemplary embodiment of the present disclosure, Fig.18 , the second storage device 625 can perform a pre-fetch operation in which data is pre-fetched into the first storage device 615 via the DMA engine 640. The DMA engine 640 can be used with Fig.12 The DMA engine 260 shown in FIG. 2 is the same as or similar to that shown in FIG.

[0147] exist Fig.18 In the example, the first storage device 615 can be connected to Fig.16 The second storage device 625 may be the same as or similar to the first storage device 315 shown in FIG. Fig.16 The first interface 610 may be the same as or similar to the second storage device 325 shown in FIG. Fig.16 The second interface 620 may be the same as or similar to the first interface 310 shown in FIG. Fig.16 The second interface 320 shown in FIG. 6 is the same as or similar to the second interface 320 shown in FIG. 6. In addition, the bus 630 can be connected to Fig.16 The first storage device 615, the second storage device 625, the DMA engine 640 and the bus 630 may constitute a storage system 635. The storage system 635 may be the same as or similar to the bus 330 shown in FIG. Fig.16 The first virtual address 600 and the second virtual address 605 may be the same as or similar to the storage system 335 shown in FIG. Fig.16 The first virtual address 300 and the second virtual address 306 shown in FIG. 3 are the same or similar.

[0148] Return to reference Fig.17 , the memory controller of the second storage device 325 modifies the physical address (operation S830). Fig.19 After the second storage device 725 pre-fetches the data predicted by the first storage device 715 via the bus 730, the memory controller of the second storage device 725 (which Fig.19 Not shown but can be used with Figure 3 The physical address in the page table 155 can be modified by the memory management unit (MMU) 740, as shown in the above reference Fig.10 described.

[0149] exist Fig.19 In the example, the first storage device 715 can be connected to Fig.16 The second storage device 725 may be the same as or similar to the first storage device 315 shown in FIG. Fig.16 The first interface 710 may be the same as or similar to the second storage device 325 shown in FIG. Fig.16 The second interface 720 may be the same as or similar to the first interface 310 shown in FIG. Fig.16 The second interface 320 shown in FIG. 7 is the same as or similar to the second interface 320 shown in FIG. 7 . Fig.16 The first storage device 715, the second storage device 725, the MMU 740 and the bus 730 may constitute a storage system 735. The storage system 735 may be the same as or similar to the bus 330 shown in FIG. Fig.16 The first virtual address 700 and the second virtual address 705 may be the same as or similar to the storage system 335 shown in FIG. Fig.16The first virtual address 300 and the second virtual address 306 shown in FIG. 3 are the same or similar.

[0150] Return to reference Fig.17 , the host 100 uses the modified physical address to access the data (operation S840). Fig.11 The operation is described in detail. Therefore, for the convenience of explanation, its further description will be omitted.

[0151] Fig. 20 is a block diagram of a storage system according to an exemplary embodiment of the present disclosure.

[0152] refer to Fig. 20 , the interface of the first storage device 415 may be a DIMM interface 410, and the interface of the second storage device 425 may be a PCIe interface 420. However, the present disclosure is not limited thereto. The DIMM interface 410 may provide data access in bytes.

[0153] The PCIe interface 420 can implement a point-to-point serial interconnection for communication between the host 100 and the second storage device 425. A switch can be used to interconnect multiple PCIe interfaces 420. As a result, a large number of devices can be connected together in a system (storage system 435). In an exemplary embodiment, the transmission data rate and the reception data rate of the PCIe interface 420 can be, but are not limited to, about 2.5 Gbit / sec.

[0154] The PCIe interface 420 uses only a few pins per device package for serial interconnection. As a result, the design cost of the PCIe interface 420 chip can be reduced, and the board design complexity can be reduced. The performance of the PCIe interface 420 can also be scalable.

[0155] exist Fig. 20 In the example, the first storage device 415 can be connected to Fig.16 The second storage device 425 may be the same as or similar to the first storage device 315 shown in FIG. Fig.16 The first interface 410 may be the same as or similar to the second storage device 325 shown in FIG. Fig.16 The second interface 420 may be the same as or similar to the first interface 310 shown in FIG. Fig.16 The second interface 320 shown in FIG. 4 is the same as or similar to the second interface 320 shown in FIG. 4. In addition, the bus 430 can be connected to Fig.16 The first storage device 415, the second storage device 425 and the bus 430 may constitute a storage system 435. The storage system 435 may be the same as or similar to the bus 330 shown in FIG. Fig.16 The first virtual address 400 and the second virtual address 405 may be the same as or similar to the storage system 335 shown in FIG. Fig.16The first virtual address 300 and the second virtual address 306 shown in FIG. 3 are the same or similar.

[0156] Fig.21 is a block diagram of a storage system according to an exemplary embodiment of the present disclosure.

[0157] refer to Fig.21 , the first storage device 515 of the storage system 535 may include DRAM, and the second storage device 525 of the storage system 535 may include NVRAM.

[0158] The first interface 510 and the second interface 520 may include the same DIMM interface. However, the present disclosure is not limited thereto.

[0159] The NVRAM may include, for example, PRAM, RRAM, MRAM, STT-MRAM, and FeRAM. Different types of memory devices may be combined, but the present disclosure is not limited thereto.

[0160] exist Fig.21 In the example, the first storage device 515 can be connected to Fig.16 The second storage device 525 may be the same as or similar to the first storage device 315 shown in FIG. Fig.16 The first interface 510 may be the same as or similar to the second storage device 325 shown in FIG. Fig.16 The second interface 520 may be the same as or similar to the first interface 310 shown in FIG. Fig.16 The second interface 320 shown in FIG. 5 is the same as or similar to the second interface 320 shown in FIG. 5. In addition, the bus 530 can be connected to Fig.16 The first storage device 515, the second storage device 525 and the bus 530 may constitute a storage system 535. The storage system 535 may be the same as or similar to the bus 330 shown in FIG. Fig.16 The first virtual address 500 and the second virtual address 505 may be the same as or similar to the storage system 335 shown in FIG. Fig.16 The first virtual address 300 and the second virtual address 306 shown in FIG. 3 are the same or similar.

[0161] As is common practice in the field of the present disclosure, exemplary embodiments are described and shown in the accompanying drawings with functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., wherein the electronic (or optical) circuits can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors, etc., they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware or implemented as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs other functions.

[0162] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. A storage device, comprising: a storage area in which first data is stored, wherein the storage area is accessed by a host using a first virtual address; and a memory controller provided outside the host and configured to control storage data stored in the storage area, The memory controller predicts second data to be accessed using a second virtual address based on the first virtual address, pre-fetches the second data into an external device, and modifies a physical address mapped to the second virtual address, wherein the external device is arranged outside the storage device. The pre-fetched second data can be accessed by the host communicating with the storage device.

2. The storage device according to claim 1, wherein: The memory controller prefetches the second data into the external device via a direct memory access (DMA) engine.

3. The storage device according to claim 1, wherein: The memory controller controls a memory management unit MMU of the host, and the pre-fetched second data can be accessed via the MMU.

4. The storage device according to claim 3, wherein: The memory controller modifies a physical address registered in a page table stored in a translation lookaside buffer (TLB) of the host.

5. The storage device according to claim 1, wherein: The storage area includes: a memory element storing the storage data; and a buffer memory storing at least a portion of the storage data stored in the memory element, Wherein, before the second data is pre-fetched into the external device, the second data is stored in the buffer memory.

6. The storage device according to claim 1, in, The first virtual address includes a third virtual address and a fourth virtual address continuous with the third virtual address, The second virtual address is continuous with the fourth virtual address and different from the third virtual address.

7. A storage system comprising: A first storage device configured to store first data, wherein a host accesses the first data at a first speed using a first virtual address; and a second storage device configured to store second data, wherein the host accesses the second data at a second speed using a second virtual address, wherein the second virtual address is different from the first virtual address, and the second speed is different from the first speed, The second storage device predicts data to be accessed by the host based on the second virtual address, and pre-fetches the predicted data into the first storage device, and the first storage device is arranged outside the second storage device.

8. The storage system according to claim 7, further comprising: a memory management unit configured to translate at least one virtual address into at least one physical address, The memory management unit stores a first physical address of the first storage device mapped to the first virtual address and a second physical address of the second storage device mapped to the second virtual address.

9. The storage system according to claim 7, wherein: The first speed is faster than the second speed.

10. The storage system according to claim 7, wherein: The host is connected to the first storage device via a first interface, and the host is connected to the second storage device via a second interface different from the first interface.

11. The storage system according to claim 10, wherein: The first interface includes a Dual In-line Memory Module (DIMM) interface that provides data access in bytes, and the second interface includes a Peripheral Component Interconnect Express (PCIe) interface.

12. The storage system according to claim 7, wherein: The host is connected to the first storage device and the second storage device using the same interface.

13. The storage system according to claim 12, wherein: The interface comprises a dual in-line memory module DIMM, the first storage device comprises a dynamic random access memory DRAM, and the second storage device comprises a non-volatile RAM, ie, NVRAM.

14. The storage system according to claim 7, further comprising: a memory management unit configured to convert the first virtual address into a first physical address of the first storage device, and to convert the second virtual address into a second physical address of the second storage device, Wherein, the second storage device modifies the memory management unit, and the host can access the pre-fetched prediction data.

15. The storage system according to claim 7, wherein: The second storage device comprises: A first storage element having a first response speed to a read command; and a second storage element having a second response speed faster than the first response speed, The second storage device pre-fetches the data stored in the second storage element into the first storage device.

16. The storage system according to claim 15, wherein: The second storage device pre-fetches the prediction data into the first storage device via a direct memory access (DMA) engine.

17. A storage system comprising: A first storage device configured to store first data, wherein a host accesses the first data using a first virtual address; and a second storage device configured to store second data, wherein the host accesses the second data using a second virtual address and a third virtual address, wherein the second virtual address and the third virtual address are different from the first virtual address, and the second virtual address and the third virtual address are adjacent to each other, The second storage device predicts data that the host wants to access using a fourth virtual address adjacent to the third virtual address based on the second virtual address and the third virtual address, and pre-fetches the predicted data into the first storage device, and the first storage device is set outside the second storage device.

18. The storage system according to claim 17, wherein: The second virtual address, the third virtual address, and the fourth virtual address are consecutive virtual addresses.

19. The storage system according to claim 17, wherein: The second virtual address, the third virtual address, and the fourth virtual address are spaced apart from each other at a constant interval.

20. The storage system according to claim 17, wherein: A first speed at which the host accesses the first data stored in the first storage device is faster than a second speed at which the host accesses the second data stored in the second storage device.

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