Memory controller, operation method thereof, and storage device

Abstract

A memory controller and an operation method thereof and a storage device are disclosed. The memory controller includes: a memory configured to store an address mapping table and a segment mapping table; and a mapping data management module configured to select at least two updated segments from among a plurality of segments included in the address mapping table as page data to be stored in a page of a non-volatile memory, wherein each of the plurality of segments includes a plurality of mapping entries representing mapping information between a logical address and a physical address, and wherein the segment mapping table includes a physical address representing an area in which each of the plurality of segments is stored in the non-volatile memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0111026, filed on September 17, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the inventive concepts relate to a semiconductor device. For example, at least some example embodiments relate to a memory controller, a method of operating a memory controller, and / or a memory device including the memory controller. Background Art

[0004] As a non-volatile memory, the flash memory can save the stored data even when the power is turned off. Recently, storage devices including non-volatile memories such as embedded multimedia cards (eMMC), universal flash memory (UFS), solid-state drives (SSD), NAND flash memories, and memory cards have been widely used. Since the non-volatile memory cannot be rewritten, when the data corresponding to the logical address is to be updated, the storage device can write the updated data to the writable area of ​​the non-volatile memory instead of writing to the existing area in the non-volatile memory where the data has been written, and the mapping information including the physical address and logical address where the actual data has been written can be updated. On the other hand, the mapping information can also be stored in the non-volatile memory for permanent preservation. Summary of the invention

[0005] Example embodiments of the inventive concepts provide a memory controller capable of efficiently storing updated mapping information in a nonvolatile memory, a method of operating the memory controller, and / or a memory device including the memory controller.

[0006] According to an example embodiment of the present invention, there is provided a memory controller, comprising: a memory configured to store an address mapping table and a segment mapping table, the segment mapping table including a physical address representing an area where each of a plurality of segments is stored in a non-volatile memory; and a processing circuit configured to determine at least two updated segments of the plurality of segments included in the address mapping table as page data to be stored in a page of the non-volatile memory, each of the plurality of segments including a plurality of mapping entries representing mapping information between logical addresses and physical addresses.

[0007] According to another example embodiment of the inventive concept, a method of operating a memory controller is provided, the operating method comprising: selecting at least two updated segments among a plurality of segments included in an address mapping table; grouping the at least two updated segments into one page of data; and instructing a nonvolatile memory to store the page of data at a physical address.

[0008] According to another example embodiment of the present invention, there is provided a storage device, comprising: a nonvolatile memory; a buffer memory, the buffer memory being configured to store an address mapping table and a segment mapping table, the segment mapping table including a physical address representing an area where each of a plurality of segments is stored in the nonvolatile memory; and a memory controller, the memory controller being configured to group at least two updated segments of the plurality of segments included in the address mapping table into page data to be stored in a page of the nonvolatile memory, and to provide the page data to the nonvolatile memory, each of the plurality of segments including a plurality of mapping entries representing mapping information between logical addresses and physical addresses. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the present inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a memory system according to an example embodiment of the inventive concept;

[0011] Figure 2A is a diagram illustrating an address mapping table according to an example embodiment of the inventive concept;

[0012] Figure 2B is a diagram illustrating a segment mapping table according to an example embodiment of the inventive concept;

[0013] Figure 3 is a diagram illustrating updating of an address mapping table according to an example embodiment of the inventive concept;

[0014] Figure 4A A method of storing an updated segment according to an example embodiment of the inventive concept is illustrated; Figure 4B A method of updating a segment mapping table according to an example embodiment of the inventive concept is illustrated;

[0015] Figure 5A and Figure 5B is a diagram illustrating a segment having a variable data size according to an example embodiment of the inventive concept;

[0016] Figure 6is a block diagram illustrating a controller according to an example embodiment of the inventive concept;

[0017] Figure 7 is a block diagram illustrating a controller 110b according to an example embodiment of the inventive concept;

[0018] Figure 8 is a diagram illustrating storage and loading of a mapping table in a memory system according to an example embodiment of the inventive concept;

[0019] Fig. 9 is a flowchart illustrating an operating method of a controller according to an example embodiment of the inventive concept;

[0020] Fig.10 is a diagram illustrating an operating method of a controller according to an example embodiment of the inventive concept;

[0021] Fig.11 is a flowchart illustrating an operating method of a controller according to an example embodiment of the inventive concept;

[0022] Fig.12 is a flowchart illustrating an operating method of a controller according to an example embodiment of the inventive concept;

[0023] FIG. 13A to FIG. 13C An embodiment of adjusting the size of a segment according to an example embodiment of the inventive concept is illustrated; and

[0024] Fig.14 is a block diagram illustrating an SSD according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0025] Hereinafter, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a block diagram illustrating a memory system according to an example embodiment of the inventive concept.

[0027] Reference Figure 1 , the memory system 100 may include a controller 110 (also referred to as a memory controller) and a non-volatile memory (NVM) 120. The memory system 100 may communicate with the host 200 through various interfaces. The memory system 100 may store data DATA in the non-volatile memory 120 or may read data DATA from the non-volatile memory 120 in response to a read / write command CMD received from the host 200.

[0028] The host 200 may refer to a data processing device capable of processing data, such as a central processing unit (CPU), a processor, a microprocessor, and an application processor (AP). The host 200 may execute an operating system (OS) and / or various application programs. For example, the host 200 may be implemented as a single chip system (SoC).

[0029] When requesting to write data DATA, the host 200 may send a write command CMD, data DATA, and a logical address LA indicating a logical area where the data DATA is to be stored to the memory system 100. When requesting to read data DATA, the host 200 may send a read command CMD and a logical address LA indicating a logical area where the data DATA is to be read to the memory system 100.

[0030] The nonvolatile memory 120 may include a memory cell array MCA, the memory cell array MCA may include memory blocks BLK1 to BLKz, and each memory block BLK1 to BLKz may include a plurality of pages PG1 to PGk. Here, z and k may be positive integers, respectively, and may be variously changed according to example embodiments. For example, a memory block may be a unit of erasure, and a page may be a unit of writing and reading. In some embodiments, the memory cell array MCA may include a plurality of planes, a plurality of bare chips (dies), or a plurality of chips. In an example embodiment, the nonvolatile memory 120 may include a flash memory device, and may include, for example, a NAND flash memory device. However, the inventive concept is not limited to these examples, and the nonvolatile memory 120 may include a resistive memory device, such as a resistive RAM (ReRAM), a phase change RAM (PRAM), and a magnetic RAM (MRAM). Hereinafter, it is assumed that the nonvolatile memory 120 is a NAND flash memory device.

[0031] In an example embodiment, the memory cell array MCA may be a three-dimensional (3D) memory array. The 3D memory array is monolithically formed on an active area arranged on a silicon substrate and on at least one physical level of the memory cell array, the at least one physical level having a circuit formed on or in the substrate as a circuit related to the operation of the memory cell. The term "monolithic" means that the layers constituting each level of the array are stacked directly on top of the layers of each underlying level of the array. In an example embodiment according to the teachings of the inventive concept, the 3D memory array includes vertical NAND strings arranged in a vertical direction such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trapping layer.

[0032] U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235 and U.S. Patent Application Publication No. 2011 / 0233648, which are incorporated herein by reference, disclose components related to a 3D memory array formed of multiple levels in which word lines and / or bit lines are shared between the levels.

[0033] The controller 110 may control the nonvolatile memory 120 to write data DATA in the memory cell array MCA in response to a write request from the host 200, or control the nonvolatile memory 120 to read data stored in the memory cell array MCA in response to a read command from the host 200. The controller 110 may convert the logical address LA received from the host 200 into a physical address PA indicating a physical area in the memory cell array MCA, and then may write the data DATA to the area indicated by the converted physical address PA in the memory cell array MCA, or may read the data DATA from the area. The controller 110 may manage address mapping information (or address mapping entries) indicating mapping information between the logical address LA and the physical address PA.

[0034] Reference Figure 1 , the controller 110 may include an address mapping table AMT, a segment mapping table SMT, and a mapping data management module MDM. For example, the address mapping table AMT and the segment mapping table SMT may be loaded into a memory in the controller 110 (eg, Figure 7 Cache memory 18). Figure 1 , it is illustrated that the address mapping table AMT and the segment mapping table SMT are included in the controller 110, but the inventive concept is not limited to this example. In some example embodiments, the address mapping table AMT and the segment mapping table SMT may be loaded into a memory chip (e.g., a dynamic random access memory (DRAM) chip) outside the controller chip implementing the controller 110, or may be loaded into a non-volatile memory chip.

[0035] Figure 2A is a diagram illustrating an address mapping table according to an example embodiment of the inventive concept.

[0036] Reference Figure 2A , the address mapping table AMT may include a plurality of segments SG0 to SGn-1, and each of the segments SG0 to SGn-1 may include a plurality of mapping entries ET0 to ET3. Figure 2A , a segment (eg, the second segment SG1) is illustrated as including four mapping entries ET0 to ET3, but the inventive concept is not limited to this example. The number of mapping entries included in a segment may be variable.

[0037] The data size of the multiple segments SG0 to SGn-1 is the same, and the data size of each segment can be smaller than the data size of the write unit of the memory cell array MCA, for example, the page data size. For example, assuming that the data size of the page is 16 kilobytes, the data size of the segment can be (16 / 2N)KB (where N is a positive integer and 2N is an integer equal to or less than 16). The data size of the multiple segments SG0 to SGn-1 can be variable.

[0038] Each of the plurality of mapping entries ET0 to ET3 may include a logical address LA and a physical address PA assigned to the logical address LA. In an example embodiment, each of the plurality of mapping entries ET0 to ET3 may include a logical page number LPN and a physical page number PPN assigned to the logical page number LPN. For example, the first mapping entry ET0 may include a logical page number LPN_a0 and a physical page number PPN_a1 assigned to the logical page number LPN_a0. In this way, a scheme of mapping a physical page number to a logical page number may be referred to as a page mapping scheme.

[0039] Since the nonvolatile memory 120 is not rewritable, when the data corresponding to the logical address LA is to be updated, the controller 110 may write the data DATA to be updated in an area (e.g., a valid area in an erased state) other than the area in which the data DATA has been previously written in the memory cell array MCA, and may update the physical address PA corresponding to the logical address LA based on the new physical address PA indicating the area in which the data has been actually written. That is, the controller 110 may update the mapping entry.

[0040] For example, in a state where data DATA corresponding to the logical page number LPN_a0 is stored in an area of ​​the memory cell array MCA corresponding to the physical page number PPN_a1, when the logical page number LPN_a0 and the data DATA to be written to the nonvolatile memory 120 and the write command CMD are received from the host 200, the controller 110 may store the data DATA in a valid page of the memory cell array MCA, and update the physical address PA of the first mapping entry ET0 based on the physical page number of the valid page. For example, when the physical page number of the valid page is PPN_a5, the physical address PA of the first mapping entry ET0 may be changed from the physical page number PPN_a1 to the physical page number PPN_a5.

[0041] The controller 110 may store the address mapping table AMT in the nonvolatile memory 120 to persist the address mapping table AMT, and may load the address mapping table AMT stored in the nonvolatile memory 120 to a memory in the controller 110 (or a DRAM chip outside the controller 110) when the memory system 100 is powered on. The controller 110 may store at least some updated segments of the multiple segments SG0 to SGn-1 of the address mapping table AMT in the nonvolatile memory 120 periodically or in response to the occurrence of an event. At this time, the updated segment means a segment including at least one updated mapping entry.

[0042] Figure 2B is a diagram illustrating a segment mapping table according to an example embodiment of the inventive concept.

[0043] Reference Figure 2B , the segment mapping table SMT includes each physical address PA corresponding to each of the multiple segments SG0 to SGn-1 of the address mapping table AMT. The physical address PA indicates an area where the segment is stored in the memory cell array MCA of the nonvolatile memory 120. The segment mapping table SMT includes segment mapping information, that is, the locations where the multiple segments SG0 to SGn-1 are stored in the memory cell array MCA of the nonvolatile memory 120.

[0044] As mentioned above Figure 2A As described above, the data size of a segment is smaller than the data size of a page, and a plurality of segments can be stored in one page of the memory cell array MCA. Therefore, the physical address PA corresponding to each segment included in the segment mapping table SMT may include a physical page number and an offset. The offset indicates the location of the storage segment in the page. For example, the offset indicates how many bytes from the first byte of the page the storage segment is.

[0045] like Figure 2B As shown in , a plurality of segments (eg, four segments) may be stored in one page. For example, when the first to fourth segments SG0 to SG3 are stored in one page, the physical page numbers of the first to fourth segments SG0 to SG3 are the same, but their offsets may be different.

[0046] As mentioned above Figure 2AAs described, some of the multiple segments SG0 to SGn-1 may be updated, and the updated segments may be stored in the nonvolatile memory 120. When the updated segments are stored in the nonvolatile memory 120, the physical address PA of the segments may be changed in the segment mapping table SMT. For example, when the second segment SG1 is updated and stored in the memory cell array MCA of the nonvolatile memory 120, the physical address PA of the second segment SG1 indicating the physical page number PPN_b0 and the offset OFF_1 may be changed to a physical address PA indicating the physical page number and the offset of the updated segment stored therein. In this way, when the updated segment is stored in the nonvolatile memory 120, the physical address PA corresponding to the segment may be updated.

[0047] On the other hand, for the persistence of the segment mapping table SMT, the controller 110 may store the segment mapping table SMT in the non-volatile memory 120. The controller 110 may store the segment mapping table SMT in the non-volatile memory 120 periodically or in response to the occurrence of an event. The controller 110 may load the segment mapping table SMT stored in the non-volatile memory 120 into a memory in the controller 110 (or a DRAM chip outside the controller 110) at the power-on time of the memory system 100. The controller 110 may load the address mapping table AMT from the non-volatile memory 120 based on the segment mapping information of the segments of the segment mapping table SMT.

[0048] Reference Figure 1 , the mapping data management module MDM may manage the address mapping table AMT and the segment mapping table SMT. The mapping data management module MDM may store the updated segments of the multiple segments SG0 to SGn-1 of the address mapping table AMT in the non-volatile memory 120. The mapping data management module MDM may select at least two segments of the multiple segments SG0 to SGn-1 as page data to be stored in one page of the non-volatile memory 120. The mapping data management module MDM may update the segment mapping table SMT based on the physical address PA indicating the page where the at least two segments are to be stored. The mapping data management module MDM may provide the non-volatile memory 120 with the physical address PA indicating the page where the at least two segments are to be stored.

[0049] In one example embodiment, as shown below Figure 7As discussed, the controller 100 may include a memory and a processor, wherein the memory stores instructions that, when executed by the processor, configure the processor as a dedicated processor to perform the functions of the mapping data management module MDM using the flash translation layer FTL of the memory. However, the inventive concept is not limited to this example, and the mapping data management module MDM may be implemented by hardware or a combination of hardware and software. Therefore, the processor (e.g., the mapping data management module MDM) may reduce the overhead of the non-volatile memory 120 by reducing unnecessary writes and / or the number of write operations, thereby improving the functionality of the memory system 100 itself.

[0050] Therefore, in the memory system 100 according to an example embodiment of the inventive concept, the controller 110 may group mapping entries of the address mapping table AMT into write units (that is, segment units smaller than page units) of the memory cell array MCA, may group at least two segments into one page of data, and may write the page data to one page of the memory cell array MCA. The controller 110 may manage the physical address PA indicating the location where each of the multiple segments included in the address mapping table AMT is stored in the memory cell array MCA by using the segment mapping table SMT, and when the updated segment is written to the memory cell array MCA, the controller 110 may update the segment mapping table SMT based on the physical address PA indicating the location to be written.

[0051] As a comparative example of an exemplary embodiment of the present invention, in order to enable the controller to manage the mapping entries of the address mapping table AMT page by page and store the updated mapping entries in the non-volatile memory 120, when the mapping entries grouped in units of pages are written to the memory cell array MCA, multiple mapping entries that have not been updated are written to the memory cell array MCA together. This may result in unnecessary writing. Moreover, when the mapping entries of multiple locations of the address mapping table AMT are updated, that is, when the mapping entries belonging to different pages are updated, in order to store the updated mapping entries in the non-volatile memory 120, multiple write operations may be performed, resulting in overhead in the non-volatile memory 120.

[0052] However, as described above, in the memory system 100 according to an example embodiment of the inventive concept, the controller 110 can manage the mapping entries in segment units smaller than the page unit, and group the updated segments including the updated mapping entries into page data to write to the memory cell array MCA, thereby reducing unnecessary writing, or minimizing unnecessary writing, and reducing the number of writing times. Therefore, the overhead of the nonvolatile memory 120 can be reduced.

[0053] The memory system 100 according to the exemplary embodiment of the present invention can be embedded in an electronic device or implemented as an electronic device. The electronic device can be implemented as, for example, a personal computer (PC), a data server, a network attached storage (NAS), an Internet of Things (IoT) device, or a portable electronic device. The portable electronic device can be a laptop, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a personal navigation device, an MP3 player, a handheld game console, an e-book, a wearable device, etc.

[0054] In some example embodiments, the memory system 100 may be an internal memory embedded in an electronic device. For example, the memory system 100 may be an SSD, an embedded universal flash memory (UFS) storage device, or an embedded multimedia card (eMMC). In some example embodiments, the memory system 100 may be an external memory that is removable from an electronic device. For example, the memory system 100 may be a UFS memory card, a compact flash memory (CF) card, a secure digital (SD) card, a micro secure digital (SD) card, a mini secure digital (SD) card, or a memory stick.

[0055] Figure 3 is a diagram illustrating update of an address mapping table according to an example embodiment of the inventive concept.

[0056] Reference Figure 3 , the address mapping table AMT may include a plurality of segments SG0 to SGn-1, each segment includes a plurality of mapping entries, each mapping entry includes a physical address PA corresponding to its logical address LA. For example, each segment may include four mapping entries.

[0057] For example, the second segment SG1 may include first to fourth mapping entries ET0 to ET3. The first mapping entry ET0 may include a logical page number LPN_a0 and its corresponding physical page number PPN_a1, the second mapping entry ET1 may include a logical page number LPN_a1 and its corresponding physical page number PPN_a2, the third mapping entry ET2 may include a logical page number LPN_a2 and its corresponding physical page number PPN_a3, and the fourth mapping entry ET3 may include a logical page number LPN_a3 and its corresponding physical page number PPN_a4.

[0058] Can be obtained from Figure 1The host 200 receives the logical address LA where data is to be stored and the write command, and when the logical page numbers LPN_a1 and LPN_a3 are received as the logical address LA, the physical page numbers corresponding to the logical page numbers LPN_a1 and LPN_a3 may be reallocated. For example, the physical page numbers PPN_b1 and PPN_b2 may be allocated to the logical page number LPN_a1 of the second mapping entry ET1 and the logical page number LPN_a3 of the fourth mapping entry ET3, respectively. The data requested to be written from the host 200 may be stored in the nonvolatile memory 120 ( Figure 1 ) of the memory cell array MCA( Figure 1 ) in the area corresponding to the physical page numbers PPN_b1 and PPN_b2.

[0059] At the same time, the physical page numbers of the second mapping entry ET1 and the fourth mapping entry ET3 may be changed to PPN_b1 and PPN_b2, respectively. In other words, the second mapping entry ET1 and the fourth mapping entry ET3 may be updated. In addition, the second segment SG1 includes the updated mapping entry and may be determined as the updated segment. In this way, a segment including at least one updated mapping entry among the plurality of segments SG0 to SGn-1 may be determined as the updated segment.

[0060] Figure 4A A method of storing an updated segment according to an exemplary embodiment of the inventive concept is illustrated. Figure 4B A method of updating a segment mapping table according to an example embodiment of the inventive concept is illustrated.

[0061] It is assumed that the data size of the plurality of segments SG0 to SGn-1 included in the address mapping table AMT is 1 / 4 of the data size of a page, and the segments SG1, SG5, SGa, and SGb among the plurality of segments SG0 to SGn-1 are updated segments.

[0062] Reference Figure 1 and Figure 4A , the mapping data management module MDM of the controller 110 may group the updated segments by page unit and may store the grouped segments in the nonvolatile memory 120. As shown in the figure, the mapping data management module MDM may group the updated segments SG1, SG5, SGa, and SGb into one page data and provide the grouped page data to the nonvolatile memory 120. The nonvolatile memory 120 may write the received page data (i.e., the data included in the grouped segments SG1, SG5, SGa, and SGb) into one page of the memory cell array MCA through one write operation.

[0063] As another example, when the data size of the plurality of segments SG0 to SGn-1 is half the data size of a page, the mapping data management module MDM may group the updated segments SG1 and SG5 into one page data, and may provide the grouped page data to the nonvolatile memory 120. In addition, the mapping data management module MDM may group the updated segments SGa and SGb into another page data, and provide the other page data to the nonvolatile memory 120. The nonvolatile memory 120 may write the received two page data to two pages of the memory cell array MCA through two write operations.

[0064] Reference Figure 1 and Figure 4B , at the same time, if Figure 4B As shown, in the segment mapping table SMTa, the physical addresses PA of the updated segments SG1, SG5, SGa, and SGb stored in the memory cell array MCA may be updated. Since the updated segments SG1, SG5, SGa, and SGb are stored in the same page in the memory cell array MCA, in the segment mapping table SMTb, the physical addresses PA corresponding to the segments SG1, SG5, SGa, and SGb have the same page number, for example, PPN_g0. In addition, the physical addresses PA corresponding to the segments SG1, SG5, SGa, and SGb may include different offsets indicating the storage locations of the segments SG1, SG5, SGa, and SGb in the page corresponding to the physical page number PPN_g0, namely, OFF_0, OFF_1, OFF_2, and OFF_3.

[0065] Figure 5A and Figure 5B is a diagram illustrating a segment having a variable data size according to an example embodiment of the inventive concept.

[0066] Reference Figure 5A and Figure 5B , the data size of segment SG can be variable. For example, Figure 5A As shown, the data size of the segment SG can be 4KB. When the data size of a page is 16KB, four segments SG can be grouped into one page so that the updated segment is stored in Figure 1 In the non-volatile memory 120. As another example, Figure 5B As shown in FIG. 1 , the data size of the segment SG can be 2KB. When the data size of a page is 16KB, eight segments SG can be grouped into one page so that the updated segment is stored in Figure 1 The non-volatile memory 120 is stored in the memory 120.

[0067] In one example embodiment, the memory system ( Figure 1The data size of the segment SG is set in the setting operation by powering on the 100 of FIG. 1. At this time, the data size of the segment SG may be variable each time it is set.

[0068] In another example embodiment, the data size of the segment SG may be set in an operation phase of the memory system 100 , and the data size of the segment SG may be variable during the operation of the memory system 100 .

[0069] Figure 6 is a block diagram illustrating a controller according to an example embodiment of the inventive concept.

[0070] Reference Figure 6 , the controller 110 a may include a processor 11 , a working memory 12 , an error correction code (ECC) engine 13 , a host interface (I / F) 14 , a DRAM interface 15 , and a non-volatile memory interface 16 , which can communicate with each other through a bus 17 .

[0071] The processor 11 may include a central processing unit, a microprocessor, etc., and may control the overall operation of the controller 110a. In an example embodiment, the processor 11 may be implemented as a multi-core processor, for example, a dual-core processor or a quad-core processor.

[0072] The working memory 12 may store firmware and data for controlling the controller 110a. The stored firmware and data may be processed by the processor 11. The working memory 12 may be implemented as a volatile memory such as a DRAM or an SRAM, or a nonvolatile memory such as a PRAM or a flash memory.

[0073] The working memory 12 may store a flash translation layer (FTL). Figure 1 The write / read operation of the nonvolatile memory 120 is performed page by page and the erase operation is performed block by block, so it is possible to perform management of the write, read, and erase operations of the nonvolatile memory 120. The FTL is system software (or firmware) for managing the write, read, and erase operations of the nonvolatile memory 120. The FTL may be loaded into the working memory 12 and operated by the processor 11.

[0074] For example, using FTL, processor 11 can manage the host ( Figure 1 The address mapping table AMT matches the logical address provided by 200 in the non-volatile memory 120 with the physical address used in the non-volatile memory 120. For example, the processor 11 may use the FTL to execute the mapping data management module ( Figure 1The mapping data management module MDM can manage the address mapping table AMT and the segment mapping table SMT. The address mapping table AMT and the segment mapping table SMT can be stored in the DRAM 130 outside the controller 110a. However, the example embodiments of the inventive concept are not limited to this example, and the working memory 12 can be used as a buffer memory, a high-speed cache memory, etc. In addition, the address mapping table AMT and the segment mapping table SMT can be stored in the working memory 12.

[0075] The ECC engine 13 may perform error correction coding on data to be written to the nonvolatile memory 120, and may perform error correction decoding on data read from the nonvolatile memory 120. The ECC engine 13 may be configured to perform error correction by using coded modulation such as a low-density parity check (LDPC) code, a BCH code, a turbo code, a Reed-Solomon code, a convolutional code, a recursive systematic code (RSC), a trellis coded modulation (TCM), or a block coded modulation (BCM), but the inventive concept is not limited to these examples. On the other hand, when a segment of the address mapping table AMT is stored in the nonvolatile memory 120, the ECC engine 13 may perform error correction coding on the segment. Therefore, the minimum unit of the segment may be set in units of ECC.

[0076] The host interface 14 may provide an interface between the host 200 and the controller 110a, and may include interfaces according to a universal serial bus (USB), a multimedia card (MMC), a PCI-Express (PCI-E), an AT attachment (ATA), a serial AT attachment (SATA), a parallel AT attachment (PATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), etc.

[0077] The DRAM interface 15 may provide an interface between the controller 110a and the DRAM 130. The DRAM 130 may temporarily store write data provided from the host 200 or data read from the non-volatile memory 120 through the DRAM interface 15. When data in the non-volatile memory 120 is cached in the DRAM 130 under a read request of the host 200, the DRAM 130 may support a cache function of directly providing the cached data to the host 200. At this time, the non-volatile memory 120 is not accessed. Generally, the data transmission rate through the bus format (e.g., SATA or SAS) of the host 200 is much higher than the data transmission rate of the storage channel of the memory system 100. That is, when the interface speed of the host 200 is high, the large-capacity DRAM 130 provides a buffering function, and therefore, the performance degradation caused by the speed difference may be reduced (or minimized). The DRAM 130 may also store an address mapping table AMT and a segment mapping table SMT read out from the non-volatile memory 120.

[0078] The nonvolatile memory interface 16 may provide an interface between the controller 110a and the nonvolatile memory 120. For example, data requested to be written or read from the host 200 may be transmitted and received between the controller 110 and the nonvolatile memory 120 through the nonvolatile memory interface 16. The address mapping table AMT and the segment mapping table SMT stored in the nonvolatile memory 120 may also be transmitted and received between the controller 110a and the nonvolatile memory 120 through the nonvolatile memory interface 16. In an example embodiment, the number of the nonvolatile memory interfaces 16 corresponds to the number of nonvolatile memory chips constituting the nonvolatile memory 120 or the number of channels between the controller 110a and the nonvolatile memory 120.

[0079] Figure 7 is a block diagram illustrating a controller 110 b according to an example embodiment of the inventive concept.

[0080] Reference Figure 7 The controller 110 b may include a processor 11 , a working memory 12 , an ECC engine 13 , a host interface 14 , a non-volatile memory interface 16 , and a cache memory 18 , which can communicate with each other through a bus 17 .

[0081] Operation and reference of the processor 11, the working memory 12, the ECC engine 13, the host interface 14 and the non-volatile memory interface 16 Figure 6 The operations described are the same, and therefore, their redundant descriptions are omitted here.

[0082] The cache memory 18 may support a cache function and may be implemented as a register, SRAM, DRAM, etc. A portion of data stored in the nonvolatile memory 120 as a nonvolatile memory may be temporarily stored in the cache memory 18, and an address mapping table AMT and a segment mapping table SMT may also be stored in the cache memory 18.

[0083] In an example embodiment, when the capacity of the cache memory 18 is insufficient to store all of the address mapping table AMT and the segment mapping table SMT, at least a portion of the address mapping table AMT (e.g., some of the multiple segments of the address mapping table AMT), or at least a portion of each of the address mapping table AMT and the segment mapping table SMT may be stored (cached) in the cache memory 18. Figure 1 When the logical address provided by the memory 200 in FIG. 200 is not included in the mapping entry included in the segment stored in the cache memory 18, other segments included in the segment mapping table stored in the nonvolatile memory 120 may be read from the nonvolatile memory 120 and stored in the cache memory 18. At this time, since the capacity of the cache memory 18 is limited, some segments stored in the cache memory 18 may be flushed. As described above, the updated segments are grouped in page units, and the grouped segments may be stored in the nonvolatile memory 120.

[0084] Figure 8 is a diagram illustrating storage and loading of a mapping table in a memory system according to an example embodiment of the inventive concept.

[0085] Reference Figure 8 , the memory cell array of the nonvolatile memory 120 may include a metadata area 121 and a user data area 122. General data requested to be written from the host 200 may be stored in the user data area 122. Metadata for managing data stored in the user data area 122 may be stored in the metadata area 121. For example, the metadata may include mapping information between logical addresses and physical addresses, write and erase counts for each block, wear leveling information, etc.

[0086] In one example embodiment, the address mapping table AMT and the segment mapping table SMT may be stored in the metadata area 121. When the memory system 100 is powered on, the controller 110 may read the segment mapping table SMT from the nonvolatile memory 120. The controller 110 may also read the address mapping table AMT from the nonvolatile memory 120. At this time, the controller 110 may read the address mapping table AMT by reading the segments from the nonvolatile memory 120 based on the segment mapping information included in the segment mapping table SMT. The segment mapping table SMT and the address mapping table AMT that have been read may be loaded into the DRAM 130. However, example embodiments of the inventive concept are not limited to this example, and in one example embodiment, the segment mapping table SMT and the address mapping table AMT may be loaded into a memory in the controller 110.

[0087] On the other hand, when at least one segment in the address mapping table AMT loaded in the DRAM 130 is updated, the controller 110 may store the at least one segment in the metadata area 121 of the nonvolatile memory 120. As described above, the controller 110 may group the updated at least two segments page by page and provide the grouped data to the nonvolatile memory 120. In addition, the controller 110 may store the updated segment mapping table SMT in the nonvolatile memory 120.

[0088] Fig. 9 is a flowchart illustrating an operating method of a controller according to an example embodiment of the inventive concept.

[0089] Reference Figure 1 and Fig. 9 In operation S110, the controller 110 may update at least two of the plurality of segments included in the address mapping table. For example, the controller 110 may store data in the nonvolatile memory 120 according to a write request (i.e., a write command and a logical address) from the host 200, and may update a mapping entry corresponding to the logical address, thereby updating the segment including the mapping entry. According to a plurality of write requests from the host 200, the controller 110 may update at least two segments.

[0090] In operation S120, the controller 110 may select at least two updated segments from the plurality of segments. For example, the controller 110 may select at least two segments as page data to be stored in one page of the nonvolatile memory 120. In one example embodiment, the controller 110 may select a segment including a relatively large number of updated mapping entries from the updated segments. In another example embodiment, the controller 110 may determine the importance (priority) of each segment, and may select a segment having a relatively high importance from the updated segments.

[0091] In operation S130, the controller 110 may store the selected at least two segments in the nonvolatile memory 120. For example, the controller 110 may group the selected at least two segments to generate page data, and provide the page data and a physical address indicating a location where the page data is to be stored to the nonvolatile memory 120. The nonvolatile memory 120 may store the page data in the memory cell array MCA based on the physical address. The page data including the at least two segments may be stored in a metadata area of ​​the memory cell array MCA.

[0092] In operation S140, the controller 110 may update the segment mapping table based on the physical addresses of the at least two segments stored in the memory cell array MCA of the nonvolatile memory 120. For example, based on the stored physical page numbers of the memory segments and their offsets, the controller 110 may manage the physical addresses of each of the plurality of segments included in the address mapping table AMT, and may update the physical addresses corresponding to the two segments.

[0093] In operation S150 , the controller 110 may store the segment mapping table SMT in the nonvolatile memory 120 periodically or when a specific event occurs, such as power off of the memory system 100 .

[0094] Fig.10 is a diagram illustrating an operating method of a controller according to an example embodiment of the inventive concept.

[0095] Reference Fig.10 , the controller 110 may include a cache memory 18, and a portion AMTa of the address mapping table AMT may be loaded (stored) into the cache memory 18. The capacity of the cache memory 18 may be relatively small and the entire address mapping table AMT may not be loaded, so a portion AMTa of the address mapping table AMT stored in the nonvolatile memory 120 may be loaded into the cache memory 18. For example, the first to eighth segments SG0 to SG7 may be loaded into the cache memory 18. In addition, although not shown, the segment mapping table SMT may be loaded into the cache memory 18.

[0096] In a state where the second segment SG1, the seventh segment SG6, and the eighth segment SG7 of the first to eighth segments SG0 to SG7 are updated, some of the updated segments may be flushed when other segments are to be loaded into the cache memory 18. That is, some of the updated segments may be stored in the nonvolatile memory 120.

[0097] The mapping data management module MDM may select some of the updated segments SG1, SG6, and SG7, and group the selected segments into page data. In an example embodiment, the mapping data management module MDM may select segments including more updated mapping entries or segments of relatively high importance. For example, the mapping data management module MDM may select the second segment SG1 and the eighth segment SG7, and may group the selected second segment SG1 and the eighth segment SG7 into page data. The second segment SG1 and the eighth segment SG7 may be provided to the nonvolatile memory 120, and the nonvolatile memory 120 may store the second segment SG1 and the eighth segment SG7 in one page of the metadata area 121.

[0098] On the other hand, among the plurality of segments included in the address mapping table AMT stored in the nonvolatile memory 120, other segments that are not loaded into the cache memory 18 may be loaded into the cache memory 18. For example, the ninth segment SG8 and the tenth segment SG9 may be cached in the cache memory 18. Therefore, another part AMTb of the address mapping table AMT may be loaded into the cache memory 18.

[0099] Fig.11 is a flowchart illustrating an operating method of a controller according to an example embodiment of the inventive concept. Fig.11 The method of operation of the controller when the memory system is powered on is shown.

[0100] Reference Figure 1 and Fig.11 , in operation S210 , the memory system 100 and the controller 110 may be powered on, and the controller 110 may enter a setup phase according to the power-on.

[0101] In operation S220, the controller 110 may load the segment mapping table SMT. For example, the controller 110 may load the segment mapping table SMT stored in the nonvolatile memory 120 into a memory in the controller 110 or a buffer (eg, DRAM) outside the controller 110.

[0102] In operation S230, the controller 110 may load the address mapping table AMT based on the segment mapping information of the segment mapping table SMT. The segment mapping table SMT includes the physical address of each segment included in the address mapping table AMT. Therefore, the controller 110 may read the segment by accessing the area where each segment in the memory cell array MCA is stored based on the segment mapping information of the segment mapping table SMT. Therefore, the segment mapping table SMT may be loaded into a memory in the controller 110 or a buffer (e.g., DRAM) outside the controller 110.

[0103] Fig.12is a flow chart illustrating an operating method of a controller according to an example embodiment of the inventive concept. In this embodiment, the controller may change the size of a segment during operation of a memory system.

[0104] Reference Figure 1 and Fig.12 In operation S310, the controller 110 may set the size (data size) of the segment to a minimum size. In an example embodiment, the minimum size may be an ECC unit, and the segment may include a plurality of map entries.

[0105] In operation S320 , the controller 110 may determine the number of updated segments among the plurality of segments included in the address mapping table AMT. For example, the controller 110 may count the number of updated segments during operation of the memory system 100 .

[0106] In operation S330, the controller 110 may reset the size of the segment based on the determined number and reset the segment mapping table. For example, the logical address LA of the data requested to be written by the host 200 may be concentrated in two specific segments, so the controller 110 may determine that the two segments have been updated. The controller 110 may set the size of the segment to 1 / 2 of the page so that the two segments can be grouped as page data. Multiple segments set to the minimum size may be reset to one segment. On the other hand, the segment mapping table includes the physical address of each of the multiple segments. When the multiple segments are reset to one segment, the physical address of each of the multiple segments may be set to the physical address corresponding to the one segment.

[0107] FIG. 13A to FIG. 13C An embodiment of adjusting the size of a segment according to an example embodiment of the inventive concept is illustrated.

[0108] Reference FIG. 13A to FIG. 13C , the address mapping table AMT may include a plurality of segments SG0 to SGn-1, the size of the segment may be 2KB, and the size of the write unit (ie, page) may be 16KB.

[0109] Reference Fig.13A , two segments SG2 and Sga among the multiple segments SG0 to SGn-1 may be updated. The controller ( Figure 1 110) can store the updated two segments SG2 and SGa in the non-volatile memory ( Figure 1120 in the nonvolatile memory 120). At this time, the controller 110 may reset the size of the segment to 8KB, and may reset four segments of the plurality of segments SG0 to SGn-1 into one segment. For example, the first to fourth segments SG0 to SG3 may be reset to the first segment SG'0. The controller 110 may group the reset segments SG'0 and SG'm including the updated segments SG2 and SGa, respectively, into one page data, and may store the page data in the nonvolatile memory 120.

[0110] Reference Fig. 13B , four segments SG2, SG7, SGa and SGb among the plurality of segments SG0 to SGn-1 may be updated. The controller ( Figure 1 110) can store the updated four segments SG2, SG7, SGa and SGb in the non-volatile memory ( Figure 1 120). At this time, the controller 110 may reset the size of the segment to 4KB, and may reset two segments of the plurality of segments SG0 to SGn-1 into one segment. For example, the first segment SG0 and the second segment SG1 may be reset to the first segment SG'0. The controller 110 may group the reset segments SG'1, SG'3, SG'r, and SG't including the updated segments SG2, SG7, SGa, and SGb, respectively, into one page data, and may store the page data in the nonvolatile memory 120.

[0111] Reference Fig. 13C , seven segments SG2, SG4, SG5, SG7, SGa, SGb, and SGn-1 among the plurality of segments SG0 to SGn-1 may be updated. The controller ( Figure 1 110) can store the updated seven segments SG2, SG4, SG5, SG7, SGa, SGb and SGn-1 in the non-volatile memory ( Figure 1 The size of the seven segments is 14KB. Therefore, there is no need to reset the segment size. The controller 110 can group the seven segments SG2, SG4, SG5, SG7, SGa, SGb, and SGn-1 into one page data and store the page data in the nonvolatile memory 120.

[0112] Thus, according to an exemplary embodiment of the inventive concept, the size of a segment may be variable during operation of the memory system 100. FIG. 13A to FIG. 13C When the size of a segment is reset, the physical address of each of the multiple segments may be set to a physical address corresponding to the segment into which the multiple segments are merged and reset. The segment mapping table SMT may be reset to include the physical address of the reset segment.

[0113] Fig.14is a block diagram illustrating an SSD according to an example embodiment of the inventive concept.

[0114] Reference Fig.14 , the SSD system 1000 includes a host 1100 and an SSD 1200 .

[0115] The SSD 1200 may include an SSD controller 1210 , a buffer memory 1220 , and a nonvolatile memory device 1230 .

[0116] The SSD controller 1210 provides a physical connection between the host 1100 and the SSD 1200. The SSD controller 1210 provides an interface to the SSD 1200 in response to a bus format of the host 1100. Specifically, the SSD controller 1210 decodes a command provided from the host 1100. According to the decoding result, the SSD controller 1210 accesses the nonvolatile memory device 1230. A universal serial bus (USB), a small computer system interface (SCSI), PCI express, ATA, parallel ATA (PATA), serial ATA (SATA), serial attached SCSI (SAS), etc. can be used as the bus format of the host 1100.

[0117] In addition, the SSD controller 1210 may include a processor configured to perform the functions of the mapping data management module MDM, and may manage the Figure 1 to Figure 1 3. When storing updated segments among the plurality of segments included in the address mapping table AMT loaded into the buffer memory 1220 into the nonvolatile memory device 1230, the SSD controller 1210 may select at least two updated segments, group the selected at least two segments into page data, and provide the page data together with the physical address to the nonvolatile memory device 1230. The segment mapping table SMT may be updated based on the physical address and the page data provided to the nonvolatile memory device 1230.

[0118] Write data provided from the host 1100 or data read from the nonvolatile memory device 1230 is temporarily stored in the buffer memory 1220. When data in the nonvolatile memory device 1230 is cached at a read request of the host 1100, the buffer memory 1220 supports a cache function of directly providing cache data to the host 1100. Generally, the rate at which the host 1100 transmits data in a bus format (e.g., SATA or SAS) is much higher than the transmission rate of the storage channel of the SSD 1200. That is, when the interface speed of the host 1100 is high, by providing a large-capacity buffer memory 1220, the performance degradation caused by the speed difference can be reduced (or minimized).

[0119] The buffer memory 1220 may also store an address mapping table AMT and a segment mapping table SMT.

[0120] The nonvolatile memory device 1230 is provided as a storage medium of the SSD 1200. For example, the nonvolatile memory device 1230 may be provided as a NAND type flash memory having a large storage capacity. The nonvolatile memory device 1230 is coupled to the SSD controller 1210 through a plurality of channels. Although the nonvolatile memory device 1230 as a storage medium has been described by the example of a NAND flash memory, the nonvolatile memory device 1230 may also be configured with other nonvolatile memory devices. For example, PRAM, MRAM, ReRAM, FRAM, NOR flash memory, etc. may be used as a storage medium, and a memory system in which different types of storage devices are combined may also be applied. In addition, a volatile memory device (e.g., DRAM) may be included as a storage medium.

[0121] As described above, example embodiments have been disclosed in the drawings and the specification. Although example embodiments have been described herein with reference to specific terms, it should be understood that they are only used for the purpose of describing the technical concept of the inventive concept, rather than for limiting the scope of the inventive concept defined in the appended claims. Therefore, it will be understood by those skilled in the art that various modifications and equivalent embodiments are possible without departing from the scope of the inventive concept. Therefore, the true scope of protection of the example embodiments of the inventive concept should be determined based on the appended claims.

Claims

1. A memory controller, comprising: a memory configured to store an address mapping table and a segment mapping table, the address mapping table comprising a plurality of segments, each of the plurality of segments comprising a plurality of mapping entries representing mapping information between logical addresses and physical addresses, and the segment mapping table comprising a physical address representing an area in a non-volatile memory where each of the plurality of segments of the address mapping table is stored; as well as a processing circuit configured to: determine at least two updated segments of the plurality of segments of the address mapping table as page data to be stored in a page of the non-volatile memory; and updating the segment mapping table based on physical addresses representing areas where the at least two updated segments are to be stored in the non-volatile memory, wherein the updated segments represent segments including at least one updated mapping entry, The memory controller is configured to: load the address mapping table from the non-volatile memory into the memory of the memory controller based on the segment mapping information in the segment mapping table.

2. The memory controller according to claim 1, wherein: Each of the physical addresses includes a physical page number and an offset, the offset indicating the location of the memory segment in the page.

3. The memory controller according to claim 1, wherein: The processing circuit is configured to determine the at least two updated segments based on a number of updated map entries associated with each segment of the plurality of segments.

4. The memory controller according to claim 1, wherein: The processing circuit is configured to determine the at least two updated segments based on priorities of the plurality of segments.

5. The memory controller according to claim 1, wherein: A data size of each of the plurality of segments is variable and smaller than a data size of the one page.

6. The memory controller according to claim 1, wherein: A minimum data size of each of the plurality of segments is equal to a unit size for performing error correction.

7. The memory controller according to claim 1, wherein: The nonvolatile memory includes a metadata area and a user data area, the metadata area is configured to store metadata, and the user data area is configured to store data provided from a host, and wherein, The memory controller is configured to store the address mapping table and the segment mapping table in the metadata area of ​​the nonvolatile memory.

8. The memory controller according to claim 7, wherein: The memory controller is further configured to load the segment mapping table from the non-volatile memory into the memory of the memory controller during a power-on setup phase.

9. The memory controller according to claim 7, wherein: The non-volatile memory includes NAND flash memory cells.

10. A method of operating a memory controller, the method comprising: selecting at least two updated segments among a plurality of segments included in an address mapping table, the address mapping table comprising a plurality of segments, each segment of the plurality of segments comprising a plurality of mapping entries representing mapping information between logical addresses and physical addresses; grouping the at least two updated segments into one page data, the updated segment representing a segment including at least one updated mapping entry; Instructing the non-volatile memory to store the page data at the physical address; updating a segment mapping table based on the physical address, the segment mapping table comprising segment mapping information indicating a location where each of the plurality of segments is stored in the non-volatile memory; as well as The address mapping table is loaded from the nonvolatile memory into a memory of the memory controller based on the segment mapping information in the segment mapping table.

11. The method according to claim 10, wherein: Each of the plurality of segments includes a plurality of mapping entries indicating mapping information between logical addresses and physical addresses, and each of the plurality of segments has a data size smaller than a write unit of the nonvolatile memory.

12. The method according to claim 10, wherein: Selecting the at least two updated segments comprises: A number of updated map entries associated with each segment of the plurality of segments is determined.

13. The method according to claim 10, further comprising: determining a number of the at least two updated segments in the plurality of segments; as well as A size of each of the plurality of segments is changed based on the number of the at least two updated segments.

14. A storage device comprising: Non-volatile memory; a buffer memory configured to store an address mapping table and a segment mapping table, the address mapping table including a plurality of segments, each of the plurality of segments including a plurality of mapping entries representing mapping information between logical addresses and physical addresses, and the segment mapping table including a physical address representing an area in the non-volatile memory where each of the plurality of segments of the address mapping table is stored; as well as a memory controller configured to: group at least two updated segments of the plurality of segments of the address mapping table into page data to be stored in one page of the non-volatile memory, provide the page data to the non-volatile memory, and update the segment mapping table based on a physical address representing an area in the non-volatile memory where the at least two updated segments are to be stored, wherein the updated segment represents a segment including at least one updated mapping entry, The memory controller is configured to: load the address mapping table from the non-volatile memory into the buffer memory based on the segment mapping information of the segment mapping table.

15. The storage device according to claim 14, wherein: The memory controller is configured to determine the at least two updated segments based on a number of updated map entries associated with each segment of the plurality of segments.

16. The storage device according to claim 14, wherein: The memory controller is configured to store the address mapping table and the segment mapping table in a metadata area of ​​the nonvolatile memory.

17. The storage device according to claim 16, wherein: The memory controller is further configured to load the segment mapping table from the non-volatile memory into the buffer memory during a power-on setup phase.

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