Crystalline silicon solar cell and manufacturing method thereof

Abstract

The present invention relates to a crystalline silicon solar cell and a method for manufacturing the same. The solar cell comprises a substrate, which comprises a P-type silicon wafer, a top passivation layer, a tunneling layer, and a bottom passivation layer. The tunneling layer is disposed on the bottom surface of the P-type silicon wafer and has hole transport capability; the bottom passivation layer is a boron-doped passivation layer disposed on the bottom surface of the tunneling layer. The present invention provides a passivation structure and method based on a P-type silicon wafer. The structure and method are highly compatible with existing PERC passivation technology and are conducive to the industrial development of solar cells. The present invention also provides a solution for using a material with hole transport capability as a tunneling layer, so that the tunneling layer blocks electron transport while selecting holes, thereby optimizing battery performance.

Description

Technical Field

[0001] The present invention relates to the field of energy, and in particular to a crystalline silicon solar cell and a method for manufacturing the same. Background Art

[0002] With the accelerating global consumption of conventional fossil fuels such as coal, oil, and natural gas, the ecological environment continues to deteriorate, and greenhouse gas emissions, in particular, leading to increasingly severe global climate change, the sustainable development of human society is under serious threat. Countries around the world are formulating their own energy development strategies to address the limited availability of conventional fossil energy resources and the environmental challenges associated with their development and utilization. Solar energy, with its reliability, safety, widespread availability, longevity, environmental friendliness, and abundant resources, has become one of the most important renewable energy sources and is expected to become a major pillar of future global electricity supply.

[0003] During this new round of energy transformation, my country's photovoltaic industry has grown into a strategic emerging industry with international competitive advantages. However, the development of the photovoltaic industry still faces many problems and challenges. Conversion efficiency and reliability are the biggest technical barriers to its development, while cost control and scale-up pose economic constraints.

[0004] Currently, heterojunction solar cells are hailed as the next generation of ultra-high-efficiency solar cell technology with the greatest potential for industrialization due to their advantages, including high conversion efficiency, short manufacturing process, thin silicon wafers, low temperature coefficient, no light-induced degradation, and the ability to generate electricity on both sides with a high bifaciality ratio. However, achieving large-scale development of solar cell technology also presents certain challenges: on the one hand, the manufacturing cost of heterojunction solar cells is relatively high; on the other hand, when solar cells are packaged using conventional packaging techniques, the stability of the tension in the soldering ribbons is difficult to control. Furthermore, some solar cells cannot be processed using the high-temperature welding processes of traditional crystalline silicon cells, requiring low-temperature welding processes and materials, making the packaging process more challenging.

[0005] To compensate for the above defects, other high-efficiency crystalline silicon solar cells can be used in some scenarios instead of heterojunction solar cells.

[0006] In recent years, a variety of new crystalline silicon technologies have emerged. Currently, PERC solar cells dominate the market, with mass production efficiencies exceeding 22%. However, further increases in PERC solar cell conversion efficiency are limited. A new passivated contact structure, based on existing PERC technology, can boost cell conversion efficiency to over 23% by adding two or three additional steps. Passivated contact technology, due to its strong compatibility with existing PERC technology, is gaining increasing favor in the market and among research institutions.

[0007] However, the existing passivation contact technology is based on N-type crystalline silicon. However, since the cost of N-type silicon wafers is higher than that of P-type silicon wafers, and more than 90% of mass-produced battery technologies on the market are based on P-type silicon wafers, if the N-type passivation contact technology is modified, it is necessary to add technologies such as boron diffusion or ion implantation, which increases the battery manufacturing cost and is not conducive to the development of passivation contact battery technology.

[0008] Therefore, it is necessary to provide a crystalline silicon solar cell and a manufacturing method thereof to at least partially solve the above problems. Summary of the Invention

[0009] The present invention aims to provide a crystalline silicon solar cell and its manufacturing method. The invention provides a passivation structure and method based on P-type silicon wafers. This structure and method are highly compatible with existing PERC passivation technology, facilitating the industrialization of solar cells. The invention also provides a solution for using a material with hole-transporting capabilities as a tunneling layer, enabling the tunneling layer to select holes while simultaneously blocking electrons, thereby optimizing cell performance.

[0010] Furthermore, the crystalline silicon solar cell provided by the present invention has a relatively simple structure and is easy to produce and manufacture, and the manufacturing method provided by the present invention has a simple process route and is easy to implement.

[0011] According to one aspect of the present invention, a crystalline silicon solar cell is provided, comprising a substrate and grid lines arranged on the top and bottom surfaces of the substrate, wherein the substrate comprises:

[0012] A P-type silicon wafer, wherein the top surface of the P-type silicon wafer is an n-type surface;

[0013] A top passivation layer, wherein the top passivation layer is disposed on the n-type surface and is a silicon dioxide passivation layer;

[0014] a tunneling layer, the tunneling layer being disposed on the bottom surface of the P-type silicon wafer and having hole transport capability;

[0015] A bottom passivation layer is provided on the bottom surface of the tunneling layer, and the bottom passivation layer is a boron-doped passivation layer.

[0016] In one embodiment, the thickness of the P-type silicon wafer is 100 μm-220 μm; and / or

[0017] The thickness of the top passivation layer is 1 nm to 20 nm; and / or

[0018] The thickness of the tunneling layer is 0.5 nm to 2 nm; and / or

[0019] The thickness of the bottom passivation layer is 40nm-250nm.

[0020] In one embodiment, the bottom passivation layer is a boron-doped polysilicon thin film layer, a boron-doped amorphous thin film layer, or a boron-doped microcrystalline thin film layer.

[0021] In one embodiment, an anti-reflection film is disposed on the top surface of the top passivation layer and the bottom surface of the bottom passivation layer.

[0022] In one embodiment, the anti-reflection film is an integral film structure made of silicon nitride; or

[0023] The anti-reflection film is an integral film structure made of silicon oxynitride; or

[0024] The anti-reflection film is a stacked structure formed by a silicon oxynitride layer and a silicon nitride layer.

[0025] In one embodiment, the thickness of the anti-reflection film is 70 nm-200 nm.

[0026] In one embodiment, the n-type surface is a phosphorus-containing surface.

[0027] In one embodiment, the tunneling layer includes at least one of an aluminum oxide layer, a molybdenum oxide layer, a tin oxide layer, a silicon oxide layer, and a nickel oxide layer.

[0028] Another aspect of the present invention provides a method for manufacturing a crystalline silicon solar cell, the method comprising providing a substrate and applying grid lines on the top and bottom surfaces of the substrate, wherein the step of providing the substrate comprises the following steps:

[0029] Setting a P-type silicon wafer;

[0030] Disposing a tunneling layer having hole tunneling capability on the bottom surface of the P-type silicon wafer;

[0031] Disposing a boron-doped bottom passivation layer on the bottom surface of the tunneling layer;

[0032] Etching the edge and top surface of the P-type silicon wafer to remove boron thereon;

[0033] A top passivation layer made of silicon dioxide is disposed on the top surface of the P-type silicon wafer.

[0034] In one embodiment, the step of providing a P-type silicon wafer includes the following steps:

[0035] Cleaning and texturing the P-type silicon wafer with a sodium hydroxide or potassium hydroxide solution;

[0036] forming a phosphorus-doped N-type surface on the top and bottom surfaces of the P-type silicon wafer by thermal diffusion or ion implantation to form a PN junction;

[0037] The phosphorus on the edge and bottom surface of the P-type silicon wafer is removed by dry or wet etching, and the phosphorus-silicate glass on the bottom and top surfaces of the P-type silicon wafer is removed.

[0038] In one embodiment, the step of providing the tunneling layer is achieved by a PECVD method, an ALD method, a LPCVD method, a thermal oxidation method, an evaporation method, or a PEALD method, and the tunneling layer is provided to have a thickness of 0.5 nm to 2 nm.

[0039] In one embodiment, the step of providing the bottom passivation layer is achieved by a PECVD method or a LPCVD method, and the bottom passivation layer is provided to have a thickness of 40 nm to 250 nm.

[0040] In one embodiment, the bottom passivation layer is a boron-doped polysilicon thin film layer, a boron-doped amorphous thin film layer, or a boron-doped microcrystalline thin film layer.

[0041] In one embodiment, the step of providing a top passivation layer includes: preparing the top passivation layer by using at least one of thermal oxidation, ozone, wet oxidation and ALD methods, and making the thickness of the top passivation layer be 1 nm-20 nm.

[0042] In one embodiment, the step of providing a base sheet further includes the step of providing an anti-reflection film on the top surface of the top passivation layer and the bottom surface of the bottom passivation layer.

[0043] In one embodiment, the step of providing the anti-reflection film includes: providing the anti-reflection film including at least one of a silicon nitride layer and a silicon oxynitride layer by a PECVD method, and forming the anti-reflection film to a thickness of 70 nm to 200 nm.

[0044] In one embodiment, the tunneling layer includes at least one of an aluminum oxide layer, a molybdenum oxide layer, a tin oxide layer, a silicon oxide layer, and a nickel oxide layer.

[0045] According to the present invention, the crystalline silicon solar cell is based on a P-type silicon wafer, which is highly compatible with existing PERC passivation technology, facilitating the industrialization of solar cells. The present invention also provides a solution for using a material with hole-transporting capabilities as a tunneling layer, enabling the tunneling layer to select holes while simultaneously blocking electron transmission, thereby optimizing cell performance. Furthermore, the crystalline silicon solar cell provided by the present invention has a relatively simple structure and is easy to manufacture, and the manufacturing method provided by the present invention has a simple and easy-to-implement process. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] To better understand the above and other objects, features, advantages, and functions of the present invention, reference may be made to the preferred embodiments shown in the accompanying drawings. Like reference numerals in the accompanying drawings refer to like components. Those skilled in the art should understand that the accompanying drawings are intended to illustrate preferred embodiments of the present invention by way of illustration and are not intended to limit the scope of the present invention. The components in the drawings are not drawn to scale.

[0047] Figure 1 A top view of a crystalline silicon solar cell according to a preferred embodiment of the present invention;

[0048] Figure 2 for Figure 1 A schematic diagram of the cross-section taken along line AA rotated 90° clockwise;

[0049] Figure 3 4 is a flow chart of a manufacturing method according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0050] Now referring to the accompanying drawings, the specific embodiments of the present invention will be described in detail. What is described here is only the preferred embodiment of the present invention. Those skilled in the art can think of other ways to implement the present invention based on the preferred embodiment, and the other ways also fall within the scope of the present invention.

[0051] The present invention provides a crystalline silicon solar cell and a manufacturing method thereof. Figures 1 to 2 shows a schematic diagram of a crystalline silicon solar cell according to a preferred embodiment of the present invention, Figure 3 Schematic diagram of the manufacturing method.

[0052] like Figure 1 As shown, the solar cell 1 includes a substrate and grid lines arranged on the top and bottom surfaces of the substrate. Figure 2 The substrate includes a P-type silicon wafer 2, a top passivation layer 4, a tunneling layer 6, and a bottom passivation layer 7. The gate lines include auxiliary gate lines and main gate lines, which can be made of one or more metals such as silver, gold, copper, aluminum, and nickel. Figure 2 , a top-side auxiliary gate line 8 located on the top side of the P-type silicon wafer 2 and a bottom-side auxiliary gate line 9 located on the bottom side of the P-type silicon wafer 2 are shown.

[0053] The top surface of the P-type silicon wafer 2 is the n-type surface 3, which may be a phosphorus-containing surface and has a thickness of 100 μm-220 μm. A top passivation layer 4 is disposed on the n-type surface 3 and is a silicon dioxide passivation layer with a thickness of approximately 1 nm-20 nm.

[0054] Tunneling layer 6 is disposed on the bottom surface of P-type silicon wafer 2 and has hole transport capabilities. For example, tunneling layer 6 may include at least one of an aluminum oxide layer, a molybdenum oxide layer, a tin oxide layer, a silicon oxide layer, and a nickel oxide layer. For example, tunneling layer 6 may be a single layer structure or a stacked structure of the aforementioned layers. Because aluminum oxide, molybdenum oxide, tin oxide, silicon oxide, and nickel oxide have hole transport capabilities, their ability to select holes while simultaneously blocking electron transport can optimize the performance of crystalline silicon solar cell 1. The thickness of tunneling layer 6 is approximately 0.5 nm to 2 nm.

[0055] A bottom passivation layer 7 is disposed on the bottom surface of the tunneling layer 6. The bottom passivation layer 7 is a boron-doped passivation layer that protects the tunneling layer 6 and provides passivation for the crystalline silicon solar cell 1. The bottom passivation layer 7 is preferably a boron-doped polycrystalline silicon thin film layer. Alternatively, the bottom passivation layer 7 may be a boron-doped amorphous silicon thin film layer or a boron-doped polycrystalline silicon thin film layer. The thickness of the bottom passivation layer 7 may be, for example, 40 nm to 250 nm.

[0056] Preferably, an anti-reflection film 5 may be further provided on the top surface of the top passivation layer 4 and the bottom surface of the bottom passivation layer 7. The anti-reflection film 5 may be made of, for example, silicon nitride or silicon oxynitride, or may be a stacked structure formed by a silicon nitride layer and a silicon oxynitride layer. The thickness of the anti-reflection film 5 may be, for example, 70 nm to 200 nm.

[0057] On the other hand, this embodiment also provides a method for manufacturing a crystalline silicon solar cell 1. Figure 3 The method includes the following steps S1 to S5 in sequence.

[0058] S1 is a step of setting a P-type silicon wafer 2. This step also includes the following sub-steps:

[0059] Cleaning and texturing the P-type silicon wafer 2 with a sodium hydroxide or potassium hydroxide solution to remove metal ions and a cut damage layer on the surface of the P-type silicon wafer 2 and form a pyramid texture surface, wherein the size of the pyramid is, for example, 2 μm to 10 μm;

[0060] Phosphorus-doped N-type surfaces are formed on the top and bottom surfaces of the P-type silicon wafer 2 by thermal diffusion or ion implantation to form a PN junction (surface resistance is 80Ω / □-240Ω / □);

[0061] The phosphorus on the edge and bottom surface of the P-type silicon wafer 2 is removed by dry or wet etching, and the phosphorus-silicate glass on the bottom and top surfaces of the P-type silicon wafer 2 is removed.

[0062] S2 is the step of providing a tunneling layer 6 on the bottom surface of the P-type silicon wafer 2. The tunneling layer 6 comprises an oxide layer. This step can be achieved by PECVD, ALD, LPCVD, thermal oxidation, evaporation, or PEALD, and the tunneling layer 6 can be provided to have a thickness of 0.5 nm to 2 nm. Preferably, in this step, a single layer structure of one of aluminum oxide, molybdenum oxide, tin oxide, silicon oxide, and nickel oxide, or a stacked structure of two or more layers, can be provided as the tunneling layer 6. Because aluminum oxide, molybdenum oxide, tin oxide, silicon oxide, and nickel oxide have the function of selecting holes while blocking electron transmission, they can optimize the performance of the crystalline silicon solar cell 1.

[0063] S3 is a step of providing a boron-doped bottom passivation layer 7 on the bottom surface of the tunneling layer 6. This step is achieved by a PECVD method or a LPCVD method, and the bottom passivation layer 7 is provided to have a thickness of 40 nm to 250 nm. Preferably, the bottom passivation layer 7 can be provided as a boron-doped polycrystalline silicon thin film layer, or a boron-doped amorphous silicon thin film layer or a boron-doped microcrystalline thin film layer.

[0064] S4 is a step of etching the edge and top surface of the P-type silicon wafer 2. This step can remove the boron plated on the edge and top surface of the P-type silicon wafer 2 by dry or wet method.

[0065] S5 is a subsequent processing step, wherein S5 may include, for example, sub-steps S51 to S53 (not shown in the figure) described below.

[0066] In S51, a top passivation layer 4 made of silicon dioxide is disposed on the top surface of the P-type silicon wafer 2, that is, on the phosphorus-containing n-type surface 3 of the top surface of the P-type silicon wafer 2. In this step, the top passivation layer 4 can be formed using at least one of thermal oxidation, ozone, wet oxidation, and ALD methods, and the thickness of the top passivation layer 4 is 1 nm to 20 nm.

[0067] S52 is, for example, a step of providing an anti-reflection film 5 on the top surface of the top passivation layer 4 and the bottom surface of the bottom passivation layer 7. This step may include: providing the anti-reflection film 5 comprising at least one of a silicon nitride layer and a silicon oxynitride layer by PECVD, and forming the anti-reflection film 5 to a thickness of 70 nm to 200 nm.

[0068] S53 is, for example, a step of printing grid lines, or a step of printing electrodes. In this step, the main grid lines and the auxiliary grid lines can be printed on the top and bottom surfaces of the substrate using one or more of silver, gold, copper, aluminum, and nickel. Figure 2 The gate lines shown in FIG are auxiliary gate lines.

[0069] The present invention provides a passivation structure and method based on P-type silicon wafers. This structure and method are highly compatible with existing PERC passivation technology, facilitating the industrial development of solar cells. The present invention also provides a solution for using a material with hole-transporting capabilities as a tunneling layer, enabling the tunneling layer to select holes while simultaneously blocking electron transmission, thereby optimizing cell performance. Furthermore, the crystalline silicon solar cell structure provided by the present invention is relatively simple and easy to manufacture, and the manufacturing method provided by the present invention has a simple and easy-to-implement process.

[0070] The above description of various embodiments of the present invention is provided for the purpose of description to one of ordinary skill in the relevant art. It is not intended to exclude or limit the present invention to a single disclosed embodiment. As mentioned above, a person of ordinary skill in the field of the above teachings will understand the various substitutions and variations of the present invention. Therefore, although some alternative embodiments are specifically described, a person of ordinary skill in the art will understand or relatively easily develop other embodiments. The present invention is intended to include all substitutions, modifications and variations of the present invention described herein, as well as other embodiments that fall within the spirit and scope of the present invention described above.

[0071] Reference numerals:

[0072] Crystalline silicon solar cell 1

[0073] P-type silicon wafer 2

[0074] n-type surface 3

[0075] Top passivation layer 4

[0076] Anti-reflection film 5

[0077] Tunneling layer 6

[0078] Bottom passivation layer 7

[0079] Top side secondary grid line 8

[0080] Bottom side secondary grid line 9.

Claims

1. A crystalline silicon solar cell, comprising a substrate and grid lines arranged on the top and bottom surfaces of the substrate, wherein the substrate comprises: A P-type silicon wafer, wherein the top surface of the P-type silicon wafer is an n-type surface; A top passivation layer, wherein the top passivation layer is disposed on the n-type surface and is a silicon dioxide passivation layer, Characterized in that the base sheet further comprises: a tunneling layer, the tunneling layer being disposed on the bottom surface of the P-type silicon wafer and having hole transport capability, the tunneling layer being a stacked structure composed of two or more of an aluminum oxide layer, a molybdenum oxide layer, a tin oxide layer, a silicon oxide layer, and a nickel oxide layer; A bottom passivation layer is provided on the bottom surface of the tunneling layer, and the bottom passivation layer is a boron-doped passivation layer.

2. The crystalline silicon solar cell according to claim 1, characterized in that: The thickness of the P-type silicon wafer is 100um-220um; and / or The thickness of the top passivation layer is 1 nm to 20 nm; and / or The thickness of the tunneling layer is 0.5 nm to 2 nm; and / or The thickness of the bottom passivation layer is 40nm-250nm.

3. The crystalline silicon solar cell according to claim 1, characterized in that: The bottom passivation layer is a boron-doped polysilicon thin film layer, a boron-doped amorphous thin film layer or a boron-doped microcrystalline thin film layer.

4. The crystalline silicon solar cell according to claim 1, characterized in that: An anti-reflection film is disposed on a top surface of the top passivation layer and a bottom surface of the bottom passivation layer.

5. The crystalline silicon solar cell according to claim 4, characterized in that: The anti-reflection film is an integral film structure made of silicon nitride; or The anti-reflection film is an integral film structure made of silicon oxynitride; or The anti-reflection film is a stacked structure formed by a silicon oxynitride layer and a silicon nitride layer.

6. The crystalline silicon solar cell according to claim 4, characterized in that: The thickness of the anti-reflection film is 70nm-200nm.

7. The crystalline silicon solar cell according to claim 1, characterized in that: The n-type surface is a phosphorus-containing surface.

8. A method for manufacturing a crystalline silicon solar cell, the method comprising providing a substrate and applying grid lines on the top and bottom surfaces of the substrate, wherein: The step of providing the substrate sheet comprises the following steps: Setting a P-type silicon wafer; A tunneling layer having hole tunneling capability is provided on the bottom surface of the P-type silicon wafer, wherein the tunneling layer has a stacked structure and is composed of two or more of an aluminum oxide layer, a molybdenum oxide layer, a tin oxide layer, a silicon oxide layer, and a nickel oxide layer; Disposing a boron-doped bottom passivation layer on the bottom surface of the tunneling layer; Etching the edge and top surface of the P-type silicon wafer to remove boron thereon; A top passivation layer made of silicon dioxide is disposed on the top surface of the P-type silicon wafer.

9. The method according to claim 8, characterized in that The steps for setting up a P-type silicon wafer include the following steps: Cleaning and texturing the P-type silicon wafer with a sodium hydroxide or potassium hydroxide solution; forming a phosphorus-doped N-type surface on the top and bottom surfaces of the P-type silicon wafer by thermal diffusion or ion implantation to form a PN junction; The phosphorus on the edge and bottom surface of the P-type silicon wafer is removed by dry or wet etching, and the phosphorus-silicate glass on the bottom and top surfaces of the P-type silicon wafer is removed.

10. The method according to claim 8, characterized in that The step of providing the tunneling layer is achieved by a PECVD method, an ALD method, a LPCVD method, a thermal oxidation method, an evaporation method or a PEALD method, and the tunneling layer is provided so as to have a thickness of 0.5 nm to 2 nm.

11. The method according to claim 8, characterized in that The step of providing a bottom passivation layer is achieved by a PECVD method or a LPCVD method, and the bottom passivation layer is provided to have a thickness of 40 nm to 250 nm.

12. The method according to claim 11, characterized in that The bottom passivation layer is a boron-doped polysilicon thin film layer, a boron-doped amorphous thin film layer or a boron-doped microcrystalline thin film layer.

13. The method according to claim 8, characterized in that The step of providing a top passivation layer includes: preparing the top passivation layer by using at least one of thermal oxidation, ozone, wet oxidation and ALD methods, and making the thickness of the top passivation layer 1 nm-20 nm.

14. The method according to claim 8, characterized in that The step of providing a base sheet further includes the step of providing an anti-reflection film on the top surface of the top passivation layer and the bottom surface of the bottom passivation layer.

15. The method according to claim 14, characterized in that The step of providing an anti-reflection film includes: providing an anti-reflection film comprising at least one of a silicon nitride layer and a silicon oxynitride layer by a PECVD method, and forming the anti-reflection film to a thickness of 70 nm to 200 nm.

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