Single-Input Multiple-Output (SIMO) Converter with Switchable Quiescent State Controller

Abstract

The present application discloses a single-input multiple-output (SIMO) converter with a controller capable of switching a quiescent state. The system (100) includes an inductor (120) and a first switch (S1) coupled between a first end of the inductor (120) and a voltage supply node (112). The system (100) also includes a second switch (S2) coupled between a first end of the inductor (120) and a negative output supply node (114). The system (100) also includes a third switch (S3) coupled between a second end of the inductor (120) and a positive output supply node (116). The system (100) also includes a fourth switch (S4) coupled between a second end of the inductor (120) and a ground node (118). The system (100) also includes a controller (104) coupled to the first, second, third, and fourth switches. The controller (104) is configured to provide an inductor charging mode, a positive boost mode, a negative boost mode, a first quiescent state involving a first switch (S1), and a second quiescent state involving a fourth switch (S4).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62 / 736,577, filed September 26, 2018, which is incorporated herein by reference. Background Art

[0003] Power supplies and power converters are used in a variety of electronic systems. Electricity is typically transmitted over long distances as an alternating current (AC) signal. The AC signal is divided and metered as needed for each commercial or domestic location and often converted to direct current (DC) for use by individual electronic devices or components. Modern electronic systems often utilize devices or components designed to operate using different DC voltages. Therefore, such systems require different DC-DC converters or DC-DC converters that support a wide range of output voltages.

[0004] There are many different DC-DC converter topologies. Available topologies differ in the components used, the amount of power handled, (one or more) input voltages, (one or more) output voltages, efficiency, reliability, size, and / or other characteristics. An example DC-DC converter topology is a single-input multiple-output (SIMO) converter, which provides multiple outputs by charging and selectively discharging a single inductor to different nodes. In some SIMO converter solutions, low efficiency and output oscillations may occur due to the components used and control issues. Summary of the Invention

[0005] According to at least one example of the present disclosure, a system includes an inductor and a first switch coupled between a first end of the inductor and a voltage supply node. The system also includes a second switch coupled between the first end of the inductor and a negative output supply node. The system also includes a third switch coupled between the second end of the inductor and a positive output supply node. The system also includes a fourth switch coupled between the second end of the inductor and a ground node. The system also includes a controller coupled to the first, second, third, and fourth switches. The controller is configured to provide an inductor charging mode, a positive boost mode, a negative boost mode, a first rest state involving the first switch, and a second rest state involving the fourth switch.

[0006] According to at least one example of the present disclosure, a single-input multiple-output (SIMO) converter circuit includes a first switch coupled between a first inductor node and a voltage supply node. The SIMO converter circuit also includes a second switch coupled between the first inductor node and a negative output supply node. The SIMO converter circuit also includes a third switch coupled between the second inductor node and a positive output supply node. The SIMO converter circuit also includes a fourth switch coupled between the second inductor node and a ground node. The SIMO converter circuit also includes a controller coupled to the first, second, third, and fourth switches. The controller is configured to switch between a first quiescent state involving the first switch and a second quiescent state involving the fourth switch.

[0007] According to at least one example of the present disclosure, a device includes a first switch coupled between a first inductor node and a voltage supply node. The device also includes a second switch coupled between the first inductor node and a negative output supply node. The device also includes a third switch coupled between the second inductor node and a positive output supply node. The device also includes a fourth switch coupled between the second inductor node and a ground node. The device also includes an asynchronous state machine coupled to the first, second, third, and fourth switches. The asynchronous state machine is configured to switch between a first quiescent state involving the first switch and a second quiescent state involving the fourth switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a detailed description of various examples, reference will now be made to the accompanying drawings, in which:

[0009] Figure 1 is a block diagram illustrating a system according to various examples;

[0010] Figure 2 is a set of schematic diagrams illustrating boost iteration schemes according to various examples;

[0011] Figure 3A and Figure 3B is a flow chart illustrating a state machine approach according to various examples; and

[0012] Figure 4 is a flow chart illustrating a single-input multiple-output (SIMO) converter control method according to various examples. DETAILED DESCRIPTION

[0013] This paper discloses a single-input multiple-output (SIMO) converter topology, which relates to a controller with a switchable quiescent state. In some examples, a SIMO converter is formed using an inductor, a first switch between a first end of the inductor and a power supply node, a second switch between a first end of the inductor and a negative output supply node, a third switch coupled between the second end of the inductor and a positive output supply node, and a fourth switch coupled between the second end of the inductor and a ground node. The SIMO converter also includes a controller coupled to the first, second, third, and fourth switches, wherein the controller instructs the operation of the first, second, third, and fourth switches to switch from a quiescent state to at least one boost iteration, and back to a quiescent state. In some examples, each boost iteration involves executing an inductor charging mode, followed by a positive or negative boost mode. As needed, multiple boost iterations are performed before switching back to a quiescent state.

[0014] As described herein, a controller is configured to switch to or from different quiescent states. In some examples, the first quiescent state involves a first switch, and the second quiescent state involves a fourth switch. More specifically, for the first quiescent state, the controller is configured to close the first switch and open the second, third, and fourth switches. Simultaneously, for the second quiescent state, the controller is configured to close the fourth switch and open the first, second, and third switches. By switching between the first and second quiescent states, the efficiency of the SIMO converter can be improved compared to using only a single quiescent state. Furthermore, using dual quiescent state operation can reduce undesirable artifacts in the positive and / or negative supply outputs compared to using only a single quiescent state. In some examples, the controller is configured to switch between single quiescent state operation and dual quiescent state operation. To provide a better understanding, the following figures describe various SIMO converter topologies and related systems and methods involving a controller with a switchable quiescent state clamp control option.

[0015] Figure 1 is a block diagram illustrating a system 100 according to various examples. Figure 1, system 100 represents a consumer product, an integrated circuit or chip, a printed circuit board (PCB) having integrated circuits and / or discrete components, and / or another electrical device. As shown, system 100 includes a SIMO converter circuit 102 coupled to a controller 104. System 100 also includes a sensing circuit 108 coupled to SIMO converter circuit 102 and controller 104. System 100 also includes a first load 126 coupled to a positive output supply node 116 of SIMO converter circuit 102. System 100 also includes a second load 128 coupled to a negative output supply node 114 of SIMO converter circuit 102. In other examples, first load 126, second load 128, and / or another load are coupled to both positive output supply node 116 and negative output supply node 114.

[0016] exist Figure 1 In the example of FIG1 , the SIMO converter circuit 102 includes a first switch (S1) coupled between a power supply (VIN) node 112 and a first inductor node (labeled “LY”) 122. The SIMO converter circuit 102 also includes a second switch (S2) coupled between the first inductor node 122 and a negative output supply node 114. The SIMO converter circuit 102 also includes a third switch (S3) coupled between a second inductor node (labeled “LX”) 124 and a positive output supply node 116. The SIMO converter circuit 102 also includes a fourth switch (S4) coupled between the second inductor node 124 and a ground node 118. In some examples, a SIMO converter circuit (such as the SIMO converter circuit 102) may have multiple positive and negative rails (output supply nodes controlled by switches). In such an example, the switches for each positive rail can be controlled together or individually. Similarly, the switches for each negative rail can be controlled together or individually.

[0017] exist Figure 1 , the inductor 120 is coupled between a first inductor node 122 and a second inductor node 124. In some examples, the inductor 120 is a discrete component that is added to the SIMO converter circuit 102 by coupling respective terminals of the inductor 120 to the first inductor node 122 and the second inductor node 124. In contrast, other elements of the SIMO converter circuit 102 may be part of an integrated circuit. In some examples, the inductor 120 is part of an integrated circuit. For example, on-chip inductors may be placed side by side or on top of other integrated circuit elements to form a multi-chip module (MCM) configuration. The MCM configuration may be packaged and commercialized as a single integrated circuit or product. In another example, the discrete inductor is packaged together with an integrated circuit that includes some elements of the system 100 to produce a single packaged product. In different illustrative examples, the single integrated circuit or multiple integrated circuits include a plurality of integrated circuits for Figure 1 1. In some examples, first load 126 and second load 128 are separate components or circuits relative to SIMO converter circuit 102, controller 104, and sensing circuit 108.

[0018] exist Figure 1 In the example of FIG, the controller 104 supports various modes of the SIMO converter circuit 102 and switchable quiescent states. More specifically, the controller 104 is configured to provide an inductor charging mode, a positive boost mode, a negative boost mode, a first quiescent state involving S1, and a second quiescent state involving S4. For the inductor charging mode, the controller 104 is configured to close S1 and S4 and disconnect S2 and S3. For the positive boost mode, the controller 104 is configured to close S1 and S3 and disconnect S2 and S4. For the negative boost mode, the controller 104 is configured to close S2 and S4 and disconnect S1 and S3. For the first quiescent state, the controller 104 is configured to close S1 and disconnect S2, S3, and S4. For the second quiescent state, the controller 104 is configured to close S4 and disconnect S1, S2, and S3.

[0019] In some examples, the controller 104 includes an asynchronous state machine 106 configured to adjust the control signals (CS1-CS4) of the SIMO converter circuits S1-S4 to achieve the various modes or quiescent states described herein without a clock signal. More specifically, in Figure 1 In some examples, the controller 104 receives various input signals from the sensing circuit 108, including a positive output supply voltage (ERP) signal corresponding to a voltage level at the positive output supply node 116, a negative output supply voltage level (ERN) signal corresponding to a voltage level at the positive output supply node 118, a positive inductor current lower threshold (RCTP), a negative inductor current lower threshold (RCTN), a positive inductor current lower threshold (RCTP), an inductor charging negative threshold (IPKN), and an inductor charging positive threshold (IPKP). In some examples, the controller 104 also receives an enable signal, such as a positive output supply enable signal (VPOS_enabled) and / or a first quiescent state enable signal (S1_IDLE).

[0020] In some examples, the asynchronous state machine 106 executes a state machine loop that includes starting in one of the first or second quiescent states. The state machine loop also includes executing at least one boost iteration that includes an inductor charging mode and a positive or negative boost mode. The state machine loop also includes returning to one of the first or second quiescent states. In some examples, the controller 104 and / or the asynchronous state machine includes arbitration logic (see, e.g., Figure 2 The arbitration logic (240) therein is configured to determine whether to use a positive boost mode or a negative boost mode in a given boost iteration. In some examples, the arbitration logic uses the sense signal from the sense circuit 108 to determine whether to use a positive boost mode or a negative boost mode in a given boost iteration.

[0021] As an example, the sense signals used by the arbitration logic to trigger a boost iteration include the positive output supply voltage level (e.g., ERP) and / or the negative output supply voltage level (e.g., ERN). For example, if ERP is farther from the corresponding target compared to ERN, the arbitration logic performs one or more boost iterations including the positive boost mode. On the other hand, if ERN is farther from the corresponding target compared to ERP, the arbitration logic performs one or more boost iterations including the negative boost mode. If both ERP and ERN are not on their respective targets, the arbitration logic may perform multiple boost iterations, which include at least one positive boost mode and at least one negative beat mode.

[0022] In another example, ERP is a logic signal that signals the controller 104 to initiate a positive boost operation. The ERP signal is generated using a voltage comparator that compares VPOS (the voltage level at the VPOS node 116) with a predetermined threshold (VPOS_THRESHOLD). If VPOS < VPOS_THRESHOLD, then ERP is logic high. Similarly, the ERN signal can be generated using a voltage comparator that compares VNEG (the voltage level at the VNEG node 114) with a predetermined threshold (VNEG_THRESHOLD). If VNEG > VNEG_THRESHOLD, then ERN is logic high.

[0023] Once a boost iteration is triggered, the controller 104 performs an inductor charging mode by closing S1 and S4 while S2 and S3 are open. In some examples, the inductor charging mode continues until IPKN and / or IPKP indicate that the inductor charge is above a threshold. After the inductor charging mode is complete, the controller 104 switches to the positive boost mode or the negative boost mode based on the arbitration result (e.g., which output supply voltage is farthest from the corresponding target and / or other criteria). After the positive or negative boost mode is complete (as indicated by RCTN or RCTP), the controller 104 switches to another boost iteration or a stationary state based on the input signal to the controller 104.

[0024] In some examples, the controller is configured to utilize different available quiescent states based on an enable signal (VPOS_enabled and / or S1_IDLE) received from an enable circuit (not shown), wherein the enable signal is used to determine whether the state machine loop returns to the first quiescent state or the second quiescent state. In some examples, the controller 104 is configured to begin in the second quiescent state (S4 closed, S1, S2, and S3 open) by default. If VPOS_enabled is low (positive output supply disabled) when the decision to return to the quiescent state is due, the controller 104 returns to the second quiescent state after one or more boost iterations are completed. On the other hand, if VPOS_enabled is high (positive output supply enabled) when the decision to return to the quiescent state is due, the controller 104 returns to the first quiescent state (S1 closed, S2, S3, and S4 open) after one or more boost iterations are completed. Additionally, if S1_IDLE is high, the controller 104 does not utilize the first quiescent state regardless of the state of VPOS_enabled. In some examples, S1_IDLE is used to determine whether controller 104 supports dual idle state mode (e.g., switching between first and second idle states based on changes in VPOS_enabled) or single idle state mode (e.g., defaulting to the second idle state until S1_IDLE goes low).

[0025] Figure 2 2 is a set of schematic diagrams illustrating a boost iteration scheme 200 according to various examples. In scheme 200, a boost iteration is initiated by transitioning from a quiescent state (not shown) for SIMO converter circuit 102 to an inductor charging mode arrangement 210. Figure 2As shown, the inductor charging mode arrangement 210 corresponds to S1 and S2 being closed while S2 and S3 are open. After the inductor charging mode is completed (e.g., signaled by IPKN and / or IPKP), the arbitration logic 240 determines whether a positive boost or a negative boost will be performed. In some examples, the arbitration logic 240 uses ERP, ERN, and the corresponding targets to determine whether to perform a positive boost or a negative boost. For example, if ERP is further from the corresponding target compared to ERN, the arbitration logic 240 performs one or more boost iterations including the positive boost mode. On the other hand, if ERN is further from the corresponding target compared to ERP, the arbitration logic 240 performs one or more boost iterations including the negative boost mode. If both ERP and ERN are not on their respective targets, the arbitration logic 240 performs multiple boost iterations, which include at least one positive boost mode and at least one negative boost mode. In another example, an ERP signal is generated using a voltage comparator that compares VPOS with a predetermined threshold (VPOS_THRESHOLD). If ERP is logic high (VPOS < VPOS_THRESHOLD), a positive boost is triggered. Similarly, an ERN signal is generated using a voltage comparator that compares VNEG with a predetermined threshold (VNEG_THRESHOLD). If ERN is logic high (VNEG > VNEG_THRESHOLD), a negative boost is triggered.

[0026] In scenario 200, a positive boost is performed by transitioning from the inductor charging mode arrangement 210 for the SIMO converter circuit 102 to the positive boost arrangement 220 for the SIMO converter circuit 102. As shown, the positive boost mode arrangement 220 corresponds to S2 and S4 being open while S1 and S3 are closed. After the positive boost mode is completed (e.g., signaled by RCTP), the arbitration logic 240 determines whether another boost iteration is needed (e.g., based on ERP and / or ERN). If so, scenario 200 returns to the inductor charging mode arrangement 210 of the SIMO converter circuit 102, and subsequently another positive or negative boost. Otherwise, if another boost iteration is not needed, the boost iteration scenario 200 is completed, and the SIMO converter circuit 102 is placed in the first or second stationary state as described herein. In some examples, the use of different stationary states depends on the enable signals as described herein (e.g., VPOS_enabled and / or S1_IDLE). <*

[0027] In scheme 200, negative boost is performed by switching from the inductor charging mode arrangement 210 for SIMO converter circuit 102 to the negative boost arrangement 230 for SIMO converter circuit 102. As shown, the negative boost mode arrangement 230 corresponds to S1 and S3 being disconnected and S2 and S4 being closed. After the negative boost mode is completed (e.g., by RCTN signaling), arbitration logic 240 determines whether another boost iteration is needed (e.g., based on ERP and / or ERN). If so, scenario 200 returns to the inductor charging mode arrangement 210 for SIMO converter circuit 102, and then performs another positive or negative boost. Otherwise, if another boost iteration is not needed, the boost iteration scheme 200 is completed and SIMO converter circuit 102 is placed in the first or second quiescent state. In some examples, the use of different quiescent states depends on the enable signal (e.g., VPOS_enabled and / or S1_IDLE) as described herein.

[0028] In some examples, the second quiescent state (S4 closed and S1, S2, and S3 open) is used by default. If VPOS_enabled is low (positive output supply disabled) when the decision to return to the quiescent state is due, the second quiescent state is used after one or more boost iterations are completed. On the other hand, if VPOS_enabled is high (positive output supply enabled) when the decision to return to the quiescent state is due, the first quiescent state (S1 closed and S2, S3, and S4 open) is used after one or more boost iterations. Furthermore, if S1_IDLE is low, the first quiescent state is not used regardless of the state of VPOS_enabled. In some examples, S1_IDLE is used to determine whether a dual quiescent state mode (e.g., switching between the first and second quiescent states based on changes in VPOS_enabled) or a single quiescent state mode (e.g., using only the second quiescent state until S1_IDLE goes high) is used.

[0029] Figure 3A and Figure 3B is a flow chart illustrating a state machine method 300 according to various examples. In some examples, the state machine method 300 is composed of Figure 1 , executed by the controller 104 (e.g., via the asynchronous state machine 106) in the state machine method 300. As shown, the state machine method 300 includes a second quiescent state 342 (labeled S4). In some examples, the second quiescent state 342 is the default quiescent state of the state machine method 300. At state 344, it is determined whether condition A is true. In some examples, condition A is given as:

[0030] A = S1_MIN / S4_MIN & ((ERP & !ERN) | ERP & ERN & !P_CHARGE_LAST)). Equation (1) In Equation 1, condition A identifies when a positive boost iteration is needed based on the change in ERP relative to the previous ERP value. If VPOS changes such that ERP is set high, or if ERP and ERN are logic high and the previous boost cycle boosted VNEG, the state machine method 300 proceeds to the positive boost iteration from the second quiescent state 342 by transitioning to the inductor charging mode state 352 for the positive boost iteration. If the VPOS voltage changes ERP or maintains ERP at logic 0, the state machine method 300 transitions from state 344 to state 346. In state 346, it is determined whether condition B is true. In some examples, condition B is given as:

[0031] B=S1_MIN / S4_MIN&((ERN&!ERP)|ERP&ERN&P_CHARGE_LAST)). Equation (2)

[0032] In Equation 2, Condition B identifies when a negative boost iteration is required based on a change in ERN relative to the previous value of ERN. If VNEG changes such that ERN is set high, or if ERP and ERN are logic high and the previous boost cycle boosted VPOS, the state machine method 300 proceeds from the second quiescent state 342 to a negative boost iteration by transitioning to the inductor charging mode state 312 (for a negative boost iteration). In the inductor charging mode state 352, S1 and S4 are closed (while S2 and S3 are open) to charge the inductor. In state 354, an S1S4 MIN determination is made, where S1S4 MIN indicates whether the minimum amount of time in inductor charging mode (S1S4 closed) has been reached. For example, the S1S4 MIN determination involves the use of a timer and an S1S4 MIN threshold. If S1S4 MIN is false (the minimum amount of time has not been reached), the state machine method 300 returns to the inductor charging mode state 352. Otherwise, if S1S4MIN is true (the minimum amount of time has been reached), then when IPKP reaches the threshold level (determined by state 356) and when S1S4MAX is true (determined by state 358), the state machine method 300 transitions to the positive boost state 360. S1S4MAX indicates that the target or maximum amount of time in the inductor charging mode has been reached. In the positive boost state 360, S1 and S3 are closed (and S2 and S3 are open).

[0033] At state 362, an S1S3 MIN determination is made, where S1S3 MIN indicates whether the minimum amount of time in the positive boost state charging mode (S1S3 closed) has been reached. If S1S3 MIN is false (the minimum amount of time has not been reached), the state machine method 300 returns to the positive boost state 360. Otherwise, if S1S3 MIN is true (the minimum amount of time has been reached), the state machine method 300 determines whether to perform another positive or negative boost iteration. More specifically, the state machine method 300 remains in the positive boost state 360 ​​unless RCTP has reached the lower threshold (determined at state 364) and S1S3 MAX is true (determined at state 366). S1S3 MAX indicates that the target or maximum amount of time in the positive boost state has been reached. If states 364 and 366 indicate that the positive boost mode is complete, then (at state 368) the ERN is used to determine whether a negative boost iteration is required. If state 368 indicates that a negative boost iteration is required (e.g., VNEG is less than the target value in magnitude), the state machine method 300 proceeds to the inductor charging mode state 312 (for negative boost iteration). If state 368 indicates that a negative boost iteration is not required (e.g., VNEG is less than the target value in magnitude), the ERP is analyzed (at state 370) to determine whether another positive boost iteration is required. If state 370 indicates that a positive boost iteration is required (VPOS is less than the target value), the state machine method 300 proceeds to the inductor charging mode state 352 (for positive boost iteration). If state 370 indicates that a positive boost iteration is not required (VPOS is less than the target value), the state machine method 300 selects one of the two quiescent states by determining whether condition C is true at state 372. In some examples, condition C is given as follows:

[0034] C=VPOS_enabled(VPOS Slave FSMin SS or ACTIVE)&S1_IDLE(Rest). Equation (3)

[0035] In Equation 3, condition C indicates whether V_POS enabled is high and S1_IDLE is high. If condition C is true, state machine method 300 transitions to first quiescent state 302. Otherwise, if condition C is not true, state machine method 300 transitions to second quiescent state 342. In some examples, state machine method 300 remains in second quiescent state 342 when the condition !POR_N|SOFT_RESET|STA NDBY|!CE|FAULT exists. This condition indicates when the device has not completed power-up (POR_N), when a soft reset command (SOFT_RESET) is sent from the host, when the device is in standby mode, when the chip enable pin is low, and when a component is in a fault state. In summary, this condition exists when the SIMO converter circuit is disabled.

[0036] When in the first quiescent state 302, the state machine method 300 remains in the first quiescent state 302 until condition A or B is true, as represented by states 304 and 306. If condition A is true, the state machine method 300 proceeds to the inductor charging mode state 352 (for positive boost iterations). If condition A is not true and condition B is true, the state machine method 300 proceeds to the inductor charging mode state 312 (for negative boost iterations).

[0037] In the Inductor Charging Mode state 312, S1 and S4 are closed (while S2 and S3 are open). At state 314, an S1S4 MIN determination is made. If S1S4 MIN is false, the state machine method 300 returns to the Inductor Charging Mode state 312. Otherwise, if S1S4 MIN is true, when IPKN reaches a threshold level (determined by state 366) and when S1S4 MAX is true (determined by state 318), the state machine method 300 transitions to the Negative Boost state 320. In the Negative Boost state 320, S2 and S4 are closed (while S1 and S3 are open).

[0038] At state 322, an S2S4 MIN determination is made. If S2S4 MIN is false, the state machine method 300 returns to the negative boost state 320. Otherwise, if S2S4 MIN is true, the state machine method 300 determines whether to perform another positive or negative boost iteration. Most specifically, the state machine method 300 remains in the negative boost state 320 unless RCTN has reached the lower threshold (determined at state 324) and S2S4 MAX is true (determined at state 326). If states 324 and 326 indicate that the negative boost mode is complete, the ERP is analyzed (at state 328) to determine whether a positive boost iteration is required. If state 328 indicates that a positive boost iteration is required (e.g., VPOS is less than the target value), the state machine method 300 proceeds to the inductor charging mode state 342 (for a positive boost iteration). If state 328 indicates that a positive boost iteration is not required (e.g., VPOS is equal to or greater than the target value), then (at state 330) ERN is analyzed to determine if another negative boost iteration is required. If state 330 indicates that a negative boost iteration is required (VNEG is less than the target value in magnitude), then the state machine method 300 proceeds to the inductor charging mode state 312 (for the negative boost iteration). If state 330 indicates that a negative boost iteration is not required (e.g., VNEG is equal to or greater than the target value in magnitude), then the state machine method 300 selects one of two quiescent states by determining whether condition C is true at state 332. If condition C is true, then the state machine method 300 transitions to the first quiescent state 302. Otherwise, if condition C is not true, then the state machine method 300 transitions to the second quiescent state 342.

[0039] Figure 4 4 is a flow chart illustrating a SIMO converter control method 400 according to various examples. In some examples, the method 400 is performed by a controller (e.g., Figure 1 104 in the controller) or a state machine (e.g., Figure 1 ) is executed by the asynchronous state machine 106 in . As shown, method 400 includes a first or second quiescent state 402. At box 404, a trigger is received (e.g., condition A or B in state machine method 300, VNEG relative to a target or threshold, VPOS relative to a target or threshold, etc.). At box 406, at least one boost iteration is performed. In some examples, each boost iteration includes an inductor charging mode and a positive or negative boost mode as described herein. If an enable signal (e.g., VPOS_enabled) is not received (determination box 408), method 400 transitions to the second quiescent state at box 410. Otherwise, if an enable signal is received (determination box 408), the method transitions to the first quiescent state at box 412. In some examples, another enable signal (e.g., S1_IDLE) determines whether the SIMO converter is operating in a dual quiescent state mode or a single quiescent state mode. From boxes 410 and 412, the method returns to box 402.

[0040] Certain terms are used throughout this specification and claims to refer to specific system components. As one skilled in the art will appreciate, different parties may refer to a component by different names. This document does not intend to distinguish between components that differ only in name, and not in their respective functions or structures. In this disclosure and claims, the terms "including" and "comprising" are used in an open-ended manner and, therefore, should be interpreted to mean "including, but not limited to..." The statement "based on" is intended to mean "based, at least in part, on." Thus, if X is based on Y, then X can be a function of Y and any number of other factors.

[0041] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Once the above disclosure is fully understood, many changes and modifications will become apparent to those skilled in the art. It is intended that the appended claims be interpreted as including all such changes and modifications.

Claims

1. A single-input multiple-output (SIMO) converter system, comprising: an inductor having a first terminal and a second terminal; a first switch coupled between the first terminal and a voltage supply terminal; a second switch coupled between the first terminal and a negative output supply terminal; a third switch coupled between the second terminal and a positive output supply terminal; a fourth switch coupled between the second terminal and a ground terminal; as well as a controller coupled to the first switch, the second switch, the third switch, and the fourth switch, the controller being configured to provide: an inductor charging mode; a positive boost mode; and a negative boost mode; a first stationary state, in which the controller closes the first switch and opens the second switch, the third switch, and the fourth switch; and a second quiescent state in which the controller closes the fourth switch and opens the first switch, the second switch, and the third switch.

2. The SIMO converter system according to claim 1 , wherein: For the inductor charging mode, the controller is configured to close the first switch and the fourth switch and open the second switch and the third switch; For the positive boost mode, the controller is configured to close the first switch and the third switch and open the second switch and the fourth switch; as well as For the negative boost mode, the controller is configured to close the second switch and the fourth switch and to open the first switch and the third switch.

3. The SIMO converter system of claim 1 , wherein the controller comprises an asynchronous state machine configured to execute a state machine cycle comprising: starting from one of the first resting state or the second resting state; performing at least one boost iteration including the inductor charging mode and the positive boost mode or the negative boost mode; and Return to one of the first quiescent state or the second quiescent state. 4 . The SIMO converter system of claim 3 , wherein the controller includes arbitration logic configured to determine whether the positive boost mode or the negative boost mode is used in a given boost iteration.

5. The SIMO converter system of claim 4 , further comprising a sensing circuit coupled to the controller, wherein: The arbitration logic is configured to determine whether to use the positive boost mode or the negative boost mode in a given boost iteration in response to a sense signal from the sense circuit.

6. The SIMO converter system according to claim 5, wherein: The sense signal includes a positive output supply voltage level and a negative output supply voltage level.

7. The SIMO converter system of claim 3, further comprising a sensing circuit coupled to the controller, wherein: A sense signal from the sense circuit is used to determine when the state machine loop returns to one of the first quiescent state or the second quiescent state.

8. The SIMO converter system of claim 3, further comprising an enable circuit coupled to the controller, wherein: An enable signal from the enable circuit is used to determine whether the state machine loop returns to the first quiescent state or the second quiescent state.

9. The SIMO converter system according to claim 3, wherein: The state machine loop is configured to start in the second quiescent state by default and to transition to the first quiescent state after a given boost iteration in response to a positive output enable signal.

10. The SIMO converter system according to claim 3, wherein: The asynchronous state machine is configured to switch between single quiescent state operation and dual quiescent state operation based on a dual quiescent state enable signal.

11. A single-input multiple-output (SIMO) converter circuit, comprising: a first switch coupled between the first inductor terminal and the voltage supply terminal; a second switch coupled between the first inductor terminal and a negative output supply terminal; a third switch coupled between the second inductor terminal and the positive output supply terminal; a fourth switch coupled between the second inductor terminal and a ground terminal; as well as a controller coupled to the first, second, third, and fourth switches, the controller configured to switch between a first quiescent state in which the controller closes the first switch and opens the second, third, and fourth switches; and a second quiescent state in which the controller closes the fourth switch and opens the first, second, and third switches.

12. The SIMO converter circuit according to claim 11 , wherein: The controller is configured to provide an inductor charging mode by closing the first switch and the fourth switch and opening the second switch and the third switch; The controller is configured to provide a positive boost mode by closing the first switch and the third switch and opening the second switch and the fourth switch; as well as The controller is configured to provide a negative boost mode by closing the second switch and the fourth switch and opening the first switch and the third switch.

13. The SIMO converter circuit according to claim 12, wherein: The controller includes an asynchronous state machine configured to execute a state machine cycle including: starting from one of the first resting state or the second resting state; performing at least one boost iteration including the inductor charging mode and the positive boost mode or the negative boost mode; and Return to one of the first quiescent state or the second quiescent state.

14. The SIMO converter circuit of claim 13 , further comprising a sensing circuit coupled to the controller, wherein the controller includes arbitration logic configured to determine whether to use the positive boost mode or the negative boost mode in a given boost iteration in response to a sense signal from the sensing circuit. 15 . The SIMO converter circuit of claim 13 , further comprising an enable circuit coupled to the controller, wherein an enable signal from the enable circuit is used to determine whether the state machine loop returns to the first quiescent state or the second quiescent state.

16. A single-input multiple-output (SIMO) converter device, comprising: a first switch coupled between the first inductor terminal and the voltage supply terminal; a second switch coupled between the first inductor terminal and a negative output supply terminal; a third switch coupled between the second inductor terminal and the positive output supply terminal; a fourth switch coupled between the second inductor terminal and a ground terminal; as well as an asynchronous state machine coupled to the first, second, third, and fourth switches, the asynchronous state machine configured to switch between a first quiescent state in which a controller closes the first switch and opens the second, third, and fourth switches; and a second quiescent state in which the controller closes the fourth switch and opens the first, second, and third switches.

17. The SIMO converter device of claim 16, wherein the asynchronous state machine is configured to execute a state machine cycle comprising: starting from one of the first resting state or the second resting state; performing at least one boost iteration including an inductor charging mode and either a positive boost mode or a negative boost mode; and Return to one of the first rest state or the second rest state.

18. The SIMO converter device of claim 17, further comprising a sensing circuit coupled to the asynchronous state machine, wherein: The asynchronous state machine includes arbitration logic configured to determine whether to use the positive boost mode or the negative boost mode in a given boost iteration in response to a sense signal from the sense circuit.

19. The SIMO converter apparatus of claim 17, further comprising an enable circuit coupled to the controller, wherein: At least one enable signal from the enable circuit is used to determine whether the state machine cycle returns to the first quiescent state or the second quiescent state.

20. The SIMO converter device according to claim 19, wherein The state machine loop is configured to start in the second quiescent state by default and transition to the first quiescent state after a given boost iteration in response to a positive output enable signal.

21. The SIMO converter device according to claim 19, wherein: The asynchronous state machine is configured to switch between single quiescent state operation and dual quiescent state operation based on a dual quiescent state enable signal.

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