Fan-out wafer-level packaging of semiconductor devices

Abstract

The present invention is entitled "Fan-out Wafer Level Packaging of Semiconductor Devices". In general aspects, the present invention provides a fan-out wafer level package (FOWLP), which may include: a semiconductor die, the semiconductor die having: an active surface; a backside surface; a plurality of side surfaces, each of the plurality of side surfaces extending between the active surface and the backside surface; a plurality of conductive bumps, the plurality of conductive bumps disposed on the active surface; and an insulating layer, the insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP may also include a molding compound, the molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and the peripheral edge of the active surface. The FOWLP may also include a signal distribution structure, the signal distribution structure disposed on the conductive bumps, the insulating layer, and the molding compound. The signal distribution structure may be configured to provide corresponding electrical connections to the plurality of conductive bumps.

Description

Technical Field

[0001] The description relates to packaged semiconductor devices and / or semiconductor device modules (packaged devices). More specifically, the description relates to semiconductor devices packaged in fan-out wafer-level packages. Background Art

[0002] Semiconductor devices (e.g., semiconductor dies) may be implemented in a number of different packaging configurations. For example, semiconductor dies such as power transistors, power diodes, etc. may be included in a wafer-level package such as a fan-out wafer-level package (FOWLP). However, current methods for producing such FOWLP packages may be cost prohibitive and / or may be susceptible to reliability issues (such as cracking of the semiconductor die included in the FOWLP). Summary of the invention

[0003] In general aspects, a fan-out wafer-level packaging (FOWLP) semiconductor device may include: a semiconductor die having: an active surface; a backside surface, the backside surface opposite to the active surface; a plurality of side surfaces, each of the plurality of side surfaces extending between the active surface and the backside surface; a plurality of conductive bumps, the plurality of conductive bumps disposed on the active surface; and an insulating layer, the insulating layer disposed on a first portion of the active surface. The first portion of the active surface may be disposed between the plurality of conductive bumps. The FOWLP may also include a molding compound that encapsulates the backside surface, the plurality of side surfaces, and a second portion of the active surface. The second portion of the active surface may be disposed between the conductive bump and a peripheral edge of the active surface. The FOWLP may also include a signal distribution structure disposed on the conductive bump, on the insulating layer, and on the molding compound. The signal distribution structure may be configured to provide corresponding electrical connections to the plurality of conductive bumps.

[0004] In another general aspect, a method for producing a fan-out wafer-level package (FOWLP) semiconductor device may include cutting a semiconductor wafer into a plurality of semiconductor dies. A semiconductor die in the plurality of semiconductor dies may include: an active surface; a backside surface, the backside surface opposite to the active surface; a plurality of side surfaces, each of the plurality of side surfaces extending between the active surface and the backside surface; a plurality of conductive bumps, the plurality of conductive bumps being disposed on the active surface; and an insulating layer, the insulating layer being disposed on a first portion of the active surface. The first portion of the active surface may be disposed between the plurality of conductive bumps. The method may also include: increasing the spacing between the plurality of semiconductor dies; and encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface of the semiconductor die in a molding compound. The second portion of the active surface may be disposed between the conductive bump and a peripheral edge of the active surface. The molding compound may also be disposed between the plurality of semiconductor dies. The method may also include forming a signal distribution structure. The signal distribution structure may be disposed on the conductive bump, the insulating layer, and the molding compound. The signal distribution structure may be configured to provide corresponding electrical connections to the plurality of conductive bumps.

[0005] In another general aspect, a method of producing a fan-out wafer-level package (FOWLP) semiconductor device may include placing a semiconductor wafer on a first carrier and cutting the semiconductor wafer into a plurality of semiconductor dies. A semiconductor die in the plurality of semiconductor dies may include: an active surface; a backside surface, the backside surface opposite to the active surface; a plurality of side surfaces, each side surface extending between the active surface and the backside surface; a plurality of conductive bumps, the plurality of conductive bumps being disposed on the active surface; and an insulating layer, the insulating layer being disposed on a first portion of the active surface. The first portion of the active surface may be disposed between the plurality of conductive bumps. The method may also include increasing the spacing between the plurality of semiconductor dies by stretching the first carrier along a first axis of the first carrier and along a second axis of the first carrier. The method may also include: after stretching the first carrier, transferring the plurality of semiconductor dies from the first carrier to a second carrier; and stretching the second carrier along the first axis of the second carrier and along the second axis of the second carrier. The method may also include encapsulating the backside surface, the plurality of side surfaces, and the second portion of the active surface of the semiconductor die in a molding compound. The second portion of the active surface may be between the conductive bump and the peripheral edge of the active surface. The molding compound may also be disposed between a plurality of semiconductor dies. The method may further include forming a signal distribution structure. The signal distribution structure may be disposed on the conductive bump, the insulating layer, and the molding compound. The signal distribution structure may be configured to provide corresponding electrical connectors to the plurality of conductive bumps. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A is a diagram showing a plan view of a fan-out wafer level package (FOWLP).

[0007] Figure 1B It is shown Figure 1A FIG. 4 is a cross-sectional view of a FOWLP.

[0008] FIG. 2A to FIG. 2N is shown for generating FOWLP such as Figure 1A and Figure 1B Diagram of the FOWLP process.

[0009] Figure 3 is a schematic diagram showing a semiconductor die disposed on a carrier for fan-out wafer level packaging.

[0010] In the drawings that are not necessarily drawn to scale, the same reference symbols may indicate the same and / or similar parts (elements, structures, etc.) in different views. The drawings generally illustrate various embodiments discussed in the present disclosure by way of example and not limitation. Reference symbols shown in one drawing may not be repeated for the same and / or similar elements in the related views. Reference symbols repeated in multiple figures may not be specifically discussed with respect to each of the figures in these figures, but are provided for context between the related views. In addition, not all similar elements in the drawings are specifically referenced with reference symbols when multiple instances of the element are shown. DETAILED DESCRIPTION

[0011] The present disclosure relates to packaged semiconductor device apparatus, and associated methods of manufacturing packaged semiconductor devices. More specifically, the present disclosure relates to fan-out wafer-level packaging (FOWLP) for packaging semiconductor devices (semiconductor dies), and associated manufacturing processes. The FOWLP and manufacturing methods disclosed herein can have reduced manufacturing costs and improved reliability compared to current FOWLP implementations.

[0012] For example, using the methods described herein, a single molding operation can be used to produce a FOWLP including a semiconductor die that is at least partially encapsulated on all sides (e.g., six-sided encapsulation) compared to current methods that may include multiple molding operations and / or molding compound grinding operations. For example, in some embodiments, such as those described herein, a FOWLP can include a semiconductor die that is fully encapsulated on five sides (e.g., a backside surface and four side surfaces) and partially encapsulated in molding compound on a frontside surface (e.g., an active surface) using a single molding operation, which can reduce manufacturing costs.

[0013] In such methods, due to this six-sided encapsulation, the semiconductor die included in the FOWLP can be mold-locked. Compared with the FOWLP produced using the current method, this mold locking can improve the structural stability of the resulting FOWLP. This improved structural stability can prevent stress at the edge of the semiconductor die, which may cause damage, such as cracking of the semiconductor die. In the current FOWLP, such stress may occur due to insufficient material coverage (e.g., gaps caused by insufficient step coverage) and / or mismatches in thermal properties (e.g., expansion and contraction) of materials included in the FOWLP (such as semiconductor materials, molding compound materials, dielectric (insulating) materials, and / or conductive materials (e.g., metal layers)).

[0014] Figure 1A and Figure 1B is a diagram showing the FOWLP 100 . Figure 1A is a diagram showing a plan view (top side view) of the FOWLP 100 . Figure 1B It is shown along Figure 1A The section line 1B-1B shown in Figure 1A FIG. 1 is a cross-sectional view of the FOWLP 100. Figure 1A and Figure 1B The following discussion is made of FOWLP 100. Figure 1A , a plan view of FOWLP 100 is shown such that the internal elements of FOWLP 100 are shown in order to illustrate the relationship between the various elements of FOWLP 100. In some embodiments, these internal elements may or may not be visible in such a plan view. That is, FOWLP 100 is not shown in FIG. Figure 1A 100 is shown as a partial X-ray or ghost view to illustrate the arrangement of the various elements of FOWLP 100. Figure 1B , FOWLP 100 is shown prior to being separated (eg, singulated) from a plurality of FOWLPs (including other semiconductor dies), such as may be simultaneously formed from a plurality of semiconductor dies produced on a semiconductor wafer.

[0015] like Figure 1A and Figure 1B As shown, FOWLP 100 may include a semiconductor die 105, an insulating layer 115, a molding compound 125, and a signal distribution (eg, fan-out) structure 135. Figure 1A In FIG. 1 , the peripheral edges (eg, four peripheral edges) of the semiconductor die are indicated by reference numeral 105. Figure 1A and Figure 1BAs shown, the semiconductor die 105 may include conductive bumps 107, edge surfaces 109, backside surfaces 111, and active surfaces 113. In some embodiments, the conductive bumps 107 may be disposed on the active surface 113 of the semiconductor die 105 and may provide electrical connections to circuits and / or electronic devices (e.g., power semiconductor devices) implemented on the active surface 113 of the semiconductor die 105 (as an integrated circuit). The conductive bumps 107 may include metal, solder, flux, and / or any suitable conductive material or combination of materials.

[0016] like Figure 1A and Figure 1B As shown, the edge surface 109 and the backside surface 111 of the semiconductor die 105 can be completely encapsulated in the molding compound 125. Figure 1A and Figure 1B As shown, molding compound 125 may wrap around, for example, side surface 109 onto a portion of active surface 113 of semiconductor die 105, thereby partially encapsulating active surface 113 and locking (fixing, mold locking, etc.) semiconductor die 105 in molding compound 125. As described above, such mold locking may prevent reliability issues in FOWLP 100, such as cracking of semiconductor die 105. Figure 1A and Figure 1B In the FOWLP 100 , the molding compound 125 may also be disposed below (eg, extend below, etc.) the signal distribution structure 135 .

[0017] like Figure 1A and Figure 1B As shown, an insulating (e.g., dielectric) layer 115 (which may be a polyimide layer, a glass layer, or any other suitable insulating material) may be disposed on the active surface 113 and between the conductive bumps 107 of the semiconductor die 105. In the FOWLP 100, portions of the active surface 113 of the semiconductor die 105 between the conductive bumps and the outer edge of the semiconductor die 105 may be free of the insulating layer 115. Thus, during a molding operation of the FOWLP 100, the molding compound may encapsulate portions of the active surface 113 free of the insulating layer 115, and the insulating layer 115 may prevent (block, etc.) the molding compound 125 from flowing between the conductive bumps 107 during the molding process.

[0018] exist Figure 1A and Figure 1BIn the FOWLP 100, the signal distribution structure 135 may include a first dielectric layer 137a (which may be referred to as an interlayer dielectric layer), a second dielectric layer 137b, an electrical connector 139, and a conductive bump 143. The first dielectric layer 137a and the second dielectric layer 137b (which may also be referred to as insulating layers 137a and 137b) may include glass, polyimide, oxide, and / or any other suitable dielectric material or dielectric material combination.

[0019] The first dielectric layer 137a may have a through-hole opening 141 formed therein, wherein a corresponding through-hole opening 141 may be formed over each of the conductive bumps 107 of the semiconductor die 105. The first dielectric layer 137a may be disposed on the conductive bumps 107, on the insulating layer 115, and on the molding compound 125. The first dielectric layer 137a may have a flat (upper) surface that may be flattened using an appropriate process for the specific dielectric material used. The electrical connector 139 of the signal distribution structure 135 may be disposed on the flat surface of the first dielectric layer 137a and disposed in a corresponding through-hole opening 141 (and extending through the through-hole opening) to electrically couple the electrical connector 139 with the conductive bump 107. In some embodiments, the electrical connector 139 may be formed by patterning a deposited conductive (metal) layer, for example, using photolithography techniques.

[0020] In FOWLP 100, second dielectric layer 137b may be disposed on first dielectric layer 137a and electrical connector 139. Like first dielectric layer 137a, second dielectric layer 137a may have a flat (upper) surface. Second dielectric layer 137b may have via openings 145 defined therein, wherein conductive bumps 143 may each be disposed in a corresponding via opening 145, thereby providing electrical connections (e.g., through electrical connections 139) from conductive bumps 143 to conductive bumps 107 of semiconductor die 105.

[0021] As mentioned above, in Figure 1B , FOWLP 100 (including semiconductor dies 105a and 105b in addition to semiconductor die 105) is shown prior to separation (eg, singulation) from a plurality of FOWLPs, such as may be formed from a plurality of semiconductor dies simultaneously. Figure 1B , only the semiconductor dies on either side of FOWLP 100 and portions (parts) of the FOWLP are shown. In some embodiments, semiconductor dies 105, 105a, and 105b may be produced on a semiconductor wafer and may implement the same or different circuits or devices, depending on the specific embodiment. Figure 1BAs shown, saw streets may be defined by spaces 150 between signal distribution structures 135 of the FOWLPs. Molding compound 125 may be cut (e.g., using a saw, laser, plasma, etc.) to separate (singulate) FOWLP 100 from other concurrently produced FOWLPs (such as corresponding FOWLPs including semiconductor dies 105a and 150b).

[0022] FIG. 2A to FIG. 2N is shown for generating FOWLP such as Figure 1A and Figure 1B FIG. 1 is a diagram of a process of FOWLP 100. In some embodiments, FIG. 2A to FIG. 2N The process may be implemented to produce FOWLPs other than FOWLP 100. For example, FIG. 2A to FIG. 2N The process of (or similar processes) can be used to produce a FOWLP including multiple semiconductor dies. In such a multiple semiconductor die FOWLP, in addition to providing external electrical connections (e.g., via conductive bumps 143), the associated signal distribution layer can include electrical connections between the multiple semiconductor dies included in such a FOWLP. In some embodiments, other manufacturing processes can be used to produce a FOWLP, such as the FOWLP described herein. However, for purposes of this disclosure and illustration, FIG. 2A to FIG. 2N The process will refer to Figure 1A and Figure 1B The FOWLP 100 is described.

[0023] refer to Figure 2A , showing a portion of semiconductor substrate 200 including semiconductor die 105 (and portions of adjacent semiconductor dies 105a and 105b). Figure 2A As shown, conductive bumps 107 may be disposed (formed, produced, etc.) on active surface 113 of semiconductor die 105. For example, conductive bumps 107 may be disposed on passivation (e.g., glass, dielectric, etc.) layer 114. Conductive bumps 107 may be electrically connected to circuits and / or semiconductor devices defined on active surface 113 of semiconductor die 105 using electrical (e.g., ohmic) contacts 210 extending through passivation layer 114 (e.g., through contact openings). For clarity, such circuits and / or semiconductor devices on active surface 113 of semiconductor die 105 are not shown in FIG. FIG. 2A to FIG. 2N Not shown.

[0024] In some embodiments, the conductive bump 107 may include a (first) conductive material 107a below, and a second conductive material 107b disposed on the conductive material 107a below. The second conductive material 107b may be formed using evaporation, electrolytic plating, electroless plating, solder ball dropping, and / or screen printing processes. In some embodiments, the second conductive material 107b may be aluminum (Al), tin (Sn), nickel (Ni), gold (Au), silver (Ag), lead (Pb), bismuth (Bi), copper (Cu), solder, and / or a combination thereof, and may also include flux. In some embodiments, the second conductive material 107b may be eutectic Sn / Pb, high-lead solder, or lead-free solder.

[0025] In some embodiments, the second conductive material 107b can be bonded to the underlying conductive material 107a using an attachment or bonding process. For example, the second conductive material 107b can be reflowed to form a solder ball or bump by heating the second conductive material 107b to above its melting point. In some embodiments, the second conductive material 107b can be reflowed a second time, which can improve electrical contact (e.g., reduce resistance) with the underlying conductive material 107a. As an example, a conductive bump 107 as described herein is disclosed as a possible electrical interconnect that can be configured to provide an electrical connector to a circuit formed on the active surface 113 of the semiconductor die 105. In some embodiments, other methods for providing such electrical connectors, such as conductive pastes, columnar bumps, microbumps, conductive posts, or other electrical connectors, can be used.

[0026] like Figure 2A As further shown, the openings between the passivation layers 114 of the semiconductor dies 105, 105a, and 105b may define scribe (saw) streets 220 (represented by dashed lines) between the semiconductor dies. Figure 2D As described in further detail, FIG. 2A to FIG. 2N As part of the FOWLP manufacturing process, semiconductor dies 105 , 105 a , and 105 b may be singulated (separated along scribe lanes 220 ).

[0027] like Figure 2BAs shown, an insulating layer 115 can be formed on the active surface 113 of the semiconductor die 105, between the conductive bumps 107. The insulating layer 115 can be formed using vapor deposition, printing, lamination, spin coating, spray coating, sintering and / or other processes. The insulating layer 115 can include one or more layers of insulating materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), hafnium oxide (HfO2), benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), molding compound, polymer and / or other dielectric materials with appropriate structural and insulating properties.

[0028] like Figure 2B (as well as Figure 1A ), the insulating layer 115 may substantially fill the space between the conductive bumps 107 on the active surface 113, but some gaps may exist between the conductive bumps 107 and the insulating layer 115. Figure 2B (as well as Figure 1A ), in this exemplary embodiment, an insulating layer 115 can be formed between the conductive bumps 107, wherein the insulating layer 115 contacts at most two sides of each conductive bump 107. In other words, in this exemplary embodiment, the area of ​​the active surface 113 between the conductive bumps 107 and the side surface 109 of the semiconductor die 105 can be free of the insulating layer 115. Depending on the specific embodiment, the insulating layer 115 can be formed as part of the wafer manufacturing process or as part of the FOWLP manufacturing process. In some embodiments, the insulating layer 115 can be formed before forming the conductive bumps 107, and a through-hole opening can be formed in the insulating layer 115. In this example, the conductive bumps 107 can electrically contact the active surface 113 of the semiconductor die 105 through the openings formed in the insulating layer 115. As also shown Figure 2B As shown, semiconductor substrate 200 (and semiconductor die 105 ) may have a thickness (eg, initial or starting thickness) T1 .

[0029] refer to Figure 2C , the semiconductor substrate 200 including the semiconductor die 105 may be obtained from Figure 2B The orientation shown in FIG. 2 is reversed and mounted on a back grinding tape (e.g., a hard polyester tape) 230 using an adhesive layer 235. Figure 2C As shown, adhesive layer 235 can contact (be disposed on) conductive bump 107 and insulating layer 115, which can secure semiconductor substrate 200 to the back grinding tape. A portion of semiconductor substrate 200 (and semiconductor die 105) can be removed from backside surface 111 using a grinding process. Figure 2C As shown, the grinding process can make the thickness of the substrate 200 from Figure 2B The thickness T1 is reduced to a thickness T2, where T2 < T1. As further shown in FIG. 2, in some embodiments, a backside metal layer 106 can be formed (e.g., using chemical vapor deposition, sputtering, etc.) on the backside surface 111 of the semiconductor die 105 (e.g., the substrate 200). Although not specifically shown in Figures 2D to 2N , in some embodiments, such a backside metal layer 106 can be included on the semiconductor die 105 of the exemplary FOWLP 100.

[0030] Then, the process can continue to Figure 2D , where although still coupled to the backgrinding tape 230 via the adhesive layer 235, the semiconductor substrate 200 can be inverted and the backside surface 111 of the substrate 200 can be coupled to the expandable dicing tape 240 and the adhesive layer 245. Then, the backgrinding tape 230 and the adhesive layer 235 can be removed from the substrate 200.

[0031] As Figure 2D shown, after the backgrinding tape 230 and the adhesive layer 235 have been removed, the semiconductor die 105 can be singulated, for example, from at least the semiconductor dies 105a and 105b by forming a dicing opening 225 through the semiconductor substrate 200 along the scribe lane 220. In some embodiments, the dicing opening 225 can be formed using plasma etching, which can have certain advantages such as forming a fine side surface 109 along the saw lane 220 and allowing for the formation of dicing openings 225 of different widths on the same semiconductor wafer. In some embodiments, a saw blade or a laser cutting tool can be used to singulate the semiconductor die 105 from the semiconductor substrate 200. The semiconductor dies 105, 105a, and 105b can remain attached to the dicing tape 240, and the FOWLP manufacturing process can move to the operations shown by Figure 2E and Figure 2F . In some embodiments, the singulated semiconductor dies can be picked up, inverted, and placed at a pitch (such as the pitches shown in Figure 2G ) on separate carriers or tapes.

[0032] As Figure 2E and Figure 2F shown, the dicing tape 240 (and the adhesive layer 245) between the dies can be stretched in the x-direction and the y-direction (as shown in Figure 2F2 (shown as the axis in FIG. 2 ) to increase the spacing (from the width of the dicing opening 225 to the spacing S1) between the semiconductor die 105 and the adjacent semiconductor die (e.g., semiconductor die 105a and 105b). In some embodiments, the dicing tape 240 and the associated adhesive layer 245 between the dies can be differentially expanded in the x-direction and the y-direction using an expansion stage that independently moves and stretches the dicing tape 240 (and the adhesive layer 245) in the x-direction and the y-direction. In some embodiments, the semiconductor dies can have a different spacing in the x-direction than in the y-direction.

[0033] In some embodiments, because the cutting tape 240 may not expand uniformly in the x-direction and the y-direction, the width of the cutting openings 225 for the saw street 220 can be different between those aligned along the x-direction and those aligned along the y-direction, which can compensate for the different amounts of expansion of the cutting tape 240 in the x-direction and the y-direction.

[0034] The process can then continue to Figure 2G , wherein the singulated semiconductor dies 105, 105a, and 105b, while still coupled to the stretched dicing tape 240 via the adhesive layer 245, can be inverted and coupled to another swellable (second swellable) carrier or tape 250 (e.g., a polymer material) using an swellable adhesive layer 255. The dicing tape 240 and adhesive layer 245 can then be removed from the singulated semiconductor dies.

[0035] like Figure 2G As shown, expandable carrier or tape 250 (and adhesive layer 255) can expand (e.g., in the x-direction and the y-direction) to further increase the spacing between semiconductor die 105 and adjacent semiconductor dies (e.g., semiconductor dies 105a and 105b), such as from Figure 2E The spacing S1 to Figure 2G , where S2>S1. In some embodiments, the carrier or tape 250 and the associated adhesive layer 255 can be differentially expanded in the x-direction and the y-direction using an expansion stage that moves independently in the x-direction and the y-direction and stretches the carrier or tape 250 (e.g., to appropriately space the singulated semiconductor dies for further processing to produce a FOWLP, such as FOWLP 100). In some embodiments, the singulated semiconductor dies can be picked up and separated at a certain spacing (such as Figure 2G ) place them on a carrier or tape (such as the ones shown below Figure 2H In other embodiments, two or more semiconductor dies may be placed so that they will be contained together in a single FOWLP.

[0036] like Figure 2HAs shown, Figure 2G The singulated and separated semiconductor dies may be transferred (e.g., using one or more carrier-to-carrier or tape-to-tape transfers, such as those described above) to a carrier or tape 260 using an (adhesive) interface layer 265. The carrier 260 may be formed of an overmolded tape, a polymer, beryllium oxide, silicon, glass, or other suitable material for structural support. The interface layer 265 may be formed over (disposed on, etc.) a surface of the carrier 260 as a temporary adhesive bonding film, etch stop layer, and / or thermal release layer. The carrier 260 and associated interface layer 265 may then be disposed over the conductive bumps 107 and insulating layer 115 for structural support, wherein a space 127 may be retained between the interface layer 265 and the active surface 113 of the semiconductor die 105 (e.g., to allow the semiconductor die 105 to be mold locked in the molding compound 125).

[0037] Also like Figure 2H As shown, after the singulated and separated semiconductor dies (e.g., with a spacing S2) are coupled to the carrier 260 with the interface layer 265, the molding compound (sealant) 125 can be disposed (e.g., deposited, flowed, etc.) over and between the semiconductor dies 105, 105a, and 105b and into the space 127 to achieve a six-sided (mold-locked) encapsulation of the semiconductor die 105 (e.g., after the molding compound 125 is cured). Depending on the specific implementation, the molding compound 125 can be formed (applied, etc.) using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, film-assisted molding, spin coating, and / or any other suitable application process. The molding compound 125 can be a polymer, a polymer composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with filler. The molding compound 125 can (should) be non-conductive and provide physical support and environmental protection for the semiconductor die 105 to protect it from external elements and contaminants.

[0038] Fig.2I After removing the carrier 260 and the interface layer 265, for example, Figure 2H The bottom side of the molded structure is shown Figure 2H The portion of the molded structure includes semiconductor die 105 . Fig.2I The arrangement of the semiconductor die 105, the conductive bumps 107 of the semiconductor die 105, the insulating layer 115, the molding compound 125, and the position of the space 127 is shown in a plan view. The space is provided on the periphery of the semiconductor die 105 around the conductive bumps 107. Fig.2I As shown, a portion of the molding compound 125 is disposed in the space 127 , but does not extend into the area of ​​the insulating layer 115 .

[0039] Figure 2J to Figure 2LThe formation of the signal distribution structure 135 of the FOWLP 100 is shown. Figure 2J As shown, after removing the carrier 260 and the interface layer 265, a dielectric layer 137a can be formed on the conductive bumps 107, the insulating layer 115, and the molding compound 125. The insulating layer 137a can be planarized using an appropriate process, such as a reflow process, a polishing process, etc. A via opening 141 can be formed in the dielectric layer 137a and extend through the dielectric layer 137a to the conductive bump 107. Then, an electrical connector 139 (e.g., a metal layer provided by patterning or formed on the dielectric layer 137a and provided in the via opening 141) can be formed. As described above, the electrical connector 139 can be electrically coupled to the corresponding conductive bump 107 of the semiconductor die 105.

[0040] Figure 2K Shows Figure 2J The cross-sectional view of Figure 2K A part of a representation. Figure 2K As shown, the electrical connector 139 can be disposed on the planar upper surface of the dielectric layer 137a and also disposed in the via opening 141 (eg, filling the via opening) to form an electrical contact with the conductive bump 107. Figure 2K As shown, molding compound 125 may fill space 127 between semiconductor die 105 and dielectric layer 137a. Figure 2K As noted, the molding compound may have a thickness T3 between the semiconductor die 105 and the dielectric layer 137a, and a width W1 between the conductive bump and the edge of the semiconductor die (edge ​​surface 109). In some embodiments, T3 may be greater than or equal to 5 micrometers (μm), and W1 may also be greater than or equal to 5 μm.

[0041] like Figure 2L As shown, in Figure 2J After the operations shown in , the dielectric layer 137b of the signal distribution structure 135 can be formed on the conductive layer 137a and the electrical connector 139. As with the insulating layer 137a, the insulating layer 137b can be planarized using a suitable process, such as a reflow process, a polishing process, etc. A via opening 145 can be formed in the dielectric layer 137b and extend through the dielectric layer 137b to the electrical connector 139. Then, the conductive bump 143 of the signal distribution structure 135 can be disposed (formed, etc.) in the via opening 143 (e.g., on the corresponding electrical connector 139). Figure 2L Corresponds to Figure 1B .

[0042] like Figure 2M As shown, after completing the signal distribution structure 135, Figure 2LThe structure (assembly) shown in FIG. 1 can be coupled to the dicing tape 270 (eg, a polymer matrix material) using an adhesive layer 275. The channel 155 can be formed along, for example, Figure 2L The saw street 150 shown in FIG. Figure 2M As shown, channel 155 may be formed completely through molding compound 125 and into adhesive layer 275 to Figure 2N The FOWLP 100 is shown singulated with other FOWLPs formed simultaneously. For example, trenches 155 can be formed around each semiconductor die 105, 105a, and 105b using, for example, a saw blade or laser cutting tool. In some embodiments, more than one semiconductor die 105 or semiconductor dies of different sizes and types can be combined into each singulated FOWLP 100. Figure 2N Corresponds to Figure 1A Therefore, for the sake of brevity, ref. Figure 1A and Figure 1B The details of the discussed FOWLP 100 are not repeated here.

[0043] Figure 3 is a schematic diagram showing semiconductor dies 105, 105a, and 105b disposed on a carrier 360 of a fan-out wafer level package. For example, the carrier 360 may be Figure 2H The carrier 260 (for example, in Figure 2E and Figure 2G After the two carrier stretching processes and the transfer of the semiconductor dies 105, 105a and 105b to the carrier 260). Therefore, reference Figure 2G , Figure 3 The spacing of the semiconductor dies 105 in the embodiment may be a spacing S2, such as Figure 3 In some embodiments, other pitches may be used, such as larger or smaller pitches, where the specific pitch between semiconductor dies may depend on the specific FOWLP being produced. FIG. 2A to FIG. 2N The process can simultaneously produce Figure 3 , where each FOWLP may include one or more of semiconductor dies 105 .

[0044] It should be understood that in the foregoing description, when an element such as a layer, a region or a substrate is mentioned as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is mentioned as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there is no intermediate element or layer. Although the term directly on, directly connected to, or directly coupled to may not be used throughout the entire detailed description, an element shown as being directly on an element, directly connected, or directly coupled can be mentioned in this manner. The claims of the present application may be revised to narrate the exemplary relationships described in the specification or shown in the accompanying drawings.

[0045] As used in this specification, the singular may include the plural unless the context clearly indicates otherwise. Spatially relative terms (e.g., above, above, above, below, below, under, below, etc.) are intended to encompass different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent can include lateral adjacent or horizontal adjacent.

[0046] Some embodiments may be implemented using various semiconductor processing and / or packaging technologies. Some embodiments may be implemented using various types of semiconductor device processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and the like.

[0047] Although certain features of the described embodiments have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented only by way of example, not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A fan-out wafer-level packaged semiconductor device, comprising: A semiconductor die having: Active surface; a backside surface, the backside surface being opposite to the active surface; a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface; a plurality of conductive bumps, the plurality of conductive bumps being disposed on the active surface; and an insulating layer disposed on a first portion of the active surface, The first portion of the active surface is disposed between the plurality of conductive bumps; a molding compound encapsulating and contacting the backside surface and the plurality of side surfaces, the molding compound also partially encapsulating a second portion of the active surface, the second portion of the active surface being disposed adjacent to the first portion of the active surface and between the plurality of conductive bumps and a peripheral edge of the active surface, the first portion of the active surface not including the molding compound; and A signal distribution structure is disposed on the plurality of conductive bumps, on the insulating layer, and on the molding compound, the signal distribution structure being configured to provide corresponding electrical connections to the plurality of conductive bumps.

2. The fan-out wafer-level package semiconductor device according to claim 1, wherein: The molding compound completely encapsulates the backside surface and the plurality of side surfaces; and The insulating layer includes a polyimide material.

3. The fan-out wafer-level package semiconductor device according to claim 1, wherein: The thickness of the molding compound on the active surface is greater than or equal to 5 microns; and A width of the molding compound on the active surface between one of the plurality of conductive bumps and the peripheral edge of the active surface is greater than or equal to 5 micrometers.

4. The fan-out wafer-level package semiconductor device according to claim 1, wherein the plurality of conductive bumps are a first plurality of conductive bumps, and the signal distribution structure comprises: a first dielectric layer, the first dielectric layer being disposed on the insulating layer, on the first plurality of conductive bumps, and on the molding compound, the first dielectric layer having a flat surface; a plurality of via openings through the first dielectric layer; a plurality of electrical connections to the first plurality of conductive bumps, each electrical connection of the plurality of electrical connections disposed on the planar surface of the first dielectric layer and disposed in a respective through-hole opening of the plurality of through-hole openings; a second dielectric layer disposed on the plurality of electrical connections and the first dielectric layer; a plurality of via openings through the second dielectric layer; and A second plurality of conductive bumps are disposed in corresponding ones of the plurality of via openings in the second dielectric layer and on corresponding ones of the plurality of electrical connectors.

5. A method for producing a fan-out wafer-level packaged semiconductor device, the method comprising: Separating the semiconductor wafer into a plurality of semiconductor dies, wherein the semiconductor dies in the plurality of semiconductor dies include: Active surface; a backside surface, the backside surface being opposite to the active surface; a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface; a plurality of conductive bumps disposed on the active surface; and an insulating layer disposed on a first portion of the active surface, The first portion of the active surface is disposed between the plurality of conductive bumps; increasing a spacing between the plurality of semiconductor dies; encapsulating the backside surface and the plurality of side surfaces in a molding compound; partially encapsulating a second portion of the active surface in a molding compound, the second portion of the active surface being disposed adjacent to the first portion of the active surface and between the plurality of conductive bumps and a peripheral edge of the active surface, the molding compound being further disposed between the plurality of semiconductor dies, the first portion of the active surface excluding the molding compound; and A signal distribution structure is formed, the signal distribution structure disposed on the plurality of conductive bumps, the insulating layer, and the molding compound, the signal distribution structure being configured to provide corresponding electrical connections to the plurality of conductive bumps.

6. The method according to claim 5, further comprising: Before separating the semiconductor wafer into the plurality of semiconductor dies, the semiconductor wafer is disposed on a first carrier, The increasing the spacing between the plurality of semiconductor dies comprises: after cutting the semiconductor wafer into the plurality of semiconductor dies: removing the plurality of semiconductor dies from the first carrier; and The plurality of semiconductor dies are placed on a second carrier at the increased pitch.

7. The method according to claim 5, further comprising: Before separating the semiconductor wafer into the plurality of semiconductor dies, placing the semiconductor wafer on a first carrier tape, Wherein increasing the spacing between the plurality of semiconductor dies comprises: After dicing the semiconductor wafer into the plurality of semiconductor dies, stretching the first carrier tape along a first axis of the first carrier tape and along a second axis of the first carrier tape; After stretching the first carrier tape, flipping and transferring the plurality of semiconductor dies from the first carrier tape to a second carrier tape; and The second carrier tape is stretched along the first axis of the second carrier tape and along the second axis of the second carrier tape.

8. The method according to claim 5, wherein: The plurality of conductive bumps are a first plurality of conductive bumps, and Forming the signal distribution structure includes: forming a first dielectric layer, the first dielectric layer being on the insulating layer, the plurality of conductive bumps and the molding compound, the first dielectric layer having a flat surface; forming a plurality of via openings through the first dielectric layer; forming a plurality of electrical connections to the plurality of conductive bumps, each electrical connection of the plurality of electrical connections disposed on the planar surface of the first dielectric layer and disposed in a corresponding via opening of the plurality of via openings; forming a second dielectric layer, the second dielectric layer being disposed on the plurality of electrical connections and the first dielectric layer; forming a plurality of via openings through the second dielectric layer; and A second plurality of conductive bumps are formed, the second plurality of conductive bumps being disposed in corresponding ones of the plurality of via openings in the second dielectric layer and on corresponding ones of the plurality of electrical connectors.

9. A method for producing a fan-out wafer-level package, the method comprising: placing a semiconductor wafer on a first carrier tape; The semiconductor wafer is separated into a plurality of semiconductor dies, wherein the semiconductor dies in the plurality of semiconductor dies include: Active surface; a backside surface, the backside surface being opposite to the active surface; a plurality of side surfaces, each side surface extending between the active surface and the backside surface; a plurality of conductive bumps disposed on the active surface; and an insulating layer disposed on a first portion of the active surface, The first portion of the active surface is disposed between the plurality of conductive bumps; Increasing the spacing between the plurality of semiconductor dies by: stretching the first carrier tape along a first axis of the first carrier tape and along a second axis of the first carrier tape; After stretching the first carrier tape, transferring the plurality of semiconductor dies from the first carrier tape to a second carrier tape; and stretching the second carrier tape along the first axis of the second carrier tape and along the second axis of the second carrier tape; encapsulating the backside surface and the plurality of side surfaces in a molding compound; partially encapsulating a second portion of the active surface in a molding compound, the second portion of the active surface being disposed adjacent to the first portion of the active surface and between the plurality of conductive bumps and a peripheral edge of the active surface, the molding compound being further disposed between the plurality of semiconductor dies, the first portion of the active surface excluding the molding compound; and A signal distribution structure is formed, the signal distribution structure disposed on the plurality of conductive bumps, the insulating layer, and the molding compound, the signal distribution structure being configured to provide corresponding electrical connections to the plurality of conductive bumps.

10. The method according to claim 9, wherein: The plurality of conductive bumps are a first plurality of conductive bumps; and Forming the signal distribution structure includes: forming a dielectric layer on the insulating layer, the first plurality of conductive bumps and the molding compound, the dielectric layer having a flat surface; forming a plurality of via openings through the dielectric layer; forming a plurality of electrical connections to the first plurality of conductive bumps, each electrical connection of the plurality of electrical connections disposed on the planar surface of the dielectric layer and disposed in a corresponding via opening of the plurality of via openings; and A second plurality of conductive bumps are formed, the second plurality of conductive bumps being disposed on corresponding electrical connectors of the plurality of electrical connectors. 11 . The method of claim 9 , further comprising forming trenches through the molding compound to singulate fan-out wafer-level packages including the semiconductor die.

12. The method according to claim 9, further comprising: Before cutting the semiconductor wafer into the plurality of semiconductor dies: grinding the backside surface of the semiconductor die to reduce the thickness of the semiconductor die; as well as A backside metal layer is formed on the backside surface of the semiconductor die.

Images