Semiconductor device

Abstract

In one case, a semiconductor device includes a substrate; a first elongated fin structure on the substrate; and a second elongated fin structure on the substrate. A longitudinal axis of the first elongated fin structure is aligned with a longitudinal axis of the second elongated fin structure. The device also includes a dummy structure extending between the first elongated fin structure and the second elongated fin structure. The dummy structure includes a dielectric material.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly, to dummy structures between fins. Background Art

[0002] In the semiconductor integrated circuit industry, technological advances in integrated circuit materials and design have enabled each generation of integrated circuits to feature smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (e.g., the number of interconnect devices per unit chip area) has generally increased as geometric dimensions (e.g., the smallest component or circuit that can be produced by the fabrication process) have decreased. Processes with smaller dimensions generally increase production capacity and reduce associated costs. However, these dimensions also increase the complexity of processing and fabricating integrated circuits.

[0003] One type of semiconductor device that can be manufactured is a fin field-effect transistor. In a fin field-effect transistor, a fin-shaped semiconductor structure is formed on a substrate. A gate structure can then be formed to cover the fin structure. In addition, an active region containing source / drain regions is then formed in the fin structure adjacent to the gate structure. A particular fin structure can be used for multiple transistors in a circuit. In some cases, it is necessary to separate one portion of the fin from another portion. In summary, a portion of the elongated fin can be removed or cut to separate the two portions of the elongated fin structure. Circuits, such as static random access memory circuits, need to be designed so that the fin structure has sufficient electrical isolation, mechanical strength, and reliability. Summary of the Invention

[0004] A semiconductor device provided by one embodiment of the present invention includes: a substrate; a first elongated fin-shaped structure located on the substrate; a second elongated fin-shaped structure located on the substrate, and the longitudinal axis of the first elongated fin-shaped structure is aligned with the longitudinal axis of the second elongated fin-shaped structure; and a dummy structure extending between the first elongated fin-shaped structure and the second elongated fin structure, and the dummy structure includes a dielectric material.

[0005] A method for manufacturing a semiconductor device provided by an embodiment of the present invention includes: forming a slender fin structure; performing an etching process to cut the slender fin structure into a first portion and a second portion; and forming a dummy structure in a gap between the first portion and the second portion.

[0006] A semiconductor device provided by one embodiment of the present invention includes: a substrate; a plurality of slender fin-shaped structures located on the substrate, and the slender fin-shaped structures include a first slender fin-shaped structure, wherein the longitudinal axis of the first slender fin-shaped structure is aligned with the longitudinal axis of the second slender fin-shaped structure; a plurality of dummy fins located between the slender fin-shaped structures; and a dummy structure located between the first slender fin structure and the second slender fin structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E 、 Figure 1F 、 Figure 1G 、 Figure 1H 、 Figure 1I 、 Figure 1J 、 Figure 1K 、 Figure 1L 、 Figure 1M 、 Figure 1N 、 Figure 1O 、 Figure 1P 、 Figure 1Q 、 Figure 1R 、 Figure 1S 、 Figure 1T 、 Figure 1U 、 Figure 1V 、 Figure 1W ,and Figure 1X 1 and 2 are cross-sectional and top views of a process for forming a dummy fin structure with a fin cut region, in an example of the principles described herein.

[0008] Figure 2 is a flow chart of an illustrative method for forming a dummy fin structure with a fin cut region, in accordance with an example of the principles described herein.

[0009] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F 、 Figure 3G 、 Figure 3H 、 Figure 3I 、 Figure 3J 、 Figure 3K ,and Figure 3L 1 is a cross-sectional view and a top view of a process for forming a base dummy structure with a fin cutting area in an example of the principles described herein.

[0010] Figure 4 is a flow chart of an illustrative method for forming a substrate dummy structure having a fin cut region, in accordance with an example of the principles described herein.

[0011] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E 、 Figure 5F 、 Figure 5G 、 Figure 5H 、 Figure 5I 、 Figure 5J ,and Figure 5K sectional views and top views of a process for forming a gate extension with a fin cut region, in accordance with an example of the principles described herein.

[0012] Figure 6 is a flow chart of an illustrative method for forming a gate extension with a fin cut region, in accordance with an example of the principles described herein.

[0013] Description of reference numerals:

[0014] 100, 300, 500 workpieces

[0015] 101, 103, 117 fin structures

[0016] 103a Part 1

[0017] 103b Part 2

[0018] 102 substrate

[0019] 104 lower part

[0020] 105, 107, 119, 317, 501, 507 deposition processes

[0021] 106 upper part

[0022] 108 hard mask layers

[0023] 109 cutting process

[0024] 110 spacer layer

[0025] 111, 121, 319 processes

[0026] 112, 304 virtual fin layer

[0027] 113, 503 chemical mechanical polishing process

[0028] 114 Fin Cutting Area

[0029] 115, 315, 505 etching process

[0030] 116 virtual fin structure

[0031] 117, 125, 305, 305a, 305b virtual fins

[0032] 118, 128 isolation layers

[0033] 120, 306, 504 gate dielectric layer

[0034] 122, 308, 506 gate devices

[0035] 123 epitaxial process

[0036] 124 source / drain region

[0037] 126 gate spacer

[0038] 130 contacts

[0039] 132, 134 height

[0040] 133 Edge

[0041] 135 source / drain contacts

[0042] 143 Interface

[0043] 200, 400, 600 methods

[0044] 202, 204, 206, 208, 210, 212, 402, 404, 406, 408, 410, 412, 602, 604, 606, 608, 610, 612, 614 Step 302 Virtual layer

[0045] Section 303

[0046] 307 base vacant structure

[0047] 321 First Size

[0048] 323 Second Size

[0049] 330 contacts

[0050] 502 interlayer dielectric layer

[0051] 508 gate extension DETAILED DESCRIPTION

[0052] The following content provides different embodiments or examples that can implement different structures of the present invention. The following specific components and configuration embodiments are used to simplify the content of the present invention and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes an embodiment in which the two are in direct contact, or an embodiment in which the two are separated by other additional components but not in direct contact. On the other hand, multiple embodiments of the present invention may repeatedly use the same reference numerals for simplicity, but elements with the same reference numerals in multiple embodiments and / or settings do not necessarily have the same corresponding relationship.

[0053] Additionally, spatially relative terms such as "below," "beneath," "below," "above," "above," or similar terms may be used to simplify descriptions of an element's relative relationship to another element in a diagram. Spatially relative terms extend to elements used in other orientations and are not limited to the orientation shown. Elements may also be rotated 90° or other angles, so directional terms are used only to describe the orientation shown in the diagram.

[0054] As mentioned above, it is necessary to design circuits such as SRAM circuits so that the fin structure has sufficient electrical isolation, mechanical strength, and reliability.

[0055] According to the principles described herein, a dummy structure is formed in the fin cut area. The fin cut area is the space left after the fin cut process, when part of the fin structure is removed. In one example, the dummy structure is a dummy fin structure extending between the fin structures at both ends. In one example, the dummy structure is a base dummy structure, which also extends between adjacent dummy fins. In one example, the dummy structure includes a gate extension extending into the fin cut area. Placing these dummy structures in the fin cut area can provide additional mechanical stability. In addition, the dummy structure can avoid shallow trench isolation loss and damage to the gate structure in subsequent processes.

[0056] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E 、 Figure 1F 、 Figure 1G 、 Figure 1H 、 Figure 1I 、 Figure 1J 、 Figure 1K 、 Figure 1L 、 Figure 1M 、 Figure 1N 、 Figure 1O 、 Figure 1P 、 Figure 1Q 、 Figure 1R 、 Figure 1S 、 Figure 1T 、 Figure 1U ,and Figure 1V 1. The invention provides a cross-sectional view and a top view of a process for forming a dummy fin structure with a fin cutting area. Figure 1A Workpiece 100 is shown after forming a plurality of fin structures 101 and 103 on substrate 102. Workpiece 100 may be a portion of a semiconductor wafer, upon which various fabrication processes may be performed to produce various circuit components such as transistors, resistors, capacitors, or the like. The circuit components may form various integrated circuit devices, such as processors containing various standard logic cells or memory chips (e.g., static random access memory chips). In some embodiments, the circuit components include analog devices such as ring oscillators. In some cases, the circuit components may be portions of n-type devices. Figure 1B FIG. 1 is a top view of the fin structures 101 and 103 formed on the substrate 102 .

[0057] In this example, a set of n-type metal oxide semiconductor fin structures 101 and a set of p-type metal oxide semiconductor fin structures 103 are formed. The p-type metal oxide semiconductor fin structure 103 includes a lower portion 104 and an upper portion 106. In one example, the lower portion 104 is composed of the same type of semiconductor material as the substrate 102. For example, the lower portion 104 may include silicon, germanium, silicon germanium, or other semiconductor materials. For example, if a silicon substrate is used, the lower portion 104 of the p-type metal oxide semiconductor fin structure 103 includes silicon. The upper portion 106 of the fin structure 103 may include a different semiconductor material, such as silicon germanium. Both fin structures 101 and 103 include a hard mask layer 108 formed on top thereof.

[0058] The fin structures 101 and 103 can be formed in a variety of ways. In one example, the fin structures can be formed by patterning the semiconductor substrate 102 using photolithography technology and performing an etching process to remove the portion between the fin structures 101 and 103. The upper portion 106 can be formed by replacing the upper portion of the substrate before the back etching process. The replacement process can involve removing the upper portion of the substrate in the p-type metal oxide semiconductor region and replacing the removed upper portion using an epitaxial growth process. Embodiments of the present invention contemplate other methods for forming the fin structures 101 and 103.

[0059] Figure 1C A conformal spacer layer 110 is formed on the fin structures 101 and 103 by a deposition process 105. The spacer layer 110 may be an oxide layer such as silicon oxide. Figure 1D Figure 1 is a top view of a compliant spacer layer 110. Spacer layer 110 can be formed using one of a variety of methods. In one example, spacer layer 110 is formed using an atomic layer deposition process. Atomic layer deposition utilizes different gaseous species in an alternating pattern to grow thin films layer by layer. Using a compliant process such as atomic layer deposition can maintain a gap between fin structures 101 and 103.

[0060] Figure 1E The workpiece 100 is shown after a deposition process 107 is performed to form a dummy fin layer 112. The dummy fin layer 112 may include silicon carbonitride, silicon nitride, silicon oxycarbonitride, or a metal oxide (eg, hafnium oxide, zirconium oxide, hafnium aluminum oxide, or hafnium silicon oxide). Figure 1F: is a top view of the dummy fin layer 112. The dummy fin layer 112 can be formed by an atomic layer deposition process. Embodiments of the present invention also take into account other process methods. The dummy fin layer 112 fills the gap between the fin structures 101 and 103. The dielectric material used for the dummy fin layer 112 is selected to selectively etch the fin layer 112 relative to the spacer layer 110. In other words, the dielectric materials of the spacer layer 110 and the dummy fin layer 112 can be selected to etch one without substantially affecting the other. The dummy fin layer 112 finally forms a dummy fin, which is parallel to the fin structures 101 and 103 and is located between the fin structures 101 and 103. The height of the dummy fin is approximately 12nm to 20nm.

[0061] Figure 1G The device is after the cutting process 109 used to remove the dummy fin layer 112, the spacer layer 110, and a portion of the fin structure 103. The cutting process 109 creates a fin cutting area 114. The fin cutting area separates the first portion 103a and the second portion 103b of the fin structure, as shown in FIG. Figure 1K shown. Figure 1H A top view of the fin cutting area 114 is shown.

[0062] Figure 1I The workpiece 100 is shown after the process 111 of forming a dummy fin structure 116 having a fin cut region. Figure 1J is a top view of dummy fin structure 116. In this example, the height of dummy fin structure 116 is less than the height of fin structure 103. In one example, the height of dummy fin structure 116 is approximately 1 nm to 30 nm. Dummy fin structure 116 can be formed using one of a variety of processes. In one example, dummy fin structure 116 is formed using an atomic layer deposition process. dummy fin structure 116 can be composed of a variety of materials. In one example, dummy fin structure 116 includes silicon carbonitride, silicon nitride, silicon oxycarbonitride, or a metal oxide (e.g., hafnium oxide, zirconium oxide, hafnium aluminum oxide, or hafnium silicon oxide).

[0063] Figure 1K The workpiece 100 is shown after a deposition process to form an isolation layer 118 in the gap above the dummy fin structure and a chemical mechanical polishing process 113 to planarize the workpiece 100. In some examples, the isolation layer 118 and the spacer layer 110 are made of the same material. Figure 1L FIG. 1 is a top view of the workpiece 100 after the chemical mechanical polishing process, where the upper surface of the fin structure 103 is exposed.

[0064] Figure 1MWorkpiece 100 after etching process 115 removes a portion of spacer layer 110 and isolation layer 118. This step exposes portions of the upper sides of fin structures 101 and 103. The etching process also exposes portions of the upper sides of dummy fin 117, which is located between and parallel to fin structures 101 and 103. Etching process 115 may be a dry etching process, such as reactive ion etching. Etching process 115 and the materials of spacer layer 110 and dummy fin layer 112 are etched, such that etching process 115 removes spacer layer 110 while leaving dummy fin layer 112 substantially intact. Figure 1N is a top view of the workpiece after the etching process 115 .

[0065] Figure 1O Workpiece 100 after deposition process 119 to form gate dielectric layer 120 over fin structures 101 and 103 and dummy fin 125. Gate dielectric layer 120 may be a high-k dielectric layer or an oxide layer. Gate dielectric layer 120 may be deposited using atomic layer deposition. Other compatible deposition processes are contemplated by the present invention. Figure 1P is a top view of the gate dielectric layer 120 .

[0066] Figure 1Q Workpiece 100 after process 121 of forming gate device 122. Gate device 122 is perpendicular to fin structures 101 and 103. Gate device 122 can be composed of a conductive material such as metal or polysilicon. Gate device 122 can be formed using a photolithography process. For example, layers of a gate stack can be deposited onto workpiece 100. A photoresist can then be formed on the gate stack. The photoresist can then be exposed to light through a mask to pattern the photoresist. An etching process can then be performed to remove the exposed portions of the gate stack. Figure 1R is a top view of the gate device 122 .

[0067] Figure 1S Epitaxial process 123 forms source / drain regions 124 on fin structures 101 and 103. Source / drain regions 124 may be formed by epitaxial growth. In one example, gate spacers 126 are formed on the sidewalls of gate device 122 before growing source / drain regions 124. As shown, since the dummy fin structure is a dielectric layer rather than a crystalline layer, source / drain regions 124 are not formed on the dummy fin structure. Figure 1T 1 is a top view of source / drain region 124. The source / drain regions on either side of the gate device can form a transistor. In some examples, the transistor is a p-type metal oxide semiconductor device, such as a pull-up transistor in a static random access memory cell. In some embodiments, the transistor is an n-type metal oxide semiconductor device in a standard logic cell.

[0068] Figure 1U FIG2 is a cross-sectional view of workpiece 100 after forming contact 130 and isolation layer 128. As shown, the height 134 of dummy fin structure 116 in the fin cut region is greater than the height 132 of dummy fin structure 117, as described in the above-described fabrication process. However, in some embodiments, dummy fin structure 116 may be coplanar with dummy fin structure 117. Figure 1V This is a top view of workpiece 100, omitting isolation layer 128 and contacts 130 for simplicity. As shown, a dummy fin structure separates a first portion 103a of the fin structure from a second portion 103b of the fin structure. The longitudinal axis of first portion 103a of the fin structure is aligned with the longitudinal axis of second portion 103b of the fin structure.

[0069] Figure 1W and 1X is a cross-sectional view of a gate structure formed on a dummy fin structure. Figure 1W In one example, the gate device 122 having the sidewall 145 extends beyond the edge 133 of the dummy fin structure 116 . Figure 1X In one example, the junction 143 between the dummy fin structure 116 and the source / drain region 124 is substantially aligned with the gate structure and the adjacent source / drain contact 135 .

[0070] Figure 2 is a flow chart of an exemplary method 200 for forming a dummy fin structure having a fin cut region. In an embodiment of the present invention, the method 200 includes step 202 for forming a fin structure. In one example, the fin structure may be used for a p-type metal oxide semiconductor device. The fin structure may correspond to Figure 1A One of the fin structures 103 shown. The fin structure can be formed on a substrate. The p-type metal oxide semiconductor fin structure can include a lower portion and an upper portion. In one example, the lower portion and the substrate 102 can be composed of the same type of semiconductor material. For example, if a silicon substrate is used, the lower portion of the p-type metal oxide semiconductor fin structure can be silicon. The upper portion of the fin structure can include a different semiconductor material such as silicon germanium. The fin structure can be formed in a variety of ways. In one example, the fin structure can be formed using a photolithography technique to pattern a semiconductor substrate and perform an etching process to define the fin structure. In addition, an epitaxial growth process can be performed to form the upper portion of the fin structure (such as the upper portion 106).

[0071] The method 200 further includes step 204 of forming a compliant spacer layer (e.g. Figure 1C A spacer layer 110 is formed on the fin structure. The spacer layer can be formed using one of a variety of methods. In one example, the spacer layer is formed using an atomic layer deposition process. A compliant process such as atomic layer deposition is used to maintain an air gap between the fin structures.

[0072] Method 200 also includes step 206 of depositing a dummy fin layer (such as dummy fin layer 112 of FIG. 1 ). The dummy fin layer may be formed using an atomic layer deposition process. The dummy fin layer fills the gaps between the fin structures. The dielectric material of the dummy fin layer is selected to selectively etch the dummy fin layer relative to the spacer layer 110. In other words, the dielectric material of the dummy fin layer is selected to selectively etch the dummy fin layer without substantially affecting other layers.

[0073] The method 200 further includes step 208 of performing a cutting process for cutting the fin structure. The cutting process may involve one or more etching steps to etch a variety of materials. For example, the cutting process involves removing a compliant spacer layer to a first depth. The cutting process also includes removing the fin structure to a second depth, wherein the second depth is deeper than the first depth. The fin cut region formed by the cutting process separates a portion (e.g., Figure 1V The first part 103a of the fin structure) and the other part (such as Figure 1V The second portion 103b of the fin structure).

[0074] The method 200 further includes step 210 to form a dummy fin structure (eg, Figure 1I A dummy fin structure 116 is formed in the fin cut area. In this example, the height of the dummy fin structure is less than the height of the fin structure. The dummy fin structure can be formed using one of a variety of processes. In one example, the dummy fin structure is formed using an atomic layer deposition process. The dummy fin structure can be composed of a variety of materials. In one example, the dummy fin structure includes silicon carbonitride, silicon nitride, silicon oxycarbonitride, or a metal oxide (such as hafnium oxide, zirconium oxide, hafnium aluminum oxide, or hafnium silicon oxide).

[0075] Method 200 also includes step 212 to form a gate and source / drain regions. Before forming the gate and source / drain regions, a deposition process is performed to form an isolation layer in the gap above the dummy fin structure, and then a chemical mechanical polishing process is performed to planarize the workpiece. An etching process is then performed to remove a portion of the spacer layer and the interlayer dielectric layer material to expose the upper portion of the fin structure. The etching process also exposes the upper portion of the dummy fin parallel to the fin structure and located between the fin structures. The gate is perpendicular to the fin structure, and the gate formation method can use multiple deposition processes to form a gate dielectric layer (such as Figure 1O A gate stack is formed starting with a gate dielectric layer 120 (e.g., a gate electrode). After forming the gate, sidewall spacers may be formed on the gate. Source / drain regions may be formed in the fin structure adjacent to the gate. The source / drain regions may be formed using an epitaxial process.

[0076] Figure 3A 、 Figure 3B 、 Figure 3C、 Figure 3D 、 Figure 3E 、 Figure 3F 、 Figure 3G 、 Figure 3H 、 Figure 3I 、 Figure 3J 、 Figure 3K ,and Figure 3L 1. The invention provides a cross-sectional view and a top view of a process for forming a base dummy structure with a fin cutting area. Figure 3A The workpiece 300 after forming the patterned dummy layer 302. The steps before forming the patterned dummy layer can be Figures 1A to 1D The steps described above are similar. The method for forming the patterned dummy layer can involve a deposition process and a patterning process. The deposition process for depositing the dummy layer material between the fin structures 101 and 103 can be an atomic layer deposition process. Embodiments of the present invention also contemplate other manufacturing processes. The patterning process can involve various photolithography processes to remove the portion 303 of the dummy layer corresponding to the location where the fin structure 103 is to be cut. Figure 3B is a top view of the workpiece 300 after depositing the dummy layer 302 but before patterning the dummy layer 302 .

[0077] Figure 3C The workpiece 300 is shown after the fin structure 103 is cut and a dummy fin layer 304 is deposited in the space left by the fin cutting process, and chemical mechanical polishing is performed. The cutting process may include an etching process. In particular, photolithography techniques may be used to form a patterned hard mask that exposes the fin cut areas to the etching process and protects other areas from being affected by the etching process.

[0078] Figure 3D The top view after these processes are performed is shown. The fin cutting process may include an etching process designed to remove the portion of the fin structure exposed by the patterned dummy layer 302 down to the substrate 102. The holes left by the etching process are then filled with dummy material. This material can be the same type as that used to form the patterned dummy layer 302.

[0079] As shown in the top view, cutting the fin structure 103 and depositing the dummy layer in this manner results in a base dummy structure 307 extending between two adjacent dummy fins 305a and 305b. The height of the base dummy structure 307 is approximately 12 nm to 20 nm. The base dummy structure 307 also extends between the first portion 103a of the fin structure and the second portion 103b of the fin structure. The first portion 103a and the second portion 103b of the fin structure are functional fin structures (e.g., non-fin structures).

[0080] Figure 3EAn etching process 315 is performed to expose the upper portion of the fin structure 103, the dummy fins 305a and 305b, and the base dummy structure 307. In one example, the etching process 315 is a dry etching process, such as a reactive ion etching process. The materials used for the etching process 315, the spacer layer 110, and the dummy layer 302 are selected so that the etching process 315 removes the spacer layer without substantially affecting the dummy layer 302 and the fin structure 103. Figure 3F It is a top view of the workpiece 300 .

[0081] Figure 3G Workpiece 300 after deposition process 317 to form gate dielectric layer 306 over fin structures 101 and 103 and dummy fin 305. Gate dielectric layer 306 may be a high-k dielectric layer. In some examples, gate dielectric layer 306 comprises silicon oxide. Gate dielectric layer 306 may be deposited using an atomic layer deposition process. Other compatible deposition processes are also contemplated by embodiments of the present invention. Figure 3H is a top view of the gate dielectric layer 306 .

[0082] Figure 3I Workpiece 100 after process 319 of forming gate device 308. Gate device 308 is perpendicular to fin structures 101 and 103. Gate device 308 can be composed of a conductive material such as metal or polysilicon. Gate device 308 can be formed using a photolithography process. For example, the layers of the gate stack can be deposited on workpiece 300. A photoresist can then be applied to the gate stack layers. The photoresist can then be exposed to light through a mask to pattern the photoresist. An etching process can then be applied to remove the exposed portions of the gate stack layers. Figure 3J This is a top view of the gate device 308. After the gate device 308 is formed, it can be used with Figure 1S The source / drain regions are formed in a similar manner to the above-described process.

[0083] Figure 3K is a cross-sectional view of the workpiece 300 after forming the contact 330. As shown in the figure, the dummy fin 305 is coplanar with the upper surface of the fin structure 103. Figure 3L is a top view of workpiece 300. As shown, base dummy fin structure 307 separates first portion 103a of the fin structure from second portion 103b of the fin structure. Base dummy fin structure 307 also extends between dummy fins 305a and 305b. A first dimension 321 of base dummy fin structure 307 is approximately 36 nm to 52 nm. A second dimension 323 of base dummy structure 307 may be approximately 40 nm to 66 nm.

[0084] Figure 4is a flow chart of a method 400 for forming a base dummy structure in a fin cut region. In this example, the method 400 includes step 402 to form a fin structure. In one example, the fin structure can be used for a p-type metal oxide semiconductor device. The fin structure can correspond to Figure 1A One of the fin structures 103 shown. The fin structure can be formed on a substrate. The p-type metal oxide semiconductor fin structure includes a lower portion and an upper portion. In one example, the composition of the lower portion can be the same type of semiconductor material as the substrate 102. For example, if the substrate is a silicon substrate, the lower portion of the p-type metal oxide semiconductor fin structure can be silicon. The upper portion of the fin structure can include a different semiconductor material such as silicon germanium. The fin structure can be formed in a variety of ways. In one example, the fin structure can be formed using photolithography technology to pattern the semiconductor substrate and perform an etching process to define the fin structure.

[0085] The method 400 further includes step 404 of forming a compliant spacer layer (e.g. Figure 1C A spacer layer 110 is formed on the fin structure. The spacer layer can be formed using one of a variety of methods. In one example, the spacer layer is formed using an atomic layer deposition process. A compliant process such as atomic layer deposition is used to maintain an air gap between the fin structures.

[0086] The method 400 also includes step 406 to deposit a dummy fin layer (e.g. Figure 3C The dummy fin layer 304 may be formed using an atomic layer deposition process. The dummy fin layer can fill the gaps between the fin structures. The dielectric material used for the dummy fin layer is selected to selectively etch the dummy fin layer relative to the spacer layer 110. In other words, the dielectric material selected allows for selective etching of the dielectric material while substantially leaving other layers unaffected.

[0087] The method 400 further includes step 408 for performing a cutting process to cut the fin structure. The cutting process may involve one or more etching steps to etch a variety of materials. For example, the cutting process involves removing the compliant spacer layer 110 and the fin structure 103 to a specific depth. The cutting process forms a fin cutting region to separate the first portion (e.g., Figure 3L The first part 103a of the fin structure) and the other part (such as Figure 3L The fin cutting area also extends between the dummy fins (e.g., Figure 3L dummy fins 305a and 305b).

[0088] The method 400 further includes step 410 to form a base dummy structure (eg Figure 3CThe base dummy structure 307 is formed in the fin cutting area. The base dummy structure can be formed by one of a variety of processes. In one example, the dummy fin structure is formed by an atomic layer deposition process. The base dummy structure can be composed of a variety of materials. In one example, the dummy fin structure includes silicon carbonitride, silicon nitride, silicon oxycarbonitride, or a metal oxide (such as hafnium oxide, zirconium oxide, hafnium aluminum oxide, or hafnium silicon oxide). In some examples, the base dummy fin structure directly contacts the underlying substrate 102.

[0089] Method 400 also includes step 412 to form a gate and source / drain regions. Before forming the gate and source / drain regions, a deposition process is performed to form an isolation layer in the gap on the dummy fin structure. A chemical mechanical polishing process is then used to planarize the workpiece. An etching process is then used to remove a portion of the spacer layer and the interlayer dielectric layer material to expose the upper portion of the fin structure. The etching process also exposes the upper portion of the dummy fin parallel to the fin structure and located between the fin structures. The gate can be perpendicular to the fin structure, and its formation method can use multiple deposition processes to form a gate stack starting from the gate dielectric layer. After forming the gate, sidewall spacers can be formed on the gate. A source / drain region can then be formed in the fin structure adjacent to the gate. The source / drain region can be formed using an epitaxial process.

[0090] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E 、 Figure 5F 、 Figure 5G 、 Figure 5H 、 Figure 5I 、 Figure 5J ,and Figure 5K sectional views and top views of a process for forming gate extensions in the fin cut region. Figure 5A The workpiece 500 is shown after depositing an interlayer dielectric layer 502 in the fin cut area. Figure 5B FIG2 is a top view of interlayer dielectric layer 502. The interlayer dielectric layer can be formed using a variety of processes. In one example, deposition process 501 for forming interlayer dielectric layer 502 is an atomic layer deposition process. Interlayer dielectric layer 502 can include a dielectric material such as a nitride or oxide material.

[0091] Figure 5C The workpiece 500 is shown after a chemical mechanical polishing process 503 is performed to planarize the workpiece 500 .

[0092] The CMP process 503 exposes the top surfaces of the dummy fin 305 , the fin structures 101 and 103 , and the interlayer dielectric layer 502 formed in the fin cut region. Figure 5Dis a top view of the workpiece 500 after the chemical mechanical polishing process 503 .

[0093] Figure 5E The workpiece 500 is shown after an etching process is performed to partially remove the interlayer dielectric layer 502 and the spacer layer 110. The etching process 505 exposes upper portions of the fin structures 101 and 103 and the dummy fin 305. Figure 5F is a top view of the workpiece after the etching process 505 .

[0094] Figure 5G Workpiece 500 after deposition process 507 to form a gate dielectric layer 504 on fin structures 101 and 103 and dummy fin 305. Gate dielectric layer 504 may be a high-k dielectric layer. Gate dielectric layer 504 may be deposited using an atomic layer deposition process. Other compatible deposition processes are also contemplated by the present invention. Figure 5H is a top view of the gate dielectric layer 504 .

[0095] Figure 5I The workpiece 100 is shown after process 319 of forming gate device 506. Gate device 506 can be made of a conductive material such as metal or polysilicon. Gate device 506 can be formed using a photolithography process. For example, the layers of a gate stack can be deposited onto workpiece 500. A photoresist can then be formed on the gate stack. The photoresist can then be exposed to light through a mask to pattern the photoresist. An etching process can then be performed to remove the exposed portions of the gate stack. Figure 5J This is a top view of the gate device 506. After forming the gate device 506, the source / drain regions can be formed. The formation method and the matching Figure 1S The above process described is similar.

[0096] In this example, the gate structure includes a gate extension 508 that extends into the area above the fin cutout. The patterning process for forming gate extension 508 can form the extension. In other words, the mask used in the gate patterning process can include a gate structure with a gate extension. The gate extension can be approximately 1 nm to 6 nm. The gate extension helps reduce shallow trench isolation loss in subsequent process steps.

[0097] Figure 5K 1 is a top view of a device with gate extensions extending into the fin cut region. As shown, gate extensions 508 are formed on both sides of the fin cut region.

[0098] Figure 6 is a flow chart of a method 600 for forming a gate extension in a fin cut region. In this example, the method 600 includes step 602 to form a fin structure. In one example, the fin structure can be a p-type metal oxide semiconductor device. The fin structure can correspond to Figure 1A One of the fin structures 103 is shown. The fin structure can be formed on a substrate. The p-type metal oxide semiconductor fin structure can include a lower portion and an upper portion. In one example, the composition of the lower portion can be the same type of semiconductor material as the substrate 102. For example, if a silicon substrate is used, the lower portion of the p-type metal oxide semiconductor fin structure can be silicon. The upper portion of the fin structure can include a different semiconductor material such as silicon germanium. The fin structure can be formed in a variety of ways. In one example, the fin structure can be formed by patterning the semiconductor substrate using photolithography and etching processes to define the fin structure.

[0099] The method 600 further includes step 604 of forming a compliant spacer layer (e.g. Figure 1C A spacer layer 110 is formed on the fin structure. The spacer layer can be formed using one of a variety of methods. In some examples, the spacer layer is formed using an atomic layer deposition process. Using a compliant process such as atomic layer deposition can maintain a gap between the fin structures.

[0100] The method 600 further includes step 606 of performing a cutting process to cut the fin structure. The cutting process may involve one or more etching steps to etch a variety of materials. For example, the cutting process involves removing the compliant spacer layer 110 and the fin structure 103 to a specific depth. The cutting process may form a fin cutting region to separate a portion (e.g., Figure 3K The first part 103a of the fin structure) and the other part (such as Figure 3K The second portion 103b of the fin structure).

[0101] The method 600 further includes step 608 of depositing an interlayer dielectric layer (e.g. Figure 5A The interlayer dielectric layer 502 is deposited into the fin cutout area. The interlayer dielectric layer 502 fills the gap between the fin structures 101 and 103 and the dummy fin 305. The material used for the interlayer dielectric layer is selected to selectively etch the interlayer dielectric layer relative to the dummy fin structure. In other words, the material selection allows etching one without substantially affecting the other.

[0102] The method 600 further includes step 610 of performing a chemical mechanical polishing process (e.g. Figure 5C The chemical mechanical polishing process 503 is used to planarize the workpiece. The chemical mechanical polishing process exposes the upper surface of the dummy fin, the fin structure, and the interlayer dielectric layer material formed in the fin cut area.

[0103] The method 600 further includes step 612 of performing an etching process (e.g. Figure 5E The etching process 505 exposes the upper portion of the fin structure and the dummy fin.

[0104] Method 600 also includes step 614 to form a gate and source / drain regions. Before forming the gate and source / drain regions, a deposition process is performed to form an isolation layer in the gap above the dummy fin structure, and then a chemical mechanical polishing process is performed to planarize the workpiece. An etching process is then performed to remove a portion of the spacer layer and the interlayer dielectric layer material to expose the upper portion of the fin structure. The etching process also exposes the upper portion of the dummy fin parallel to the fin structure and located between the fin structures. The gate is perpendicular to the fin structure, and the gate formation method can use multiple deposition processes to form a gate stack starting from the gate dielectric layer. The gate device includes a gate extension (such as Figure 5I The gate extension 508 is formed by a patterning process that forms the gate extension 508, extending into the area above the fin cut region. In other words, the mask used in the gate patterning process may include a gate structure with a gate extension. The gate extension may be approximately 1 nm to 6 nm in thickness. The gate extension helps reduce shallow trench isolation losses in subsequent process steps.

[0105] After forming the gate, sidewall spacers may be formed on the gate. Next, source / drain regions may be formed in the fin structure adjacent to the gate. The source / drain regions may be formed using an epitaxial growth process.

[0106] The semiconductor device includes a substrate; a first elongated fin-shaped structure disposed on the substrate; and a second elongated fin-shaped structure disposed on the substrate. The longitudinal axis of the first elongated fin-shaped structure is aligned with the longitudinal axis of the second elongated fin-shaped structure. The device also includes a dummy structure extending between the first elongated fin-shaped structure and the second elongated fin-shaped structure. The dummy structure comprises a dielectric material.

[0107] In one embodiment, the dummy structure includes a dummy fin structure directly contacting the first elongated fin structure and the second elongated fin structure, and the first elongated fin structure and the second elongated fin structure are functional fin structures.

[0108] In one embodiment, the height of the dummy fin structure is smaller than the height of the first elongated fin structure.

[0109] In one embodiment, the height difference between the dummy fin structure and the elongated fin structure is 1 nm to 30 nm.

[0110] In one embodiment, the first elongated fin structure and the second elongated fin structure include silicon germanium.

[0111] In one embodiment, a length of the dummy structure from one end of the first elongated fin structure to one end of the second elongated fin structure is approximately 12 nm to 20 nm.

[0112] In one embodiment, the dummy structure includes silicon carbonitride, silicon nitride, silicon oxycarbonitride, hafnium oxide, hafnium aluminum oxide, or hafnium silicon oxide.

[0113] In one embodiment, the dummy structure extends between the first dummy fin and the second dummy fin, and the first dummy fin and the second dummy fin are parallel to the first elongated fin structure and the second elongated fin structure.

[0114] In one embodiment, the gap between the first elongated fin structure and the second elongated fin structure is approximately 36 nm to 52 nm.

[0115] In one embodiment, the gap between the first dummy fin and the second dummy fin is approximately 40 nm to 66 nm.

[0116] In one embodiment, the elongated fin structure is part of a transistor for an n-type device.

[0117] In one embodiment, the elongated fin structure is part of a transistor used in a static random access memory device.

[0118] In one embodiment, the transistor is a pull-up transistor.

[0119] The manufacturing method of the semiconductor device includes: forming a slender fin structure; performing an etching process to cut the slender fin structure into a first part and a second part; and forming a dummy structure in a gap between the first part and the second part.

[0120] In one embodiment, the dummy structure includes a dummy fin structure extending between the first portion and the second portion, and a height of the dummy fin structure is smaller than a height of the elongated fin structure.

[0121] In one embodiment, the dummy structure includes a base structure extending between the first portion and the second portion in a first direction, and the base structure extends between two parallel dummy fins in a second direction, and the first direction is perpendicular to the second direction.

[0122] In one embodiment, the dummy structure and the dummy fin are formed in the same process.

[0123] The semiconductor device includes a substrate and a plurality of elongated fin structures disposed on the substrate. The elongated fin structures include a first elongated fin structure. The longitudinal axis of the first elongated fin structure is aligned with the longitudinal axis of the second elongated fin structure. A plurality of dummy fins are disposed between the elongated fin structures. The dummy fins are disposed between the first elongated fin structure and the second elongated fin structure.

[0124] In one embodiment, the dummy structure includes a dummy fin structure extending between the first elongated fin structure and the second elongated fin structure, and a height of the dummy structure is different from a height of the elongated fin structure.

[0125] In one embodiment, the dummy structure is a base dummy structure extending between the dummy fin structures in a direction perpendicular to the longitudinal axis.

[0126] The features of the above-described embodiments will facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present invention may be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and that changes, substitutions, or modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device comprising: a substrate; a first elongated fin-shaped structure located on the substrate; a second elongated fin structure disposed on the substrate, wherein a longitudinal axis of the first elongated fin structure is aligned with a longitudinal axis of the second elongated fin structure, wherein the first elongated fin structure and the second elongated fin structure are part of a transistor used in a static random access memory device; a dummy structure extending between the first elongated fin structure and the second elongated fin structure, wherein the dummy structure comprises a dielectric material; and A gate device is located on the dummy structure and contacts the top surface of the dummy structure. 2 . The semiconductor device of claim 1 , wherein the dummy structure comprises a dummy fin structure directly contacting the first elongated fin structure and the second elongated fin structure, and the first elongated fin structure and the second elongated fin structure are functional fin structures. 3 . The semiconductor device of claim 2 , wherein a height of the dummy fin structure is smaller than a height of the first elongated fin structure. 4 . The semiconductor device of claim 3 , wherein a height difference between the dummy fin structure and the first and second elongated fin structures is 1 nm to 30 nm. 5 . The semiconductor device of claim 1 , wherein the first elongated fin structure and the second elongated fin structure comprise silicon germanium. 6 . The semiconductor device of claim 1 , wherein a length of the dummy structure from one end of the first elongated fin structure to one end of the second elongated fin structure is 12 nm to 20 nm. 7 . The semiconductor device of claim 1 , wherein the dummy structure comprises silicon carbonitride, silicon nitride, silicon oxycarbonitride, hafnium oxide, zirconium oxide, hafnium aluminum oxide, or hafnium silicon oxide. 8 . The semiconductor device of claim 1 , wherein the first elongated fin structure and the second elongated fin structure are part of transistors for n-type devices.

9. The semiconductor device as claimed in claim 1, wherein the transistor is a pull-up transistor.

10. A method for manufacturing a semiconductor device, comprising: Forming an elongated fin-like structure; performing an etching process to cut the elongated fin structure into a first portion and a second portion, wherein the first portion and the second portion of the elongated fin structure are portions of a transistor used in a static random access memory device; forming a dummy structure in a gap between the first portion and the second portion; as well as A gate device is formed on the dummy structure and contacts the top surface of the dummy structure. 11 . The method for fabricating a semiconductor device according to claim 10 , wherein the dummy structure comprises a dummy fin structure extending between the first portion and the second portion, and a height of the dummy fin structure is smaller than a height of the elongated fin structure.

12. A method for manufacturing a semiconductor device as described in claim 10, wherein the dummy structure includes a base structure extending between the first portion and the second portion in a first direction, and the base structure extends between two parallel dummy fins in a second direction, and the first direction is perpendicular to the second direction. 13 . The method for fabricating a semiconductor device according to claim 12 , wherein the dummy structure and the dummy fin are formed in a same process.

14. A semiconductor device comprising: a substrate; a plurality of elongated fin structures disposed on the substrate, the elongated fin structures comprising a first elongated fin structure and a second elongated fin structure, wherein a longitudinal axis of the first elongated fin structure is aligned with a longitudinal axis of the second elongated fin structure, wherein the first elongated fin structure and the second elongated fin structure are part of a transistor used in a static random access memory device; a plurality of dummy fins located between the elongated fin structures; a dummy structure located between the first elongated fin-shaped structure and the second elongated fin-shaped structure; as well as A gate device is located on the dummy structure and contacts the top surface of the dummy structure.

15. The semiconductor device of claim 14, wherein the elongated fin structure is part of a transistor for an n-type device. The semiconductor device as claimed in claim 14 , wherein the transistor is a pull-up transistor. 17 . The semiconductor device of claim 14 , wherein the dummy structure comprises a dummy fin structure extending between the first elongated fin structure and the second elongated fin structure, and a height of the dummy structure is different from a height of the elongated fin structure. 18 . The semiconductor device of claim 17 , wherein the dummy structure comprises silicon carbonitride, silicon nitride, silicon oxycarbonitride, hafnium oxide, zirconium oxide, hafnium aluminum oxide, or hafnium silicon oxide.

19. A semiconductor device comprising: an elongated fin-shaped structure, wherein the elongated fin-shaped structure includes a first portion and a second portion, wherein a longitudinal axis of the first portion is aligned with a longitudinal axis of the second portion, wherein the first portion and the second portion of the elongated fin-shaped structure are parts of a transistor used in a static random access memory device; a dummy structure separating the first portion and the second portion; as well as A gate device is located on the dummy structure and contacts the top surface of the dummy structure. 20 . The semiconductor device of claim 19 , wherein the dummy structure comprises a dummy fin structure extending between the first portion and the second portion. The semiconductor device of claim 20 , wherein a height of the dummy fin structure is smaller than a height of the elongated fin structure.

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