A silicon-based heterojunction solar cell and manufacturing method

Abstract

The present invention provides a silicon-based heterojunction solar cell and a manufacturing method thereof. The silicon-based heterojunction solar cell includes an N-type single-crystalline silicon wafer, which has a first surface and a second surface arranged opposite to each other. On the first surface, a first intrinsic passivation layer, an N-type back surface field layer, a first transparent conductive layer, and a first electrode are sequentially arranged from inside to outside. On the second surface, a second intrinsic passivation layer, a P-type emitter layer, a second transparent conductive layer, and a second electrode are sequentially arranged from inside to outside. Among them, a transparent conductive film buffer layer is further arranged between the first transparent conductive layer and the N-type back surface field layer. In this way, the contact resistance between the first transparent conductive layer and the N-type amorphous or microcrystalline silicon layer can be made lower.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular, to a silicon-based heterojunction solar cell and a manufacturing method thereof. Background Art

[0002] Silicon-based heterojunction solar cells have high photoelectric conversion efficiency and low temperature coefficient, which is an important development direction of solar cells and has broad market prospects and research significance. The transparent conductive layer is an important part of the silicon-based heterojunction solar cell. It is not only the light-trapping and antireflection layer of the cell, but also responsible for collecting the carriers of the cell. However, the transparent conductive layer is an N-type semiconductor, and there is a high contact resistance between it and the N-type amorphous or microcrystalline silicon layer of the silicon-based heterojunction solar cell, resulting in low cell efficiency. Summary of the Invention

[0003] The purpose of the embodiments of the present invention is to provide a silicon-based heterojunction solar cell and a manufacturing method thereof, which solve the problem of high contact resistance between the transparent conductive layer and the N-type amorphous or microcrystalline silicon layer of the silicon-based heterojunction solar cell.

[0004] To achieve the above object, the embodiments of the present invention provide a silicon-based heterojunction solar cell, including:

[0005] An N-type single-crystalline silicon wafer, the N-type single-crystalline silicon wafer having a first surface and a second surface disposed opposite to each other. On the first surface, a first intrinsic passivation layer, an N-type back surface field layer, a first transparent conductive layer, and a first electrode are sequentially disposed from inside to outside. On the second surface, a second intrinsic passivation layer, a P-type emitter layer, a second transparent conductive layer, and a second electrode are sequentially disposed from inside to outside;

[0006] Wherein, a transparent conductive film buffer layer is further disposed between the first transparent conductive layer and the N-type back surface field layer.

[0007] Optionally, the transparent conductive film buffer layer includes at least one of an indium tin oxide buffer layer, an aluminum-doped zinc oxide buffer layer, and a tungsten-doped indium oxide buffer layer.

[0008] Optionally, the transparent conductive film buffer layer is the aluminum-doped zinc oxide buffer layer formed by rapid annealing treatment.

[0009] Optionally, the transparent conductive film buffer layer is the indium tin oxide buffer layer formed by rapid annealing treatment or water vapor treatment.

[0010] Optionally, the transparent conductive film buffer layer is the tungsten-doped indium oxide buffer layer deposited by reactive plasma deposition technology.

[0011] Optionally, the first electrode is disposed on the first transparent conductive layer by screen printing, and the second electrode is disposed on the second transparent conductive layer by screen printing.

[0012] Optionally, the first intrinsic passivation layer is a first intrinsic amorphous or microcrystalline passivation layer, the N-type back surface field layer is an N-type amorphous or microcrystalline layer, the second intrinsic passivation layer is a second intrinsic amorphous or microcrystalline passivation layer, and the P-type emitter layer is a P-type amorphous or microcrystalline layer.

[0013] An embodiment of the present invention further provides a manufacturing method of a silicon-based heterojunction solar cell, including:

[0014] Providing an N-type monocrystalline silicon wafer, the N-type monocrystalline silicon wafer including a first surface and a second surface disposed opposite to each other;

[0015] Sequentially depositing a first intrinsic passivation layer, an N-type back surface field layer, a transparent conductive film buffer layer, and a first transparent conductive layer on the first surface of the N-type monocrystalline silicon wafer;

[0016] Sequentially depositing a second intrinsic passivation layer, a P-type emitter layer, and a second transparent conductive layer on the second surface of the N-type monocrystalline silicon wafer;

[0017] Disposing a first electrode on the first transparent conductive layer and a second electrode on the second transparent conductive layer, respectively.

[0018] Optionally, the sequentially depositing a first intrinsic passivation layer, an N-type back surface field layer, a transparent conductive film buffer layer, and a first transparent conductive layer on the first surface of the N-type monocrystalline silicon wafer specifically includes:

[0019] Depositing the transparent conductive film buffer layer on the N-type back surface field layer by magnetron sputtering.

[0020] Optionally, the transparent conductive film buffer layer is an aluminum-doped zinc oxide buffer layer or an indium tin oxide buffer layer;

[0021] The sequentially depositing a first intrinsic passivation layer, an N-type back surface field layer, a transparent conductive film buffer layer, and a first transparent conductive layer on the first surface of the N-type monocrystalline silicon wafer specifically includes:

[0022] After depositing the transparent conductive film buffer layer on the N-type back surface field layer and before depositing the first transparent conductive layer on the transparent conductive film buffer layer,

[0023] Performing rapid annealing treatment on the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer.

[0024] Optionally, the transparent conductive film buffer layer is an aluminum-doped zinc oxide buffer layer;

[0025] The rapid annealing treatment of the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer specifically includes:

[0026] Within 0.5 minutes to 5 minutes, raise the temperature of the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer to a first annealing temperature, and at the first annealing temperature, keep the transparent conductive film buffer layer warm for 0.2 to 3.5 minutes. After the heat preservation is completed, perform a cooling treatment on the transparent conductive film buffer layer. Among them, the first annealing temperature is greater than or equal to 450 °C and less than or equal to 600 °C.

[0027] Optionally, the transparent conductive film buffer layer is an indium tin oxide buffer layer;

[0028] The rapid annealing treatment of the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer specifically includes:

[0029] Within 0.5 minutes to 5 minutes, raise the temperature of the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer to a second annealing temperature, and at the second annealing temperature, keep the indium tin oxide buffer layer warm for 0.2 to 3.5 minutes. After the heat preservation is completed, perform a cooling treatment on the transparent conductive film buffer layer. Among them, the second annealing temperature is greater than or equal to 500 °C and less than or equal to 600 °C.

[0030] Optionally, the transparent conductive film buffer layer is an indium tin oxide buffer layer;

[0031] The deposition of a first intrinsic passivation layer, an N-type back surface field layer, a transparent conductive film buffer layer, and a first transparent conductive layer on the first surface of the N-type monocrystalline silicon wafer specifically includes:

[0032] After depositing the transparent conductive film buffer layer on the N-type back surface field layer and before depositing the first transparent conductive layer on the transparent conductive film buffer layer,

[0033] Perform a water vapor treatment on the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer through a constant temperature and humidity chamber.

[0034] Optionally, the step of performing a water vapor treatment on the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer through a constant temperature and humidity chamber includes:

[0035] Introduce water vapor into the constant temperature and humidity chamber where the indium tin oxide buffer layer is placed, so that the humidity in the constant temperature and humidity chamber is greater than or equal to 80% and less than or equal to 95%, and at a preset temperature, keep the indium tin oxide buffer layer warm for 3 minutes to 50 minutes. After the heat preservation is completed, perform a cooling treatment on the indium tin oxide buffer layer. Among them, the preset temperature is greater than or equal to 80 °C and less than or equal to 200 °C.

[0036] Optionally, the transparent conductive film buffer layer is an indium tungsten oxide buffer layer;

[0037] The steps of sequentially depositing a first intrinsic passivation layer, an N-type back surface field layer, a transparent conductive film buffer layer, and a first transparent conductive layer on the first surface of the N-type monocrystalline silicon wafer specifically include:

[0038] Deposit the transparent conductive film buffer layer on the N-type back surface field layer by reactive plasma deposition.

[0039] Optionally, the step of depositing the transparent conductive film buffer layer on the N-type back surface field layer by reactive plasma deposition includes:

[0040] Introduce argon, oxygen, and water vapor, and deposit the transparent conductive film buffer layer on the N-type back surface field layer by a plasma deposition device, wherein the flow rate ratio of argon to water vapor is greater than or equal to 1:1 and less than or equal to 100:1, the flow rate ratio of argon to oxygen is greater than or equal to 1:1 and less than or equal to 50:1, and the chamber pressure is greater than or equal to 0.1 Pascal and less than or equal to 1 Pascal.

[0041] Optionally, the steps of respectively providing a first electrode on the first transparent conductive layer and a second electrode on the second transparent conductive layer include:

[0042] Provide a first electrode on the first transparent conductive layer and a second electrode on the second transparent conductive layer respectively by screen printing.

[0043] Optionally, the first intrinsic passivation layer is a first intrinsic amorphous or microcrystalline passivation layer, the N-type back surface field layer is an N-type amorphous or microcrystalline layer, the second intrinsic passivation layer is a second intrinsic amorphous or microcrystalline passivation layer, and the P-type emitter layer is a P-type amorphous or microcrystalline layer.

[0044] One of the above technical solutions has the following advantages or beneficial effects:

[0045] In the embodiment of the present invention, a transparent conductive film buffer layer is provided between the first transparent conductive layer and the N-type back surface field layer, which can effectively reduce the contact resistance between the first transparent conductive layer and the N-type back surface field layer. Description of the Drawings

[0046] Figure 1 It is a schematic structural diagram of a silicon-based heterojunction solar cell provided by an embodiment of the present invention;

[0047] Figure 2 It is a schematic diagram of a manufacturing method of a silicon-based heterojunction solar cell provided by an embodiment of the present invention. Detailed implementation manners

[0048] To make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will be described in detail with reference to the accompanying drawings and specific embodiments.

[0049] As Figure 1 shown, an embodiment of the present invention provides a silicon-based heterojunction solar cell, including an N-type monocrystalline silicon wafer 1. The N-type monocrystalline silicon wafer 1 has a first surface and a second surface disposed opposite to each other. On the first surface, a first intrinsic passivation layer 2, an N-type back surface field layer 3, a first transparent conductive layer 4 and a first electrode 5 are sequentially disposed from inside to outside. On the second surface, a second intrinsic passivation layer 6, a P-type emitter layer 7, a second transparent conductive layer 8 and a second electrode 9 are sequentially disposed from inside to outside;

[0050] Wherein, a transparent conductive film buffer layer 10 is further disposed between the first transparent conductive layer 4 and the N-type back surface field layer 3.

[0051] In the embodiment of the present invention, the above-mentioned silicon-based heterojunction solar cell refers to a heterojunction solar cell based on a silicon substrate. The first transparent conductive layer 4 is a conductive layer made of a transparent conductive film material. The transparent conductive film has dual functions of optical transparency and conductivity, plays a key role in the collection of effective carriers, can reduce the reflection of light, and thus plays a good light trapping role. Among them, the transparent conductive thin film mainly includes a pure metal thin film and a metal compound thin film, and the metal compound thin film generally refers to oxides, nitrides or fluorides with transparent conductivity, etc.; among them, the oxide can also refer to a doped oxide and a mixed oxide; specifically, the first transparent conductive layer 4 can be made of materials such as indium tin oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide, selenium-doped fluorine oxide and boron-doped zinc oxide. Preferably, the first transparent conductive layer 4 can be an indium tin oxide transparent conductive layer; this is because indium tin oxide is an N-type degenerate semiconductor with tin and oxygen vacancies as donors, has good conductivity at room temperature, its intrinsic absorption is in the ultraviolet region, and has little influence on the visible light transmittance; it can be said that indium tin oxide has the best transparency and conductivity, high transparency and surface conductivity among metal oxide conductive substances. In addition, it also has good mechanical and chemical properties; it has good dimensional stability when heated, has excellent durability, and has excellent etching processability, etc.

[0052] For the first transparent conductive layer 4, the most commonly used preparation method at present is to deposit a first transparent conductive layer 4 on the N-type back surface field layer 3 by magnetron sputtering; there is still room for further optimization in terms of the material properties of the first transparent conductive layer 4 prepared by the conventional magnetron sputtering method. For example, for the first transparent conductive layer 4 prepared by this process method, its properties may not be very stable and in a microcrystalline phase state, that is, a mixed phase state of polycrystal and amorphous, which may lead to a large crystal change rate of the transparent conductive layer prepared in different batches, making it difficult to control. In addition, there are problems such as interface contact defects and high contact resistance between the first transparent conductive layer 4 and the N-type back surface field layer 3.

[0053] To solve the above problems, optimization can be carried out in various parameters of the deposition process method, subsequent annealing process, and early nucleation, etc. For example, before preparing the first transparent conductive layer 4, we can pre-deposit a transparent conductive film buffer layer 10 on the N-type back surface field layer 3, and through this buffer layer, a good ohmic contact can be formed at the interface of the first transparent conductive layer 4, thereby effectively reducing the interface contact resistance between the first transparent conductive layer 4 and the n surface of the battery. In addition, through this buffer layer, it is beneficial for the initial nucleation of the transparent conductive thin film, improving the growth quality of the subsequent thin film, and ultimately making the properties of the thin film more stable.

[0054] It should be noted that the above transparent conductive film buffer layer 10 can refer to a buffer film layer made of a transparent conductive thin film material; for example, the aforementioned indium tin oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide, selenium-doped fluorine oxide, and boron-doped zinc oxide and other transparent conductive thin film materials can all be used to prepare this buffer layer. Preferably, the thickness of the above transparent conductive film buffer layer 10 is less than 40 nm.

[0055] In this way, in the embodiment of the present invention, by providing a transparent conductive film buffer layer 10 between the first transparent conductive layer 4 and the N-type back surface field layer 3, the contact resistance between the first transparent conductive layer 4 and the N-type back surface field layer 3 can be effectively reduced.

[0056] Optionally, the first intrinsic passivation layer 2 is a first intrinsic amorphous or microcrystalline passivation layer, the N-type back surface field layer 3 is an N-type amorphous or microcrystalline layer, the second intrinsic passivation layer 6 is a second intrinsic amorphous or microcrystalline passivation layer, and the P-type emitter layer 7 is a P-type amorphous or microcrystalline layer. In this embodiment, the silicon-based heterojunction solar cell with this structure has higher cell efficiency and stability. Of course, the above silicon-based heterojunction solar cell can also be made of other structures, and this is not limited.

[0057] Optionally, the transparent conductive film buffer layer 10 includes at least one of an indium tin oxide buffer layer, an aluminum-doped zinc oxide buffer layer, and an indium tungsten oxide buffer layer.

[0058] Among them, indium tin oxide, aluminum-doped zinc oxide, and indium oxide doped with tungsten all have good electrical conductivity and good light transmittance. In this way, the transparent conductive film buffer layer 10 is at least one of an indium tin oxide buffer layer, an aluminum-doped zinc oxide buffer layer, and an indium oxide doped with tungsten buffer layer; this can result in a relatively high cell efficiency for the silicon-based heterojunction solar cell. It should be noted that by using different deposition process methods for the above three thin film buffer layers, the solar cell can also be optimized differently. For example, rapid annealing treatment of the aluminum-doped zinc oxide buffer layer, etc.

[0059] Optionally, the transparent conductive film buffer layer 10 is an aluminum-doped zinc oxide buffer layer formed by rapid annealing treatment.

[0060] In this embodiment, the above rapid annealing treatment can be as follows: after depositing an aluminum-doped zinc oxide buffer layer on the N-type back surface field layer 3, the aluminum-doped zinc oxide buffer layer is placed in a rapid annealing furnace and argon gas is introduced for protection, so that the temperature of the rapid annealing furnace rapidly rises from room temperature to the annealing temperature of 500 °C within 2 minutes, and after rising to 500 °C, it is kept at this temperature for 3 minutes. After the heat preservation is completed, the aluminum-doped zinc oxide buffer layer is cooled. Preferably, the annealing temperature can be 450 °C to 600 °C, the time for rising from room temperature to the annealing temperature can be 0.5 to 5 minutes, and the heat preservation time can be 0.2 to 3.5 minutes. Of course, the aluminum-doped zinc oxide buffer layer can also be rapidly annealed according to other rapid annealing conditions, and no limitation is imposed on this.

[0061] In this way, for the aluminum-doped zinc oxide buffer layer that has experienced short-time high-temperature annealing, the properties of the amorphous silicon are not damaged, and the deposited aluminum-doped zinc oxide buffer layer is rapidly crystallized, reducing the defects in the aluminum-doped zinc oxide material body. And through the aluminum-doped zinc oxide seed layer, the first transparent conductive layer 4 grown at room temperature has relatively good crystallinity, few defects in the material body, and high process controllability and repeatability.

[0062] Optionally, the transparent conductive film buffer layer 10 is an indium tin oxide buffer layer formed by rapid annealing treatment or water vapor treatment.

[0063] Among them, for the indium tin oxide buffer layer formed by the above rapid annealing treatment, its steps and principles are the same as those of the aluminum-doped zinc oxide buffer layer formed by rapid annealing treatment above. To avoid repetition, they will not be elaborated here.

[0064] Preferably, the rapid annealing conditions for the indium tin oxide buffer layer can be: the annealing temperature can be 500 °C to 600 °C, the time for rising from room temperature to the annealing temperature can be 0.5 to 5 minutes, and the heat preservation time can be 0.2 to 3.5 minutes. Of course, the aluminum-doped zinc oxide buffer layer can also be rapidly annealed according to other annealing conditions, and no limitation is imposed on this.

[0065] In this way, for the indium tin oxide buffer layer subjected to short-time high-temperature annealing, the properties of the amorphous silicon are not damaged, and the deposited indium tin oxide buffer layer is rapidly crystallized, reducing the defects in the indium tin oxide buffer layer material. And through this seed layer of the indium tin oxide buffer layer, the first transparent conductive layer 4 grown at room temperature has relatively good crystallinity, few defects in the material, and high process controllability and repeatability.

[0066] In addition, the indium tin oxide buffer layer formed by water vapor treatment can be that after depositing the indium tin oxide buffer layer on the N-type back surface field layer 3, the indium tin oxide buffer layer is placed in a constant temperature and humidity chamber, water vapor is introduced, the humidity in the constant temperature and humidity chamber is between 80% and 95%, the temperature of the constant temperature and humidity chamber is set to 80 degrees Celsius to 200 degrees Celsius. After the indium tin oxide buffer layer is heated to the set temperature, it is kept warm for 3 minutes to 50 minutes, and then cooled after the heat preservation is completed. Of course, the temperature of the constant temperature and humidity chamber and the heat preservation time can also be other values, and no specific limitations are imposed on this.

[0067] In this way, for the indium tin oxide buffer layer treated with water vapor, the degree of crystallization tends to transform into an amorphous phase. And growing the first transparent conductive layer 4 on this amorphous-phase indium tin oxide buffer layer can make the newly grown first transparent conductive layer 4 amorphous, thus making the properties of the first transparent conductive layer 4 more stable.

[0068] Preferably, the thickness of the indium tin oxide buffer layer in this embodiment can be 1 nanometer to 40 nanometers. Of course, it can also be other thicknesses, and no limitations are imposed on this.

[0069] Optionally, the transparent conductive film buffer layer 10 is a tungsten-doped indium oxide buffer layer formed by reactive plasma deposition technology.

[0070] Among them, the tungsten-doped indium oxide buffer layer formed by reactive plasma deposition technology can be that by using a plasma deposition device, argon, oxygen and water vapor are introduced, and a layer of tungsten-doped indium oxide buffer layer is deposited on the N-type back surface field layer 3; the flow ratio of argon to water vapor can be 20:1, the flow ratio of argon to oxygen is 30:1, and the chamber pressure is kept at 0.3 pascal. Of course, it can also be other reactive plasma deposition conditions, and no limitations are imposed on this.

[0071] In this way, for the tungsten-doped indium oxide buffer layer formed by reactive plasma deposition technology, its degree of crystallization is relatively high, which is equivalent to providing a seed layer for the subsequent preparation of the first transparent conductive layer 4. And the first transparent conductive layer 4 grown on this tungsten-doped indium oxide seed layer has relatively good crystallinity, few defects in the material, and high process controllability and repeatability.

[0072] Optionally, the first electrode 5 is disposed on the first transparent conductive layer 4 by screen printing, and the second electrode 9 is disposed on the second transparent conductive layer 8 by screen printing.

[0073] In this way, by disposing the first electrode 5 and the second electrode 9 by screen printing, there are advantages such as flexible design, low cost, and mass production. Of course, the first electrode 5 and the second electrode 9 can also be disposed by other means, and this is not limited.

[0074] Such as Figure 2 shown, an embodiment of the present invention further provides a manufacturing method of a silicon-based heterojunction solar cell, which is applied to a silicon-based heterojunction solar cell as Figure 1 shown, and the above method includes:

[0075] S1. Provide an N-type single-crystalline silicon wafer 1, and the N-type single-crystalline silicon wafer 1 includes a first surface and a second surface disposed opposite to each other.

[0076] Among them, the above N-type single-crystalline silicon wafer 1 is the substrate of the silicon-based heterojunction solar cell, mainly serving as the carrier of the silicon-based heterojunction solar cell. Preferably, the thickness of the N-type single-crystalline silicon wafer 1 can be 200 microns; of course, the N-type single-crystalline silicon wafer 1 can also be of other thicknesses, and this is not limited.

[0077] S2. Sequentially deposit a first intrinsic passivation layer 2, an N-type back surface field layer 3, a transparent conductive film buffer layer 10, and a first transparent conductive layer 4 on the first surface of the N-type single-crystalline silicon wafer 1.

[0078] Among them, the above transparent conductive film buffer layer 10 refers to a buffer layer made of a transparent conductive film material, and its specific description has been elaborated in detail in the first embodiment and will not be repeated here. Among them, the first intrinsic passivation layer 2 and the N-type back surface field layer 3 can be deposited by chemical vapor deposition.

[0079] It should be noted that the transparent conductive film buffer layer 10 is a buffer layer deposited on the N-type back surface field layer 3 after the N-type back surface field layer 3 is deposited. Preferably, the transparent conductive film buffer layer 10 can be deposited by magnetron sputtering. Of course, the transparent conductive film buffer layer 10 can also be deposited by other means, such as chemical vapor deposition, etc., and this is not limited.

[0080] Optionally, sequentially depositing the first intrinsic passivation layer 2, the N-type back surface field layer 3, the transparent conductive film buffer layer 10, and the first transparent conductive layer 4 on the first surface of the N-type single-crystalline silicon wafer 1 specifically includes:

[0081] Deposit the transparent conductive film buffer layer 10 on the N-type back surface field layer 3 by magnetron sputtering.

[0082] In this embodiment, depositing the transparent conductive film buffer layer 10 on the N-type back surface layer 3 by magnetron sputtering may specifically be: introducing argon and oxygen, and depositing a transparent conductive film buffer layer 10 on the N-type back surface layer 3 through a magnetron sputtering device; wherein, the gas flow ratio of argon to oxygen may be from 1:1 to 100:1, the chamber pressure may be maintained at 0.1 to 10 pascals, and the power density of the power supply may be 0.2 to 3 watts per square centimeter. Of course, the transparent conductive film buffer layer 10 may also be deposited according to other magnetron sputtering conditions; for example, the gas flow ratio of argon to oxygen may also be from 1:1 to 10:1, and the chamber pressure may also be maintained at 0.1 to 1 pascals, and no limitation is made thereto.

[0083] In this way, the transparent conductive film buffer layer 10 is deposited on the N-type back surface layer 3 by magnetron sputtering; it can have a relatively fast deposition rate, cause less loss to the film layer, and the obtained thin film has a relatively high purity; in addition, it also has good process repeatability.

[0084] Optionally, the transparent conductive film buffer layer 10 is an aluminum-doped zinc oxide buffer layer or an indium tin oxide buffer layer;

[0085] Depositing a first intrinsic passivation layer 2, an N-type back surface layer 3, a transparent conductive film buffer layer 10, and a first transparent conductive layer 4 in sequence on the first surface of the N-type single crystal silicon wafer 1 specifically includes:

[0086] After depositing the transparent conductive film buffer layer 10 on the N-type back surface layer 3 and before depositing the first transparent conductive layer 4 on the transparent conductive film buffer layer 10,

[0087] Performing a rapid annealing treatment on the N-type single crystal silicon wafer 1 deposited with the transparent conductive film buffer layer 10. The detailed description of this embodiment has been elaborated in the first embodiment in detail. To avoid repetition, it will not be elaborated here.

[0088] In this way, for the transparent conductive film buffer layer 10 that has experienced short-time high-temperature annealing, the properties of the amorphous silicon are not damaged, and the deposited transparent conductive film buffer layer 10 is rapidly crystallized, reducing the defects in the body of the transparent conductive film buffer layer 10 material. And through this seed layer of the transparent conductive film buffer layer 10, the first transparent conductive layer 4 grown at room temperature has relatively good crystallinity, few defects in the material body, and relatively high process controllability and repeatability.

[0089] Optionally, the transparent conductive film buffer layer 10 is an aluminum-doped zinc oxide buffer layer;

[0090] Performing a rapid annealing treatment on the N-type single crystal silicon wafer 1 deposited with the transparent conductive film buffer layer 10 specifically includes:

[0091] Within 0.5 minute to 5 minutes, raise the temperature of the N-type monocrystalline silicon wafer 1 deposited with the transparent conductive film buffer layer 10 to the first annealing temperature, and at the first annealing temperature, keep the transparent conductive film buffer layer 10 warm for 0.2 to 3.5 minutes. After the warming is completed, perform a cooling treatment on the transparent conductive film buffer layer 10, wherein the first annealing temperature is 450 degrees Celsius to 600 degrees Celsius. To better illustrate this embodiment, for comparison by way of example, the following is a reference comparative example of manufacturing a silicon-based heterojunction solar cell using an existing manufacturing method: First step, sequentially deposit a first intrinsic passivation layer 2 and an N-type back surface field layer 3 on the first surface of the N-type monocrystalline silicon wafer 1, and sequentially deposit a second intrinsic passivation layer 6 and a P-type emitter layer 7 on the second surface of the N-type monocrystalline silicon wafer 1; wherein, the deposition conditions of the first intrinsic amorphous or microcrystalline silicon passivation layer 2 and the second intrinsic amorphous or microcrystalline silicon passivation layer 6 are: the power of the power supply is 330 watts, the gas flow ratio of hydrogen to silane is 3:1, the pressure is 0.75 pascal, and the substrate temperature during deposition is 215 degrees Celsius; the deposition conditions of the N-type back surface field layer 3 are: the power of the power supply is 400 watts, the gas flow ratio of hydrogen to silane is 4:1, the gas flow ratio of phosphine to silane is 3:100, the pressure is 0.65 pascal, and the temperature of the substrate during deposition is 215 °C; wherein the deposition conditions of the P-type emitter layer 7 are: the power of the power supply is 230 W, the gas flow ratio of hydrogen to silane is 3:1, the gas flow ratio of borane to silane is 3:97, the pressure is 0.35 pascal, and the temperature of the substrate during deposition is 215 degrees Celsius. Second step, introduce argon and oxygen at room temperature, set the gas flow ratio of argon to oxygen at 50:1, keep the chamber pressure at 1.2 pascals, turn on the sputtering power supply, the power density of the power supply is 2 watts per square centimeter, and use magnetron sputtering to deposit a first transparent conductive layer 4 and a second transparent conductive layer 8 on the N-type amorphous or microcrystalline silicon layer 3 and the P-type amorphous or microcrystalline silicon layer 7 respectively, wherein both the first transparent conductive layer 4 and the second transparent conductive layer 8 are indium tin oxide transparent conductive layers. Finally, screen-print the first electrode and the second electrode on the first transparent conductive layer 4 and the second transparent conductive layer 8 respectively. In addition, another complete example adopting this embodiment is: The first step is the same as the first step in the reference comparative example and will not be elaborated here. Second step, introduce argon and oxygen at room temperature, set the gas flow ratio of argon to oxygen at 50:1, keep the chamber pressure at 1.2 pascals, the power density of the power supply is 2 watts per square centimeter, and use magnetron sputtering to deposit a second transparent conductive layer 8 on the P-type amorphous or microcrystalline silicon layer 7, with a thickness of 80 nanometers, and the second transparent conductive layer 8 is an indium tin oxide transparent conductive layer. Third step, introduce argon and oxygen, and deposit an aluminum-doped zinc oxide buffer layer on the N-type back surface field layer 3 through a magnetron sputtering device; wherein, the gas flow ratio of argon to oxygen is 10:1, the chamber pressure can be kept at 0.8 pascals, the power density of the power supply can be 3 watts per square centimeter, and the thickness of the aluminum-doped zinc oxide buffer layer is 20 nanometers.After that, the aluminum-doped zinc oxide buffer layer is placed in a rapid annealing furnace, and argon is introduced for protection, so that the temperature of the rapid annealing furnace rises rapidly from room temperature to the first annealing temperature of 500 °C within 2 minutes. After the temperature rises to 500 °C, it is kept warm for 3 minutes. After the heat preservation is completed, the aluminum-doped zinc oxide buffer layer is cooled. In the fourth step, argon and oxygen are introduced at room temperature, the gas flow ratio of argon to oxygen is set at 20:1, the chamber pressure is maintained at 0.8 Pascal, and the power density of the power supply is 4 watts per square centimeter. The first transparent conductive layer with a thickness of 60 nm is deposited on the aluminum-doped zinc oxide buffer layer by magnetron sputtering. The first transparent conductive layer is an indium tin oxide transparent conductive layer. In the fifth step, the first electrode 5 and the second electrode 9 are screen-printed on the first transparent conductive layer 4 and the second transparent conductive layer 8 respectively. Here, taking this reference comparative example as a reference, through detection, it can be known that for the battery obtained by using the complete example of this embodiment, its open circuit voltage is increased by 0.50%, the short circuit current is increased by 2.10%, the fill factor is increased by 1.90%, and the battery efficiency is increased by 3.44%.

[0092] In this embodiment, the process of rapid annealing treatment of the aluminum-doped zinc oxide buffer layer can be further optimized. For the aluminum-doped zinc oxide buffer layer undergoing short-time high-temperature annealing, the properties of amorphous silicon are not damaged, and the deposited aluminum-doped zinc oxide buffer layer is rapidly crystallized, reducing the defects in the aluminum-doped zinc oxide material body. Through this seed layer of the aluminum-doped zinc oxide buffer layer, the first transparent conductive layer 4 grown at room temperature has good crystallinity, few defects in the material body, and high process controllability and repeatability.

[0093] Optionally, the transparent conductive film buffer layer 10 is an indium tin oxide buffer layer;

[0094] The rapid annealing treatment of the N-type monocrystalline silicon wafer 1 deposited with the transparent conductive film buffer layer 10 specifically includes:

[0095] Within 0.5 minutes to 5 minutes, the temperature of the N-type monocrystalline silicon wafer 1 deposited with the transparent conductive film buffer layer 10 is raised to the second annealing temperature, and at the second annealing temperature, the indium tin oxide buffer layer is kept warm for 0.2 to 3.5 minutes. After the heat preservation is completed, the transparent conductive film buffer layer 10 is cooled. Among them, the second annealing temperature is greater than or equal to 500 °C and less than or equal to 600 °C.

[0096] To better illustrate this embodiment, a complete example is given: Since the steps of the first, second, and fifth steps in this example are the same as those in the complete example given in the previous embodiment, and only the thickness of the first transparent conductive layer 4 in the fourth step is changed to 45 nanometers, and other conditions remain unchanged, these steps will not be elaborated here, and only the third step will be described. Third step: Deposit an indium tin oxide buffer layer on the N-type back surface layer 3 through a magnetron sputtering device; wherein, the gas flow ratio of argon to oxygen is 3:1, the chamber pressure is maintained at 0.7 pascals, the power density of the power supply is 0.3 watts per square centimeter, and the thickness of the indium tin oxide buffer layer is 35 nanometers. Then, put the indium tin oxide buffer layer into a rapid annealing furnace and introduce argon for protection, so that the temperature of the rapid annealing furnace rapidly rises from room temperature to the second annealing temperature of 530 degrees Celsius within 2 minutes, and after rising to 530 degrees Celsius, keep it warm for 2 minutes. After the heat preservation is completed, cool the indium tin oxide buffer layer. Here, still taking the previously listed reference comparative example as a reference, through detection, it can be known that for the battery obtained by using the complete example of this embodiment, its open circuit voltage has increased by 0.70%, the short circuit current has increased by 1.55%, the fill factor has increased by 1.80%, and the battery efficiency has increased by 3.08%.

[0097] This embodiment can further optimize the process of rapid annealing treatment of the indium tin oxide buffer layer. For the indium tin oxide buffer layer that has experienced short-time high-temperature annealing, the properties of the amorphous silicon have not been damaged, and the deposited indium tin oxide buffer layer is rapidly crystallized, reducing the defects in the indium tin oxide buffer layer material body. And through this seed layer of the indium tin oxide buffer layer, the first transparent conductive layer 4 grown at room temperature has better crystallinity, fewer defects in the material body, and higher process controllability and repeatability.

[0098] Optionally, the transparent conductive film buffer layer 10 is an indium tin oxide buffer layer;

[0099] Deposit a first intrinsic passivation layer 2, an N-type back surface layer 3, a transparent conductive film buffer layer 10, and a first transparent conductive layer 4 on the first surface of the N-type single crystal silicon wafer 1 in sequence, specifically including:

[0100] After depositing the transparent conductive film buffer layer 10 on the N-type back surface layer 3 and before depositing the first transparent conductive layer 4 on the transparent conductive film buffer layer 10,

[0101] Through a constant temperature and humidity chamber, perform water vapor treatment on the N-type single crystal silicon wafer 1 on which the transparent conductive film buffer layer 10 is deposited.

[0102] In this embodiment, the water vapor treatment of the N-type monocrystalline silicon wafer 1 with the deposited transparent conductive film buffer layer 10 mainly refers to the water vapor treatment of the transparent conductive film buffer layer 10. This is because the transparent conductive film buffer layer 10 is deposited on the N-type back surface field layer 3 of the N-type monocrystalline silicon wafer 1, and they are an integral whole.

[0103] In this way, for the transparent conductive film buffer layer 10 after water vapor treatment, the degree of crystallization tends to transform into an amorphous phase. Continuing to grow the first transparent conductive layer 4 on this amorphous-phase transparent conductive film buffer layer 10 can make the newly grown first transparent conductive layer 4 amorphous, thereby making the properties of the first transparent conductive layer 4 more stable.

[0104] Optionally, the step of performing water vapor treatment on the N-type monocrystalline silicon wafer 1 with the deposited transparent conductive film buffer layer 10 through a thermostatic and humidistatic chamber includes:

[0105] Introducing water vapor into the thermostatic and humidistatic chamber with an indium tin oxide buffer layer, making the humidity in the thermostatic and humidistatic chamber greater than or equal to 80% and less than or equal to 95%, and maintaining the indium tin oxide buffer layer at a preset temperature for 3 minutes to 50 minutes. After the heat preservation is completed, the indium tin oxide buffer layer is cooled. Among them, the preset temperature is greater than or equal to 80 °C and less than or equal to 200 °C.

[0106] To better illustrate this embodiment, a complete example is given: Since the steps of the first, second, and fifth steps in this example are the same as those in the complete example given in the previous embodiment, and only the thickness of the first transparent conductive layer is changed to 65 nanometers in the fourth step while other conditions remain unchanged, these steps will not be elaborated here, and only the third step will be described. Step 3: Depositing a layer of indium tin oxide buffer layer on the N-type back surface field layer 3 through a magnetron sputtering device; among them, the gas flow ratio of argon to oxygen is 2:1, the chamber pressure is maintained at 0.3 pascals, the power density of the power supply is 0.3 watts per square centimeter, and the thickness of the indium tin oxide buffer layer is 15 nanometers. Then, water vapor is introduced into the thermostatic and humidistatic chamber with the indium tin oxide buffer layer, making the humidity in the thermostatic and humidistatic chamber body 90%, and maintaining the indium tin oxide buffer layer at a preset temperature of 130 °C for 20 minutes. After the heat preservation is completed, the indium tin oxide buffer layer is cooled. Here, still taking the previously listed reference comparative example as a reference, through detection, it can be known that for the battery obtained by using the complete example of this embodiment, its open circuit voltage is increased by 0.50%, the short circuit current is increased by 3.00%, the fill factor is increased by 1.81%, and the battery efficiency is increased by 3.94%. Of course, water vapor treatment can also be performed according to other water vapor treatment parameters, and there is no limitation on this.

[0107] In this embodiment, the indium tin oxide buffer layer after water vapor treatment has a crystallization degree tending to transform into an amorphous phase. Continuing to grow the first transparent conductive layer 4 on this amorphous indium tin oxide buffer layer can make the newly grown first transparent conductive layer 4 amorphous, thus making the properties of the first transparent conductive layer 4 more stable.

[0108] Optionally, the transparent conductive film buffer layer 10 is a tungsten-doped indium oxide buffer layer;

[0109] The first intrinsic passivation layer 2, the N-type back surface field layer 3, the transparent conductive film buffer layer 10, and the first transparent conductive layer 4 are sequentially deposited on the first surface of the N-type monocrystalline silicon wafer 1, specifically including:

[0110] The transparent conductive film buffer layer 10 is deposited on the N-type back surface field layer 3 by reactive plasma deposition.

[0111] The reactive plasma deposition method is a chemical vapor deposition method. Its principle can be that under the action of a high-frequency or direct current electric field, the source gas is ionized to form a plasma, the substrate is immersed in the plasma or placed below the plasma, and the reaction particles adsorbed on the substrate surface are bombarded by high-energy electrons, the bonding is broken to become active particles, and a solid film is formed by chemical reaction.

[0112] In this way, the transparent conductive film buffer layer 10 formed by deposition through the reactive plasma deposition technology has a high crystallization degree, which is equivalent to providing a seed layer for the subsequent preparation of the first transparent conductive layer 4. The first transparent conductive layer 4 continuously grown on this tungsten-doped indium oxide seed layer has good crystallinity, few defects in the material body, and high process controllability and repeatability.

[0113] Optionally, the step of depositing the transparent conductive film buffer layer 10 on the N-type back surface field layer 3 by reactive plasma deposition includes:

[0114] Argon, oxygen, and water vapor are introduced, and the transparent conductive film buffer layer 10 is deposited on the N-type back surface field layer 3 by a plasma deposition device. Among them, the flow ratio of argon to water vapor is greater than or equal to 1:1 and less than or equal to 100:1, the flow ratio of argon to oxygen is greater than or equal to 1:1 and less than or equal to 50:1, and the chamber pressure is greater than or equal to 0.1 Pascal and less than or equal to 1 Pascal.

[0115] To better illustrate this embodiment, a complete example is given: Since the steps of the first, second, and fifth steps in this example are the same as those in the complete example given in the previous embodiment, and in the fourth step, only the thickness of the first transparent conductive layer is changed to 75 nanometers while other conditions remain unchanged, these steps will not be elaborated here, and only the third step will be described. Step 3: Introduce argon, oxygen, and water vapor, and use a plasma deposition device to deposit an indium tungsten oxide buffer layer on the N-type back surface layer 3. Among them, the flow rate ratio of argon to water vapor is 20:1, the flow rate ratio of argon to oxygen is 30:1, the chamber pressure is 0.3 pascal, and the thickness of the indium tungsten oxide buffer layer is 5 nanometers. Here, still taking the previously listed reference comparative example as a reference, through detection, it can be known that for the battery obtained by using the complete example of this embodiment, its open circuit voltage has increased by 0.50%, the short circuit current has increased by 0.7%, the fill factor has increased by 1.90%, and the battery efficiency has increased by 3.13%. Among them, the chamber pressure is the pressure of the deposition chamber.

[0116] In this embodiment, for the indium tin oxide buffer layer treated with water vapor, the degree of crystallization tends to transform into an amorphous phase, and growing the first transparent conductive layer 4 on this amorphous indium tin oxide buffer layer can make the newly grown first transparent conductive layer 4 amorphous, thereby making the properties of the first transparent conductive layer 4 more stable.

[0117] S3. Deposit a second intrinsic passivation layer 6, a P-type emitter layer 7, and a second transparent conductive layer 8 on the second surface of the N-type monocrystalline silicon wafer 1 in sequence.

[0118] Among them, the second intrinsic passivation layer 6, the P-type emitter layer 7, and the second transparent conductive layer 8 are all film layers on the P side, that is, the second surface, of the silicon-based heterojunction battery. The deposition conditions of the second intrinsic passivation layer 6 can be the same as those of the first intrinsic passivation layer 2, and the description in S1 can be referred to. The deposition conditions of the P-type emitter layer 7 can be: the power supply power is 230W, the gas flow rate ratio of hydrogen to silane is 3:1, the gas flow rate ratio of borane to silane is 3:97, the pressure is 0.35 pascal, and the temperature of the substrate during deposition is 215°C. The second transparent conductive layer 8 can be deposited on the P-type emitter layer 7 by magnetron sputtering; preferably, the thickness of the second transparent conductive layer 8 can be 80 nanometers. Of course, the above film layers can also be deposited by other methods, and no limitation is made thereto.

[0119] Optionally, the first intrinsic passivation layer 2 is a first intrinsic amorphous or microcrystalline passivation layer, the N-type back surface field layer 3 is an N-type amorphous or microcrystalline layer, the second intrinsic passivation layer 6 is a second intrinsic amorphous or microcrystalline passivation layer, and the P-type emitter layer 7 is a P-type amorphous or microcrystalline layer. In this embodiment, the silicon-based heterojunction solar cell with such a structure has relatively high cell efficiency and stability, and is relatively convenient to manufacture. Of course, the above-mentioned silicon-based heterojunction solar cell can also be made with other structures, and this is not limited.

[0120] S4. A first electrode 5 is respectively disposed on the first transparent conductive layer 4 and a second electrode 9 is disposed on the second transparent conductive layer 8.

[0121] Wherein, after the first electrode 5 and the second electrode 9 are disposed, a silicon-based heterojunction solar cell is manufactured.

[0122] Optionally, the steps of respectively disposing the first electrode 5 on the first transparent conductive layer 4 and the second electrode 9 on the second transparent conductive layer 8 include:

[0123] The first electrode 5 is respectively disposed on the first transparent conductive layer 4 and the second electrode 9 is disposed on the second transparent conductive layer 8 by screen printing.

[0124] The detailed description of this embodiment has been elaborated in the first embodiment. To avoid repetition, it will not be described herein again.

[0125] In this way, by disposing the first electrode 5 and the second electrode 9 by screen printing, it has the advantages of flexible design, low cost, and batch production. Of course, in addition to the screen printing method, the first electrode 5 and the second electrode 9 can also be deposited by physical vapor deposition methods, such as magnetron sputtering, etc., and this is not limited.

[0126] In the embodiment of the present invention, a transparent conductive film buffer layer 10 is deposited and formed between the first transparent conductive layer 4 and the N-type back surface field layer 3; in this way, the contact resistance between the first transparent conductive layer 4 and the N-type back surface field layer 3 can be effectively reduced.

[0127] The above is the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle described in the present invention, several improvements and refinements can still be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A silicon-based heterojunction solar cell, characterized in that, It includes an N-type monocrystalline silicon wafer, the N-type monocrystalline silicon wafer having a first surface and a second surface disposed opposite to each other. On the first surface, a first intrinsic passivation layer, an N-type back surface field layer, a first transparent conductive layer, and a first electrode are sequentially disposed from inside to outside. On the second surface, a second intrinsic passivation layer, a P-type emitter layer, a second transparent conductive layer, and a second electrode are sequentially disposed from inside to outside; Wherein, a transparent conductive film buffer layer is further disposed between the first transparent conductive layer and the N-type back surface field layer; The transparent conductive film buffer layer is an indium tin oxide buffer layer or an aluminum-doped indium oxide buffer layer; The transparent conductive film buffer layer is formed by rapid annealing treatment; The first electrode is disposed on the first transparent conductive layer by screen printing, and the second electrode is disposed on the second transparent conductive layer by screen printing; The first intrinsic passivation layer is a first intrinsic amorphous or microcrystalline passivation layer, the N-type back surface field layer is an N-type amorphous or microcrystalline layer, the second intrinsic passivation layer is a second intrinsic amorphous or microcrystalline passivation layer, and the P-type emitter layer is a P-type amorphous or microcrystalline layer; The deposition of the first intrinsic passivation layer, the N-type back surface field layer, the transparent conductive film buffer layer, and the first transparent conductive layer on the first surface of the N-type monocrystalline silicon wafer specifically includes: Depositing the transparent conductive film buffer layer on the N-type back surface field layer by magnetron sputtering; The transparent conductive film buffer layer is an aluminum-doped zinc oxide buffer layer or an indium tin oxide buffer layer; After depositing the transparent conductive film buffer layer on the N-type back surface field layer, before depositing the first transparent conductive layer on the transparent conductive film buffer layer, performing rapid annealing treatment on the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer; The rapid annealing treatment of the N-type monocrystalline silicon wafer deposited with the aluminum-doped zinc oxide buffer layer specifically includes: Within 0.5 minutes to 5 minutes, raising the temperature of the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer to a first annealing temperature, and at the first annealing temperature, keeping the transparent conductive film buffer layer warm for 0.2 to 3.5 minutes. After the heat preservation is completed, cooling treatment is performed on the transparent conductive film buffer layer, wherein the first annealing temperature is greater than or equal to 450 degrees Celsius and less than or equal to 600 degrees Celsius; The rapid annealing treatment of the N-type monocrystalline silicon wafer deposited with the indium tin oxide buffer layer specifically includes: Within 0.5 minutes to 5 minutes, raising the temperature of the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer to a second annealing temperature, and at the second annealing temperature, keeping the indium tin oxide buffer layer warm for 0.2 to 3.5 minutes. After the heat preservation is completed, cooling treatment is performed on the transparent conductive film buffer layer, wherein the second annealing temperature is greater than or equal to 500 degrees Celsius and less than or equal to 600 degrees Celsius.

2. A manufacturing method of a silicon-based heterojunction solar cell, characterized in that, It includes: Providing an N-type monocrystalline silicon wafer, the N-type monocrystalline silicon wafer including a first surface and a second surface disposed opposite to each other; Sequentially depositing a first intrinsic passivation layer, an N-type back surface field layer, a transparent conductive film buffer layer, and a first transparent conductive layer on the first surface of the N-type monocrystalline silicon wafer; A second intrinsic passivation layer, a P-type emitter layer, and a second transparent conductive layer are sequentially deposited on the second surface of the N-type monocrystalline silicon wafer; A first electrode is disposed on the first transparent conductive layer and a second electrode is disposed on the second transparent conductive layer, respectively; The steps of sequentially depositing a first intrinsic passivation layer, an N-type back surface field layer, a transparent conductive film buffer layer, and a first transparent conductive layer on the first surface of the N-type monocrystalline silicon wafer specifically include: Depositing the transparent conductive film buffer layer on the N-type back surface field layer by means of magnetron sputtering; The transparent conductive film buffer layer is an aluminum-doped zinc oxide buffer layer or an indium tin oxide buffer layer; After depositing the transparent conductive film buffer layer on the N-type back surface field layer, and before depositing the first transparent conductive layer on the transparent conductive film buffer layer, a rapid annealing treatment is performed on the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer; The rapid annealing treatment of the N-type monocrystalline silicon wafer deposited with the aluminum-doped zinc oxide buffer layer specifically includes: Within 0.5 minutes to 5 minutes, the temperature of the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer is raised to a first annealing temperature, and at the first annealing temperature, the transparent conductive film buffer layer is kept warm for 0.2 to 3.5 minutes. After the heat preservation is completed, the transparent conductive film buffer layer is cooled, wherein the first annealing temperature is greater than or equal to 450 degrees Celsius and less than or equal to 600 degrees Celsius; The rapid annealing treatment of the N-type monocrystalline silicon wafer deposited with the indium tin oxide buffer layer specifically includes: Within 0.5 minutes to 5 minutes, the temperature of the N-type monocrystalline silicon wafer deposited with the transparent conductive film buffer layer is raised to a second annealing temperature, and at the second annealing temperature, the indium tin oxide buffer layer is kept warm for 0.2 to 3.5 minutes. After the heat preservation is completed, the transparent conductive film buffer layer is cooled, wherein the second annealing temperature is greater than or equal to 500 degrees Celsius and less than or equal to 600 degrees Celsius.

3. The manufacturing method of the silicon-based heterojunction solar cell according to claim 2, wherein The steps of respectively disposing a first electrode on the first transparent conductive layer and a second electrode on the second transparent conductive layer include: By means of screen printing, a first electrode is respectively disposed on the first transparent conductive layer and a second electrode is disposed on the second transparent conductive layer.

4. The manufacturing method of the silicon-based heterojunction solar cell according to claim 3, characterized in that, The first intrinsic passivation layer is a first intrinsic amorphous or microcrystalline passivation layer, the N-type back surface field layer is an N-type amorphous or microcrystalline layer, the second intrinsic passivation layer is a second intrinsic amorphous or microcrystalline passivation layer, and the P-type emitter layer is a P-type amorphous or microcrystalline layer.

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