Pixels and display devices

Abstract

Disclosed are pixels and a display device. Each of the pixels of the display device includes: a light emitting portion including a first light emitting device connected in a forward direction between a first electrode and a second electrode and a second light emitting device connected in a reverse direction between the first electrode and the second electrode; a pixel circuit configured to: receive a data voltage in synchronization with a scan signal, generate a driving current based on the data voltage, and output the driving current to a first node; and a light emitting circuit configured to: be controlled by a control signal, provide the driving current to the first light emitting device during a first emission time period, and provide the driving current to the second light emitting device during a second emission time period.

Description

[0001] This application claims the benefit of and priority to Korean Patent Application No. 10-2018-0119300 filed on October 5, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] One or more embodiments of the present disclosure relate to a pixel and a display device, and more particularly, to a pixel and a display device each including a micro light emitting diode (LED). Background Art

[0003] Light-emitting devices such as light-emitting diodes (LEDs) have high light conversion efficiency, very low energy consumption and semi-permanent life, and are environmentally friendly. In order to use LEDs in lighting devices or display devices, it is necessary to connect the LEDs between a pair of electrodes that can supply power to the LEDs. The LEDs can be connected to the electrodes in various forms and methods, such as by directly growing the LEDs on a pair of electrodes and growing the LEDs separately and then arranging the LEDs on the electrodes. In the latter case, in the case where the LEDs are nano-sized or micron-sized LEDs, it is difficult to arrange the LEDs on the electrodes. In addition, since the LEDs have polarity, it is difficult to arrange the LEDs between the electrodes according to the polarity. Summary of the invention

[0004] One or more embodiments of the present disclosure include a display device capable of emitting light with uniform brightness in a pixel unit even when a ratio of independently manufactured micro light emitting diodes (LEDs) disposed between a pair of electrodes in a forward direction is uneven.

[0005] One or more embodiments include pixels capable of emitting light from a micro LED disposed between a pair of electrodes in a reverse direction and a micro LED disposed between a pair of electrodes in a forward direction.

[0006] Additional aspects of the disclosure will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the exemplary embodiments disclosed herein.

[0007] According to one or more embodiments, a display device includes: a display unit including a plurality of pixels arranged along a first direction and a second direction; a scan driver configured to send scan signals to the plurality of pixels through a plurality of scan lines; a data driver configured to send data voltages to the plurality of pixels through a plurality of data lines; a control driver configured to send control signals to the plurality of pixels through control lines; and a voltage generator configured to supply a first drive voltage and a second drive voltage to the plurality of pixels through a first power line and a second power line, respectively.

[0008] Each of the plurality of pixels includes: a light emitting portion including a first light emitting device connected in a forward direction between a first electrode and a second electrode and a second light emitting device connected in a reverse direction between the first electrode and the second electrode; a pixel circuit configured to: receive a corresponding data voltage among the data voltages in synchronization with a corresponding scan signal among the scan signals, generate a driving current based on the corresponding data voltage, and output the driving current to a first node; and a light emitting circuit configured to: be controlled by the control signal to provide the driving current to the first light emitting device during a first emission time period, and to provide the driving current to the second light emitting device during a second emission time period.

[0009] According to one or more embodiments, a pixel is connected to a scan line for receiving a scan signal, a data line for receiving a data voltage, a control line for receiving a control signal, a first power line for receiving a first driving voltage, and a second power line for receiving a second driving voltage. The pixel includes: a light emitting portion including a first light emitting device connected in a forward direction between a first electrode and a second electrode and a second light emitting device connected in a reverse direction between the first electrode and the second electrode; a pixel circuit configured to: receive the data voltage in synchronization with the scan signal, generate a driving current from the first driving voltage supplied from the first power line based on the data voltage, and output the driving current to a first node; and a light emitting circuit configured to: be controlled by the control signal, provide the driving current to the first light emitting device during a first emission period, and provide the driving current to the second light emitting device during a second emission period, the light emitting circuit being connected to the first electrode and the second electrode, the first node, the second power line, and the control line.

[0010] Aspects, features, and advantages in addition to the foregoing description may be more readily understood by reference to the drawings, claims, and the following detailed description of exemplary embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] These and / or other aspects will become clear and more easily understood through the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram of a display device according to an embodiment;

[0013] Figure 2 is a block diagram of a pixel according to an embodiment;

[0014] Figure 3 is a schematic plan view of a light emitting portion according to an embodiment;

[0015] FIG. 4A to FIG. 4D are views of light emitting devices according to various embodiments;

[0016] Figure 5A is a circuit diagram of a light emitting circuit according to an embodiment, Figure 5B yes Figure 5A A driving timing diagram of a light emitting circuit;

[0017] Fig. 6A is a circuit diagram of a light emitting circuit according to another embodiment, Figure 6B yes Fig. 6A A driving timing diagram of a light emitting circuit;

[0018] Fig. 7A is a circuit diagram of a pixel circuit according to an embodiment;

[0019] Figure 7B is a circuit diagram of a pixel circuit according to another embodiment;

[0020] Figure 7C is a circuit diagram of a pixel circuit according to yet another embodiment;

[0021] Fig. 8A is a circuit diagram of a pixel according to an embodiment, Figure 8B yes Fig. 8A A timing diagram of a pixel of

[0022] Fig. 9 A graph showing the perceived brightness of pixels having different degrees of orientation according to various embodiments is shown. DETAILED DESCRIPTION

[0023] Since the present disclosure allows various changes and many embodiments, the exemplary embodiments will be shown in the drawings and described in detail in the written description. By referring to the contents described in detail below in conjunction with the drawings, the effects and features of the present disclosure and the methods for realizing them will be clear. However, the present disclosure is not limited to the following exemplary embodiments and can be implemented in various forms.

[0024] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings. In order to clearly describe the present disclosure, parts irrelevant to the description may be omitted, and the same reference numerals may be used for the same or corresponding elements, and when describing with reference to the accompanying drawings, their repeated description may be omitted.

[0025] For the convenience of explanation, the size of the components in the drawings may be exaggerated. In other words, since the size and thickness of the components shown in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0026] It will be understood that when a layer, region or component is referred to as being “connected” to another layer, region or component, it may be “directly connected” to the other layer, region or component or may be “indirectly connected” to the other layer, region or component with other layers, regions or components interposed therebetween.

[0027] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will be understood that when a first element includes or has a second element, unless otherwise specifically described, the first element does not exclude the other element and may include the other element.

[0028] The term "corresponding" or "corresponding" in this specification may mean being arranged or connected in the same row and / or the same column. For example, it will be understood that when a first member is connected to a "corresponding" second member among a plurality of second members, the first member is connected to a second member arranged in the same row and / or the same column as the first member. For example, it will be understood that in the case where a plurality of pixel circuits and a plurality of light-emitting devices (such as light-emitting diodes (LEDs)) are arranged on a substrate in row directions and column directions, respectively, when a light-emitting device is connected to a corresponding pixel circuit, the light-emitting device is connected to a pixel circuit among a plurality of pixel circuits that is arranged in the same row and the same column as the light-emitting device.

[0029] For example, in the accompanying drawings, variations in the shapes shown may be expected based on manufacturing techniques and / or tolerances. Therefore, the following embodiments should not be interpreted as being limited to the specific shapes of the regions shown in this specification. In other words, the following embodiments include variations and changes in shape that may be caused or expected during the manufacturing process.

[0030] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] Figure 1 is a block diagram of a display device 100 according to an embodiment.

[0032] Reference Figure 1 , the display device 100 may include a display unit 110 , a scan driver 120 , a data driver 130 , a control driver 140 , a timing controller 150 , and a voltage generator 160 .

[0033] The display unit 110 may include pixels PX arranged along a first direction (eg, a row direction) and a second direction (eg, a column direction). Figure 1 Only one pixel PX is shown in FIG.

[0034] The pixels PX may be connected to scan lines SL1 to SLn and data lines DL1 to DLm. The scan lines SL1 to SLn may transmit scan signals S1 to Sn output from the scan driver 120 to the pixels PX in the same row, respectively, and the data lines DL1 to DLm may transmit data voltages D1 to Dm output from the data driver 130 to the pixels PX in the same column, respectively. Each pixel PX may be connected to a scan line located in the same row among the scan lines SL1 to SLn, and may be connected to a data line located in the same column among the data lines DL1 to DLm. Here, the scan line and the data line connected to the pixel PX are referred to as a scan line SL and a data line DL, respectively, and the scan signal and the data voltage transmitted to the pixel PX are referred to as a scan signal SCAN and a data voltage DATA, respectively.

[0035] The pixels PX may be connected to the control lines CL. The control lines CL may transfer the control signals EM output from the control driver 140 to the pixels PX.

[0036] The control line CL may include a plurality of sub-control lines, and the sub-control lines are connected to the pixels PX arranged in the row direction and the column direction. According to an embodiment, the sub-control lines may extend in the row direction parallel to the scan lines SL1 to SLn. The scan lines SL1 to SLn may transmit the scan signals S1 to Sn to the pixels PX at different timings, but all the sub-control lines may transmit the control signal EM to the pixels PX at the same timing. All the sub-control lines electrically connected to each other may be collectively referred to as the control line CL.

[0037] According to another embodiment, Fig. 6A As shown in , the control lines CL may include a first control line CL1 for transmitting a first control signal EM1 to the pixel PX and a second control line CL2 for transmitting a second control signal EM2 to the pixel PX.

[0038] The pixel PX may be connected to the first power line PL1 and the second power line PL2. The first power line PL1 and the second power line PL2 may transmit the first driving voltage ELVDD and the second driving voltage ELVSS output from the voltage generator 160 to the pixel PX, respectively.

[0039] The first power line PL1 may further include a plurality of first sub power lines connected to the pixels PX. According to an embodiment, the first sub power lines may extend in a column direction parallel to the data lines DL1 to DLm. All first sub power lines electrically connected to each other may be collectively referred to as the first power line PL1.

[0040] The second power line PL2 may further include a plurality of second sub-power lines connected to the pixel PX. According to an embodiment, the second sub-power lines may extend in a column direction parallel to the data lines DL1 to DLm. All the second sub-power lines electrically connected to each other may be collectively referred to as the second power line PL2. According to another example, the second power line PL2 may be connected to the pixel PX in the form of a common electrode.

[0041] The pixel PX may include a light-emitting portion, a pixel circuit, and a light-emitting circuit. The light-emitting portion may include a first light-emitting device connected in a forward direction between a first electrode and a second electrode and a second light-emitting device connected in a reverse direction between the first electrode and the second electrode. The pixel circuit may receive a data voltage DATA synchronously with a scan signal SCAN, and may generate a drive current based on the data voltage DATA and output the drive current to a first node. The light-emitting circuit may be controlled by a control signal EM, and may provide a drive current to the first light-emitting device during a first emission time period, and provide a drive current to the second light-emitting device during a second emission time period. Since the first light-emitting device emits light during a first emission time period within a frame period and the second light-emitting device emits light during a second emission time period within the same frame period, the brightness of the light emitted by the pixel PX may be perceived as constant regardless of the ratio of the number of second light-emitting devices to the number of first light-emitting devices. The pixel PX may correspond to a portion of a pixel (e.g., a sub-pixel) that is capable of displaying full color. Referring to FIG. 10A and FIG. 11B , the pixel PX may correspond to a portion of a pixel (e.g., a sub-pixel) that is capable of displaying full color. Figure 2 The pixel PX is described in more detail.

[0042] The voltage generator 160 may generate voltages required for the operation of the scan driver 120 and the control driver 140. For example, the voltage generator 160 may generate a first driving voltage ELVDD and a second driving voltage ELVSS. The first driving voltage ELVDD is a voltage applied to the pixel PX through the first power line PL1, and the second driving voltage ELVSS is a voltage applied to the pixel PX through the second power line PL2. The level of the second driving voltage ELVSS may be lower than that of the first driving voltage ELVDD.

[0043] The voltage generator 160 may also generate a first gate voltage VGH and a second gate voltage VGL to control a switching transistor of the pixel PX. The level of the first gate voltage VGH may be greater than that of the second gate voltage VGL.

[0044] In the case where the conductivity type of the switching transistor is n-type, when the first gate voltage VGH is applied to the gate electrode of the switching transistor, the switching transistor is turned on, and when the second gate voltage VGL is applied to the gate electrode of the switching transistor, the switching transistor is turned off. In this case, the first gate voltage VGH can be referred to as the turn-on voltage, and the second gate voltage VGL can be referred to as the turn-off voltage. On the contrary, in the case where the conductivity type of the switching transistor is p-type, when the first gate voltage VGH is applied to the gate electrode of the switching transistor, the switching transistor is turned off, and when the second gate voltage VGL is applied to the gate electrode of the switching transistor, the switching transistor is turned on. In this case, the first gate voltage VGH can be referred to as the turn-off voltage, and the second gate voltage VGL can be referred to as the turn-on voltage.

[0045] In addition to the four voltages (ie, ELVDD, ELVSS, VGH, and VGL), the voltage generator 160 may generate voltages of other levels and may provide the generated voltages to the control driver 140. For example, the voltage generator 160 may generate gamma reference voltages and may provide the gamma reference voltages to the data driver 130.

[0046] The timing controller 150 can control the display unit 110 by controlling the operation timing of the scan driver 120, the data driver 130, and the control driver 140. The pixels PX of the display unit 110 can receive a new data voltage DATA every frame period, and emit light with a brightness corresponding to the received data voltage DATA, thereby displaying an image corresponding to the image data RGB (also referred to herein as a digital data signal) of one frame. According to an embodiment, one frame period is a period for displaying an image of one frame by the pixels PX of the display unit 110. Each pixel PX can receive the data voltage DATA in synchronization with the scan signal SCAN every frame, and emit light with a brightness corresponding to the data voltage DATA within one frame period.

[0047] The timing controller 150 may receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK, and image data RGB from the outside. The timing controller 150 may control the operation timing of the scan driver 120, the data driver 130, and the control driver 140 by using timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the clock signal CLK. The timing controller 150 may determine the frame period by counting the data enable signal DE for one horizontal scanning period, in which case the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync supplied from the outside may be omitted. The image data RGB may include brightness information of the pixel PX. The brightness may have a predetermined number of bits representing a grayscale level, for example, 1024 (2 10)、256(2 8 ) or 64(2 6 ) grayscale.

[0048] The timing controller 150 may generate control signals including a first gate timing control signal GDC1 for controlling the operation timing of the scan driver 120 , a data timing control signal DDC for controlling the operation timing of the data driver 130 , and a second gate timing control signal GDC2 for controlling the operation timing of the control driver 140 .

[0049] The first gate timing control signal GDC1 may include, but is not limited to, a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE) signal, etc. GSP is supplied to the scan driver 120 to generate a first scan signal at the start time of a scan cycle. GSC is a clock signal input to the scan driver 120 and is a clock signal for shifting GSP. The GOE signal controls the output of the scan driver 120. The second gate timing control signal GDC2 is supplied to the control driver 140.

[0050] The data timing control signal DDC may include, but is not limited to, a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE) signal, etc. The SSP controls the data sampling start time of the data driver 130 and is provided to the data driver 130 at the start time of the scanning period. The SSC is a clock signal for controlling the sampling operation of data in the data driver 130 based on a rising edge or a falling edge. The SOE signal may control the output of the data driver 130. The SSP supplied to the data driver 130 may be omitted according to the data transmission scheme.

[0051] The scan driver 120 may sequentially generate scan signals S1 to Sn in response to a first gate timing control signal GDC1 supplied from the timing controller 150 by using a first gate voltage VGH and a second gate voltage VGL supplied from the voltage generator 160. The scan driver 120 may provide the scan signals S1 to Sn to the pixels PX of the display unit 110 through the scan lines SL1 to SLn.

[0052] The data driver 130 may sample and latch the digital data signal RGB supplied from the timing controller 150 in response to the data timing control signal DDC supplied from the timing controller 150 to convert the digital data signal RGB into parallel data. When the data driver 130 converts the digital data signal RGB into parallel data, the data driver 130 may convert the digital data signal RGB into a gamma reference voltage and convert the gamma reference voltage into an analog data voltage. The data driver 130 may provide the data voltages D1 to Dm to the pixels PX of the display unit 110 through the data lines DL1 to DLm. The pixels PX may receive the data voltages DATA in response to the scan signal SCAN.

[0053] The control driver 140 may drive the control line CL in response to the second gate timing control signal GDC2 supplied from the timing controller 150 by using the first gate voltage VGH and the second gate voltage VGL provided from the voltage generator 160. The control driver 140 may output the first gate voltage VGH and the second gate voltage VGL alternately to the control line CL in response to the second gate timing control signal GDC2. The first gate voltage VGH and the second gate voltage VGL transmitted through the control line CL may be a control signal EM having a first logic level and a control signal EM having a second logic level, respectively. During one frame period, the control driver 140 may output the first gate voltage VGH and the second gate voltage VGL alternately to the control line CL multiple times. For example, the control driver 140 may sequentially output four gate voltages to the control line CL in the order of the first gate voltage VGH, the second gate voltage VGL, the first gate voltage VGH, and the second gate voltage VGL within one frame period. According to another example, the control driver 140 can sequentially output eight gate voltages to the control line CL in the order of a first gate voltage VGH, a second gate voltage VGL, a first gate voltage VGH, a second gate voltage VGL, a first gate voltage VGH, a second gate voltage VGL, a first gate voltage VGH, a second gate voltage VGL, a first gate voltage VGH, and a second gate voltage VGL within one frame period.

[0054] Figure 2 is a block diagram of a pixel PX according to an embodiment.

[0055] Reference Figure 2 , the pixel PX may include a pixel circuit PC, a light emitting circuit EC, and a light emitting portion ED. The pixel PX may be connected to a first power line PL1 and a second power line PL2 and receive a first driving voltage ELVDD and a second driving voltage ELVSS. In addition, the pixel PX may receive a scan signal SCAN, a data voltage DATA, and a control signal EM.

[0056] The light emitting portion ED may include a first light emitting device connected in a forward direction between the first electrode ELa and the second electrode ELb and a second light emitting device connected in a reverse direction between the first electrode ELa and the second electrode ELb. Figure 2 In the embodiment, first light emitting devices connected between the first electrode ELa and the second electrode ELb in a forward direction are collectively referred to as first light emitting devices FED, and second light emitting devices connected between the first electrode ELa and the second electrode ELb in a reverse direction are collectively referred to as second light emitting devices RED.

[0057] The pixel circuit PC may be connected between the first power line PL1 and the first node N, and may receive a scan signal SCAN and a data voltage DATA. The pixel circuit PC may receive the data voltage DATA in synchronization with the scan signal SCAN, and may generate a driving current Id based on the data voltage DATA and output the driving current Id to the first node N. The magnitude of the driving current Id may be determined according to the voltage level of the data voltage DATA.

[0058] The light emitting circuit EC may be connected between the first node N and the second power line PL2, and may receive a control signal EM. The light emitting circuit EC may be connected to the light emitting portion ED through the first electrode ELa and the second electrode ELb. The light emitting circuit EC may be controlled by the control signal EM. The light emitting circuit EC may provide a driving current Id to the first light emitting device FED during a first emission time period, and provide a driving current Id to the second light emitting device RED during a second emission time period. The time length of the first emission time period and the time length of the second emission time period may be equal to each other. One frame period may be an even multiple of four or more times the time length of the first emission time period or the time length of the second emission time period. In this case, because the time length of the first emission time period and the time length of the second emission time period are shorter than 1 / 2 of one frame period, the flicker phenomenon does not appear in the display unit 110 or is not recognized by the viewer.

[0059] Figure 3 is a schematic plan view of a light emitting portion ED according to an embodiment.

[0060] Reference Figure 3 The light emitting portion ED may include a light emitting device connected in a forward direction between the first electrode ELa and the second electrode ELb and a light emitting device connected in a reverse direction between the first electrode ELa and the second electrode ELb.

[0061] The light emitting device connected in the forward direction between the first electrode ELa and the second electrode ELb is referred to as a first light emitting device nLED_F, and the light emitting device connected in the reverse direction between the first electrode ELa and the second electrode ELb is referred to as a second light emitting device nLED_R. However, the first light emitting device nLED_F and the second light emitting device nLED_R may have substantially the same structure and characteristics, and may be collectively referred to as light emitting devices nLED. Each light emitting device nLED may be a micro light emitting diode (LED) that may have an anode and a cathode and may emit light when a voltage exceeding a threshold voltage is applied between the anode and the cathode. Figure 3 , a line st indicating a cathode is shown in each light emitting device nLED.

[0062] In the first light emitting device nLED_F connected in the forward direction between the first electrode ELa and the second electrode ELb, the cathode indicated by the line st is connected to the second electrode ELb, and the anode is connected to the first electrode ELa. In the second light emitting device nLED_R connected in the reverse direction between the first electrode ELa and the second electrode ELb, the cathode indicated by the line st is connected to the first electrode ELa, and the anode is connected to the second electrode ELb.

[0063] Figure 3 The first and second emission parts ED1 and ED2 are different from each other. The first and second emission parts ED1 and ED2 may constitute different pixels PX in the same display device 100. For example, a pixel PX including the first emission part ED1 and a pixel PX including the second emission part ED2 may be disposed adjacent to each other.

[0064] The ratio of the first light-emitting device nLED_F in one light-emitting section to the total light-emitting devices nLED in the light-emitting section may be different between the first light-emitting section ED1 and the second light-emitting section ED2. For example, in the first light-emitting section ED1, the ratio of the first light-emitting device nLED_F to the total light-emitting devices nLED is about 80%, and in the second light-emitting section ED2, the ratio of the first light-emitting device nLED_F to the total light-emitting devices nLED is about 70%. However, it is understood that these ratios of the first light-emitting device nLED_F to the total light-emitting devices nLED are only examples, and each pixel PX included in the display device 100 may have a different ratio without departing from the scope of the present disclosure. Because the light-emitting device nLED in each pixel PX emits light in the first emission time period or the second emission time period during one frame period regardless of their polarity, even if the ratio varies due to the pixel PX in the display device 100, the brightness of the display device 100 can be kept uniform.

[0065] The light emitting portion ED can be formed by applying a voltage between the first electrode ELa and the second electrode ELb, each of which is formed on the substrate, thereby forming an electric field. Then, a mixed liquid containing the light emitting device nLED is dropped onto the first electrode ELa and the second electrode ELb, and the light emitting device nLED is oriented on the first electrode ELa and the second electrode ELb by the electric field.

[0066] Figure 3 As shown in , some light-emitting devices nLED may be connected in the forward direction between the first electrode ELa and the second electrode ELb, and other light-emitting devices nLED may be connected in the reverse direction between the first electrode ELa and the second electrode ELb. When the light-emitting portion ED is formed in this manner, the number of light-emitting devices nLED included in each pixel PX may not be accurately controlled. In addition, in each pixel PX, the ratio of the number of second light-emitting devices nLED_R to the number of first light-emitting devices nLED_F may not be constant. That is, for each pixel PX, the ratio of the second light-emitting device nLED_R connected in the reverse direction to the total light-emitting devices nLED may be different.

[0067] When the pixel PX is designed so that the driving current flows only from the first electrode ELa to the second electrode ELb, the second light emitting device nLED_R may not emit light. If the ratio of the first light emitting device nLED_F to all light emitting devices nLED changes, the pixel PX designed to emit light with the same brightness at the same gray level may emit light with different brightness.

[0068] The first electrode ELa and the second electrode ELb may be spaced apart at regular intervals. Figure 3 1 shows a structure in which the first electrodes ELa and the second electrodes ELb are alternately arranged, parts of the first electrodes ELa (eg, branches or protrusions) are connected to each other at the top, and parts of the second electrodes ELb (eg, branches or protrusions) are connected to each other at the bottom, but Figure 3 The structure shown in is only an example. The first electrode ELa and the second electrode ELb may be disposed in parallel with each other, or may be disposed in a spiral shape at regular intervals. The arrangement of the first electrode ELa and the second electrode ELb does not limit the scope of the present disclosure.

[0069] FIG. 4A to FIG. 4D 2 is a view of a light emitting device nLED according to various embodiments.

[0070] Reference Figure 4A, the light emitting device nLED according to the embodiment may include a first electrode layer 410, a second electrode layer 420, a first semiconductor layer 430, a second semiconductor layer 440, and an active layer 450 located between the first semiconductor layer 430 and the second semiconductor layer 440. According to the embodiment, the first electrode layer 410, the first semiconductor layer 430, the active layer 450, the second semiconductor layer 440, and the second electrode layer 420 may be sequentially stacked along the length direction of the light emitting device nLED. The length of the light emitting device nLED may be about 1 μm to about 10 μm, and the diameter of the light emitting device nLED may be about 0.5 μm to about 500 μm; however, it is noted that the present disclosure is not limited to this exemplary embodiment, and the length, diameter, and shape of the light emitting device nLED may vary without departing from the scope of the present disclosure.

[0071] The first electrode layer 410 and the second electrode layer 420 may be ohmic contact electrodes. However, the first electrode layer 410 and the second electrode layer 420 are not limited thereto and may be other types of contact electrodes, such as Schottky contact electrodes. The first electrode layer 410 and the second electrode layer 420 may include one or more metals, such as aluminum, titanium, indium, gold, and silver. The materials included in the first electrode layer 410 and the second electrode layer 420 may be the same or different from each other.

[0072] The first semiconductor layer 430 may include, for example, an n-type semiconductor layer, and the second semiconductor layer 440 may include, for example, a p-type semiconductor layer. The first semiconductor layer 430 may include, but is not limited to, semiconductor materials such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN. The first semiconductor layer 430 may be doped with n-type dopants such as Si, Ge, and Sn. The second semiconductor layer 440 may be doped with p-type dopants such as Mg, Zn, Ca, Sr, and Ba. However, the present disclosure is not limited thereto, and the first semiconductor layer 430 may include a p-type semiconductor layer, and the second semiconductor layer 440 may include an n-type semiconductor layer.

[0073] The active layer 450 may be disposed between the first semiconductor layer 430 and the second semiconductor layer 440, and may have, for example, a single quantum well structure or a multi-quantum well structure. The active layer 450 corresponds to a region where electrons and holes recombine. When electrons and holes recombine, the active layer 450 may transition to a lower energy level and generate light having a wavelength corresponding thereto. The active layer 450 may be positioned differently depending on the type of the light-emitting device nLED. It is noted that the light-emitting device nLED is not limited to the above-described embodiments. For example, the light-emitting device nLED may further include a separate phosphor layer, an active layer, a semiconductor layer, and / or an electrode layer located above the first semiconductor layer 430 and below the second semiconductor layer 440. The light generated from the active layer 450 may be emitted to the outer surface and / or both side surfaces of the light-emitting device nLED.

[0074] The light emitting device nLED may further include an insulating layer 470 covering its outer surface. In an embodiment, the insulating layer 470 may cover the active layer 450 and prevent the active layer 450 from contacting the first electrode ELa or the second electrode ELb. The insulating layer 470 may also prevent a reduction in emission efficiency by protecting the outer surface of the light emitting device nLED including the outer surface of the active layer 450.

[0075] Figure 4B Shown with Figure 4A The light emitting device nLED shown in FIG. 1 is different from the light emitting device nLED in that the insulating layer 470 covers the entire outer surface of the light emitting device nLED, but the other structures are the same as those in FIG. Figure 4A The structure is basically the same.

[0076] Figure 4C Shown with Figure 4A Compared with the light emitting device nLED of the embodiment of the present invention, the second electrode layer 420 is omitted. However, this is only an example and may be Figure 4A In the light-emitting device nLED, any one of the first electrode layer 410 and the second electrode layer 420 (ie, the second electrode layer 420) is omitted.

[0077] exist Figure 4C In the light emitting device nLED, the insulating layer 470 covers a portion of the outer surface of the first electrode layer 410 and a portion of the outer surface of the second semiconductor layer 440. According to another embodiment, the insulating layer 470 may cover the entire outer surface of the second semiconductor layer 440.

[0078] Figure 4D Shown with Figure 4A Compared with the light-emitting device nLED of FIG. 1 , the light-emitting device nLED of FIG. 1 is a light-emitting device in which both the first electrode layer 410 and the second electrode layer 420 are omitted. Figure 4DAs shown in FIG, the insulating layer 470 covers the entire outer surface of the first semiconductor layer 430, the active layer 450, and the second semiconductor layer 440, but the present disclosure is not limited thereto. The insulating layer 470 may cover at least a portion of the outer surface of the first semiconductor layer 430 and the second semiconductor layer 440 and expose a portion of the outer surface thereof.

[0079] Figure 5A is a circuit diagram of a lighting circuit ECa according to an embodiment, Figure 5B yes Figure 5A Driving timing diagram of the light-emitting circuit ECa.

[0080] Reference Figure 5A , the light emitting circuit ECa may be connected between the node N and the second power line PL2, and may also be connected to the control line CL to receive the control signal EM. In addition, the light emitting circuit ECa may be connected to the light emitting portion ED through the first electrode ELa and the second electrode ELb. As described above, the light emitting portion ED may include one or more first light emitting devices nLED_F connected in a forward direction between the first electrode ELa and the second electrode ELb, and one or more second light emitting devices nLED_R connected in a reverse direction between the first electrode ELa and the second electrode ELb. Figure 5A In the figure, the first light emitting devices nLED_F are collectively expressed as first light emitting devices FED, and the second light emitting devices nLED_R are collectively expressed as second light emitting devices RED.

[0081] The light emitting circuit ECa may include a first transistor M1 connected between a node N and a first electrode ELa, a second transistor M2 connected between a node N and a second electrode ELb, a third transistor M3 connected between the first electrode ELa and a second power line PL2, and a fourth transistor M4 connected between the second electrode ELb and the second power line PL2. All gate electrodes of the first to fourth transistors M1 to M4 may be connected to a control line CL, and therefore, the first to fourth transistors M1 to M4 may all be controlled by a control signal EM.

[0082] The conductivity types of the first transistor M1 and the fourth transistor M4 may be opposite to the conductivity types of the second transistor M2 and the third transistor M3. Figure 5A As shown in , the conductivity type of the first transistor M1 and the fourth transistor M4 may be n-type, and the conductivity type of the second transistor M2 and the third transistor M3 may be p-type. According to another example, the conductivity type of the first transistor M1 and the fourth transistor M4 may be p-type, and the conductivity type of the second transistor M2 and the third transistor M3 may be n-type.

[0083] Reference Figure 5BThe first emission time period E1 may be a time period during which the first light emitting device FED emits light, and the second emission time period E2 may be a time period during which the second light emitting device RED emits light. Figure 5A In the case of the light emitting circuit ECa shown in FIG. 1 , the control signal EM may have a high level VGH during the first emission period E1 and a low level VGL during the second emission period E2. According to another example, when the conductivity types of the first to fourth transistors M1 to M4 are different from each other, the control signal EM may have a high level VGH during the first emission period E1 and a low level VGL during the second emission period E2. Figure 5A In contrast to that shown in , the control signal EM may have a low level VGL during the first emission period E1 and a high level VGH during the second emission period E2.

[0084] During the first emission period E1, the first transistor M1 and the fourth transistor M4 are turned on by the control signal EM having a high level VGH, and the second transistor M2 and the third transistor M3 are turned off by the control signal EM having a high level VGH. Figure 2 The pixel circuit PC outputs the driving current (ie, Figure 2 The driving current Id in the first light emitting device FED flows through the first light emitting device FED. During the second emission period E2, the second transistor M2 and the third transistor M3 are turned on by the control signal EM having a low level VGL, and the first transistor M1 and the fourth transistor M4 are turned off by the control signal EM having a low level VGL. In this case, Figure 2 The pixel circuit PC outputs the driving current (ie, Figure 2 The driving current Id) in flows through the second light emitting device RED.

[0085] During the first transmission period E1, Figure 1 The control driver 140 may output a control signal EM having a first logic level (ie, a high level VGH) to the control line CL to turn on the first transistor M1 and the fourth transistor M4 and turn off the second transistor M2 and the third transistor M3, so that the driving current (ie, Figure 2 During the second emission period E2, the driving current Id) flows through the first light emitting device FED. Figure 1 The control driver 140 may output a control signal EM having a second logic level (ie, a low level VGL) to the control line CL to turn on the second transistor M2 and the third transistor M3 and turn off the first transistor M1 and the fourth transistor M4, so that the driving current (ie, Figure 2 The driving current Id) in flows through the second light emitting device RED.

[0086] A plurality of first emission time periods E1 and a plurality of second emission time periods E2 may alternately appear within one frame period represented by "1 frame". Figure 5B In the timing diagram of , two first emission time periods E1 and two second emission time periods E2 may appear alternately in one frame period "1 frame". However, this case is only an example, and without departing from the scope of the present disclosure, three or more first emission time periods E1 and three or more second emission time periods E2 may appear alternately in one frame period "1 frame". For this reason, Figure 1 The control driver 140 may alternately output a control signal EM having a first logic level (eg, a high level VGH) and a control signal EM having a second logic level (eg, a low level VGL) multiple times within one frame period "1 frame". Figure 1 The flicker phenomenon can be reduced in the display unit 110.

[0087] According to one embodiment, the time length of the first emission time period E1 and the time length of the second emission time period E2 may be the same. The time length of the first emission time period E1 and the time length of the second emission time period E2 may be 1 / (2k) of a frame period "1 frame" (where k is a natural number of 2 or greater). However, it is noted that the time length of the first emission time period E1 and the time length of the second emission time period E2 may vary according to various parameters (e.g., the ratio of the number of second light-emitting devices to the number of first light-emitting devices, or vice versa).

[0088] Fig. 6A is a circuit diagram of a light emitting circuit ECb according to another embodiment, Figure 6B yes Fig. 6A Driving timing diagram of the light-emitting circuit ECb.

[0089] Reference Fig. 6A According to another embodiment, the light emitting circuit ECb may be connected between the node N and the second power line PL2, and may also be connected to the light emitting portion ED through the first electrode ELa and the second electrode ELb. In addition, the light emitting circuit ECb may be connected to the first control line CL1 to receive the first control signal EM1, and may be connected to the second control line CL2 to receive the second control signal EM2.

[0090] The light emitting circuit ECb may include a first transistor M1 connected between a node N and a first electrode ELa, a second transistor M2 connected between a node N and a second electrode ELb, a third transistor M3 connected between the first electrode ELa and a second power line PL2, and a fourth transistor M4 connected between the second electrode ELb and the second power line PL2. The first transistor M1 and the fourth transistor M4 may have the same conductivity type. In FIG6 , the conductivity types of the first transistor M1 and the fourth transistor M4 are n-type. However, this case is only an example, and the conductivity types of the first transistor M1 and the fourth transistor M4 may be p-type.

[0091] The gate electrodes of the first transistor M1 and the fourth transistor M4 may be commonly connected to the first control line CL1, and the first transistor M1 and the fourth transistor M4 may be controlled by the first control signal EM1. The gate electrodes of the second transistor M2 and the third transistor M3 may be commonly connected to the second control line CL2, and the second transistor M2 and the third transistor M3 may be controlled by the second control signal EM2.

[0092] Reference Figure 6B The first transmission time period E1 may be Fig. 6A The second emission period E2 may be a period during which the first light emitting device FED emits light. Fig. 6A The time period during which the second light emitting device RED emits light. Fig. 6A In the case of the light emitting circuit ECb shown in FIG, the first control signal EM1 may have a high level VGH during the first emission period E1 and a low level VGL during the remaining period. The second control signal EM2 may have a high level VGH during the second emission period E2 and a low level VGL during the remaining period.

[0093] During the first emission period E1, the first transistor M1 and the fourth transistor M4 are turned on by the first control signal EM1 having a high level VGH, and the second transistor M2 and the third transistor M3 are turned off by the second control signal EM2 having a low level VGL. Figure 2 The pixel circuit PC outputs the driving current (ie, Figure 2 The driving current Id in (i.e., the ... Figure 2 The driving current Id) in flows through the second light emitting device RED.

[0094] During the first transmission period E1, Figure 1 The control driver 140 may output a first control signal EM1 having a turn-on level (e.g., a high level VGH) to the first control line CL1 to turn on the first transistor M1 and the fourth transistor M4, and output a second control signal EM2 having a turn-off level (e.g., a low level VGL) to the second control line CL2 to turn off the second transistor M2 and the third transistor M3, so that the driving current (i.e., Figure 2 During the second emission period E2, the driving current Id) flows through the first light emitting device FED. Figure 1 The control driver 140 may output a first control signal EM1 having a cut-off level (e.g., a low level VGL) to the first control line CL1 to turn off the first transistor M1 and the fourth transistor M4, and output a second control signal EM2 having a turn-on level (e.g., a high level VGH) to the second control line CL2 to turn on the second transistor M2 and the third transistor M3, so that the driving current (i.e., Figure 2 The driving current Id) in flows through the second light emitting device RED.

[0095] The first control line CL1 may be connected to all pixels PX in the display unit 110. The second control line CL2 may also be connected to all pixels PX in the display unit 110.

[0096] Figure 1 The control driver 140 can be Figure 1 Under the timing controller 150, a first duty ratio as a ratio of the conduction level of the first control signal EM1 and a second duty ratio as a ratio of the conduction level of the second control signal EM2 are controlled. The first duty ratio of the first control signal EM1 and the second duty ratio of the second control signal EM2 may be equal to each other. The first duty ratio and the second duty ratio may be 50% or less. When the first duty ratio and the second duty ratio decrease, the overall brightness of the pixel PX of the display unit 110 decreases. The timing controller 150 may adjust the overall brightness of the display unit 110 by controlling the first duty ratio of the first control signal EM1 and the second duty ratio of the second control signal EM2 by controlling the driver 140.

[0097] Fig. 7A is a circuit diagram of a pixel circuit PCa according to the embodiment.

[0098] Reference Fig. 7A, the pixel circuit PCa may be connected between the first power line PL1 and the node N, and may also be connected to the data line DL and the scan line SL to receive the data voltage DATA and the scan signal SCAN. The pixel circuit PCa may receive the data voltage DATA in synchronization with the scan signal SCAN, and may generate a driving current Id from the first driving voltage ELVDD supplied from the first power line PL1 based on the data voltage DATA, and output the driving current Id to the node N.

[0099] like Fig. 7A As shown in , the pixel circuit PCa may include a driving transistor Tdr connected between the first power line PL1 and the node N and generating a driving current Id according to the data voltage DATA. The pixel circuit PCa may include a switching transistor Tsw connected between the data line DL and the gate electrode of the driving transistor Tdr and controlled by the scan signal SCAN. The pixel circuit PCa may include a storage capacitor Cst connected to the gate electrode of the driving transistor Tdr and storing the data voltage DATA for one frame period. The storage capacitor Cst may be connected between the gate electrode of the driving transistor Tdr and the first power line PL1.

[0100] like Fig. 7A As shown in , the driving transistor Tdr and the switching transistor Tsw may be p-type MOSFETs.

[0101] Figure 7B is a circuit diagram of a pixel circuit PCb according to another embodiment.

[0102] In addition to the conductivity types of the driving transistor Tdr and the switching transistor Tsw, Figure 7B The pixel circuit PCb shown in FIG. Fig. 7A The pixel circuit PCa shown in FIG. is substantially the same. Figure 7B As shown in FIG. 1 , the driving transistor Tdr and the switching transistor Tsw of the pixel circuit PCb may be n-type MOSFETs.

[0103] Figure 7C is a circuit diagram of a pixel circuit PCc according to still another embodiment.

[0104] Reference Figure 7C, the pixel circuit PCc may be connected between the first power line PL1 and the node N, and may also be connected to the data line DL to receive the data voltage DATA. The pixel circuit PCc may receive the first scan signal SCAN1 through the first scan line SL1, and may receive the second scan signal SCAN2 through the second scan line SL2. The pixel circuit PCc may be connected to a third power line PL3 for carrying a reference voltage Vref. The pixel circuit PCc may receive the data voltage DATA in synchronization with the first scan signal SCAN1, and may generate a driving current Id from the first driving voltage ELVDD supplied from the first power line PL1 based on the data voltage DATA, and output the driving current Id to the node N.

[0105] like Figure 7C As shown in , the pixel circuit PCc may include a driving transistor Tdr connected between a first power line PL1 and a node N and generating a driving current Id according to a data voltage DATA. The pixel circuit PCc may include a first switching transistor Tsw1 connected between a data line DL and a gate electrode of the driving transistor Tdr and controlled by a first scan signal SCAN1. The pixel circuit PCc may include a storage capacitor Cst connected between the gate electrode of the driving transistor Tdr and the node N and storing the data voltage DATA for one frame period. The pixel circuit PCc may include a second switching transistor Tsw2 connected between a third power line PL3 carrying a reference voltage Vref and the node N. The second switching transistor Tsw2 may be controlled by a second scan signal SCAN2.

[0106] According to various embodiments, the pixel PX may include Figure 5A The lighting circuit ECa shown in Fig. 6A One of the lighting circuits ECb shown in FIG. 1 and may include 7A to 7C One of the pixel circuits PCa, PCb and PCc shown in .

[0107] Fig. 8A is a circuit diagram of a pixel PX according to an embodiment, Figure 8B yes Fig. 8A Timing diagram of pixel PX.

[0108] Reference Fig. 8A , pixel PX includes Fig. 7A The pixel circuit PCa shown in Figure 5A The lighting circuit ECa and the lighting part ED shown in FIG.

[0109] Reference Figure 8B, when the scan signal SCAN has a turn-on level (e.g., a low level VGL), the data voltage DATA is received by the pixel circuit PCa. The storage capacitor Cst of the pixel circuit PCa can store the data voltage DATA for one frame period "1 frame". The pixel circuit PCa can generate a driving current Id according to the received data voltage DATA, and output the generated driving current Id to the node N.

[0110] The control signal EM may have a first logic level (e.g., a high level VGH) during the first emission period E1, and a second logic level (e.g., a low level VGL) during the second emission period E2. During the first emission period E1, when the drive current Id flows through the first transistor M1, the first light emitting device FED, and the fourth transistor M4, the first light emitting device FED may emit light. During the second emission period E2, when the drive current Id flows through the second transistor M2, the second light emitting device RED, and the third transistor M3, the second light emitting device RED may emit light.

[0111] Fig. 9 Shown is a graph illustrating the perceived brightness of pixels having different degrees of orientation according to various embodiments.

[0112] The orientation degree indicates the ratio of the first light emitting device connected in the forward direction to all the light emitting devices included in the pixel PX. When the orientation degree is 100%, it indicates that all the light emitting devices in the pixel PX are connected between the first electrode ELa and the second electrode ELb in the forward direction. When the orientation degree is 80%, it indicates that 80% of the light emitting devices in the pixel PX are connected between the first electrode ELa and the second electrode ELb in the forward direction, and the remaining 20% ​​of the light emitting devices are connected between the first electrode ELa and the second electrode ELb in the reverse direction.

[0113] The first light emitting device connected in the forward direction (ie, Figure 3 The first light emitting device nLED_F in the first emission period E1 emits light, and the second light emitting device connected in the reverse direction (ie, Figure 3 The second light emitting device nLED_R) in the embodiment emits light in the second emission time period E2.

[0114] When the orientation degree is 100%, since all the light emitting devices emit light in the first emission period E1, the relative brightness (in the range of 0 to 100) in the first emission period E1 is 100, and since none of the light emitting devices emit light in the second emission period E2, the relative brightness in the second emission period E2 is 0. When the length of the first emission period E1 and the length of the second emission period E2 are equal to each other, the perceived brightness (in the range of 0 to 100) perceived by the viewer is 50.

[0115] When the orientation degree is 80%, because 80% of the light emitting devices emit light in the first emission period E1, the relative brightness in the first emission period E1 is 80, and because 20% of the light emitting devices emit light in the second emission period E2, the relative brightness in the second emission period E2 is 20. Therefore, the perceived brightness perceived by the viewer is 50.

[0116] When the orientation degree is 60%, because 60% of the light-emitting devices emit light in the first emission time period E1, the relative brightness in the first emission time period E1 is 60, and because 40% of the light-emitting devices emit light in the second emission time period E2, the relative brightness in the second emission time period E2 is 40. In this case, the perceived brightness is 50.

[0117] When the orientation degree is 40%, because 40% of the light-emitting devices emit light in the first emission time period E1, the relative brightness in the first emission time period E1 is 40, and because 60% of the light-emitting devices emit light in the second emission time period E2, the relative brightness in the second emission time period E2 is 60. In this case, the perceived brightness is 50.

[0118] When the orientation degree is 20%, because 20% of the light-emitting devices emit light in the first emission time period E1, the relative brightness in the first emission time period E1 is 20, and because 80% of the light-emitting devices emit light in the second emission time period E2, the relative brightness in the second emission time period E2 is 80. In this case, the perceived brightness is 50.

[0119] Therefore, according to various embodiments, not only the light-emitting device connected in the forward direction between the first electrode ELa and the second electrode ELb emits light, but also the light-emitting device connected in the reverse direction between the first electrode ELa and the second electrode ELb emits light, and thus, the perceived brightness perceived by the observer can be kept constant, thereby improving the brightness uniformity of the display device.

[0120] According to various embodiments, in a display device in which some micro LEDs are disposed between a pair of electrodes in the reverse direction, the micro LEDs disposed in the reverse direction also emit light, and thus, uniformity of perceived brightness can be improved.

[0121] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as applicable to other similar features or aspects in other embodiments.

[0122] Although one or more embodiments have been described with reference to the drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the claims.

Claims

1. A display device, comprising: A display unit including a plurality of pixels arranged along a first direction and a second direction; A scan driver configured to: send a scan signal to the plurality of pixels through a plurality of scan lines; a data driver configured to: send data voltages to the plurality of pixels through a plurality of data lines; A control driver configured to: send a control signal to the plurality of pixels through a control line; as well as a voltage generator configured to supply a first driving voltage and a second driving voltage to the plurality of pixels through a first power line and a second power line, respectively; Wherein, each pixel of the plurality of pixels comprises: a light emitting portion including a first light emitting device connected in a forward direction between a first electrode and a second electrode and a second light emitting device connected in a reverse direction between the first electrode and the second electrode; a pixel circuit configured to: receive a corresponding data voltage among the data voltages in synchronization with a corresponding scan signal among the scan signals, generate a driving current based on the corresponding data voltage, and output the driving current to a first node; and a light emitting circuit configured to: be controlled by the control signal to supply the driving current to the first light emitting device during a first emission time period within a frame period in which an image of one frame is displayed by pixels of a display unit, and to supply the driving current to the second light emitting device during a second emission time period within the same frame period, Wherein, the first light emitting device and the second light emitting device are micro light emitting diodes, wherein each of the first light emitting devices has an anode connected to the first electrode and a cathode connected to the second electrode, wherein each of the second light emitting devices has an anode connected to the second electrode and a cathode connected to the first electrode, and Wherein, a ratio of the number of the second light emitting devices included in each of the plurality of pixels to the number of the first light emitting devices is not constant.

2. The display device according to claim 1, wherein: Each of the plurality of pixels emits light alternately between a plurality of first emission time periods and a plurality of second emission time periods within one frame period.

3. The display device according to claim 1, wherein: The lighting circuit comprises: a first transistor connected between the first node and the first electrode; a second transistor connected between the first node and the second electrode; a third transistor connected between the first electrode and the second power line; and The fourth transistor is connected between the second electrode and the second power line.

4. The display device according to claim 3, wherein: The conductivity types of the first transistor and the fourth transistor are opposite to the conductivity types of the second transistor and the third transistor, The gate electrodes of the first transistor to the fourth transistor are commonly connected to the control line.

5. The display device according to claim 4, wherein: The control driver is further configured to: outputting the control signal having a first logic level to the control line so that during the first emission period, the first transistor and the fourth transistor are turned on and the second transistor and the third transistor are turned off, and the drive current flows through the first light emitting device, and The control signal having a second logic level is output to the control line so that during the second emission period, the second transistor and the third transistor are turned on and the first transistor and the fourth transistor are turned off, and the driving current flows through the second light emitting device.

6. The display device according to claim 5, wherein: The control driver is further configured to alternately output the control signal having the first logic level and the control signal having the second logic level a plurality of times during one frame period.

7. The display device according to claim 3, wherein: The control lines include: a first control line for transmitting a first control signal to the plurality of pixels, and a second control line for transmitting a second control signal to the plurality of pixels, The gate electrodes of the first transistor and the fourth transistor are commonly connected to the first control line, and the gate electrodes of the second transistor and the third transistor are commonly connected to the second control line.

8. The display device according to claim 7, wherein: The control driver is further configured to: During the first emission period, the first control signal having an on level is output to the first control line, and the second control signal having an off level is output to the second control line, and During the second emission period, the second control signal having the on-level is output to the second control line, and the first control signal having the off-level is output to the first control line.

9. The display device according to claim 8, wherein: The control driver is further configured to output the first control signal at the conduction level with a first duty ratio and the second control signal at the conduction level with a second duty ratio to the light emitting circuit of each of the plurality of pixels.

10. The display device according to claim 9, wherein: The first duty cycle of the first control signal and the second duty cycle of the second control signal are adjusted by the control driver to control the brightness of the display unit.

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