Image sensor

Abstract

The image sensor includes: a first organic optoelectronic conversion layer located on a base layer; a floating diffusion region located in the base layer; a first storage node including a first electrode layer configured to receive a bias signal, a first portion of a first semiconductor layer including a semiconductor material, and a first portion of a first dielectric layer. The first dielectric layer extends between the first electrode layer and the first semiconductor layer. The first storage node is electrically connected to the first organic optoelectronic conversion layer. The image sensor includes: a first transfer transistor including a first dielectric layer, a first semiconductor layer, and a first transfer gate electrode configured to receive a first transfer control signal. The first transfer transistor has a first end electrically connected to the first storage node and a second end electrically connected to the floating diffusion region.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2018 - 0120525, filed on October 10, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to an image sensor. Background art

[0004] An image sensor is a semiconductor device for converting optical information into an electrical signal. As semiconductor devices have become highly integrated, image sensors have also become highly integrated. Therefore, a shared structure may be required in which one or more pixel regions form a single unit pixel region and share pixel transistors. At the same time, each pixel region of the unit pixel region may include a semiconductor photoelectric conversion layer, and the unit pixel region may share an organic photoelectric conversion layer. In this case, transfer transistors corresponding to the semiconductor photoelectric conversion layer and the organic photoelectric conversion layer may be required. Summary of the invention

[0005] Embodiments of the inventive concept provide an image sensor including a storage node and a transfer transistor corresponding to an organic photoelectric conversion layer, and thus may reduce noise by increasing charge mobility.

[0006] However, embodiments of the inventive concept are not limited to those set forth herein. The above and other embodiments of the inventive concept will become more apparent to those of ordinary skill in the art to which the inventive concept pertains by referring to the detailed description of the embodiments of the inventive concept given below.

[0007] According to some embodiments of the inventive concept, there is provided an image sensor including: a first organic photoelectric conversion layer located on a base layer; a floating diffusion region located in the base layer; a first storage node including a first electrode layer configured to receive a bias signal, a first portion of a first semiconductor layer, and a first portion of a first dielectric layer extending between the first electrode layer and the first semiconductor layer, the first storage node being electrically connected to the first organic photoelectric conversion layer; and a first transfer transistor including a second portion of the first dielectric layer, a second portion of the first semiconductor layer, and a first transfer gate electrode configured to receive a first transfer control signal. The first transfer transistor has a first end electrically connected to the first storage node and a second end electrically connected to the floating diffusion region.

[0008] According to the above and other embodiments of the inventive concept, there is provided an image sensor including: a first organic optoelectronic conversion layer on a base layer; a first transfer gate electrode in the base layer; a first storage node in the base layer and including a first electrode layer, a first semiconductor layer, and a first dielectric layer extending between the first electrode layer and the first semiconductor layer; and a via electrode extending through the base layer to connect the first organic optoelectronic conversion layer and the first storage node. The first electrode layer is spaced apart from the first transfer gate electrode, and the first dielectric layer and the first semiconductor layer are stacked on the first transfer gate electrode.

[0009] According to the above and other embodiments of the inventive concept, there is provided an image sensor including: a first organic optoelectronic conversion layer on a base layer; an insertion layer between the base layer and the first organic optoelectronic conversion layer; a first dielectric layer between the first organic optoelectronic conversion layer and the insertion layer; a first semiconductor layer between the first dielectric layer and the first organic optoelectronic conversion layer; a first via electrode extending from the first semiconductor layer into the base layer to connect to a first wiring in the base layer; and a second via electrode extending from the insertion layer into the base layer to be electrically connected to a second wiring in the base layer, the second via electrode being spaced apart from the first via electrode.

[0010] Other features and embodiments will become apparent from the following detailed description, drawings, and claims. Description of the Drawings

[0011] The above and other embodiments and features of the inventive concept will become more apparent by describing embodiments of the inventive concept in detail with reference to the drawings, in which:

[0012] Figure 1 is a schematic diagram showing a base layer of an image sensor according to some embodiments of the inventive concept;

[0013] Figure 2 is a layout diagram showing a unit pixel region of an image sensor according to some embodiments of the inventive concept;

[0014] Figure 3 、 Figure 8 and Figure 12 are circuit diagrams of an image sensor according to some embodiments of the inventive concept;

[0015] Figure 4 、 Figure 6 、 Figure 7 、 Figure 9 、 Figure 11 、 Figure 13 and Figure 15 are cross-sectional views showing a pixel region of an image sensor according to some embodiments of the inventive concept;

[0016] Figure 5 is an enlarged view of region J that shows Figure 4 ;

[0017] Figure 10 is an enlarged view of region K that shows Figure 9 ; and

[0018] Figure 14 is an enlarged view of region M that shows Figure 13 . DETAILED DESCRIPTION

[0019] It should be noted that although aspects of the inventive concept described with reference to one embodiment are not specifically described with reference to different embodiments, these aspects may be included in different embodiments. That is, all embodiments and / or features of any embodiment may be combined in any manner and / or combination. These and other objects and / or aspects of the inventive concept are explained in detail in the following description. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. When an expression such as "at least one" follows a list of elements, it modifies the entire list of elements and not individual elements in the list. Hereinafter, an image sensor according to some embodiments of the inventive concept will be described with reference to Figures 1 to 5 . Referring to Figure 1 , the base layer 100 may include a sensor array region I and a peripheral circuit region II. For example, the sensor array region I may be a region in which an active pixel sensor array capable of converting an optical signal into an electrical signal is formed. The active pixel sensor array may include a plurality of unit pixel regions. The plurality of unit pixel regions may include a unit pixel region PU. The peripheral circuit region II may be formed to surround the sensor array region I, but the inventive concept is not limited thereto. For example, the peripheral circuit region II may be a region in which a correlated double sampler capable of double sampling a specific noise level and an electrical signal level and outputting a difference between the noise level and the electrical signal level and an analog-to-digital converter capable of converting an analog signal output from the correlated double sampler into a digital signal are formed.

[0020] Figure 2 is an enlarged view of the unit pixel region PU that is part of the sensor array region I of Figure 1 . For clarity, Figure 2 does not show elements other than the unit pixel region PU and the pixel transistor formation region PXTR. Referring to Figure 2 and Figure 3 , the unit pixel region PU may include a pixel transistor formation region PXTR and at least one pixel region PR. For example, the pixel transistor formation region PXTR may be around and / or surround the pixel region PR. The unit pixel region PU is inFigure 2 It is shown in the middle as including a single pixel region PR, but the inventive concept is not limited thereto. Alternatively, the unit pixel region PU may include a plurality of pixel regions, and the plurality of pixel regions may be isolated from each other. The plurality of pixel regions may share a pixel transistor formation region PXTR.

[0021] For example, the unit pixel region PU may include a first storage node SN1, a semiconductor photoelectric conversion layer PD, a first organic photoelectric conversion layer OPD1, a first transfer transistor TR1 and a second transfer transistor TR2, a floating diffusion region FD, a reset transistor TRR, a source follower transistor SF, and a selection transistor SEL. It should be understood that although terms such as first, second, third, etc. are used herein to describe various elements, the elements should not be limited by these terms. Instead, these terms are only used to distinguish one element from another. Thus, without departing from the scope of the inventive concept, the first element discussed may be referred to as the second element.

[0022] The first storage node SN1, the semiconductor photoelectric conversion layer PD, the first transfer transistor TR1, the second transfer transistor TR2, and the floating diffusion region FD may form a first group GA. The reset transistor TRR, the source follower transistor SF, and the selection transistor SEL may form a second group GB. In some embodiments, the first group GA may be disposed in the pixel region PR, and the second group GB may be disposed in the pixel transistor formation region PXTR. For example, the first organic photoelectric conversion layer OPD1 may be disposed only in the pixel region PR, or disposed in both the pixel region PR and the pixel transistor formation region PXTR.

[0023] For example, the semiconductor photoelectric conversion layer PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof. The semiconductor photoelectric conversion layer PD and the first organic photoelectric conversion layer OPD1 may detect light of different wavelengths. The semiconductor photoelectric conversion layer PD and the first organic photoelectric conversion layer OPD1 may receive light (e.g., Figure 6 the L in Figure 6 through a microlens (e.g., the ML in

[0024] and may generate a first optical signal and a second optical signal in proportion to the amount of light L incident thereon, respectively.

[0025] A first end of the first transfer transistor TR1 may be connected to a second end of the first storage node SN1 and the first organic optoelectronic conversion layer OPD1, and a second end of the first transfer transistor TR1 may be connected to the floating diffusion region FD. A first transfer gate TG1 of the first transfer transistor TR1 may be gated by a first transfer control signal TX1.

[0026] When the first transfer transistor TR1 is turned off and a bias signal S1 is input to the first storage node SN1, the first storage node SN1 may store a first optical signal, which is charge generated by the first organic optoelectronic conversion layer OPD1. When the first transfer transistor TR1 is turned off and the bias signal S1 is input to the first storage node SN1, the reset transistor TRR may reset the floating diffusion region FD to the power supply voltage V DD . When the first optical signal generated by the first organic optoelectronic conversion layer OPD1 is stored in the first storage node SN1 and the first transfer transistor TR1 connecting the first storage node SN1 and the floating diffusion region FD is turned off, the floating diffusion region FD may be reset to the power supply voltage V DD to ensure the reliability of the operation of the image sensor according to some embodiments of the inventive concept.

[0027] When the first transfer transistor TR1 is turned on by the first transfer control signal TX1, the first transfer transistor TR1 may transfer the first optical signal stored in the first storage node SN1 to the floating diffusion region FD. The first transfer transistor TR1 does not have to be always turned on. In other words, since the first storage node SN1 stores the first optical signal, the first optical signal may be transferred to the floating diffusion region FD by turning on the first transfer transistor TR1 when necessary. Accordingly, the power consumption of the image sensor according to some embodiments of the inventive concept may be reduced. In addition, since the image sensor according to some embodiments of the inventive concept uses the first storage node SN1 always input with the bias signal S1 and the first transfer transistor TR1 corresponding to the first organic optoelectronic conversion layer OPD1, the first optical signal may be accurately transferred to the floating diffusion region FD.

[0028] A first end of the second transfer transistor TR2 may be connected to the semiconductor optoelectronic conversion layer PD, and a second end of the second transfer transistor TR2 may be connected to the floating diffusion region FD. A second transfer gate TG2 of the second transfer transistor TR2 may be gated by a second transfer control signal TX2. The second transfer transistor TR2 may transfer a second optical signal (i.e., charge generated by the semiconductor optoelectronic conversion layer PD) to the floating diffusion region FD according to the second transfer control signal TX2. The first transfer transistor TR1 and the second transfer transistor TR2 may share the floating diffusion region FD. The floating diffusion region FD may receive and cumulatively store the first optical signal and / or the second optical signal.

[0029] The first terminal of the reset transistor TRR may be connected to the power supply voltage V DD , and the second terminal of the reset transistor TRR may be connected to the floating diffusion region FD. The reset gate RG of the reset transistor TRR may be gated by a reset control signal RX. The reset transistor TRR may reset the floating diffusion region FD to the power supply voltage V DD . The first terminal of the source follower transistor SF may be connected to the power supply voltage V DD , and the second terminal of the source follower transistor SF may be connected to the first terminal of the selection transistor SEL. The source follower transistor SF may be a driving transistor capable of generating an output voltage Vout by being controlled by the floating diffusion region FD. The source follower transistor SF may be combined with a constant current source located outside the unit pixel region PU, and thus may be used as a source follower buffer amplifier. In addition, the source follower transistor SF may amplify the potential change in the floating diffusion region FD and may generate the output voltage Vout. The output voltage Vout may be output to the selection transistor SEL. The first terminal of the selection transistor SEL may be connected to the second terminal of the source follower transistor SF, and the second terminal of the selection transistor SEL may be connected to the column line CL. The selection transistor SEL may be gated by a selection control signal SX. The selection transistor SEL may output the output voltage Vout to the column line CL connected to the unit pixel region PU.

[0030] Reference Figure 4 and Figure 5 , an image sensor according to some embodiments of the inventive concept may include a base layer 100, a first interlayer insulating film 201, a first dielectric layer 211, a first semiconductor layer 221, a first organic photoelectric conversion layer OPD1, a first upper electrode layer 231, and a microlens ML.

[0031] The first interlayer insulating film 201, the first dielectric layer 211, the first semiconductor layer 221, the first organic photoelectric conversion layer OPD1, the first upper electrode layer 231, and the microlens ML may be disposed on the base layer 100. The base layer 100 may include a first interlayer insulating film 103, a substrate 101, a protective planarization film 107, and a second interlayer insulating film 105. The substrate 101, the protective planarization film 107, and the second interlayer insulating film 105 may be sequentially stacked on the first interlayer insulating film 103.

[0032] The substrate 101 may include a first surface 101_1 and a second surface 101_2 that face each other. The second surface 101_2 of the substrate 101 may be the surface on which the light L is incident. For example, the substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate 101 may be a silicon substrate or may include other materials such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In some embodiments, the substrate 101 may have an epitaxial layer formed on its base substrate. Hereinafter, the substrate 101 will be described as a silicon substrate.

[0033] The semiconductor photoelectric conversion layer PD may be disposed in the base layer 100. For example, the semiconductor photoelectric conversion layer PD may be disposed in the substrate 101 of the pixel region PR. The semiconductor photoelectric conversion layer PD may be formed by doping impurities having a conductivity type opposite to that of the substrate 101 into the interior of the substrate 101. The impurity concentration may be different between the upper and lower portions of the semiconductor photoelectric conversion layer PD to have a potential gradient along the first direction D1. For example, the semiconductor photoelectric conversion layer PD may be formed by stacking a plurality of impurity regions. Here, the first direction D1 may be the direction from the second surface 101_2 of the substrate 101 facing the first surface 101_1 of the substrate 101.

[0034] The floating diffusion region FD may be disposed in the base layer 100. The floating diffusion region FD may be disposed in the substrate 101 on one side of the first surface 101_1 of the substrate 101 in the pixel region PR.

[0035] The second transfer gate TG2 may be disposed on the first surface 101_1 of the substrate 101. The floating diffusion region FD may be disposed on one side of the second transfer gate TG2. The source region 124 of the second transfer transistor TR2 may be disposed on the other side of the second transfer gate TG2. The source region 124 of the second transfer transistor TR2 may be disposed in the substrate 101 on one side of the first surface 101_1 of the substrate 101. The drain region of the second transfer transistor TR2 may be the floating diffusion region FD. The second transfer gate TG2 may include a second transfer gate electrode 120 and a second transfer gate insulating film 121.

[0036] In some embodiments, the second transfer gate electrode 120 may include a first portion and a second portion. The first portion of the second transfer gate electrode 120 may be disposed in the substrate 101. The first portion of the second transfer gate electrode 120 may extend from the first surface 101_1 of the substrate 101 toward the second surface 101_2 of the substrate 101. The first portion of the second transfer gate electrode 120 may be disposed on the second portion of the second transfer gate electrode 120. The second portion of the second transfer gate electrode 120 may protrude from the first surface 101_1 of the substrate 101 in the first direction D1. The second portion of the second transfer gate electrode 120 may be disposed in the first interlayer insulating film 103.

[0037] In some embodiments, the width of the first portion of the second transfer gate electrode 120 may be less than the width of the second portion of the second transfer gate electrode 120. In some embodiments, the width of the first portion of the second transfer gate electrode 120 may be substantially the same as the width of the second portion of the second transfer gate electrode 120. The widths of the first portion and the second portion of the second transfer gate electrode 120 may be measured in the second direction D2. For example, the second transfer gate electrode 120 may include a conductive material. For example, the conductive material may include doped polysilicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium (Ti), tantalum (Ta), or tungsten (W), but the inventive concept is not limited thereto.

[0038] The second transfer gate insulating film 121 may be inserted between the second transfer gate electrode 120 and the substrate 101. For example, the second transfer gate insulating film 121 may be disposed between the second portion of the second transfer gate electrode 120 and the first surface 101_1 of the substrate 101 and between the first portion of the second transfer gate electrode 120 and the substrate 101. For example, the second transfer gate insulating film 121 may include a high-k material. For example, the high-k material may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, or lanthanum aluminum oxide, but the inventive concept is not limited thereto. In some embodiments, the second transfer gate insulating film 121 may include a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0039] The second transfer gate spacers 123 may be disposed on both sides of the second portion of the second transfer gate electrode 120. The second transfer gate spacers 123 may be disposed in the first interlayer insulating film 103. For example, the second transfer gate spacers 123 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), and combinations thereof.

[0040] The protective planarization film 107 may be disposed on the second surface 101_2 of the substrate 101. The protective planarization film 107 may be a high-concentration impurity layer and may be formed by doping the substrate 101 with a P-type impurity such as boron (B), but the inventive concept is not limited thereto. In some embodiments, the protective planarization film 107 may be formed of an oxide film having a negative charge. The protective planarization film 107 may reduce or possibly prevent the generation of a depletion well on the surface adjacent to the substrate 101 due to, for example, dangling bond defects of silicon, surface defects caused by etching stress, or potential reduction caused by interface traps. In addition, the protective planarization film 107 may provide a potential gradient such that photo charges generated near the substrate 101 may flow into the floating diffusion region FD.

[0041] The second interlayer insulating film 105 may be disposed on the protective planarization film 107. The second interlayer insulating film 105 may include an insulating material.

[0042] The color filter CF may be disposed in the second interlayer insulating film 105 on the protective planarization film 107. The color filter CF may be disposed between the semiconductor photoelectric conversion layer PD and the first organic photoelectric conversion layer OPD1. The color filter CF may allow light L of a specific wavelength to pass therethrough. For example, the color filter CF may allow light L that has not been converted into an electrical signal by the first organic photoelectric conversion layer OPD1 to pass therethrough.

[0043] The first insertion layer 201 may be disposed on the second interlayer insulating film 105. The first insertion layer 201 may be disposed between the base layer 100 and the first organic photoelectric conversion layer OPD1. The first insertion layer 201 may include a first electrode layer 201a, a first insulating pattern 201P1, a first transfer gate electrode 201b, a second insulating pattern 201P2, and a first pad 201c. The first electrode layer 201a and the first transfer gate electrode 201b may be separated by the first insulating pattern 201P1. The first transfer gate electrode 201b and the first pad 201c may be separated by the second insulating pattern 201P2. For example, the first insulating pattern 201P1 and the second insulating pattern 201P2 may include the same material as the material of the second interlayer insulating film 105.

[0044] A bias signal S1 may be input to the first electrode layer 201a. For example, the first electrode layer 201a and the first transfer gate electrode 201b may be transparent electrodes. For example, the first electrode layer 201a and the first transfer gate electrode 201b may include indium tin oxide (ITO). The first pad 201c may include a conductive material.

[0045] The first dielectric layer 211 may be disposed between the first organic optoelectronic conversion layer OPD1 and the first insertion layer 201. The first dielectric layer 211 may extend between the first electrode layer 201a and the first semiconductor layer 221 and may not completely cover the first pad 201c.

[0046] The first dielectric layer 211 may include a first portion 211a and a second portion 211b. The first portion 211a of the first dielectric layer 211 may overlap with the first electrode layer 201a in the first direction D1. For example, the first portion 211a of the first dielectric layer 211 may be the portion of the first dielectric layer 211 between the first electrode layer 201a and the first semiconductor layer 221. The second portion 211b of the first dielectric layer 211 may overlap with the first transfer gate electrode 201b in the first direction D1. For example, the second portion 211b of the first dielectric layer 211 may be the portion of the first dielectric layer 211 between the first transfer gate electrode 201b and the first semiconductor layer 221. The first dielectric layer 211 may include a dielectric material. For example, the first dielectric layer 211 may include one of aluminum oxide, silicon nitride, silicon oxide, and combinations thereof. For example, the first dielectric layer 211 may include Al 2 O 3 and SiO 2 one of them. For example, the first dielectric layer 211 may include an organic insulator.

[0047] The first semiconductor layer 221 may include a first portion 221_1 and a second portion 221_2. The first portion 221_1 of the first semiconductor layer 221 may be disposed on the first dielectric layer 211. The second portion 221_2 of the first semiconductor layer 221 may be the portion of the first semiconductor layer 221 that is inserted into the first dielectric layer 211 from the first portion 221_1 of the first semiconductor layer 221. The second portion 221_2 of the first semiconductor layer 221 may protrude from the first portion 221_1 of the first semiconductor layer 221 toward the base layer 100 in the first direction D1. For example, the second portion 221_2 of the first semiconductor layer 221 may pass through the first dielectric layer 211.

[0048] The first portion 221_1 of the first semiconductor layer 221 may include a first region 221a and a second region 221b. The first region 221a of the first portion 221_1 of the first semiconductor layer 221 may be the portion of the first portion 221_1 that overlaps with the first electrode layer 201a and the first portion 211a of the first dielectric layer 211 in the first direction D1. The second region 221b of the first portion 221_1 of the first semiconductor layer 221 may be the portion of the first portion 221_1 that overlaps with the first transfer gate electrode 201b and the second portion 211b of the first dielectric layer 211 in the first direction D1. For example, the first semiconductor layer 221 may include a semiconductor material. For example, the first semiconductor layer 221 may include CdSe, CdS, ZnO, SnO 2 , MoS 2 , TiO 2 , Fe 2 O 3 , WO 3 , InGaZnO, ZnO-Rh 2 O 3 , In 2 O 3 , ZnInO, InGaO, InZnO, ZnSnO, and one of their combinations. For example, the first semiconductor layer 221 may include indium gallium zinc oxide (IGZO). For example, the first semiconductor layer 221 may include an organic semiconductor. For example, the first semiconductor layer 221 may include dibenzothieno[6,5-b:6',5'-f]thieno[3,2-b]thiophene (DBTTT).

[0049] The first electrode layer 201a, the first portion 211a of the first dielectric layer 211, and the first region 221a of the first portion 221_1 of the first semiconductor layer 221 may be sequentially stacked on the base layer 100 to form Figure 3 the first storage node SN1. The first transfer gate electrode 201b, the second portion 211b of the first dielectric layer 211, and the second region 221b of the first portion 221_1 of the first semiconductor layer 221 may be sequentially stacked on the base layer 100 to form Figure 3 the first transfer transistor TR1.

[0050] The first organic optoelectronic conversion layer OPD1 may be disposed on the first semiconductor layer 221. For example, the first organic optoelectronic conversion layer OPD1 may generate an electrical signal (i.e., a first optical signal) in response to light L of a specific color incident thereon via the microlens ML. For example, the first organic optoelectronic conversion layer OPD1 may generate charges (e.g., electrons) in response to light L incident thereon via the microlens ML. For example, the first organic optoelectronic conversion layer OPD1 may include a non-silicon material such as an organic semiconductor, a quantum dot material, a chalcogenide, or an amorphous silicon (a-Si) material.

[0051] The first upper electrode layer 231 may be disposed on the first organic optoelectronic conversion layer OPD1. For example, different voltages may be input to the first upper electrode layer 231 and the first electrode layer 201a. Additionally, for example, different voltages may be input to the first upper electrode layer 231 and the first transfer gate electrode 201b. The microlens ML may be disposed on the first upper electrode layer 231. The microlens ML may have a convex shape and may have a predetermined radius of curvature. The microlens ML may be formed of, for example, a light-transmitting resin. The microlens ML may converge the light L into the pixel region PR.

[0052] The first interlayer insulating film 103 may be disposed under the first surface 101_1 of the substrate 101. The first interlayer insulating film 103 may include an insulating material. For example, the first interlayer insulating film 103 may include a high density plasma (HDP) layer, a tosyl azide (TOSZ) layer, a spin-on glass (SOG) layer, or an undoped silicon glass (USG), but the inventive concept is not limited thereto. The first interlayer insulating film 103 may include a first wiring 151, a second wiring 152, and a third wiring 153, which are disposed in the first interlayer insulating film 103 and spaced apart from each other. Each of the first wiring 151, the second wiring 152, and the third wiring 153 may include a conductive material.

[0053] The first wiring 151 may be connected to the first semiconductor layer 221 via the first via electrode 131. The first via electrode 131 may extend through the base layer 100 from the first pad 201c of the first insertion layer 201 to the first wiring 151. The first via electrode 131 may be connected to the second portion 221_2 of the first semiconductor layer 221 via the first pad 201c. For example, the first via electrode 131 may pass through the second interlayer insulating film 105, the protective planarization film 107, and the substrate 101, and may extend through a portion of the first interlayer insulating film 103. The first via electrode 131 may be spaced apart from the first electrode layer 201a and the first transfer gate electrode 201b. The first via electrode 131 may include a first portion 131a, a second portion 131b, and a third portion 131c.

[0054] The first part 131a of the first through electrode 131 may be disposed in the second interlayer insulating film 105 and the protective planarization film 107. For example, the first part 131a of the first through electrode 131 may be in contact with the first pad 201c. The second part 131b of the first through electrode 131 may be disposed in the substrate 101. For example, the second part 131b of the first through electrode 131 may be surrounded by the first insulating film 141 and / or surround the first insulating film 141. The third part 131c of the first through electrode 131 may be disposed in the first interlayer insulating film 103. For example, the third part 131c of the first through electrode 131 may be in contact with the first wiring 151.

[0055] The first wiring 151 may be connected to the floating diffusion region FD via the first wiring layer 160. For example, the first wiring 151 may be directly connected to the first contact 161. Additionally, the floating diffusion region FD may be directly connected to the second contact 162. The first contact 161 and the second contact 162 may be connected by the first wiring 163. For example, the first wiring 163 may be connected to Figure 3 the second end of the reset transistor TRR in

[0056] The second wiring 152 may be connected to the first transfer gate electrode 201b via the second through electrode 132. The first transfer control signal TX1 may be input to the first transfer gate electrode 201b via the second wiring 152 and the second through electrode 132. The second through electrode 132 may extend through the base layer 100 from the first transfer gate electrode 201b of the first insertion layer 201 to the second wiring 152. For example, the second through electrode 132 may pass through the second interlayer insulating film 105, the protective planarization film 107, and the substrate 101, and may extend through a portion of the first interlayer insulating film 103. The second through electrode 132 may be spaced apart from the first through electrode 131. The second through electrode 132 may also be spaced apart from the first pad 201c and the first electrode layer 201a. The second through electrode 132 may include a first part 132a, a second part 132b, and a third part 132c.

[0057] The first part 132a of the second through electrode 132 may be disposed in the second interlayer insulating film 105 and the protective planarization film 107. For example, the first part 132a of the second through electrode 132 may be in contact with the first transfer gate electrode 201b. The second part 132b of the second through electrode 132 may be disposed in the substrate 101. For example, the second part 132b of the second through electrode 132 may be surrounded by the first insulating film 141 and / or surround the first insulating film 141. The third part 132c of the second through electrode 132 may be disposed in the first interlayer insulating film 103. For example, the third part 132c of the second through electrode 132 may be in contact with the second wiring 152.

[0058] The third wiring 153 may be connected to the second transfer gate TG2 via the third contact 139. The third contact 139 may extend in the first interlayer insulating film 103 from the second transfer gate electrode 120 to the third wiring 153.

[0059] Figure 4 It is shown that the sidewalls of the first through electrode 131, the sidewalls of the second through electrode 132, and the sidewalls of each of the first contact 161, the second contact 162, and the third contact 139 are perpendicular to the first surface 101_1 of the substrate 101, but the inventive concept is not limited thereto. Alternatively, the sidewalls of the first through electrode 131, the sidewalls of the second through electrode 132, and the sidewalls of each of the first contact 161, the second contact 162, and the third contact 139 may have a predetermined slope with respect to the first surface 101_1 of the substrate 101. Additionally, the sidewalls of the first portion 131a of the first through electrode 131, the sidewalls of the second portion 131b of the first through electrode 131, and the sidewalls of the third portion 131c of the first through electrode 131 may have different slopes with respect to the first surface 101_1 of the substrate 101. Additionally, the sidewalls of the first portion 132a of the second through electrode 132, the sidewalls of the second portion 132b of the second through electrode 132, and the sidewalls of the third portion 132c of the second through electrode 132 may have different slopes with respect to the first surface 101_1 of the substrate 101.

[0060] Figure 4 It is shown that the first portion 131a and the second portion 131b of the first through electrode 131 have the same width, and the third portion 131c of the first through electrode 131 has a width different from the widths of the first portion 131a and the second portion 131b of the first through electrode 131, but the inventive concept is not limited thereto. In some embodiments, all of the first portion 131a, the second portion 131b, and the third portion 131c of the first through electrode 131 may have different widths. Additionally, Figure 4 It is shown that the first portion 132a and the second portion 132b of the second through electrode 132 have the same width, and the third portion 132c of the second through electrode 132 has a width different from the widths of the first portion 132a and the second portion 132b of the second through electrode 132, but the inventive concept is not limited thereto. In some embodiments, all of the first portion 132a, the second portion 132b, and the third portion 132c of the second through electrode 132 may have different widths.

[0061] For example, the first through electrode 131 and the second through electrode 132 may include a conductive material. For example, the first through electrode 131 and the second through electrode 132 may include one of tungsten, aluminum, copper, and doped silicon. Additionally, for example, the first through electrode 131 and the second through electrode 132 may include a combination of a metal material and doped silicon.

[0062] Figure 3 The bias signal S1 in Figure 5 may be input to the first electrode layer 201a of the first storage node SN1 in. In response to light L incident on the microlens ML, the first organic optoelectronic conversion layer OPD1 may generate charges (e.g., electrons). Due to the bias signal S1 input to the first electrode layer 201a of the first storage node SN1, in Figure 5 the first region 221a of the first part 221_1 of the first semiconductor layer 221 of the first storage node SN1 in, the charges (i.e., the first optical signal) generated by the first organic optoelectronic conversion layer OPD1 may be captured. When the first transfer control signal TX1 has not been applied to the first transfer gate electrode 201b, due to the potential barrier of the first transfer gate electrode 201b, the captured charges may not move to the second part 221_2 of the first semiconductor layer 221.

[0063] While the charges (i.e., the first optical signal) generated by the first organic optoelectronic conversion layer OPD1 are captured in the first region 221a of the first part 221_1 of the first semiconductor layer 221 because the first transfer control signal TX1 has not been applied to the first transfer gate electrode 201b, Figure 3 the reset transistor TRR in may reset the floating diffusion region FD to the power supply voltage V DD .

[0064] After the floating diffusion region FD is reset, the first transfer control signal TX1 may be input to the first transfer gate electrode 201b via the second wiring 152 and the second through electrode 132. The first transfer gate electrode 201b, the second part 211b of the first dielectric layer 211, and the second region 221b of the first part 221_1 of the first semiconductor layer 221 may form a metal-oxide-semiconductor (MOS) transistor (e.g., the first transfer transistor TR1). As the first transfer control signal TX1 is input to the first transfer gate electrode 201b, the potential barrier of the first transfer gate electrode 201b can be reduced. Due to the reduction of the potential barrier of the first transfer gate electrode 201b, the charges captured in the first region 221a of the first part 221_1 of the first semiconductor layer 221 may move to the second part 221_2 of the first semiconductor layer 221 and may be accumulated in the floating diffusion region FD via the first through electrode 131.

[0065] In response to light L incident on the microlens ML, the semiconductor photoelectric conversion layer PD may generate charges (i.e., the second optical signal). Since the second transfer control signal TX2 is input via the third wiring 153 and the third contact 139, the charges generated by the semiconductor photoelectric conversion layer PD may move to and accumulate in the floating diffusion region FD.

[0066] In the image sensor according to some embodiments of the inventive concept, since the first transfer gate electrode 201b is disposed between the base layer 100 and the first dielectric layer 211, the mobility of the charges generated by the first organic photoelectric conversion layer OPD1 may be improved. In addition, by moving all the charges captured in the first region 221a of the first portion 221_1 of the first semiconductor layer 221 to the second portion 221_2 of the first semiconductor layer 221, noise may be reduced. In addition, by not applying the first transfer control signal TX1 to the first transfer gate electrode 201b, charges may be captured in the first region 221a of the first portion 221_1 of the first semiconductor layer 221, and as a result, the reset accuracy of the floating diffusion region FD may be improved.

[0067] Hereinafter, reference will be made to Figure 2 、 Figure 3 and Figure 6 to describe an image sensor according to some embodiments of the inventive concept. For clarity, the description of the elements and features that have been described above will be omitted or at least simplified. Referring to Figure 2 、 Figure 3 and Figure 6 , the first insertion layer 201' may not include the first electrode layer 201a. The first transfer gate electrode 201b, the first dielectric layer 211, and the first semiconductor layer 221 may together form the first storage node SN1 and may also together form the first transfer transistor TR1. In response to the bias signal S1 being applied to the first transfer gate electrode 201b, the charges generated by the first organic photoelectric conversion layer OPD1 may be captured in the first semiconductor layer 221. In response to the first transfer control signal TX1 being applied to the first transfer gate electrode 201b via the second wiring 152 and the second through electrode 132, the charges generated by the first organic photoelectric conversion layer OPD1 may move to the floating diffusion region FD via the first through electrode 131.

[0068] Hereinafter, reference will be made to Figure 2 、 Figure 3 and Figure 7 to describe an image sensor according to some embodiments of the inventive concept. For clarity, the description of the elements and features that have been described above will be omitted or at least simplified. Referring to Figure 2 、 Figure 3 and Figure 7, the first storage node SN1 and the first transfer transistor TR1 may be disposed in the base layer 100. For example, the first storage node SN1 and the first transfer transistor TR1 may be disposed in the first interlayer insulating film 103. The first storage node SN1 may include a first electrode layer 201a, a first portion 211a of the first dielectric layer 211, and a first region 221a of the first semiconductor layer 221. The first transfer transistor TR1 may include a first transfer gate electrode 201b, a second portion 211b of the first dielectric layer 211, and a second region 221b of the first semiconductor layer 221.

[0069] The first insertion layer 201” may include only the first pad 201c. The first through electrode 131 may connect the first organic optoelectronic conversion layer OPD1 and the first storage node SN1. For example, the first wiring 151 may be connected to the first storage node SN1 via the first contact 161. Therefore, the first through electrode 131 may electrically connect the first organic optoelectronic conversion layer OPD1 and the first storage node SN1 by using the first pad 201c, the first wiring 151, and the first contact 161.

[0070] The first electrode layer 201a and the first transfer gate electrode 201b may be spaced apart from each other and may be disposed in the first interlayer insulating film 103. The first dielectric layer 211 may be disposed on the first electrode layer 201a and the first transfer gate electrode 201b. The first semiconductor layer 221 may be disposed on the first dielectric layer 211. For example, the first semiconductor layer 221 may be in contact with the first contact 161. The first region 221a of the first semiconductor layer 221 may overlap the first electrode layer 201a and the first portion 211a of the first dielectric layer 211 in the first direction D1. The second region 221b of the first semiconductor layer 221 may overlap the first transfer gate electrode 201b and the second portion 211b of the first dielectric layer 211 in the first direction D1.

[0071] In some embodiments, the first electrode layer 201a, the first transfer gate electrode 201b, the first dielectric layer 211, and the first semiconductor layer 221 may be formed in the back-end-of-line (BEOL) processing stage. By forming the first storage node SN1 and the first transfer transistor TR1 in the base layer 100 (specifically, in the first interlayer insulating film 103), the threshold voltage of the first transfer gate TG1 can be made stable.

[0072] The second contact 162 and the first connection line 163 may connect the first transfer transistor TR1 and the floating diffusion region FD by using the first semiconductor layer 221.

[0073] The bias signal S1 can be input to the first electrode layer 201a of the first storage node SN1. In response to light L being incident on the microlens ML, the first organic optoelectronic conversion layer OPD1 can generate charges (e.g., electrons). The charges generated by the first organic optoelectronic conversion layer OPD1 (i.e., the first optical signal) can move to the first region 221a of the first semiconductor layer 221 via the first pad 201c, the first through electrode 131, the first wiring 151, and the first contact 161. When the first transfer control signal TX1 has not been applied to the first transfer gate electrode 201b, due to the barrier of the first transfer gate electrode 201b, the charges generated by the first organic optoelectronic conversion layer OPD1 can be trapped in the first region 221a of the first semiconductor layer 221.

[0074] While the charges generated by the first organic optoelectronic conversion layer OPD1 are trapped in the first region 221a of the first semiconductor layer 221 because the first transfer control signal TX1 has not been applied to the first transfer gate electrode 201b, the reset transistor TRR can reset the floating diffusion region FD to the power supply voltage V DD .

[0075] After the floating diffusion region FD is reset, the first transfer control signal TX1 can be input to the first transfer gate electrode 201b. The first transfer gate electrode 201b, the second portion 211b of the first dielectric layer 211, and the second region 221b of the first semiconductor layer 221 can form a MOS transistor (e.g., the first transfer transistor TR1). As the first transfer control signal TX1 is input to the first transfer gate electrode 201b, the barrier of the first transfer gate electrode 201b can be reduced. Due to the reduction of the barrier of the first transfer gate electrode 201b, the charges trapped in the first region 221a of the first semiconductor layer 221 can move to and accumulate in the floating diffusion region FD via the first connection line 163 and the second contact 162.

[0076] Hereinafter, reference will be made to Figure 2 , Figure 8 , Figure 9 and Figure 10 to describe an image sensor according to some embodiments of the inventive concept. For clarity, the description of the elements and features that have been described above will be omitted or at least simplified. Reference will be made to Figure 2 , Figure 8 , Figure 9 and Figure 10, An image sensor according to some embodiments of the inventive concept may further include a third through electrode 133, a second organic photoelectric conversion layer OPD2, a second storage node SN2, and a third transfer transistor TR3. The second storage node SN2 and the third transfer transistor TR3 may be included in the first group GA. A first end of the second storage node SN2 may receive a bias signal S1. A second end of the second storage node SN2 may be connected to a first end of the third transfer transistor TR3 and the second photoelectric conversion layer OPD2.

[0077] The first end of the third transfer transistor TR3 may be connected to the second end of the second storage node SN2 and the second organic photoelectric conversion layer OPD2, and a second end of the third transfer transistor TR3 may be connected to the floating diffusion region FD. A third transfer gate TG3 of the third transfer transistor TR3 may be gated by a third transfer control signal TX3.

[0078] The first upper electrode layer 231 may surround and / or enclose the third interlayer insulating film 109. The second insertion layer 202 may be disposed on the third interlayer insulating film 109. The second insertion layer 202 may include a second electrode layer 202a, a third insulating pattern 202P1, a third transfer gate electrode 202b, a fourth insulating pattern 202P2, and a second pad 202c. The bias signal S1 may be input to the second electrode layer 202a. The second electrode layer 202a and the third transfer gate electrode 202b may be separated by the third insulating pattern 202P1. The third transfer gate electrode 202b and the second pad 202c may be separated by the fourth insulating pattern 202P2.

[0079] The above description of Figure 4 and Figure 5 the first electrode layer 201a, the first insulating pattern 201P1, the second insulating pattern 201P2, the first dielectric layer 211, and the first semiconductor layer 221 in

[0080] may be directly applied to the second electrode layer 202a, the third insulating pattern 202P1, the fourth insulating pattern 202P2, the second dielectric layer 212, and the second semiconductor layer 222.

[0081] The second organic optoelectronic conversion layer OPD2 may be disposed on the second semiconductor layer 222. For example, the second organic optoelectronic conversion layer OPD2 may generate an electrical signal (i.e., a third optical signal) in response to light L of a specific color incident thereon via the microlens ML. The second organic optoelectronic conversion layer OPD2 may respond to light L of a color different from the color of light that the first organic optoelectronic conversion layer OPD1 and the semiconductor optoelectronic conversion layer PD respond to. For example, the second organic optoelectronic conversion layer OPD2 may generate charges (e.g., electrons) in response to light L incident thereon via the microlens ML.

[0082] In the case where an image sensor according to some embodiments of the inventive concept includes the first organic optoelectronic conversion layer OPD1 and the second organic optoelectronic conversion layer OPD2, the image sensor according to some embodiments of the inventive concept may not include a color filter.

[0083] The second upper electrode layer 232 may be disposed on the second organic optoelectronic conversion layer OPD2. For example, different voltages may be input to the second upper electrode layer 232 and the second electrode layer 202a. Additionally, for example, different voltages may be input to the second upper electrode layer 232 and the third transfer gate electrode 202b. The first through electrode 131 may further include a fourth portion 131d. The fourth portion 131d of the first through electrode 131 may be a portion of the first through electrode 131 extending from the second pad 202c to the first pad 201c. The fourth portion 131d of the first through electrode 131 may be disposed in the third interlayer insulating film 109, the first upper electrode layer 231, the first organic optoelectronic conversion layer OPD1, and the first semiconductor layer 221. The fourth portion 131d of the first through electrode 131 may be connected to the first portion 131a of the first through electrode 131. The fourth portion 131d of the first through electrode 131 may be surrounded by the second insulating film 241 and / or may surround the second insulating film 241.

[0084] The first interlayer insulating film 103 may further include a fourth wiring 154. The fourth wiring 154 may be connected to the third transfer gate electrode 202b via the third through electrode 133. The third transfer control signal TX3 may be input to the third transfer gate electrode 202b via the fourth wiring 154 and the third through electrode 133.

[0085] The third through electrode 133 may extend from the third transfer gate electrode 202b of the second insertion layer 202 to the fourth wiring 154. The third through electrode 133 may be spaced apart from the first through electrode 131 and the second through electrode 132. The third through electrode 133 may include a first portion 133a, a second portion 133b, a third portion 133c, and a fourth portion 133d.

[0086] The first part 133a of the third through electrode 133 may be disposed in the second interlayer insulating film 105 and the protective planarization film 107. The second part 133b of the third through electrode 133 may be disposed in the substrate 101. For example, the second part 133b of the third through electrode 133 may be surrounded by and / or surround the first insulating film 141. The third part 133c of the third through electrode 133 may be disposed in the first interlayer insulating film 103. For example, the third part 133c of the third through electrode 133 may be in contact with the fourth wiring 154. The fourth part 133d of the third through electrode 133 may be disposed in the third interlayer insulating film 109, the first upper electrode layer 231, the first organic optoelectronic conversion layer OPD1, the first semiconductor layer 221, the first dielectric layer 211, and the first electrode layer 201a. The fourth part 133d of the third through electrode 133 may be surrounded by and / or surround the second insulating film 241.

[0087] The first electrode layer 201a and the second electrode layer 202b may be connected by the fourth through electrode 134. The fourth through electrode 134 may penetrate through the third interlayer insulating film 109.

[0088] Hereinafter, reference will be made to Figure 2 、 Figure 8 and Figure 11 to describe an image sensor according to some embodiments of the inventive concept. For clarity, descriptions of elements and features that have been described above will be omitted or at least simplified. Referring to Figure 2 、 Figure 8 and Figure 11 , the second storage node SN2 and the third transfer transistor TR3 may be disposed in the base layer 100. For example, the second storage node SN2 and the third transfer transistor TR3 may be disposed in the first interlayer insulating film 103. The second storage node SN2 may include a second electrode layer 202a, a first part 212a of the second dielectric layer 212, and a first region 222a of the second semiconductor layer 222. The third transfer transistor TR3 may include a third transfer gate electrode 202b, a second part 212b of the second dielectric layer 212, and a second region 222b of the second semiconductor layer 222.

[0089] The second insertion layer 202' may include only the second pad 202c. The second interlayer insulating film 105 may not include a color filter. The bias signal S1 may be input to the first electrode layer 201a and the second electrode layer 202a via the second wiring layer 170.

[0090] The third through electrode 133 may be connected to the second organic optoelectronic conversion layer OPD2 and the second storage node SN2. For example, the sixth wiring 156 in the first interlayer insulating film 103 may be connected to the second storage node SN2 via the fifth contact 165. Accordingly, the third through electrode 133 may connect the second organic optoelectronic conversion layer OPD2 and the second storage node SN2 by using the sixth wiring 156 and the fifth contact 165.

[0091] The above description of Figure 7 the first electrode layer 201a, the first transfer gate electrode 201b, the first dielectric layer 211, and the first semiconductor layer 221 in

[0092] may be directly applied to the second electrode layer 202a, the third transfer gate electrode 202b, the second dielectric layer 212, and the second semiconductor layer 222.

[0093] The first semiconductor layer 221 of the first storage node SN1 may be connected to the fifth wiring 155 via the fourth contact 164. The second semiconductor layer 222 of the second storage node SN2 may be connected to the seventh wiring 157 via the sixth contact 166. The fifth wiring 155 and the seventh wiring 157 may be connected to the floating diffusion region FD via the first semiconductor layer 221 and the second semiconductor layer 222, respectively.

[0094] Hereinafter, reference will be made to Figure 2 and Figures 12 to 14 to describe an image sensor according to some embodiments of the inventive concept. For clarity, descriptions of elements and features that have been described above will be omitted or at least simplified. Referring to Figure 2 and Figures 12 to 14 an image sensor according to some embodiments of the inventive concept may further include a fifth through electrode 135, a third organic optoelectronic conversion layer OPD3, a third storage node SN3, and a fourth transfer transistor TR4. The base layer 100 may include the first interlayer insulating film 103, but may not include the substrate 101 and the second interlayer insulating film 105.

[0095] The third storage node SN3 and the fourth transfer transistor TR4 may be included in the first group GA. A first end of the third storage node SN3 may receive a bias signal S1. A second end of the third storage node SN3 may be connected to the third organic optoelectronic conversion layer OPD3 and a first end of the fourth transfer transistor TR4.

[0096] The first end of the fourth transfer transistor TR4 may be connected to the second end of the third storage node SN3 and the third organic optoelectronic conversion layer OPD3, and the second end of the fourth transfer transistor TR4 may be connected to the floating diffusion region FD. The fourth transfer gate TG4 of the fourth transfer transistor TR4 may be gated by a fourth transfer control signal TX4.

[0097] The second upper electrode layer 232 may be surrounded by the fourth interlayer insulating film 110 and / or surround the fourth interlayer insulating film 110. The third insertion layer 203 may be disposed on the fourth interlayer insulating film 110. The third insertion layer 203 may include a third electrode layer 203a, a fifth insulating pattern 203P1, a fourth transfer gate electrode 203b, a sixth insulating pattern 203P2, and a third pad 203c. A bias signal S1 may be input to the third electrode layer 203a. The third electrode layer 203a and the fourth transfer gate electrode 203b may be separated by the fifth insulating pattern 203P1. The fourth transfer gate electrode 203b and the third pad 203c may be separated by the sixth insulating pattern 203P2.

[0098] The above description of Figure 4 and Figure 5 the first electrode layer 201a, the first insulating pattern 201P1, the second insulating pattern 202P2, the first dielectric layer 211, and the first semiconductor layer 221 in

[0099] may be directly applied to the third electrode layer 203a, the fifth insulating pattern 203P1, the sixth insulating pattern 203P2, the third dielectric layer 213, and the third semiconductor layer 223.

[0100] The third organic optoelectronic conversion layer OPD3 may be disposed on the third semiconductor layer 223. For example, the third organic optoelectronic conversion layer OPD3 may generate an electrical signal (i.e., a fourth optical signal) in response to light L of a specific color incident thereon via a microlens ML. The third organic optoelectronic conversion layer OPD3 may respond to light L of a color different from the colors of the light to which the first organic optoelectronic conversion layer OPD1 and the second organic optoelectronic conversion layer OPD2 respond. For example, the third organic optoelectronic conversion layer OPD3 may generate charges (e.g., electrons) in response to light L incident thereon via a microlens ML.

[0101] In a case where an image sensor according to some embodiments of the inventive concept includes a first organic photoelectric conversion layer OPD1, a second organic photoelectric conversion layer OPD2, and a third organic photoelectric conversion layer OPD3, the image sensor according to some embodiments of the inventive concept may not include a color filter.

[0102] The third upper electrode layer 233 may be disposed on the third organic photoelectric conversion layer OPD3. For example, different voltages may be input to the third upper electrode layer 233 and the third electrode layer 203a. Additionally, for example, different voltages may be input to the third upper electrode layer 233 and the fourth transfer gate electrode 203b.

[0103] The first through electrode 131 may include a third portion 131c, a fourth portion 131d, and a fifth portion 131e, but may not include a first portion 131a and a second portion 131b. The fifth portion 131e of the first through electrode 131 may be a portion of the first through electrode 131 extending from the third pad 203c to the second pad 201c. The fifth portion 131e of the first through electrode 131 may be disposed in the fourth interlayer insulating film 110, the second upper electrode layer 232, the second organic photoelectric conversion layer OPD2, the second semiconductor layer 222, and the second dielectric layer 212. The fifth portion 131e of the first through electrode 131 may be connected to the fourth portion 131d of the first through electrode 131 via the second pad 201c. The fifth portion 131e of the first through electrode 131 may be surrounded by the third insulating film 341 and / or may surround the third insulating film 341. The first through electrode 131 may be connected to the first organic photoelectric conversion layer OPD1, the second organic photoelectric conversion layer OPD2, and the third organic photoelectric conversion layer OPD3 via the third portion 131c, the fourth portion 131d, and the fifth portion 131e, respectively. Charges generated by the first organic photoelectric conversion layer OPD1, the second organic photoelectric conversion layer OPD2, and the third organic photoelectric conversion layer OPD3 may be accumulated in the first wiring 151 via the first through electrode 131. The first transfer transistor TR1, the third transfer transistor TR3, and the fourth transfer transistor TR4 are electrically connected to the floating diffusion region FD via the first through electrode 131 and the first wiring 151.

[0104] The second through electrode 132 may include only the third portion 132c. The first transfer gate electrode 201b and the second wiring 152 may be directly connected through the third portion 132c of the second through electrode 132. The third through electrode 133 may include a third portion 133c and a fourth portion 133d, but may not include the first portion 133a and the second portion 133b. The fourth through electrode 134 may include a first portion 134a, a second portion 134b, and a third portion 134c. The first portion 134a of the fourth through electrode 134 may extend between the third electrode layer 203a and the second electrode layer 202a. The second portion 134b of the fourth through electrode 134 may extend between the second electrode layer 202a and the first electrode layer 201a. The third portion 134c of the fourth through electrode 134 may extend between the ninth wiring 159 in the first interlayer insulating film 103 and the first electrode layer 201a. The bias signal S1 may be input to the first electrode layer 201a, the second electrode layer 202a, and the third electrode layer 203a via the fourth through electrode 134.

[0105] The fifth through electrode 135 may extend from the fourth transfer gate electrode 203b to the eighth wiring 158 in the first interlayer insulating film 103. The eighth wiring 158 may be connected to the fourth transfer gate electrode 203b via the fifth through electrode 135. The fourth transfer control signal TX4 may be input to the fourth gate electrode 203b via the eighth wiring 158 and the fifth through electrode 135. The fifth through electrode 135 may be spaced apart from the first through electrode 131, the second through electrode 132, the third through electrode 133, and the fourth through electrode 134. The fifth through electrode 135 may include a first portion 135a, a second portion 135b, and a third portion 135c.

[0106] The first portion 135a of the fifth through electrode 135 may be disposed in the fourth interlayer insulating film 110, the second upper electrode layer 232, the second organic photoelectric conversion layer OPD2, the second semiconductor layer 222, the second dielectric layer 212, and the second electrode layer 202a. The second portion 135b of the fifth through electrode 135 may be disposed in the third interlayer insulating film 109, the first upper electrode layer 231, the first organic photoelectric conversion layer OPD1, the first semiconductor layer 221, the first dielectric layer 211, and the first electrode layer 201a. The first portion 135a and the second portion 135b of the fifth through electrode 135 may be surrounded by and / or surround the fourth insulating film 441. The third portion 135c of the fifth through electrode 135 may be disposed in the first interlayer insulating film 103. For example, the third portion 135c of the fifth through electrode 135 may be in contact with the eighth wiring 158.

[0107] It has been referred to above Figure 13The described base layer 100 only includes the first interlayer insulating film 103, but the inventive concept is not limited thereto. For example, the base layer 100 may further include a second interlayer insulating film 105 disposed on the first interlayer insulating film 103. In this example, the first insertion layer 201 may be disposed on the second interlayer insulating film 105, and the first through electrode 131, the second through electrode 132, the third through electrode 133, the fourth through electrode 134, and / or the fifth through electrode 135 may penetrate through the second interlayer insulating film 105 to extend into the first interlayer insulating film 103.

[0108] Hereinafter, reference will be made to Figure 2 , Figure 12 and Figure 15 to describe an image sensor according to some embodiments of the inventive concept. For clarity, descriptions of elements and features that have been described above will be omitted or at least simplified. Referring to Figure 2 , Figure 12 and Figure 15 , the third storage node SN3 and the fourth transfer transistor TR4 may be disposed in the base layer 100. For example, the third storage node SN3 and the fourth transfer transistor TR4 may be disposed in the first interlayer insulating film 103. The third storage node SN3 may include a third electrode layer 203a, a first portion 213a of the third dielectric layer 213, and a first region 223a of the third semiconductor layer 223. The fourth transfer transistor TR4 may include a fourth transfer gate electrode 203b, a second portion 213b of the third dielectric layer 213, and a second region 223b of the third semiconductor layer 223.

[0109] The third insertion layer 203' may only include a third pad 203c. A bias signal S1 may be input to the first electrode layer 201a, the second electrode layer 202a, and the third electrode layer 203a via the second wiring layer 170.

[0110] The sixth through electrode 136 may connect the third organic photoelectric conversion layer OPD3 and the third storage node SN3. For example, the tenth wiring 181 in the first interlayer insulating film 103 may be connected to the third storage node SN3 via the seventh contact 167. Accordingly, the sixth through electrode 136 may connect the third organic photoelectric conversion layer OPD3 and the third storage node SN3 by using the tenth wiring 181 and the seventh contact 167.

[0111] The above description of Figure 7 the first electrode layer 201a, the first transfer gate electrode 201b, the first dielectric layer 211, and the first semiconductor layer 221 may be directly applied to the third electrode layer 203a, the fourth transfer gate electrode 203b, the third dielectric layer 213, and the third semiconductor layer 223.

[0112] In some embodiments, the third electrode layer 203a, the fourth transfer gate electrode 203b, the third dielectric layer 213, and the third semiconductor layer 223 may be formed in a BEOL processing stage. The third semiconductor layer 223 of the third storage node SN3 may be connected to the eleventh wiring 182 via the eighth contact 168. The fifth wiring 155, the seventh wiring 157, and the eleventh wiring 182 may be connected to the second end of the reset transistor TRR via the first semiconductor layer 221, the second semiconductor layer 222, and the third semiconductor layer 223, respectively. In some embodiments, the fifth wiring 155, the seventh wiring 157, and the eleventh wiring 182 may be connected to the floating diffusion region FD via the first semiconductor layer 221, the second semiconductor layer 222, and the third semiconductor layer 223, respectively.

[0113] Summarizing the above detailed description, those skilled in the art should understand that many changes and modifications can be made to the preferred embodiments without materially departing from the principles of the inventive concept. Therefore, the preferred embodiments of the inventive concept disclosed herein are for general and descriptive purposes only and not for the purpose of limitation.

Claims

1. An image sensor, comprising: a first organic optoelectronic conversion layer located on a base layer; a floating diffusion region located in the base layer; a first storage node including a first electrode layer configured to receive a bias signal, a first portion of a first semiconductor layer, and a first portion of a first dielectric layer, wherein the first dielectric layer extends between the first electrode layer and the first semiconductor layer, and wherein the first storage node is electrically connected to the first organic optoelectronic conversion layer; and a first transfer transistor including a second portion of the first dielectric layer, a second portion of the first semiconductor layer, and a first transfer gate electrode configured to receive a first transfer control signal, wherein the first transfer transistor is electrically connected to the first storage node and the floating diffusion region, and the first electrode layer is spaced apart from the first transfer gate electrode, and the first dielectric layer and the first semiconductor layer are sequentially stacked on the first electrode layer and the first semiconductor layer.

2. The image sensor according to claim 1, further comprising: a semiconductor optoelectronic conversion layer located in the base layer; and a second transfer transistor having a first end electrically connected to the semiconductor optoelectronic conversion layer and a second end electrically connected to the floating diffusion region.

3. The image sensor according to claim 1, wherein, the first transfer gate electrode and the first electrode layer are spaced apart from each other between the base layer and the first organic optoelectronic conversion layer, wherein the image sensor further includes: a first via electrode extending from the first semiconductor layer to a first wiring in the base layer in the base layer; and a second via electrode extending from the first transfer gate electrode to a second wiring in the base layer in the base layer, wherein the first wiring and the second wiring are spaced apart from each other, wherein the first via electrode and the second via electrode are spaced apart from each other, and wherein the first via electrode is electrically connected to the floating diffusion region via a wiring layer.

4. The image sensor according to claim 3, wherein, the second portion of the first dielectric layer is located between the first transfer gate electrode and the first organic optoelectronic conversion layer, and the first portion of the first dielectric layer is located between the first electrode layer and the first organic optoelectronic conversion layer, wherein a third portion of the first semiconductor layer protrudes from the second portion of the first semiconductor layer toward the base layer, and wherein the first via electrode extends from the third portion of the first semiconductor layer.

5. The image sensor according to claim 3, wherein, the first transfer control signal is configured to be input to the first transfer gate electrode via the second wiring and the second via electrode.

6. The image sensor according to claim 3, further comprising: a semiconductor optoelectronic conversion layer located in the base layer; and a second transfer transistor having a first end electrically connected to the semiconductor optoelectronic conversion layer and a second end electrically connected to the floating diffusion region, Wherein, the base layer includes: a first interlayer insulating film including the first wiring, the second wiring, and the connection layer; a substrate including the semiconductor photoelectric conversion layer and the floating diffusion region on the first interlayer insulating film; and a second interlayer insulating film located between the substrate and the first transfer gate electrode and between the substrate and the first electrode layer, and wherein, the second interlayer insulating film includes a color filter.

7. The image sensor according to claim 3, further including: a second organic photoelectric conversion layer located on the first organic photoelectric conversion layer; a second electrode layer to which the bias signal is input, wherein the second electrode layer is located between the first organic photoelectric conversion layer and the second organic photoelectric conversion layer; a second transfer gate electrode located between the first organic photoelectric conversion layer and the second organic photoelectric conversion layer and spaced apart from the second electrode layer; a second dielectric layer located on the second electrode layer and the second transfer gate electrode; a second semiconductor layer including: a first portion between the second dielectric layer and the second organic photoelectric conversion layer and a second portion protruding from the first portion toward the first organic photoelectric conversion layer, wherein the second semiconductor layer includes a semiconductor material; a third through electrode passing through the first organic photoelectric conversion layer, the first semiconductor layer, the first dielectric layer, and the first electrode layer to extend from the second transfer gate electrode to a third wiring in the base layer; and a fourth through electrode extending from the second semiconductor layer to pass through the first organic photoelectric conversion layer and the first semiconductor layer and electrically connected to the first through electrode, wherein the third through electrode is spaced apart from the first through electrode and the second through electrode.

8. The image sensor according to claim 1, wherein, the first transfer gate electrode and the first storage node are located in the base layer, and wherein the image sensor further includes: a first through electrode electrically connecting the first organic photoelectric conversion layer and the first storage node and extending into the base layer.

9. The image sensor according to claim 8, further including: a semiconductor photoelectric conversion layer located in the base layer; and a second transfer transistor having a first end electrically connected to the semiconductor photoelectric conversion layer and a second end electrically connected to the floating diffusion region.

10. The image sensor according to claim 9, wherein, the floating diffusion region is electrically connected to the first semiconductor layer via a connection layer.

11. The image sensor according to claim 8, further including: a second organic photoelectric conversion layer located on the first organic photoelectric conversion layer; a second storage node including: a second electrode layer located in the base layer and spaced apart from the first transfer gate electrode and the first storage node; a second dielectric layer located on the second electrode layer; and a second semiconductor layer located on the second dielectric layer and including a semiconductor material; A second through electrode that penetrates through the base layer to connect the second organic optoelectronic conversion layer and the second storage node and is spaced apart from the first through electrode; and A second transfer transistor that includes the second dielectric layer, the second semiconductor layer, and a second transfer gate electrode to which a second transfer control signal is input, the second transfer transistor having a first end electrically connected to the second storage node and a second end electrically connected to the floating diffusion region, wherein the second storage node is configured to receive the bias signal, and wherein the second electrode layer and the second transfer gate electrode are spaced apart from each other.

12. The image sensor according to claim 1, wherein, the first semiconductor layer includes indium gallium zinc oxide.

13. An image sensor, comprising: A first organic optoelectronic conversion layer located on a base layer; A first transfer gate electrode located in the base layer; A first storage node located in the base layer and including a first electrode layer, a first semiconductor layer, and a first dielectric layer extending between the first electrode layer and the first semiconductor layer; and A through electrode that extends through the base layer to connect the first organic optoelectronic conversion layer and the first storage node, wherein the first electrode layer is spaced apart from the first transfer gate electrode, and wherein the first dielectric layer and the first semiconductor layer are stacked on the first transfer gate electrode, wherein the first transfer gate electrode, the first dielectric layer, and the first semiconductor layer form a first transfer transistor, and the first transfer transistor has a first end electrically connected to the first storage node and a second end electrically connected to the floating diffusion region.

14. The image sensor according to claim 13, further comprising: A semiconductor optoelectronic conversion layer located in the base layer on the first storage node; and A second transfer transistor having a first end electrically connected to the semiconductor optoelectronic conversion layer and a second end electrically connected to the floating diffusion region, wherein the floating diffusion region is electrically connected to the first semiconductor layer.

15. The image sensor according to claim 14, wherein, the first transfer gate electrode is input with a first transfer control signal.

16. An image sensor, comprising: A first organic optoelectronic conversion layer located on a base layer; An insertion layer located between the base layer and the first organic optoelectronic conversion layer; A first dielectric layer located between the first organic optoelectronic conversion layer and the insertion layer; A first semiconductor layer located between the first dielectric layer and the first organic optoelectronic conversion layer; A first through electrode that extends from the insertion layer into the base layer to be electrically connected to a first wiring in the base layer; and A second through electrode that extends from the insertion layer into the base layer to be electrically connected to a second wiring in the base layer, wherein the second through electrode is spaced apart from the first through electrode, Wherein, the insertion layer includes a first transfer gate electrode, a first electrode layer, and a first insulating pattern, and the first insulating pattern separates the first transfer gate electrode from the first electrode layer. Wherein, the first through electrode is spaced apart from the first transfer gate electrode and the first electrode layer, and Wherein, the second through electrode is electrically connected to the first transfer gate electrode and is spaced apart from the first electrode layer.

17. The image sensor according to claim 16, Wherein, the insertion layer further includes a pad and a second insulating pattern, wherein the pad is electrically connected to the first semiconductor layer, and the pad is separated from the first transfer gate electrode by the second insulating pattern, and wherein, the first through electrode is electrically connected to the first semiconductor layer via the pad.

18. The image sensor according to claim 16, further comprising: a semiconductor photoelectric conversion layer located in the base layer; a floating diffusion region located in the base layer; and a second transfer transistor including a first end electrically connected to the semiconductor photoelectric conversion layer and a second end electrically connected to the floating diffusion region.

19. The image sensor according to claim 16, Wherein, the insertion layer includes a first electrode layer and a pad separated by a first insulating pattern, wherein, the first through electrode is electrically connected to the first semiconductor layer via the pad, and wherein, the second through electrode is electrically connected to the first electrode layer.

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